1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd 4 * 5 * author: 6 * Herman Chen <herman.chen@rock-chips.com> 7 */ 8 #ifndef __ROCKCHIP_MPP_RKVDEC2_LINK_H__ 9 #define __ROCKCHIP_MPP_RKVDEC2_LINK_H__ 10 11 #include "mpp_rkvdec2.h" 12 13 #define RKVDEC_REG_IMPORTANT_BASE 0x2c 14 #define RKVDEC_REG_IMPORTANT_INDEX 11 15 #define RKVDEC_SOFTREST_EN BIT(20) 16 17 #define RKVDEC_REG_SECOND_EN_BASE 0x30 18 #define RKVDEC_REG_SECOND_EN_INDEX 12 19 #define RKVDEC_WAIT_RESET_EN BIT(7) 20 21 #define RKVDEC_REG_EN_MODE_SET 13 22 23 #define RKVDEC_REG_DEBUG_INT_BASE 0x440 24 #define RKVDEC_REG_DEBUG_INT_INDEX 272 25 #define RKVDEC_BIT_BUS_IDLE BIT(0) 26 27 #define RKVDEC_REG_TIMEOUT_THRESHOLD 32 28 29 /* define for link hardware */ 30 #define RKVDEC_LINK_ADD_CFG_NUM 1 31 32 #define RKVDEC_LINK_IRQ_BASE 0x000 33 #define RKVDEC_LINK_BIT_IRQ_DIS BIT(2) 34 #define RKVDEC_LINK_BIT_IRQ BIT(8) 35 #define RKVDEC_LINK_BIT_IRQ_RAW BIT(9) 36 #define RKVDEC_LINK_BIT_CORE_WORK_MODE BIT(16) 37 #define RKVDEC_LINK_BIT_CCU_WORK_MODE BIT(17) 38 39 #define RKVDEC_LINK_CFG_ADDR_BASE 0x004 40 41 #define RKVDEC_LINK_MODE_BASE 0x008 42 #define RKVDEC_LINK_BIT_ADD_MODE BIT(31) 43 44 #define RKVDEC_LINK_CFG_CTRL_BASE 0x00c 45 #define RKVDEC_LINK_BIT_CFG_DONE BIT(0) 46 47 #define RKVDEC_LINK_DEC_NUM_BASE 0x010 48 49 #define RKVDEC_LINK_TOTAL_NUM_BASE 0x014 50 51 #define RKVDEC_LINK_EN_BASE 0x018 52 #define RKVDEC_LINK_BIT_EN BIT(0) 53 54 #define RKVDEC_LINK_NEXT_ADDR_BASE 0x01c 55 56 #define RKVDEC_LINK_STA_BASE 0x024 57 58 #define RKVDEC_LINK_REG_CYCLE_CNT 179 59 60 /* define for ccu link hardware */ 61 #define RKVDEC_CCU_CTRL_BASE 0x000 62 #define RKVDEC_CCU_BIT_AUTOGATE BIT(0) 63 #define RKVDEC_CCU_BIT_FIX_RCB BIT(20) 64 65 #define RKVDEC_CCU_CFG_ADDR_BASE 0x004 66 #define RKVDEC_CCU_LINK_MODE_BASE 0x008 67 #define RKVDEC_CCU_BIT_ADD_MODE BIT(31) 68 69 #define RKVDEC_CCU_CFG_DONE_BASE 0x00c 70 #define RKVDEC_CCU_BIT_CFG_DONE BIT(0) 71 72 #define RKVDEC_CCU_DEC_NUM_BASE 0x010 73 #define RKVDEC_CCU_TOTAL_NUM_BASE 0x014 74 75 #define RKVDEC_CCU_WORK_BASE 0x018 76 #define RKVDEC_CCU_BIT_WORK_EN BIT(0) 77 78 #define RKVDEC_CCU_SEND_NUM_BASE 0x024 79 #define RKVDEC_CCU_WORK_MODE_BASE 0x040 80 #define RKVDEC_CCU_BIT_WORK_MODE BIT(0) 81 82 #define RKVDEC_CCU_CORE_WORK_BASE 0x044 83 #define RKVDEC_CCU_CORE_STA_BASE 0x048 84 #define RKVDEC_CCU_CORE_IDLE_BASE 0x04c 85 #define RKVDEC_CCU_CORE_ERR_BASE 0x054 86 87 #define RKVDEC_CCU_CORE_RW_MASK 0x30000 88 89 #define RKVDEC_MAX_WRITE_PART 6 90 #define RKVDEC_MAX_READ_PART 2 91 92 struct rkvdec_link_part { 93 /* register offset of table buffer */ 94 u32 tb_reg_off; 95 /* start idx of task register */ 96 u32 reg_start; 97 /* number of task register */ 98 u32 reg_num; 99 }; 100 101 struct rkvdec_link_status { 102 u32 dec_num_mask; 103 u32 err_flag_base; 104 u32 err_flag_bit; 105 }; 106 107 struct rkvdec_link_info { 108 dma_addr_t iova; 109 /* total register for link table buffer */ 110 u32 tb_reg_num; 111 /* next link table addr in table buffer */ 112 u32 tb_reg_next; 113 /* current read back addr in table buffer */ 114 u32 tb_reg_r; 115 /* secondary enable in table buffer */ 116 u32 tb_reg_second_en; 117 u32 part_w_num; 118 u32 part_r_num; 119 120 struct rkvdec_link_part part_w[RKVDEC_MAX_WRITE_PART]; 121 struct rkvdec_link_part part_r[RKVDEC_MAX_READ_PART]; 122 123 /* interrupt read back in table buffer */ 124 u32 tb_reg_int; 125 u32 tb_reg_cycle; 126 bool hack_setup; 127 struct rkvdec_link_status reg_status; 128 }; 129 130 struct rkvdec_link_dev { 131 struct device *dev; 132 struct mpp_dev *mpp; 133 void __iomem *reg_base; 134 u32 enabled; 135 u32 link_mode; 136 u32 decoded_status; 137 u32 irq_status; 138 u32 iova_curr; 139 u32 iova_next; 140 u32 decoded; 141 u32 total; 142 u32 error; 143 u32 hack_task_running; 144 145 struct rkvdec_link_info *info; 146 struct mpp_dma_buffer *table; 147 u32 link_node_size; 148 u32 link_reg_count; 149 150 /* taskqueue variables */ 151 u32 task_running; 152 atomic_t task_pending; 153 /* timeout can be trigger in different thread so atomic is needed */ 154 atomic_t task_timeout; 155 u32 task_timeout_prev; 156 157 /* link mode hardware status */ 158 atomic_t power_enabled; 159 u32 irq_enabled; 160 161 /* debug variable */ 162 u32 statistic_count; 163 u64 task_cycle_sum; 164 u32 task_cnt; 165 u64 stuff_cycle_sum; 166 u32 stuff_cnt; 167 168 /* link info */ 169 u32 task_capacity; 170 struct mpp_dma_buffer *table_array; 171 struct list_head unused_list; 172 struct list_head used_list; 173 }; 174 175 enum RKVDEC2_CCU_MODE { 176 RKVDEC2_CCU_MODE_NULL = 0, 177 RKVDEC2_CCU_TASK_SOFT = 1, 178 RKVDEC2_CCU_TASK_HARD = 2, 179 RKVDEC2_CCU_MODE_BUTT, 180 }; 181 182 struct rkvdec2_ccu { 183 struct device *dev; 184 /* register base */ 185 void __iomem *reg_base; 186 187 atomic_t power_enabled; 188 struct mpp_clk_info aclk_info; 189 #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS 190 struct proc_dir_entry *procfs; 191 #endif 192 struct reset_control *rst_a; 193 enum RKVDEC2_CCU_MODE ccu_mode; 194 u32 ccu_core_work_mode; 195 196 struct mpp_dma_buffer *table_array; 197 struct list_head unused_list; 198 struct list_head used_list; 199 u32 timeout_flag; 200 }; 201 202 extern struct rkvdec_link_info rkvdec_link_rk356x_hw_info; 203 extern struct rkvdec_link_info rkvdec_link_v2_hw_info; 204 extern struct rkvdec_link_info rkvdec_link_vdpu382_hw_info; 205 206 int rkvdec_link_dump(struct mpp_dev *mpp); 207 208 int rkvdec2_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec); 209 int rkvdec2_link_procfs_init(struct mpp_dev *mpp); 210 int rkvdec2_link_remove(struct mpp_dev *mpp, struct rkvdec_link_dev *link_dec); 211 212 irqreturn_t rkvdec2_link_irq_proc(int irq, void *param); 213 int rkvdec2_link_process_task(struct mpp_session *session, 214 struct mpp_task_msgs *msgs); 215 int rkvdec2_link_wait_result(struct mpp_session *session, 216 struct mpp_task_msgs *msgs); 217 void rkvdec2_link_worker(struct kthread_work *work_s); 218 void rkvdec2_link_session_deinit(struct mpp_session *session); 219 220 /* for ccu link */ 221 int rkvdec2_attach_ccu(struct device *dev, struct rkvdec2_dev *dec); 222 int rkvdec2_ccu_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec); 223 void *rkvdec2_ccu_alloc_task(struct mpp_session *session, struct mpp_task_msgs *msgs); 224 int rkvdec2_ccu_iommu_fault_handle(struct iommu_domain *iommu, 225 struct device *iommu_dev, 226 unsigned long iova, int status, void *arg); 227 irqreturn_t rkvdec2_soft_ccu_irq(int irq, void *param); 228 void rkvdec2_soft_ccu_worker(struct kthread_work *work_s); 229 230 int rkvdec2_ccu_alloc_table(struct rkvdec2_dev *dec, 231 struct rkvdec_link_dev *link_dec); 232 irqreturn_t rkvdec2_hard_ccu_irq(int irq, void *param); 233 void rkvdec2_hard_ccu_worker(struct kthread_work *work_s); 234 235 #endif 236