1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166
167 #define HDMITX_MAX_PIXEL_CLK 597000000 //Max cupported pixel clock
168 //-------------------------------------------------------------------------------------------------
169 // Local Structures
170 //-------------------------------------------------------------------------------------------------
171
172 //*********************//
173 // Video //
174 //*********************//
175
176 typedef enum
177 {
178 E_HDMITX_VIDEO_INTERLACE_MODE = 0,
179 E_HDMITX_VIDEO_PROGRESSIVE_MODE = 1,
180 } MDrv_HDMITx_VIDEO_MODE;
181
182 typedef enum
183 {
184 E_HDMITX_VIDEO_POLARITY_HIGH = 0,
185 E_HDMITX_VIDEO_POLARITY_LOW = 1,
186 } MDrv_HDMITx_VIDEO_POLARITY;
187
188 typedef struct
189 {
190 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
191 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
192 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
193 MS_U16 vs_width; // Vsync pulse width
194 MS_U16 vs_bporch; // Vsync back-porch
195 MS_U16 vde_width; // Vde active width
196 MS_U16 vs_delayline; // Vsync line delay
197 MS_U16 vs_delaypixel; // Vsync pixel delay
198 MS_U16 hs_width; // Hsync pulse width
199 MS_U16 hs_bporch; // Hsync back-porch
200 MS_U16 hde_width; // Hde active width
201 MS_U16 hs_delay; // Hsync delay
202 MS_U16 vtotal; // Vsync total
203 MS_U16 htotal; // Hsync total
204 MS_U16 frame_rate; // Frame Rate
205 MS_U32 pixel_clk; //pixel clock
206 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
207
208 //*********************//
209 // Packet //
210 //*********************//
211
212 typedef enum
213 {
214 E_HDMITX_ACT_GCP_CMD = 0,
215 E_HDMITX_ACT_ACR_CMD = 1,
216 E_HDMITX_ACT_AVI_CMD = 2,
217 E_HDMITX_ACT_AUD_CMD = 3,
218 E_HDMITX_ACT_SPD_CMD = 4,
219 E_HDMITX_ACT_MPG_CMD = 5,
220 E_HDMITX_ACT_VSP_CMD = 6,
221 E_HDMITX_ACT_NUL_CMD = 7,
222 E_HDMITX_ACT_ACP_CMD = 8,
223 E_HDMITX_ACT_ISRC_CMD = 9,
224 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
225 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
226 } MDrvHDMITX_PKTS_ACT_CMD;
227
228 typedef struct PKT
229 {
230 MS_BOOL User_Define;
231 MsHDMITX_PACKET_PROCESS Define_Process;
232 MS_U8 Define_FCnt;
233 }PKT_Behavior;
234 //*********************//
235 // Audio //
236 //*********************//
237 typedef struct
238 {
239 MS_U8 CH_Status3;
240 MS_U32 NcodeValue;
241 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
242
243 //-------------------------------------------------------------------------------------------------
244 // Global Variables
245 //-------------------------------------------------------------------------------------------------
246 MS_U8 gDivider = 0x00;
247 MS_BOOL gDivFlag = FALSE;
248 static MS_U8 gu8ChipVerNum = 0x00;
249 MS_BOOL g_bSupportSCDC = FALSE;
250
251 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
252 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
253
254 // User defined packet behavior
255 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
256 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
257 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
258 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
259 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
260 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
261 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
262 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
263 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
264 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
265
266 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
267 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
268 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
269 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
270 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
271 //-------------------------------------------------------------------------------------------------
272 // Local Variables
273 //-------------------------------------------------------------------------------------------------
274
275 //*********************//
276 // Video //
277 //*********************//
278
279 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
280 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
281 {
282 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
283 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320, 60, 25175000}, // 0: 640x480p
284 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4, 60, 27000000}, // 1: 720x480i
285 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0, 50, 27000000}, // 2: 720x576i
286 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A, 60, 27000000}, // 3: 720x480p
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360, 50, 27000000}, // 4: 720x576p
288 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC, 50, 74250000}, // 5: 1280x720p_50Hz
289 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672, 60, 74250000}, // 6: 1280x720p_60Hz
290 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 74250000}, // 7: 1920x1080i_50Hz
291 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 74250000}, // 8: 1920x1080i_60Hz
292 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE, 24, 74250000}, // 9: 1920x1080p_24Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 25, 74250000}, // 10: 1920x1080p_25Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 30, 74250000}, // 11: 1920x1080p_30Hz
295 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 148500000}, // 12: 1920x1080p_50Hz
296 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 148500000}, // 13: 1920x1080p_60Hz
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE, 24, 148500000}, // 14: 1920x2205p_24Hz //3D: 1920x1080p_24Hz x2
298 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC, 50, 148500000}, // 15: 1280x1470p_50Hz //3D: 1280x720_50Hz x2
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672, 60, 148500000}, // 16: 1280x1470p_60Hz //3D: 1280x720_60Hz x2
300 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
301 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C, 24, 297000000}, // 17:93: 3840x2160p_24Hz
302 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 25, 297000000}, // 18:94: 3840x2160p_25Hz
303 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 30, 297000000}, // 19:95: 3840x2160p_30Hz
304 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 50, 594000000}, // 20:96: 3840x2160p_50Hz
305 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 60, 594000000}, // 21:97: 3840x2160p_60Hz
306
307 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C, 24, 297000000}, // 22:98: 4096x2160p_24Hz
308 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 25, 297000000}, // 23:99: 4096x2160p_25Hz
309 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 30, 297000000}, // 24:100: 4096x2160p_30Hz
310 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 50, 594000000}, // 25:101: 4096x2160p_50Hz
311 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 60, 594000000}, // 26:102: 4096x2160p_60Hz
312 };
313
314 //atop setting
315 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
316 {
317 //color depth = 8bit
318 {
319 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
320 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
321 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
322 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
323 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
324 // 74Mhz
325 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
326 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
327 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
328 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
329 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
330 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
331 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
332 // 148Mhz
333 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
334 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
335 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
336 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
337 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
338 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
339 // 300Mhz
340 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
341 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
342 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
343 // 600Mhz
344 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
345 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
346 // 300Mhz
347 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
348 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
349 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
350 // 600Mhz
351 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
352 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
353 },
354
355 //color depth = 10 bit
356 {
357 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
358 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
359 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
360 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
361 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
362 // 74Mhz
363 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
364 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
365 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
366 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
367 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
368 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
369 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
370 // 148Mhz
371 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
372 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
373 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
374 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
375 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
376 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
377 // 300Mhz
378 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
379 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
380 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
381 // 600Mhz ==> not support !!!
382 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
383 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
384 // 300Mhz
385 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
386 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
387 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
388 // 600Mhz ==> not support !!!
389 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
390 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
391 },
392
393 //color depth = 12 bit
394 {
395 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
396 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
397 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
398 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
399 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
400 // 74Mhz
401 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
402 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
403 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
404 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
405 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
406 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
407 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
408 // 148Mhz
409 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
410 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
411 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
412 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
413 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
414 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
415 // 300Mhz
416 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
417 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
418 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
419 // 600Mhz ==> not support !!!
420 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
421 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
422 // 300Mhz
423 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
424 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
425 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
426 // 600Mhz ==> not support !!!
427 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
428 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
429 },
430
431 //color depth = 16 bit
432 {
433 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
434 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
435 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
436 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
437 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
438 // 74Mhz
439 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
440 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
441 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
442 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
443 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
444 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
445 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
446 // 148Mhz
447 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
448 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
449 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
450 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
451 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
452 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
453 // 300Mhz
454 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
455 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
456 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
457 // 600Mhz ==> Not support !!!
458 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
459 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
460 // 300Mhz
461 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
462 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
463 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
464 // 600Mhz ==> Not support !!!
465 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
466 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
467 },
468 };
469
470 //*********************//
471 // Audio //
472 //*********************//
473
474 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
475 {
476 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
477 };
478
479 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
480 {
481 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
482 };
483
484 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
485 {
486 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
487 };
488
489 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
490 {
491 {0x02, 0x001800}, // No signal, set to 48 KHz
492 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
493 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
494 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
495 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
496 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
497 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
498 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
499 };
500
501 //*********************//
502 // Packet //
503 //*********************//
504
505 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
506 {
507 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
508 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
509 };
510
511 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
512 {
513 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
514 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102,
515 };
516
517 MS_U8 HDMITX_VendorName[8] =
518 {
519 "MStar "
520 };
521
522 MS_U8 HDMITX_ProductName[16] =
523 {
524 "HDMI Tx Demo",
525 };
526
527 MS_U8 _gHPDGpioPin = 0;
528
529 //-------------------------------------------------------------------------------------------------
530 // Debug Functions
531 //-------------------------------------------------------------------------------------------------
532
533 #ifdef MS_DEBUG
534 #define DBG_HDMITX(_f) (_f)
535 #else
536 #define DBG_HDMITX(_f)
537 #endif
538
539 //-------------------------------------------------------------------------------------------------
540 // Local Functions
541 //-------------------------------------------------------------------------------------------------
542
543
544 //-------------------------------------------------------------------------------------------------
545 // Global Functions
546 //-------------------------------------------------------------------------------------------------
547 /*********************************************************************/
548 /* */
549 /* HDCP22 Relative */
550 /* */
551 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)552 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
553 {
554 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
555 if (bEnable)
556 {
557 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
558 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
559 }
560 }
561
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)562 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
563 {
564 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
565 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
566 }
567
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)568 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
569 {
570 #define DEF_HDCP2CIPHER_DBG 0
571 #define SIZE_OF_KSXORLC128 16
572 #define SIZE_OF_RIV 8
573
574 MS_U8 cnt = 0;
575
576 #if (DEF_HDCP2CIPHER_DBG == 1)
577 printf("Ks^LC128:\r\n");
578 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
579 {
580 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
581 }
582 printf("\r\n");
583
584 printf("Riv:\r\n");
585 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
586 {
587 printf("0x%02X ", *(pu8Riv + cnt));
588 }
589 printf("\r\n");
590 #endif
591
592 #undef DEF_HDCP2CIPHER_DBG
593 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
594 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
595
596 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
597 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
598
599 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
600 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
601 }
602
Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)603 void Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)
604 {
605 g_bSupportSCDC = bFlag;
606 }
607
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)608 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
609 {
610 gu8ChipVerNum = u8ChipVer;
611 }
612
613 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
614 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
615 // Interrupt helper functoins
616 //------------------------------------------------------------------------------
617 /// @brief Disable interrupt
618 /// @param[in] u32Int interrupter value
619 /// @return None
620 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)621 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
622 {
623 //MS_U16 u16reg_val = 0;
624
625 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
626 // [9]: mask FIQ, [8]: mask IRQ
627 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
628
629 #if 0 // K1 HPD pin doesn't have interrupt function
630 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
631 {
632 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
633 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
634 {
635 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
636 }
637 }
638 #endif
639 }
640
641 //------------------------------------------------------------------------------
642 /// @brief Enable interrupt
643 /// @param[in] u32Int interrupter value
644 /// @return None
645 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)646 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
647 {
648 //MS_U16 u16reg_val = 0;
649
650 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
651 // [9]: mask FIQ, [8]: unmask IRQ
652 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
653
654 #if 0 // K1 HPD pin doesn't have interrupt function
655 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
656 {
657 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
658 if(u32Int & E_HDMITX_IRQ_12)
659 {
660 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
661 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
662 }
663 }
664 #endif
665 }
666
667 //------------------------------------------------------------------------------
668 /// @brief MHal_HDMITx_Int_Clear
669 /// @param[in] u32Int interrupter value
670 /// @return None
671 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)672 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
673 {
674 //MS_U16 u16reg_val = 0;
675
676 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
677 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
678
679 #if 0 // K1 HPD pin doesn't have interrupt function
680 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
681 {
682 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
683 if(u32Int & E_HDMITX_IRQ_12)
684 {
685 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
686 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
687 }
688 }
689 #endif
690 }
691
692 //------------------------------------------------------------------------------
693 /// @brief MHal_HDMITx_Int_Status
694 /// @param[in] u32Int interrupter value
695 /// @return None
696 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)697 MS_U32 MHal_HDMITx_Int_Status(void)
698 {
699 //MS_U16 u16reg_val = 0;
700 MS_U32 reg_value=0;
701
702 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
703 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
704
705 #if 0 // K1 HPD pin doesn't have interrupt function
706 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
707 {
708 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
709 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
710 }
711 #endif
712 return reg_value;
713 }
714
715
716 //------------------------------------------------------------------------------
717 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
718 /// @return MsHDMITX_RX_STATUS
719 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)720 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
721 {
722 MS_BOOL dviclock_s, hpd_s = FALSE;
723 MsHDMITX_RX_STATUS state;
724
725 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
726
727 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
728
729 if((dviclock_s == FALSE) && (hpd_s == FALSE))
730 state = E_HDMITX_DVIClock_L_HPD_L;
731 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
732 state = E_HDMITX_DVIClock_L_HPD_H;
733 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
734 state = E_HDMITX_DVIClock_H_HPD_L;
735 else
736 state = E_HDMITX_DVIClock_H_HPD_H;
737
738 return state;
739 }
740
741
742 //------------------------------------------------------------------------------
743 /// @brief MHal_HDMITX_SetHDCPConfig
744 /// @param[in] u32Int HDCP mode
745 /// @return None
746 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)747 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
748 {
749 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
750 }
751
752
753 //------------------------------------------------------------------------------
754 /// @brief MHal_HDMITX_GetM02Bytes
755 /// @param[in] u16Int index
756 /// @return M0 2 bytes
757 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)758 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
759 {
760 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
761 }
762
763
764 //------------------------------------------------------------------------------
765 /// @brief MHal_HDMITx_InitSeq
766 /// @param[in] None
767 /// @return None
768 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)769 void MHal_HDMITx_InitSeq(void)
770 {
771 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
772
773 //wilson@temp solution
774 MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
775
776 //MAC setting
777 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
778 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
779 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
780 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
781
782 //sw reset modules
783 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
784 {
785 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
786 }
787 else
788 {
789 //disable power down
790 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
791 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
792 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
793 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
794 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
795 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
796 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
797 }
798
799 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
800
801 //enable PHY setting
802 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
803 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
804 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
805 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
806
807 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
808
809 //disable power down
810 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
811 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
812
813 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
814 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
815
816 //txpll input div 1
817 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
818
819 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
820 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
821 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
822 //Curry only, Follow suggestion from Analog RD(Eric Lu) and set this value to 0x10
823 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0010); //REG_ICTRL_DRV_MAIN_CLK
824
825 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
826 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
827 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
828
829 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
830
831 //lane fifo setting
832 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
833 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
834 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
835 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
836
837 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
838 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
839
840 //QD980 CTS compatibility issue. Change SSCP
841 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, 0x8000);
842
843 }
844
845 //------------------------------------------------------------------------------
846 /// @brief This routine is the initialization for Video module.
847 /// @return None
848 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)849 void MHal_HDMITx_VideoInit(void)
850 {
851 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
852 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
853 }
854
855 //------------------------------------------------------------------------------
856 /// @brief This routine is the initialization for Audio module.
857 /// @return None
858 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)859 void MHal_HDMITx_AudioInit(void)
860 {
861 int num;
862
863 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
864 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
865 }
866
867
868 //------------------------------------------------------------------------------
869 /// @brief This routine turn on/off HDMI PLL
870 /// @return None
871 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)872 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
873 {
874 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
875 }
876
877
MHal_HDMITx_PKT_User_Define_Clear(void)878 void MHal_HDMITx_PKT_User_Define_Clear(void)
879 {
880 MS_U8 i = 0;
881
882 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
883 {
884 gbGeneralPktList[i].EnableUserDef = FALSE;
885 gbGeneralPktList[i].FrmCntNum = 0x00;
886 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
887 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
888 }
889
890 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
891 {
892 gbInfoFrmPktList[i].EnableUserDef = FALSE;
893 gbInfoFrmPktList[i].FrmCntNum = 0x00;
894 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
895 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
896 }
897 }
898
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)899 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
900 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
901 {
902 if (packet_type & 0x80) //infoframe packet type
903 {
904 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
905 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
906 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
907 }
908 else
909 {
910 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
911 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
912 gbGeneralPktList[packet_type].enPktCtrl = def_process;
913 }
914 }
915
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)916 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
917 {
918 MS_BOOL bRet = TRUE;
919 MS_U8 i, j, *ptr;
920 ptr = data;
921
922 switch(packet_type)
923 {
924 case E_HDMITX_VS_INFOFRAME:
925 for (i=0; i < length; i++)
926 {
927 j = i>>1;
928
929 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
930 {
931 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
932 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
933 break;
934 }
935
936 if((i%2)==0)
937 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
938 else
939 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
940 }
941 break;
942 case E_HDMITX_SPD_INFOFRAME:
943 for(i=0;i<length;i++)
944 {
945 j = i>>1;
946
947 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
948 {
949 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
950 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
951 break;
952 }
953
954 if((i%2)==0)
955 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
956 else
957 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
958 }
959 break;
960
961 case E_HDMITX_AVI_INFOFRAME:
962 for ( i = 0; i < length; i++ )
963 {
964 j = i >> 1;
965
966 if (((REG_PKT_AVI_1_09 + j) > REG_PKT_AVI_7_0F) || (((REG_PKT_AVI_1_09 + j) == REG_PKT_AVI_7_0F) && (i % 2 == 1)))
967 {
968 DBG_HDMITX(printf("AVI packet over size, length = %d \n", length));
969 break;
970 }
971
972 if ((i % 2) == 0)
973 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0x00FF, *(ptr+i));
974 else
975 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0xFF00, *(ptr+i) << 8);
976 }
977 break;
978
979 //wilson@kano HDR packet
980 case E_HDMITX_HDR_INFOFRAME:
981 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
982 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
983 //fill length and version
984 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
985
986 if (length >= 3)
987 {
988 for ( i = 0; i < (length-3); i++ )
989 {
990 j = i >> 1;
991
992 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
993 {
994 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
995 break;
996 }
997
998 if ((i % 2) == 0)
999 {
1000 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1001 }
1002 else
1003 {
1004 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1005 }
1006 }
1007 }
1008 break;
1009
1010 case E_HDMITX_AUDIO_INFOFRAME:
1011 {
1012 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1013
1014 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1015
1016 for ( i = 0; i < length; i++ )
1017 {
1018 j = i >> 1;
1019
1020 if ((i % 2) == 0)
1021 {
1022 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1023 }
1024 else
1025 {
1026 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1027 }
1028 }
1029 }
1030 break;
1031
1032 default:
1033 i = 0;
1034 j = 0;
1035 bRet = FALSE;
1036 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1037 break;
1038 }
1039
1040 return bRet;
1041 }
1042
1043 //------------------------------------------------------------------------------
1044 /// @brief This routine turn on/off HDMI Tx TMDS signal
1045 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1046 /// @return None
1047 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1048 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1049 {
1050 if(bRB_Swap) // R/B channel swap
1051 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1052 else
1053 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1054
1055 //reg_atop_en_data_out[13..15]: Enable data channel data output
1056 if (bTMDS == TRUE)
1057 {
1058 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1059 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1060 //TBD: turn off tmds clock
1061
1062 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1063 MsOS_DelayTask(10);
1064 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1065 }
1066 else
1067 {
1068 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1069 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1070 //TBD: turn off tmds clock
1071 }
1072 }
1073
1074 //------------------------------------------------------------------------------
1075 /// @brief This routine turn on/off HDMI Tx video output
1076 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1077 /// @return None
1078 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1079 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1080 {
1081 if (bVideo == TRUE)
1082 {
1083 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1084 }
1085 else
1086 {
1087 MS_U8 i = 0x00;
1088
1089 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1090
1091 // enable test pattern
1092 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1093 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1094 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1095 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1096
1097 for ( i = 0; i < 6; i++ )
1098 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1099 }
1100 }
1101
1102 //------------------------------------------------------------------------------
1103 /// @brief This routine sets video color formatt
1104 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1105 /// @return None
1106 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1107 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1108 {
1109 if (bCSC) // YUV -> RGB
1110 {
1111 DBG_HDMITX(printf("YUV -> RGB \n"));
1112 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1113 }
1114 else // bypass
1115 {
1116 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1117 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1118 }
1119
1120 // YUV422 12 bits output
1121 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1122 }
1123
1124 //------------------------------------------------------------------------------
1125 /// @brief This routine get CSC capability
1126 /// @param[in]
1127 /// @return False : not support R2Y. Ture : ok.
1128 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1129 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1130 {
1131 pDatatIn = pDatatIn;
1132 return HDMITX_CSC_SUPPORT_R2Y;
1133 }
1134
1135 //------------------------------------------------------------------------------
1136 /// @brief This routine sets color domain and color range transform
1137 /// @param[in]
1138 /// @return False : not support this command. Ture : ok.
1139 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1140 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1141 {
1142 MS_BOOL bReturn = FALSE;
1143
1144 if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1145 {
1146 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1147 {
1148 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1149 { //LR -> LY
1150 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1151 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1152 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1153 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1154 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1155 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1156 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1157 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1158 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1159 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1160 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1161 bReturn = TRUE;
1162 DBG_HDMITX(printf("LR->LY! \n"));
1163 }
1164 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1165 { //LR -> FY
1166 #if 1
1167 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1168 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1169 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1170 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1171 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1172 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1173 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1174 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1175 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1176 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1177 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1178
1179 DBG_HDMITX(printf("Not Support This! Replace by LR -> LY\n"));
1180 DBG_HDMITX(printf("LR->FY! \n"));
1181 bReturn = FALSE;
1182 #else
1183 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1184 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1185 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1186 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1187 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1188 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1189 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1190 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1191 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1192 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1193 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1194 bReturn = TRUE;
1195 DBG_HDMITX(printf("LR->FY! \n"));
1196 #endif
1197 }
1198 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1199 { //LR -> FR
1200 #if 1
1201 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1202 DBG_HDMITX(printf("Not Support This! \n"));
1203 DBG_HDMITX(printf("LR->FR! \n"));
1204 bReturn = FALSE;
1205 #else
1206 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1207 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1208 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1209 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1210 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1211 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1212 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1213 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1214 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1215 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1216 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1217 bReturn = TRUE;
1218 DBG_HDMITX(printf("LR->FR! \n"));
1219 #endif
1220 }
1221 else
1222 {
1223 DBG_HDMITX(printf("LR->LR! \n"));
1224 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1225 DBG_HDMITX(printf("In/Out Same Color! \n"));
1226 bReturn = TRUE;
1227 }
1228
1229 }
1230 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1231 {
1232 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1233 { //FR -> LY
1234 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1235 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1236 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1237 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1238 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1239 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1240 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1241 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1242 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1243 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1244 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1245 bReturn = TRUE;
1246 DBG_HDMITX(printf("FR->LY! \n"));
1247 }
1248 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1249 { //FR -> FY
1250 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1251 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1252 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1253 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1254 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1255 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1256 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1257 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1258 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1259 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1260 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1261 bReturn = TRUE;
1262 DBG_HDMITX(printf("FR->FY! \n"));
1263 }
1264 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1265 { //FR -> LR
1266 #if 1
1267 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1268 DBG_HDMITX(printf("Not Support This! \n"));
1269 DBG_HDMITX(printf("FR->LR! \n"));
1270 bReturn = FALSE;
1271 #else
1272 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1273 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1274 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1275 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1276 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1277 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1278 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1279 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1280 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1281 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1282 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1283 bReturn = TRUE;
1284 DBG_HDMITX(printf("FR->LR! \n"));
1285 #endif
1286 }
1287 else
1288 {
1289 DBG_HDMITX(printf("FR->FR! \n"));
1290 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1291 DBG_HDMITX(printf("In/Out Same Color! \n"));
1292 bReturn = TRUE;
1293 }
1294 }
1295 else
1296 {
1297 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1298 DBG_HDMITX(printf("Not Support This! \n"));
1299 }
1300 }
1301 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1302 {
1303 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1304 {
1305 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1306 {//LY->FR
1307 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1308 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1309 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1310 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1311 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1312 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1313 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1314 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1315 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1316 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1317 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1318 bReturn = TRUE;
1319 DBG_HDMITX(printf("LY->FR! \n"));
1320 }
1321 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1322 {//LY->LR
1323 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1324 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1325 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1326 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1327 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1328 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1329 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1330 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1331 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1332 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1333 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1334 bReturn = TRUE;
1335 DBG_HDMITX(printf("May over range! \n"));
1336 DBG_HDMITX(printf("LY->LR! \n"));
1337 }
1338 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1339 {//LY->FY
1340 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1341 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1342 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1343 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1344 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1345 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1346 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1347 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1348 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1349 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1350 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1351 bReturn = TRUE;
1352 DBG_HDMITX(printf("LY->FY! \n"));
1353 }
1354 else
1355 {
1356 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1357 DBG_HDMITX(printf("In/Out Same Color! \n"));
1358 DBG_HDMITX(printf("LY->LY! \n"));
1359 bReturn = TRUE;
1360 }
1361
1362 }
1363 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1364 {
1365 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1366 {//FY->FR
1367 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1368 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1369 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1370 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1371 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1372 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1373 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1374 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1375 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1376 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1377 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1378 bReturn = TRUE;
1379 DBG_HDMITX(printf("FY->FR! \n"));
1380 }
1381 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1382 {//FY->LR
1383 #if 1
1384 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1385 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1386 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1387 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1388 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1389 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1390 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1391 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1392 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1393 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1394 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1395
1396 DBG_HDMITX(printf("Not Support This! Replace by FY -> FR\n"));
1397 DBG_HDMITX(printf("FY->LR! \n"));
1398 bReturn = FALSE;
1399 #else
1400 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1401 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1402 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1403 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1404 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1405 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1406 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1407 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1408 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1409 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1410 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1411 bReturn = TRUE;
1412 DBG_HDMITX(printf("FY->LR! \n"));
1413 #endif
1414 }
1415 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1416 {//FY->LY
1417 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1418 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1419 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1420 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1421 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1424 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1425 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1427 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1428 bReturn = TRUE;
1429 DBG_HDMITX(printf("FY->LY! \n"));
1430 }
1431 else
1432 {
1433 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1434 DBG_HDMITX(printf("In/Out Same Color! \n"));
1435 DBG_HDMITX(printf("FY->FY! \n"));
1436 bReturn = TRUE;
1437 }
1438 }
1439 else
1440 {
1441 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1442 DBG_HDMITX(printf("Not Support This! \n"));
1443 }
1444 }
1445 else
1446 {
1447 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1448 DBG_HDMITX(printf("Not Support This! \n"));
1449 }
1450
1451 //if((bReturn == TRUE) && (outcolor == E_HDMITX_VIDEO_COLOR_YUV422))
1452 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1453
1454 return bReturn;
1455 }
1456
1457 //------------------------------------------------------------------------------
1458 /// @brief This routine will set or stop all HDMI packet generation
1459 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1460 /// @return None
1461 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1462 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1463 {
1464 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1465 }
1466
1467 //------------------------------------------------------------------------------
1468 /// @brief This routine sets HDMI/DVI mode
1469 /// @param[in] bflag
1470 /// @return None
1471 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1472 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1473 {
1474 MS_U8 ucRegVal = 0x00;
1475
1476 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1477
1478 if (bflag) // HDMI mode
1479 {
1480 switch(cd_val)
1481 {
1482 case E_HDMITX_VIDEO_CD_NoID:
1483 case E_HDMITX_VIDEO_CD_24Bits:
1484 default:
1485 ucRegVal = 0x00;
1486 break;
1487
1488 case E_HDMITX_VIDEO_CD_30Bits:
1489 ucRegVal = 0x40;
1490 break;
1491
1492 case E_HDMITX_VIDEO_CD_36Bits:
1493 ucRegVal = 0x80;
1494 break;
1495
1496 case E_HDMITX_VIDEO_CD_48Bits:
1497 ucRegVal = 0xC0;
1498 break;
1499 }
1500
1501 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1502 }
1503 else // DVI
1504 {
1505 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1506 }
1507 }
1508
1509
1510 //------------------------------------------------------------------------------
1511 /// @brief This routine sets audio on/off
1512 /// @param[in] bflag
1513 /// @return None
1514 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1515 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1516 {
1517 MS_U8 num;
1518
1519 if(bflag) // audio on
1520 {
1521 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1522 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1523 }
1524 else // audio off
1525 {
1526 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1527 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1528 }
1529 }
1530
1531 //------------------------------------------------------------------------------
1532 /// @brief This routine sets audio sampling freq.
1533 /// @return None
1534 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1535 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1536 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1537 )
1538 {
1539 // HDMI audio channel setting
1540 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1541 {
1542 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1543 }
1544 else // 8 channels
1545 {
1546 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1547 }
1548
1549 // Audio channel status
1550 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1551 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1552 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1553 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1554 #else
1555 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1556 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1557 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1558 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1559 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1560 #endif
1561 // ACR N code
1562 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1563 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1564
1565 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1566 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1567 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1568 }
1569
1570 //------------------------------------------------------------------------------
1571 /// @brief This routine sets audio source format.
1572 /// @return None
1573 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1574 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1575 {
1576 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1577 }
1578
1579 //------------------------------------------------------------------------------
1580 /// @brief This routine Get Audio CTS value
1581 /// @return CTS
1582 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1583 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1584 {
1585 MS_U32 ret;
1586
1587 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1588 return ret;
1589 }
1590
1591 //------------------------------------------------------------------------------
1592 /// @brief This routine Mute Audio FIFO
1593 /// @param[in] bflag: True: mute audio, False: unmute audio
1594 /// @return None
1595 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1596 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1597 {
1598 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1599 }
1600
1601 //------------------------------------------------------------------------------
1602 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1603 /// @return None
1604 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1605 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1606 {
1607 if(hdcp_flag) // HDCP on
1608 {
1609 if (hdmi_flag) // HDMI EESS
1610 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1611 else // DVI OESS
1612 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1613 // HDCP encryption
1614 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1615 }
1616 else // HDCP off
1617 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1618 }
1619
1620 //------------------------------------------------------------------------------
1621 /// @brief This routine calculate check sum of infoframes.
1622 /// @param[in] packet_type packet type
1623 /// @return checksum
1624 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1625 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1626 {
1627 MS_U8 ucSumVal = 0;
1628 MS_U8 i = 0;
1629 MS_U8 j = 0;
1630 MS_U16 wRegVal = 0;
1631
1632 switch (packet_type)
1633 {
1634 case E_HDMITX_VS_INFOFRAME:
1635 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1636
1637 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1638 {
1639 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1640
1641 for ( j = 0; j < 2; j++ )
1642 {
1643 if ((i == 13) && (j==1))
1644 {
1645 ucSumVal += 0x00;
1646 }
1647 else
1648 {
1649 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1650 }
1651 }
1652 }
1653 break;
1654
1655 case E_HDMITX_AVI_INFOFRAME:
1656 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1657
1658 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1659 {
1660 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1661
1662 for ( j = 0; j < 2; j++ )
1663 {
1664 if ((i == 1) && (j == 0)) // SC[1:0]
1665 {
1666 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1667 }
1668 else if ((i == 1) && (j == 1)) // VIC[6:0]
1669 {
1670 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1671 }
1672 else if ((i == 2) && (j == 0)) // PR[3:0]
1673 {
1674 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1675 }
1676 #if 0 //not resevered byte anymore; should be counted
1677 else if ((i == 2) && (j == 1)) // reserved
1678 {
1679 ucSumVal += 0x00;
1680 }
1681 #endif
1682 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1683 {
1684 ucSumVal += 0x00;
1685 }
1686 else
1687 {
1688 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1689 }
1690 }
1691 }
1692 break;
1693
1694 case E_HDMITX_SPD_INFOFRAME:
1695 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1696
1697 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1698 {
1699 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1700
1701 for ( j = 0; j < 2; j++ )
1702 {
1703 if ((i == 12) && (j == 0))
1704 {
1705 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1706 }
1707 else if ((i == 12) && (j == 1)) //reserved
1708 {
1709 ucSumVal += 0x00;
1710 }
1711 else
1712 {
1713 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1714 }
1715 }
1716 }
1717 break;
1718
1719 case E_HDMITX_AUDIO_INFOFRAME:
1720 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1721
1722 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1723 {
1724 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1725
1726 if (i == 1)
1727 {
1728 for ( j = 0; j < 2; j++ )
1729 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1730 }
1731
1732 if (i == 0)
1733 {
1734 for ( j = 0; j < 2; j++ )
1735 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1736 }
1737
1738 if (i == 2)
1739 {
1740 for ( j = 0; j < 2; j++ )
1741 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1742 }
1743 }
1744 break;
1745
1746 case E_HDMITX_MPEG_INFOFRAME:
1747 //TBD
1748 break;
1749
1750 case E_HDMITX_HDR_INFOFRAME:
1751 {
1752 MS_U8 u8PktLen = 0x00;
1753
1754 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1755 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1756
1757 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1758 {
1759 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1760
1761 for ( j = 0; j < 2; j++ )
1762 {
1763 if ((i == 0x0D) && (j % 2 == 0x00))
1764 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1765 else
1766 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1767 }
1768 }
1769 }
1770 break;
1771
1772 default:
1773 break;
1774 }
1775
1776 return (MS_U8)((~ucSumVal) + 0x01);
1777
1778 }
1779
1780 //------------------------------------------------------------------------------
1781 /// @brief This routine sets video output mode (color/repetition/regen)
1782 /// @param[in] idx: gHDMITxInfo.output_video_timing
1783 /// @return None
1784 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1785 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
1786 {
1787 //MS_U16 reg_value=0;
1788 MS_U8 ucCDIdx = 0;
1789 MS_U16 wHfront = 0;
1790 MS_U16 wVfront = 0;
1791 MS_BOOL bIsHDMI20 = FALSE;
1792 MS_BOOL bIs420Fmt = FALSE;
1793 MS_BOOL bIsRPMode = FALSE;
1794
1795 //wilson@kano:TBD
1796 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
1797 // Deep color FIFO reset
1798 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
1799 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
1800 MsOS_DelayTask(10);
1801
1802 // Interlace mode
1803 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1804 {
1805 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1806 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1807 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1808 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1809 }
1810 else
1811 {
1812 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1813 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1814 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
1815 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1816 }
1817
1818 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
1819 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
1820 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
1821 ((idx > E_HDMITX_RES_1280x1470p_60Hz) && (cd_val > E_HDMITX_VIDEO_CD_24Bits))))
1822 bIsHDMI20 = TRUE;
1823
1824 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
1825 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
1826 (cd_val > E_HDMITX_VIDEO_CD_24Bits))
1827 bIsHDMI20 = TRUE;
1828
1829 if (g_bSupportSCDC == TRUE)
1830 {
1831 //for 2.0
1832 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
1833 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
1834
1835 //scdc
1836 if (bIsHDMI20 == TRUE)
1837 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
1838 else
1839 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
1840 }
1841 else
1842 {
1843 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, 0x00);
1844 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, 0x00);
1845 }
1846
1847 //Curry only, RD suggests(Eric Lu) 0x41[15:8] = 0x11 and 0x42[15:0] = 0x1111 if TMDS is less than 300MHz
1848 if(!bIsHDMI20)
1849 {
1850 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_41, 0xFF00, 0x1100);
1851 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_42, 0xFFFF, 0x1111);
1852 }
1853 else
1854 {
1855 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_41, 0xFF00, 0x0000);
1856 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_42, 0xFFFF, 0x0000);
1857 }
1858
1859 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
1860 {
1861 switch (idx)
1862 {
1863 case E_HDMITX_RES_3840x2160p_50Hz:
1864 idx = E_HDMITX_RES_3840x2160p_25Hz;
1865 break;
1866
1867 case E_HDMITX_RES_3840x2160p_60Hz:
1868 idx = E_HDMITX_RES_3840x2160p_30Hz;
1869 break;
1870
1871 case E_HDMITX_RES_4096x2160p_50Hz:
1872 idx = E_HDMITX_RES_4096x2160p_25Hz;
1873 break;
1874
1875 case E_HDMITX_RES_4096x2160p_60Hz:
1876 idx = E_HDMITX_RES_4096x2160p_30Hz;
1877 break;
1878
1879 default:
1880 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
1881 break;
1882 }
1883
1884 bIs420Fmt = TRUE;
1885 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
1886 }
1887
1888 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
1889 {
1890 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
1891
1892 bIsRPMode = TRUE;
1893 }
1894 else
1895 {
1896 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
1897
1898 bIsRPMode = FALSE;
1899 }
1900
1901 //enable H, VSync regen
1902 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
1903 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
1904 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
1905
1906 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
1907
1908 //deep color setting
1909 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
1910
1911 //HDMITx phy clock
1912 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
1913
1914 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
1915
1916 //sythesizer setting
1917 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
1918 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
1919
1920 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
1921 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
1922
1923 //atop
1924 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
1925 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
1926 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
1927
1928 #if 0
1929 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1930 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
1931 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
1932 #else //RD suggestion
1933 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
1934 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
1935 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
1936 #endif
1937
1938 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1939 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
1940 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
1941
1942 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
1943
1944
1945 // Timing regeneration
1946 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
1947
1948 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
1949 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
1950 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
1951 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
1952 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
1953
1954 //for PG
1955 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
1956 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
1957
1958 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
1959 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
1960 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
1961 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
1962 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
1963 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
1964
1965 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
1966 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
1967 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
1968 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
1969 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
1970
1971 if(!bIsHDMI20)
1972 MHal_HDMITx_EnableSSC(ubSSCEn);
1973
1974 // fifo reset
1975 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
1976 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
1977 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x0FFF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0FFF0000) >> 16));
1978 }
1979
1980 //------------------------------------------------------------------------------
1981 /// @brief This routine will power on or off HDMITx clock (power saving)
1982 /// @param[in] bEnable: TRUE/FALSE
1983 /// @return None
1984 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)1985 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
1986 {
1987 if (bEnable)
1988 {
1989 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
1990 }
1991 else
1992 {
1993 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
1994 }
1995 }
1996
1997
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)1998 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
1999 {
2000 //wilson@kano:TBD
2001 #if 0
2002 return FALSE;
2003 #else
2004 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2005 if (bflag == TRUE)
2006 {
2007 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2008
2009 //Note: change frequency tolerance if need
2010 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2011 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2012 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2013 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2014 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2015 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2016 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2017
2018 //Enable Fifo and select input source
2019 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2020
2021 #if 0
2022 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2023 {
2024 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2025 }
2026 #endif
2027
2028 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2029 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2030 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2031 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2032
2033 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2034
2035 //synthesizer setting //TBD
2036 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2037 //ssc_set = 0x140000
2038 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2039 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2040
2041 #if 0 //with SSC clock
2042 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2043 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2044 #else //without SSC clock
2045 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2046 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2047 #endif
2048
2049 //ATOP setting
2050 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2051 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2052 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2053 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2054 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2055 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2056 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2057 }
2058 else
2059 {
2060 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2061 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2062 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2063 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2064 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2065 }
2066
2067 return TRUE;
2068
2069 #endif
2070 }
2071
2072
2073 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2074 /// @return None
2075 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2076 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2077 {
2078 #if 0
2079 return FALSE;
2080 #else
2081 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2082 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2083 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2084 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2085 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2086
2087 return TRUE;
2088 #endif
2089 }
2090
2091
2092 //------------------------------------------------------------------------------
2093 /// @brief This routine will set GPIO pin for HPD
2094 /// @param[in] u8pin: GPIO0 ~ 12
2095 /// @return None
2096 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2097 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2098 {
2099 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2100 _gHPDGpioPin = u8pin;
2101 }
2102
2103 //------------------------------------------------------------------------------
2104 /// @brief This routine return CHIP capability of DVI mode
2105 /// @return TRUE, FALSE
2106 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2107 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2108 {
2109 return TRUE;
2110 }
2111
2112 // ************* For customer NDS **************//
2113
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2114 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2115 {
2116 MS_U16 tmp_value=0;
2117
2118 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2119 {
2120 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2121 }
2122 else
2123 {
2124 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0080, 0x80); // EIA version 2
2125 switch(content_type)
2126 {
2127 case E_HDMITX_AVI_PIXEL_FROMAT:
2128 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0060, *data);
2129 break;
2130 case E_HDMITX_AVI_ASPECT_RATIO:
2131 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2132 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2133 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2134 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2135 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2136 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0xFFFF, *(data+5));
2137 break;
2138 case E_HDMITX_AVI_COLORIMETRY:
2139 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2140 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2141 break;
2142 default:
2143 break;
2144 }
2145
2146 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2147 // cyclic packet
2148 if (IS_CYCLIC_PKT(packet_process))
2149 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2150 // single packet
2151 else
2152 {
2153 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2154 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2155 }
2156 }
2157 }
2158
2159 //wilson@kano
2160 //**************************************************************************
2161 // [Function Name]:
2162 // MHal_HDMITx_SetGCPParameter()
2163 // [Description]:
2164 // setting General Control packet attribute
2165 // [Arguments]:
2166 // [stGC_PktPara] stPktPara
2167 // [Return]:
2168 // void
2169 //
2170 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2171 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2172 {
2173 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2174 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2175 }
2176
2177 //**************************************************************************
2178 // [Function Name]:
2179 // MHal_HDMITx_SetPktAttribute()
2180 // [Description]:
2181 // configure settings to corresponding packet
2182 // [Arguments]:
2183 // [MsHDMITX_PACKET_TYPE] enPktType
2184 // [MS_BOOL] bEnUserDef
2185 // [MS_U8] u8FrmCntNum
2186 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2187 // [Return]:
2188 // void
2189 //
2190 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2191 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2192 {
2193 if (enPktType & 0x80) //infoframe packet type
2194 {
2195 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2196 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2197 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2198 }
2199 else
2200 {
2201 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2202 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2203 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2204 }
2205 }
2206
2207 //**************************************************************************
2208 // [Function Name]:
2209 // MHal_HDMITx_SetAVIInfoParameter()
2210 // [Description]:
2211 // Assign content to AVI Infoframe packet
2212 // [Arguments]:
2213 // [stAVIInfo_PktPara] stPktPara
2214 // [Return]:
2215 // void
2216 //
2217 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2218 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2219 {
2220 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2221 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2222 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2223 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2224 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorimetry = stPktPara.enColorimetry;
2225 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2226 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2227 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2228 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2229 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2230 }
2231
2232 //**************************************************************************
2233 // [Function Name]:
2234 // MHal_HDMITx_SetVSInfoParameter()
2235 // [Description]:
2236 // Assign content to VendorSpecific Infoframe packet
2237 // [Arguments]:
2238 // [stVSInfo_PktPara] stPketPara
2239 // [Return]:
2240 // void
2241 //
2242 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2243 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2244 {
2245 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2246 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2247 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2248 }
2249
2250 //**************************************************************************
2251 // [Function Name]:
2252 // MHal_HDMITx_SetVSInfoParameter()
2253 // [Description]:
2254 // Assign content to VendorSpecific Infoframe packet
2255 // [Arguments]:
2256 // [stVSInfo_PktPara] stPketPara
2257 // [Return]:
2258 // void
2259 //
2260 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2261 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2262 {
2263 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2264 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2265 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2266 }
2267
2268 //**************************************************************************
2269 // [Function Name]:
2270 // MHal_HDMITx_SendPacket()
2271 // [Description]:
2272 // configure packet content and process according to user define or defalut setting
2273 // [Arguments]:
2274 // [MsHDMITX_PACKET_TYPE] enPktType
2275 // [Return]:
2276 // void
2277 //
2278 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2279 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2280 {
2281 if (enPktType & 0x80) //info frame packet
2282 {
2283 MS_U8 ucInfoPktType = enPktType & (~0x80);
2284 MS_U8 ucChkSum = 0;
2285
2286 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2287
2288 switch (enPktType)
2289 {
2290 case E_HDMITX_VS_INFOFRAME:
2291 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2292 {
2293 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2294 }
2295 else
2296 {
2297 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2298 {
2299 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2300
2301 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2302 {
2303 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2304 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2305 }
2306 else
2307 {
2308 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2309 }
2310 }
2311 else
2312 {
2313 //fill IEEE HDMI tag
2314 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2315
2316 //check content
2317 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2318 {
2319 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2320 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2321 }
2322 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2323 {
2324 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2325 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2326 }
2327 else
2328 {
2329 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2330 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2331 }
2332
2333 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2334
2335 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2336 {
2337 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2338 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2339 }
2340 else
2341 {
2342 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2343 }
2344 }
2345 }
2346 break;
2347
2348 case E_HDMITX_AVI_INFOFRAME:
2349 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2350 {
2351 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2352 }
2353 else
2354 {
2355 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2356 {
2357 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2358
2359 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2360 {
2361 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2362 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2363 }
2364 else
2365 {
2366 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2367 }
2368 }
2369 else
2370 {
2371 MS_U8 ucPktVal = 0;
2372
2373 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2374 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2375 //A0 field
2376 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2377 //S1, S0 field
2378 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2379
2380 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2381
2382 //C1, C0, M1, M0
2383 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2384 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2385 {
2386 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2387 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2388 }
2389 else
2390 {
2391 //HD timing is always 16:9
2392 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2393 }
2394
2395 //R3, R2, R1, R0: active porting aspect ration
2396 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2397 {
2398 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2399 }
2400
2401 //ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2402
2403 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry != E_HDMITX_COLORIMETRY_MAX)
2404 {
2405 ucPktVal = (ucPktVal & 0x3F) | ( ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry & 0x03) << 6);
2406 }
2407
2408 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2409
2410 //EC0, EC1, EC2
2411 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2412 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2413 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2414
2415 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2416 {
2417 //Q1, Q0
2418 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2419 {
2420 ucPktVal = 1;
2421 }
2422 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2423 {
2424 ucPktVal = 2;
2425 }
2426 else
2427 {
2428 ucPktVal = 0;
2429 }
2430
2431 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2432 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2433 }
2434 else
2435 {
2436 //YQ1, YQ0
2437 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2438 {
2439 ucPktVal = 0;
2440 }
2441 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2442 {
2443 ucPktVal = 1;
2444 }
2445 else
2446 {
2447 ucPktVal = 3;
2448 }
2449
2450 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2451 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2452 }
2453
2454 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2455 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2456
2457 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2458 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2459 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2460 {
2461 ucPktVal += 1;
2462 }
2463 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2464 {
2465 MS_U8 AR21_9MappingTbl[14][2] = {
2466 {60, 65},
2467 {61, 66},
2468 {62, 67},
2469 {19, 68},
2470 { 4, 69},
2471 {41, 70},
2472 {47, 71},
2473 {32, 72},
2474 {33, 73},
2475 {34, 74},
2476 {31, 75},
2477 {16, 76},
2478 {64, 77},
2479 {63, 78}
2480 };
2481
2482 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2483 {
2484 ucPktVal += 10;
2485 }
2486 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= 17) &&\
2487 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= 19))
2488 {
2489 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - 17));
2490 }
2491 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2492 {
2493 //do nothing;
2494 }
2495 else
2496 {
2497 MS_U8 i = 0;
2498 MS_BOOL bValidVIC = FALSE;
2499
2500 for ( i = 0; i < 14; i++ )
2501 {
2502 if (AR21_9MappingTbl[i][0] == ucPktVal)
2503 {
2504 ucPktVal = AR21_9MappingTbl[i][1];
2505 bValidVIC = TRUE;
2506 break;
2507 }
2508 }
2509
2510 if (!bValidVIC)
2511 {
2512 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2513 }
2514 }
2515 }
2516
2517 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
2518
2519 //check repetition
2520 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
2521 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
2522 {
2523 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
2524 }
2525 else
2526 {
2527 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2528 }
2529
2530 //YQ1, YQ0
2531 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
2532
2533 //AVI version
2534 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
2535 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
2536
2537 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2538
2539 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2540 {
2541 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2542 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2543 }
2544 else
2545 {
2546 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
2547 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
2548 }
2549 }
2550 }
2551 break;
2552
2553 case E_HDMITX_SPD_INFOFRAME:
2554 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2555 {
2556 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
2557 }
2558 else
2559 {
2560 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2561 {
2562 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2563
2564 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2565 {
2566 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2567 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2568 }
2569 else
2570 {
2571 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2572 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
2573 }
2574 }
2575 else
2576 {
2577 MS_U8 i = 0;
2578 MS_U8 ucPktVal = 0;
2579
2580 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
2581 {
2582 if (i < 4) // vendor name
2583 {
2584 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
2585 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
2586 }
2587 else if ((i >= 4) && (i < 12)) // product description
2588 {
2589 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
2590 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
2591 }
2592 else // source device information
2593 {
2594 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
2595 }
2596 }
2597
2598 #if 0
2599 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
2600 {
2601 if ( i < 8 )
2602 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
2603 else
2604 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
2605 }
2606
2607 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
2608 #endif
2609
2610 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2611
2612 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2613 {
2614 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2615 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2616 }
2617 else
2618 {
2619 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
2620 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
2621 }
2622 }
2623 }
2624
2625 break;
2626
2627 case E_HDMITX_AUDIO_INFOFRAME:
2628 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2629 {
2630 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
2631 }
2632 else
2633 {
2634 // Modified for HDMI CTS test -
2635 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
2636 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
2637 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
2638 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
2639 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
2640
2641 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
2642 {
2643 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
2644 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
2645 }
2646 else //8- channel
2647 {
2648 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
2649 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
2650 }
2651 //clear LFEP value
2652 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
2653
2654 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
2655
2656 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2657 {
2658 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
2659 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
2660 }
2661 else
2662 {
2663 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2664 {
2665 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2666 }
2667 else
2668 {
2669 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
2670 }
2671 }
2672 }
2673
2674 //NOTE:: Kano move channel status from 0x00 to 0x0A
2675 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
2676 {
2677 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
2678 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
2679 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
2680 }
2681 // Audio sampling frequency
2682 // 1 1 0 0 32 kHz
2683 // 0 0 0 0 44.1 kHz
2684 // 0 0 0 1 88.2 kHz
2685 // 0 0 1 1 176.4 kHz
2686 // 0 1 0 0 48 kHz
2687 // 0 1 0 1 96 kHz
2688 // 0 1 1 1 192 kHz
2689 // 1 0 0 1 768 kHz
2690 break;
2691
2692 case E_HDMITX_MPEG_INFOFRAME:
2693 //TBD
2694 break;
2695
2696 case E_HDMITX_HDR_INFOFRAME:
2697 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2698 {
2699 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
2700 }
2701 else
2702 {
2703 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2704 {
2705 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2706
2707 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2708 {
2709 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2710 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2711 }
2712 else
2713 {
2714 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2715 }
2716 }
2717 else
2718 {
2719 //TBD
2720 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2721
2722 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2723 {
2724 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2725 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2726 }
2727 else
2728 {
2729 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
2730 }
2731
2732 }
2733 }
2734 break;
2735
2736 default:
2737 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2738 break;
2739 }
2740 }
2741 else //general packet
2742 {
2743 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
2744
2745 switch (enPktType)
2746 {
2747 case E_HDMITX_NULL_PACKET:
2748 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2749 {
2750 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
2751 }
2752 else
2753 {
2754 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2755 {
2756 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
2757 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
2758 }
2759 else
2760 {
2761 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2762 {
2763 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
2764 }
2765 else
2766 {
2767 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
2768 }
2769 }
2770 }
2771 break;
2772
2773 case E_HDMITX_ACR_PACKET:
2774 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2775 {
2776 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
2777 }
2778 else
2779 {
2780 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2781 {
2782 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
2783 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
2784 }
2785 else //cyclic
2786 {
2787 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2788 {
2789 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
2790 }
2791 else
2792 {
2793 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
2794 }
2795 }
2796 }
2797 break;
2798
2799 case E_HDMITX_AS_PACKET:
2800 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2801 {
2802 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
2803 }
2804 else
2805 {
2806 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
2807 }
2808 break;
2809
2810 case E_HDMITX_GC_PACKET:
2811 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2812 {
2813 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
2814 }
2815 else
2816 {
2817 //fill color depth information
2818 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
2819
2820 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2821 {
2822 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
2823 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
2824 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
2825 }
2826 else //cyclic
2827 {
2828 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2829 {
2830 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
2831 }
2832 else
2833 {
2834 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
2835 }
2836 }
2837 }
2838 break;
2839
2840 case E_HDMITX_ACP_PACKET:
2841 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2842 {
2843 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
2844 }
2845 else
2846 {
2847 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
2848
2849 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2850 {
2851 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
2852 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
2853 }
2854 else //cyclic
2855 {
2856 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2857 {
2858 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2859 }
2860 else
2861 {
2862 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
2863 }
2864 }
2865 }
2866 break;
2867
2868 case E_HDMITX_ISRC1_PACKET:
2869 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2870 {
2871 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2872 }
2873 else
2874 {
2875 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2876 {
2877 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
2878 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2879 }
2880 else //cyclic
2881 {
2882 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2883 {
2884 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
2885 else
2886 {
2887 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2888 }
2889 }
2890 }
2891 break;
2892
2893 case E_HDMITX_ISRC2_PACKET:
2894 //check ISRC cnt value
2895 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
2896 {
2897 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2898 {
2899 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2900 }
2901 else
2902 {
2903 MS_U8 u8ISRCCntVal = 0x80;
2904
2905 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2906 {
2907 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
2908 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2909 }
2910 else //cyclic
2911 {
2912 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2913 {
2914 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2915 }
2916 else
2917 {
2918 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2919 }
2920 }
2921 }
2922 }
2923 break;
2924
2925 case E_HDMITX_DSD_PACKET:
2926 //TBD
2927 break;
2928
2929 case E_HDMITX_HBR_PACKET:
2930 //TBD
2931 break;
2932
2933 case E_HDMITX_GM_PACKET:
2934 //TBD
2935 break;
2936
2937 default:
2938 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2939 break;
2940 }
2941 }
2942 }
2943
MHal_HDMITx_EnableSSC(MS_BOOL bEnable)2944 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable)
2945 {
2946 #define HDMITX_MPLL_CLK 432 //432MHz
2947 #define HDMITX_SSC_CLK 30 //30KHz
2948 #define HDMITX_SSC_DEVIATION 0.001 // 0.1%
2949 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
2950 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
2951 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
2952 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
2953 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
2954
2955 double ub2x19times = 524288;// 2^ 19
2956 double dSYNCLK = 1;
2957 double ub432MHz = HDMITX_MPLL_CLK;
2958 double ubSSCClk = HDMITX_SSC_CLK;
2959 double dSSc_Deviation= HDMITX_SSC_DEVIATION;
2960 MS_U32 ubSYNSet = 0;
2961 double dSSC_Span = 0;
2962 double dSSC_Step = 0;
2963 double dPixel_Clk = 0;
2964
2965 if(!bEnable)
2966 {
2967 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
2968 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
2969 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
2970 return;
2971 }
2972
2973
2974 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
2975 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
2976
2977 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet);
2978
2979 dSSC_Span = dSYNCLK * 1000 / (ubSSCClk * 4); //Span = SYN_CLK / (SSC_CLK * 4)
2980 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span
2981
2982 printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
2983
2984 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
2985 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
2986
2987 //Read tmds clock
2988 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
2989 dPixel_Clk = (double) ( (double)(MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
2990 printf("dPixel_Clk=%f\r\n", dPixel_Clk);
2991
2992 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
2993 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
2994 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
2995 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
2996 else
2997 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
2998 }
2999
MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx,MsHDMITX_VIDEO_COLOR_FORMAT color_fmt,MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)3000 MS_U32 MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT color_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)
3001 {
3002 MS_U32 dwTMDSDataRate = 0;
3003 MS_U8 ubBitNum = 8;
3004
3005 switch(color_depth)
3006 {
3007 case E_HDMITX_VIDEO_CD_NoID:
3008 case E_HDMITX_VIDEO_CD_24Bits:
3009 {
3010 ubBitNum = 8;
3011 }
3012 break;
3013
3014 case E_HDMITX_VIDEO_CD_30Bits:
3015 {
3016 ubBitNum = 10;
3017 }
3018 break;
3019
3020 case E_HDMITX_VIDEO_CD_36Bits:
3021 {
3022 ubBitNum = 12;
3023 }
3024 break;
3025
3026 case E_HDMITX_VIDEO_CD_48Bits:
3027 {
3028 ubBitNum = 16;
3029 }
3030 break;
3031
3032 default:
3033 {
3034 ubBitNum = 8;
3035 }
3036 break;
3037 }
3038
3039 dwTMDSDataRate = (HDMITxVideoModeTbl[idx].pixel_clk/1000) * ubBitNum / 8;
3040
3041 if(color_fmt == E_HDMITX_VIDEO_COLOR_YUV420)
3042 dwTMDSDataRate = dwTMDSDataRate/2;
3043
3044 printf("Time_ID = %d, C_FMT = %d, C_DEP = %d, PXL_CLK = %d\r\n", idx, color_fmt, color_depth, dwTMDSDataRate);
3045 return dwTMDSDataRate;
3046 }
3047
MHal_HDMITx_GetMaxPixelClk(void)3048 MS_U32 MHal_HDMITx_GetMaxPixelClk(void)
3049 {
3050 return HDMITX_MAX_PIXEL_CLK/1000;
3051 }
3052