1 /*
2 * Copyright (C) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c:
6 * Copyright (C) 2012 rockchips
7 * zyw <zyw@rock-chips.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <log.h>
16 #include <linux/delay.h>
17 #include <power/rk8xx_pmic.h>
18 #include <power/pmic.h>
19 #include <power/regulator.h>
20
21 #ifndef CONFIG_SPL_BUILD
22 #define ENABLE_DRIVER
23 #endif
24
25 /* Not used or exisit register and configure */
26 #define NA -1
27
28 /* Field Definitions */
29 #define RK808_BUCK_VSEL_MASK 0x3f
30 #define RK808_BUCK4_VSEL_MASK 0xf
31 #define RK808_LDO_VSEL_MASK 0x1f
32
33 #define RK818_BUCK_VSEL_MASK 0x3f
34 #define RK818_BUCK4_VSEL_MASK 0x1f
35 #define RK818_LDO_VSEL_MASK 0x1f
36 #define RK818_LDO3_ON_VSEL_MASK 0xf
37 #define RK818_BOOST_ON_VSEL_MASK 0xe0
38 #define RK818_USB_ILIM_SEL_MASK 0x0f
39 #define RK818_USB_CHG_SD_VSEL_MASK 0x70
40
41 /* RK809 BUCK5 */
42 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1)
43 #define RK809_BUCK5_VSEL_MASK 0x07
44
45 /* RK817 BUCK */
46 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1))
47 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1))
48 #define RK817_BUCK_VSEL_MASK 0x7f
49 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3)
50
51 /* RK817 LDO */
52 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1))
53 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1))
54 #define RK817_LDO_VSEL_MASK 0x7f
55
56 /* RK817 ENABLE */
57 #define RK817_POWER_EN(n) (0xb1 + (n))
58 #define RK817_POWER_SLP_EN(n) (0xb5 + (n))
59
60 /* RK817 BOOST */
61 #define RK817_BOOST_OTG_CONFIG0 (0xde)
62 #define RK817_BOOST_CONFIG1 (0xdf)
63 #define RK817_BOOST_VSEL_MASK 0x07
64
65 /*
66 * Ramp delay
67 */
68 #define RK805_RAMP_RATE_OFFSET 3
69 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET)
70 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET)
71 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
72 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
73 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
74
75 #define RK808_RAMP_RATE_OFFSET 3
76 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
77 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
78 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
79 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
80 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
81
82 #define RK817_RAMP_RATE_OFFSET 6
83 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
84 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
85 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
86 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
87 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
88
89 struct rk8xx_reg_info {
90 uint min_uv;
91 uint step_uv;
92 u8 vsel_reg;
93 u8 vsel_sleep_reg;
94 u8 config_reg;
95 u8 vsel_mask;
96 u8 min_sel;
97 /* only for buck now */
98 u8 max_sel;
99 u8 range_num;
100 };
101
102 static const struct rk8xx_reg_info rk806_buck[] = {
103 /* buck 1 */
104 { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
105 { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xec, 3},
106 { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
107 /* buck 2 */
108 { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
109 { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
110 { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
111 /* buck 3 */
112 { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
113 { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
114 { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
115 /* buck 4 */
116 { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
117 { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
118 { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
119 /* buck 5 */
120 { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
121 { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
122 { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
123 /* buck 6 */
124 { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
125 { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
126 { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
127 /* buck 7 */
128 { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
129 { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
130 { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
131 /* buck 8 */
132 { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
133 { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
134 { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
135 /* buck 9 */
136 { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
137 { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
138 { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
139 /* buck 10 */
140 { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3},
141 { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3},
142 { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3},
143 };
144
145 static const struct rk8xx_reg_info rk806_nldo[] = {
146 /* nldo1 */
147 { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, },
148 { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
149 /* nldo2 */
150 { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, },
151 { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
152 /* nldo3 */
153 { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, },
154 { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
155 /* nldo4 */
156 { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, },
157 { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
158 /* nldo5 */
159 { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, },
160 { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xE8, },
161 };
162
163 static const struct rk8xx_reg_info rk806_pldo[] = {
164 /* pldo1 */
165 { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, },
166 { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
167 /* pldo2 */
168 { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, },
169 { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
170 /* pldo3 */
171 { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, },
172 { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
173 /* pldo4 */
174 { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, },
175 { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
176 /* pldo5 */
177 { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, },
178 { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
179 /* pldo6 */
180 { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, },
181 { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
182 };
183
184 static const struct rk8xx_reg_info rk808_buck[] = {
185 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
186 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
187 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
188 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK,0x00, 0x0f, 1},
189 };
190
191 static const struct rk8xx_reg_info rk816_buck[] = {
192 /* buck 1 */
193 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3},
194 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3},
195 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3},
196 /* buck 2 */
197 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3},
198 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3},
199 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3},
200 /* buck 3 */
201 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
202 /* buck 4 */
203 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x1b, 1},
204 };
205
206 static const struct rk8xx_reg_info rk809_buck5[] = {
207 /* buck 5 */
208 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00, 4},
209 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03, 4},
210 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05, 4},
211 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07, 4},
212 };
213
214 static const struct rk8xx_reg_info rk817_buck[] = {
215 /* buck 1 */
216 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
217 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
218 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
219 /* buck 2 */
220 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
221 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
222 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
223 /* buck 3 */
224 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
225 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3},
226 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3},
227 /* buck 4 */
228 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3},
229 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62, 3},
230 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x63, 3},
231 };
232
233 static const struct rk8xx_reg_info rk818_buck[] = {
234 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
235 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1},
236 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1},
237 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x10, 1},
238 };
239
240 #ifdef ENABLE_DRIVER
241 static const struct rk8xx_reg_info rk808_ldo[] = {
242 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
243 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
244 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, },
245 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
246 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
247 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
248 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
249 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
250 };
251
252 static const struct rk8xx_reg_info rk816_ldo[] = {
253 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
254 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
255 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
256 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
257 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
258 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
259 };
260
261 static const struct rk8xx_reg_info rk817_ldo[] = {
262 /* ldo1 */
263 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, },
264 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, },
265 /* ldo2 */
266 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, },
267 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, },
268 /* ldo3 */
269 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, },
270 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, },
271 /* ldo4 */
272 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, },
273 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, },
274 /* ldo5 */
275 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, },
276 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, },
277 /* ldo6 */
278 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, },
279 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, },
280 /* ldo7 */
281 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, },
282 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, },
283 /* ldo8 */
284 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, },
285 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, },
286 /* ldo9 */
287 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, },
288 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, },
289 };
290
291 static const struct rk8xx_reg_info rk818_ldo[] = {
292 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
293 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
294 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, },
295 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
296 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
297 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
298 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
299 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
300 };
301
302 static const struct rk8xx_reg_info rk817_boost[] = {
303 /* boost */
304 { 4700000, 100, RK817_BOOST_OTG_CONFIG0, RK817_BOOST_CONFIG1, NA, RK817_BOOST_VSEL_MASK, 0x00, },
305 };
306 #endif
307
308 static const u16 rk818_chrg_cur_input_array[] = {
309 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
310 };
311
312 static const uint rk818_chrg_shutdown_vsel_array[] = {
313 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
314 };
315
get_buck_reg(struct udevice * pmic,int num,int uvolt)316 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
317 int num, int uvolt)
318 {
319 struct rk8xx_priv *priv = dev_get_priv(pmic);
320
321 switch (priv->variant) {
322 case RK806_ID:
323 switch (num) {
324 case 0 ... 9:
325 if (uvolt < 1500000)
326 return &rk806_buck[num * 3 + 0];
327 else if (uvolt < 3400000)
328 return &rk806_buck[num * 3 + 1];
329 else
330 return &rk806_buck[num * 3 + 2];
331 }
332 case RK805_ID:
333 case RK816_ID:
334 switch (num) {
335 case 0:
336 case 1:
337 if (uvolt <= 1450000)
338 return &rk816_buck[num * 3 + 0];
339 else if (uvolt <= 2200000)
340 return &rk816_buck[num * 3 + 1];
341 else
342 return &rk816_buck[num * 3 + 2];
343 default:
344 return &rk816_buck[num + 4];
345 }
346
347 case RK809_ID:
348 case RK817_ID:
349 switch (num) {
350 case 0 ... 2:
351 if (uvolt < 1500000)
352 return &rk817_buck[num * 3 + 0];
353 else if (uvolt < 2400000)
354 return &rk817_buck[num * 3 + 1];
355 else
356 return &rk817_buck[num * 3 + 2];
357 case 3:
358 if (uvolt < 1500000)
359 return &rk817_buck[num * 3 + 0];
360 else if (uvolt < 3400000)
361 return &rk817_buck[num * 3 + 1];
362 else
363 return &rk817_buck[num * 3 + 2];
364 /* BUCK5 for RK809 */
365 default:
366 if (uvolt < 1800000)
367 return &rk809_buck5[0];
368 else if (uvolt < 2800000)
369 return &rk809_buck5[1];
370 else if (uvolt < 3300000)
371 return &rk809_buck5[2];
372 else
373 return &rk809_buck5[3];
374 }
375 case RK818_ID:
376 return &rk818_buck[num];
377 default:
378 return &rk808_buck[num];
379 }
380 }
381
_buck_set_value(struct udevice * pmic,int buck,int uvolt)382 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
383 {
384 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
385 struct rk8xx_priv *priv = dev_get_priv(pmic);
386 int mask = info->vsel_mask;
387 int val;
388
389 if (info->vsel_reg == NA)
390 return -ENOSYS;
391
392 if (info->step_uv == 0) /* Fixed voltage */
393 val = info->min_sel;
394 else
395 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
396
397 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
398 __func__, uvolt, buck + 1, info->vsel_reg, mask, val);
399
400 if (priv->variant == RK816_ID) {
401 pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
402 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7);
403 } else {
404 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
405 }
406 }
407
_buck_set_enable(struct udevice * pmic,int buck,bool enable)408 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
409 {
410 uint mask, value, en_reg;
411 int ret;
412 struct rk8xx_priv *priv = dev_get_priv(pmic);
413
414 switch (priv->variant) {
415 case RK806_ID:
416 en_reg = RK806_POWER_EN(buck / 4);
417 if (enable)
418 value = ((1 << buck % 4) | (1 << (buck % 4 + 4)));
419 else
420 value = ((0 << buck % 4) | (1 << (buck % 4 + 4)));
421
422 ret = pmic_reg_write(pmic, en_reg, value);
423 break;
424 case RK805_ID:
425 case RK816_ID:
426 if (buck >= 4) {
427 buck -= 4;
428 en_reg = RK816_REG_DCDC_EN2;
429 } else {
430 en_reg = RK816_REG_DCDC_EN1;
431 }
432 if (enable)
433 value = ((1 << buck) | (1 << (buck + 4)));
434 else
435 value = ((0 << buck) | (1 << (buck + 4)));
436 ret = pmic_reg_write(pmic, en_reg, value);
437 break;
438
439 case RK808_ID:
440 case RK818_ID:
441 mask = 1 << buck;
442 if (enable) {
443 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX,
444 0, 3 << (buck * 2));
445 if (ret)
446 return ret;
447 }
448 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask,
449 enable ? mask : 0);
450 break;
451 case RK809_ID:
452 case RK817_ID:
453 if (buck < 4) {
454 if (enable)
455 value = ((1 << buck) | (1 << (buck + 4)));
456 else
457 value = ((0 << buck) | (1 << (buck + 4)));
458 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value);
459 /* BUCK5 for RK809 */
460 } else {
461 if (enable)
462 value = ((1 << 1) | (1 << 5));
463 else
464 value = ((0 << 1) | (1 << 5));
465 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value);
466 }
467 break;
468 default:
469 ret = -EINVAL;
470 }
471
472 return ret;
473 }
474
475 #ifdef ENABLE_DRIVER
_buck_set_suspend_value(struct udevice * pmic,int buck,int uvolt)476 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
477 {
478 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
479 int mask = info->vsel_mask;
480 int val;
481
482 if (info->vsel_sleep_reg == NA)
483 return -ENOSYS;
484
485 if (info->step_uv == 0)
486 val = info->min_sel;
487 else
488 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
489
490 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
491 __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
492
493 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
494 }
495
_buck_get_enable(struct udevice * pmic,int buck)496 static int _buck_get_enable(struct udevice *pmic, int buck)
497 {
498 struct rk8xx_priv *priv = dev_get_priv(pmic);
499 uint mask = 0;
500 int ret = 0;
501
502 switch (priv->variant) {
503 case RK806_ID:
504 mask = 1 << buck % 4;
505 ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4));
506 break;
507 case RK805_ID:
508 case RK816_ID:
509 if (buck >= 4) {
510 mask = 1 << (buck - 4);
511 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2);
512 } else {
513 mask = 1 << buck;
514 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1);
515 }
516 break;
517 case RK808_ID:
518 case RK818_ID:
519 mask = 1 << buck;
520 ret = pmic_reg_read(pmic, REG_DCDC_EN);
521 if (ret < 0)
522 return ret;
523 break;
524 case RK809_ID:
525 case RK817_ID:
526 if (buck < 4) {
527 mask = 1 << buck;
528 ret = pmic_reg_read(pmic, RK817_POWER_EN(0));
529 /* BUCK5 for RK809 */
530 } else {
531 mask = 1 << 1;
532 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
533 }
534 break;
535 }
536
537 if (ret < 0)
538 return ret;
539
540 return ret & mask ? true : false;
541 }
542
_buck_set_ramp_delay(struct udevice * pmic,int buck,u32 ramp_delay)543 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay)
544 {
545 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0);
546 struct rk8xx_priv *priv = dev_get_priv(pmic);
547 u32 ramp_value, ramp_mask;
548 int reg_value, ramp_reg1, ramp_reg2;
549
550 if (info->config_reg == NA)
551 return -ENOSYS;
552
553 switch (priv->variant) {
554 case RK805_ID:
555 ramp_mask = RK805_RAMP_RATE_MASK;
556 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
557 switch (ramp_delay) {
558 case 0 ... 3000:
559 ramp_value = RK805_RAMP_RATE_3MV_PER_US;
560 break;
561 case 3001 ... 6000:
562 ramp_value = RK805_RAMP_RATE_6MV_PER_US;
563 break;
564 case 6001 ... 12500:
565 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
566 break;
567 case 12501 ... 25000:
568 ramp_value = RK805_RAMP_RATE_25MV_PER_US;
569 break;
570 default:
571 printf("buck%d ramp_delay: %d not supported\n",
572 buck, ramp_delay);
573 }
574 break;
575 case RK806_ID:
576 switch (ramp_delay) {
577 case 1 ... 390:
578 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
579 break;
580 case 391 ... 961:
581 ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK;
582 break;
583 case 962 ... 1560:
584 ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK;
585 break;
586 case 1561 ... 3125:
587 ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK;
588 break;
589 case 3126 ... 6250:
590 ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK;
591 break;
592 case 6251 ... 12500:
593 ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK;
594 break;
595 case 12501 ... 25000:
596 ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
597 break;
598 case 25001 ... 50000: /* 50mV/us */
599 ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK;
600 break;
601 default:
602 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
603 printf("buck%d ramp_delay: %d not supported\n",
604 buck, ramp_delay);
605 return -EINVAL;
606 }
607 ramp_reg1 = RK806_RAMP_RATE_REG1(buck);
608 if (buck < 8)
609 ramp_reg2 = RK806_RAMP_RATE_REG1_8;
610 else
611 ramp_reg2 = RK806_RAMP_RATE_REG9_10;
612
613 reg_value = pmic_reg_read(pmic, ramp_reg1);
614 if (reg_value < 0) {
615 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg1, reg_value);
616 return reg_value;
617 }
618 reg_value &= 0x3f;
619
620 pmic_reg_write(pmic,
621 ramp_reg1,
622 reg_value | (ramp_value & 0x03) << 0x06);
623
624 reg_value = pmic_reg_read(pmic, ramp_reg2);
625 if (reg_value < 0) {
626 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg2, reg_value);
627 return reg_value;
628 }
629
630 return pmic_reg_write(pmic,
631 ramp_reg2,
632 reg_value | (ramp_value & 0x04) << (buck % 8));
633 case RK808_ID:
634 case RK816_ID:
635 case RK818_ID:
636 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
637 ramp_mask = RK808_RAMP_RATE_MASK;
638 switch (ramp_delay) {
639 case 1 ... 2000:
640 ramp_value = RK808_RAMP_RATE_2MV_PER_US;
641 break;
642 case 2001 ... 4000:
643 ramp_value = RK808_RAMP_RATE_4MV_PER_US;
644 break;
645 case 4001 ... 6000:
646 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
647 break;
648 case 6001 ... 10000:
649 ramp_value = RK808_RAMP_RATE_6MV_PER_US;
650 break;
651 default:
652 printf("buck%d ramp_delay: %d not supported\n",
653 buck, ramp_delay);
654 }
655 break;
656 case RK809_ID:
657 case RK817_ID:
658 ramp_mask = RK817_RAMP_RATE_MASK;
659 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
660 switch (ramp_delay) {
661 case 0 ... 3000:
662 ramp_value = RK817_RAMP_RATE_3MV_PER_US;
663 break;
664 case 3001 ... 6300:
665 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US;
666 break;
667 case 6301 ... 12500:
668 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
669 break;
670 case 12501 ... 25000:
671 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
672 break;
673 default:
674 printf("buck%d ramp_delay: %d not supported\n",
675 buck, ramp_delay);
676 }
677 break;
678 default:
679 return -EINVAL;
680 }
681
682 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value);
683 }
684
_buck_set_suspend_enable(struct udevice * pmic,int buck,bool enable)685 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
686 {
687 uint mask;
688 int ret;
689 struct rk8xx_priv *priv = dev_get_priv(pmic);
690
691 switch (priv->variant) {
692 case RK805_ID:
693 case RK816_ID:
694 mask = 1 << buck;
695 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask,
696 enable ? mask : 0);
697 break;
698 case RK806_ID:
699 if (buck <= 7) {
700 mask = 1 << buck;
701 ret = pmic_clrsetbits(pmic, RK806_BUCK_SUSPEND_EN, mask,
702 enable ? mask : 0);
703 } else {
704 if (buck == 8)
705 mask = 0x40;
706 else
707 mask = 0x80;
708 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
709 enable ? mask : 0);
710 }
711 break;
712 case RK808_ID:
713 case RK818_ID:
714 mask = 1 << buck;
715 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask,
716 enable ? 0 : mask);
717 break;
718 case RK809_ID:
719 case RK817_ID:
720 if (buck < 4)
721 mask = 1 << buck;
722 else
723 mask = 1 << 5; /* BUCK5 for RK809 */
724 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
725 enable ? mask : 0);
726 break;
727 default:
728 ret = -EINVAL;
729 }
730
731 return ret;
732 }
733
_buck_get_suspend_enable(struct udevice * pmic,int buck)734 static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
735 {
736 struct rk8xx_priv *priv = dev_get_priv(pmic);
737 int ret, val;
738 uint mask;
739
740 switch (priv->variant) {
741 case RK805_ID:
742 case RK816_ID:
743 mask = 1 << buck;
744 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
745 if (val < 0)
746 return val;
747 ret = val & mask ? 1 : 0;
748 break;
749 case RK806_ID:
750 if (buck <= 7) {
751 mask = 1 << buck % 7;
752 val = pmic_reg_read(pmic, RK806_BUCK_SUSPEND_EN);
753 } else {
754 mask = 1 << ((buck - 7) + 6);
755 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
756 }
757
758 if (val < 0)
759 return val;
760 ret = val & mask ? 1 : 0;
761 break;
762 case RK808_ID:
763 case RK818_ID:
764 mask = 1 << buck;
765 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
766 if (val < 0)
767 return val;
768 ret = val & mask ? 0 : 1;
769 break;
770 case RK809_ID:
771 case RK817_ID:
772 if (buck < 4)
773 mask = 1 << buck;
774 else
775 mask = 1 << 5; /* BUCK5 for RK809 */
776
777 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
778 if (val < 0)
779 return val;
780 ret = val & mask ? 1 : 0;
781 break;
782 default:
783 ret = -EINVAL;
784 }
785
786 return ret;
787 }
788
get_ldo_reg(struct udevice * pmic,int num,int uvolt)789 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
790 int num, int uvolt)
791 {
792 struct rk8xx_priv *priv = dev_get_priv(pmic);
793
794 switch (priv->variant) {
795 case RK805_ID:
796 case RK816_ID:
797 return &rk816_ldo[num];
798 case RK806_ID:
799 if (uvolt < 3400000)
800 return &rk806_nldo[num * 2];
801 else
802 return &rk806_nldo[num * 2 + 1];
803 case RK809_ID:
804 case RK817_ID:
805 if (uvolt < 3400000)
806 return &rk817_ldo[num * 2 + 0];
807 else
808 return &rk817_ldo[num * 2 + 1];
809 case RK818_ID:
810 return &rk818_ldo[num];
811 default:
812 return &rk808_ldo[num];
813 }
814 }
815
_ldo_get_enable(struct udevice * pmic,int ldo)816 static int _ldo_get_enable(struct udevice *pmic, int ldo)
817 {
818 struct rk8xx_priv *priv = dev_get_priv(pmic);
819 uint mask = 0;
820 int ret = 0;
821
822 switch (priv->variant) {
823 case RK805_ID:
824 case RK816_ID:
825 if (ldo >= 4) {
826 mask = 1 << (ldo - 4);
827 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2);
828 } else {
829 mask = 1 << ldo;
830 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1);
831 }
832 break;
833 case RK806_ID:
834 if (ldo < 4) {
835 mask = 1 << ldo % 4;
836 ret = pmic_reg_read(pmic, RK806_NLDO_EN(ldo / 4));
837 } else {
838 mask = 1 << 2;
839 ret = pmic_reg_read(pmic, RK806_NLDO_EN(2));
840 }
841 break;
842 case RK808_ID:
843 case RK818_ID:
844 mask = 1 << ldo;
845 ret = pmic_reg_read(pmic, REG_LDO_EN);
846 if (ret < 0)
847 return ret;
848 break;
849 case RK809_ID:
850 case RK817_ID:
851 if (ldo < 4) {
852 mask = 1 << ldo;
853 ret = pmic_reg_read(pmic, RK817_POWER_EN(1));
854 } else if (ldo < 8) {
855 mask = 1 << (ldo - 4);
856 ret = pmic_reg_read(pmic, RK817_POWER_EN(2));
857 } else if (ldo == 8) {
858 mask = 1 << 0;
859 ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
860 } else {
861 return false;
862 }
863 break;
864 }
865
866 if (ret < 0)
867 return ret;
868
869 return ret & mask ? true : false;
870 }
871
_ldo_set_enable(struct udevice * pmic,int ldo,bool enable)872 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
873 {
874 struct rk8xx_priv *priv = dev_get_priv(pmic);
875 uint mask, value, en_reg;
876 int ret = 0;
877
878 switch (priv->variant) {
879 case RK805_ID:
880 case RK816_ID:
881 if (ldo >= 4) {
882 ldo -= 4;
883 en_reg = RK816_REG_LDO_EN2;
884 } else {
885 en_reg = RK816_REG_LDO_EN1;
886 }
887 if (enable)
888 value = ((1 << ldo) | (1 << (ldo + 4)));
889 else
890 value = ((0 << ldo) | (1 << (ldo + 4)));
891
892 ret = pmic_reg_write(pmic, en_reg, value);
893 break;
894 case RK806_ID:
895 if (ldo < 4) {
896 en_reg = RK806_NLDO_EN(0);
897 if (enable)
898 value = ((1 << ldo % 4) | (1 << (ldo % 4 + 4)));
899 else
900 value = ((0 << ldo % 4) | (1 << (ldo % 4 + 4)));
901 ret = pmic_reg_write(pmic, en_reg, value);
902 } else {
903 en_reg = RK806_NLDO_EN(2);
904 if (enable)
905 value = 0x44;
906 else
907 value = 0x40;
908 ret = pmic_reg_write(pmic, en_reg, value);
909 }
910 break;
911 case RK808_ID:
912 case RK818_ID:
913 mask = 1 << ldo;
914 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask,
915 enable ? mask : 0);
916 break;
917 case RK809_ID:
918 case RK817_ID:
919 if (ldo < 4) {
920 en_reg = RK817_POWER_EN(1);
921 } else if (ldo < 8) {
922 ldo -= 4;
923 en_reg = RK817_POWER_EN(2);
924 } else if (ldo == 8) {
925 ldo = 0; /* BIT 0 */
926 en_reg = RK817_POWER_EN(3);
927 } else {
928 return -EINVAL;
929 }
930 if (enable)
931 value = ((1 << ldo) | (1 << (ldo + 4)));
932 else
933 value = ((0 << ldo) | (1 << (ldo + 4)));
934 ret = pmic_reg_write(pmic, en_reg, value);
935 break;
936 }
937
938 if (enable)
939 udelay(500);
940
941 return ret;
942 }
943
_ldo_set_suspend_enable(struct udevice * pmic,int ldo,bool enable)944 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
945 {
946 struct rk8xx_priv *priv = dev_get_priv(pmic);
947 uint mask;
948 int ret = 0;
949
950 switch (priv->variant) {
951 case RK805_ID:
952 case RK816_ID:
953 mask = 1 << ldo;
954 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask,
955 enable ? mask : 0);
956 break;
957 case RK806_ID:
958 mask = 1 << ldo;
959 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask,
960 enable ? mask : 0);
961 break;
962 case RK808_ID:
963 case RK818_ID:
964 mask = 1 << ldo;
965 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask,
966 enable ? 0 : mask);
967 break;
968 case RK809_ID:
969 case RK817_ID:
970 if (ldo == 8) {
971 mask = 1 << 4; /* LDO9 */
972 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
973 enable ? mask : 0);
974 } else {
975 mask = 1 << ldo;
976 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask,
977 enable ? mask : 0);
978 }
979 break;
980 }
981
982 return ret;
983 }
984
_ldo_get_suspend_enable(struct udevice * pmic,int ldo)985 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
986 {
987 struct rk8xx_priv *priv = dev_get_priv(pmic);
988 int val, ret = 0;
989 uint mask;
990
991 switch (priv->variant) {
992 case RK805_ID:
993 case RK816_ID:
994 mask = 1 << ldo;
995 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
996 if (val < 0)
997 return val;
998 ret = val & mask ? 1 : 0;
999 break;
1000 case RK806_ID:
1001 mask = 1 << ldo;
1002 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN);
1003
1004 if (val < 0)
1005 return val;
1006 ret = val & mask ? 1 : 0;
1007 break;
1008 case RK808_ID:
1009 case RK818_ID:
1010 mask = 1 << ldo;
1011 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
1012 if (val < 0)
1013 return val;
1014 ret = val & mask ? 0 : 1;
1015 break;
1016 case RK809_ID:
1017 case RK817_ID:
1018 if (ldo == 8) {
1019 mask = 1 << 4; /* LDO9 */
1020 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
1021 if (val < 0)
1022 return val;
1023 ret = val & mask ? 1 : 0;
1024 } else {
1025 mask = 1 << ldo;
1026 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
1027 if (val < 0)
1028 return val;
1029 ret = val & mask ? 1 : 0;
1030 }
1031 break;
1032 }
1033
1034 return ret;
1035 }
1036
buck_get_value(struct udevice * dev)1037 static int buck_get_value(struct udevice *dev)
1038 {
1039 int buck = dev->driver_data - 1;
1040 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
1041 int mask = info->vsel_mask;
1042 int i, ret, val;
1043
1044 if (info->vsel_reg == NA)
1045 return -ENOSYS;
1046
1047 ret = pmic_reg_read(dev->parent, info->vsel_reg);
1048 if (ret < 0)
1049 return ret;
1050
1051 val = ret & mask;
1052 if (val >= info->min_sel && val <= info->max_sel)
1053 goto finish;
1054
1055 /* unlucky to try */
1056 for (i = 1; i < info->range_num; i++) {
1057 info++;
1058 if (val <= info->max_sel && val >= info->min_sel)
1059 break;
1060 }
1061
1062 finish:
1063 return info->min_uv + (val - info->min_sel) * info->step_uv;
1064 }
1065
buck_set_value(struct udevice * dev,int uvolt)1066 static int buck_set_value(struct udevice *dev, int uvolt)
1067 {
1068 int buck = dev->driver_data - 1;
1069
1070 return _buck_set_value(dev->parent, buck, uvolt);
1071 }
1072
buck_get_suspend_value(struct udevice * dev)1073 static int buck_get_suspend_value(struct udevice *dev)
1074 {
1075 int buck = dev->driver_data - 1;
1076 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
1077 int mask = info->vsel_mask;
1078 int i, ret, val;
1079
1080 if (info->vsel_sleep_reg == NA)
1081 return -ENOSYS;
1082
1083 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
1084 if (ret < 0)
1085 return ret;
1086
1087 val = ret & mask;
1088 if (val <= info->max_sel && val >= info->min_sel)
1089 goto finish;
1090
1091 /* unlucky to try */
1092 for (i = 1; i < info->range_num; i++) {
1093 info++;
1094 if (val <= info->max_sel && val >= info->min_sel)
1095 break;
1096 }
1097
1098 finish:
1099 return info->min_uv + (val - info->min_sel) * info->step_uv;
1100 }
1101
buck_set_suspend_value(struct udevice * dev,int uvolt)1102 static int buck_set_suspend_value(struct udevice *dev, int uvolt)
1103 {
1104 int buck = dev->driver_data - 1;
1105
1106 return _buck_set_suspend_value(dev->parent, buck, uvolt);
1107 }
1108
buck_set_enable(struct udevice * dev,bool enable)1109 static int buck_set_enable(struct udevice *dev, bool enable)
1110 {
1111 int buck = dev->driver_data - 1;
1112
1113 return _buck_set_enable(dev->parent, buck, enable);
1114 }
1115
buck_set_suspend_enable(struct udevice * dev,bool enable)1116 static int buck_set_suspend_enable(struct udevice *dev, bool enable)
1117 {
1118 int buck = dev->driver_data - 1;
1119
1120 return _buck_set_suspend_enable(dev->parent, buck, enable);
1121 }
1122
buck_get_suspend_enable(struct udevice * dev)1123 static int buck_get_suspend_enable(struct udevice *dev)
1124 {
1125 int buck = dev->driver_data - 1;
1126
1127 return _buck_get_suspend_enable(dev->parent, buck);
1128 }
1129
buck_set_ramp_delay(struct udevice * dev,u32 ramp_delay)1130 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay)
1131 {
1132 int buck = dev->driver_data - 1;
1133
1134 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay);
1135 }
1136
buck_get_enable(struct udevice * dev)1137 static int buck_get_enable(struct udevice *dev)
1138 {
1139 int buck = dev->driver_data - 1;
1140
1141 return _buck_get_enable(dev->parent, buck);
1142 }
1143
ldo_get_value(struct udevice * dev)1144 static int ldo_get_value(struct udevice *dev)
1145 {
1146 int ldo = dev->driver_data - 1;
1147 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
1148 int mask = info->vsel_mask;
1149 int ret, val;
1150
1151 if (info->vsel_reg == NA)
1152 return -ENOSYS;
1153 ret = pmic_reg_read(dev->parent, info->vsel_reg);
1154 if (ret < 0)
1155 return ret;
1156 val = ret & mask;
1157
1158 return info->min_uv + val * info->step_uv;
1159 }
1160
ldo_set_value(struct udevice * dev,int uvolt)1161 static int ldo_set_value(struct udevice *dev, int uvolt)
1162 {
1163 int ldo = dev->driver_data - 1;
1164 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
1165 int mask = info->vsel_mask;
1166 int val;
1167
1168 if (info->vsel_reg == NA)
1169 return -ENOSYS;
1170
1171 if (info->step_uv == 0)
1172 val = info->min_sel;
1173 else
1174 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1175
1176 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
1177 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
1178
1179 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
1180 }
1181
ldo_set_suspend_value(struct udevice * dev,int uvolt)1182 static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
1183 {
1184 int ldo = dev->driver_data - 1;
1185 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
1186 int mask = info->vsel_mask;
1187 int val;
1188
1189 if (info->vsel_sleep_reg == NA)
1190 return -ENOSYS;
1191
1192 if (info->step_uv == 0)
1193 val = info->min_sel;
1194 else
1195 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1196
1197 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
1198 __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
1199
1200 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
1201 }
1202
ldo_get_suspend_value(struct udevice * dev)1203 static int ldo_get_suspend_value(struct udevice *dev)
1204 {
1205 int ldo = dev->driver_data - 1;
1206 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
1207 int mask = info->vsel_mask;
1208 int val, ret;
1209
1210 if (info->vsel_sleep_reg == NA)
1211 return -ENOSYS;
1212
1213 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
1214 if (ret < 0)
1215 return ret;
1216
1217 val = ret & mask;
1218
1219 return info->min_uv + val * info->step_uv;
1220 }
1221
ldo_set_enable(struct udevice * dev,bool enable)1222 static int ldo_set_enable(struct udevice *dev, bool enable)
1223 {
1224 int ldo = dev->driver_data - 1;
1225
1226 return _ldo_set_enable(dev->parent, ldo, enable);
1227 }
1228
ldo_set_suspend_enable(struct udevice * dev,bool enable)1229 static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
1230 {
1231 int ldo = dev->driver_data - 1;
1232
1233 return _ldo_set_suspend_enable(dev->parent, ldo, enable);
1234 }
1235
ldo_get_suspend_enable(struct udevice * dev)1236 static int ldo_get_suspend_enable(struct udevice *dev)
1237 {
1238 int ldo = dev->driver_data - 1;
1239
1240 return _ldo_get_suspend_enable(dev->parent, ldo);
1241 }
1242
ldo_get_enable(struct udevice * dev)1243 static int ldo_get_enable(struct udevice *dev)
1244 {
1245 int ldo = dev->driver_data - 1;
1246
1247 return _ldo_get_enable(dev->parent, ldo);
1248 }
1249
switch_set_enable(struct udevice * dev,bool enable)1250 static int switch_set_enable(struct udevice *dev, bool enable)
1251 {
1252 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1253 const char *supply_name = { "vcc9-supply"};
1254 int ret = 0, sw = dev->driver_data - 1;
1255 struct udevice *supply;
1256 uint mask = 0;
1257
1258 switch (priv->variant) {
1259 case RK808_ID:
1260 mask = 1 << (sw + 5);
1261 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
1262 enable ? mask : 0);
1263 break;
1264 case RK817_ID:
1265 sw = 0;
1266 mask = (1 << (sw + 2)) | (1 << (sw + 6));
1267 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
1268 enable ? mask : (1 << (sw + 6)));
1269 if (enable)
1270 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1271 dev_get_parent(dev),
1272 supply_name,
1273 &supply))
1274 ret = regulator_set_enable(supply, enable);
1275 break;
1276 case RK809_ID:
1277 mask = (1 << (sw + 2)) | (1 << (sw + 6));
1278 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
1279 enable ? mask : (1 << (sw + 6)));
1280 break;
1281 case RK818_ID:
1282 mask = 1 << 6;
1283 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
1284 enable ? mask : 0);
1285 break;
1286 }
1287
1288 debug("%s: switch%d, enable=%d, mask=0x%x\n",
1289 __func__, sw + 1, enable, mask);
1290
1291 return ret;
1292 }
1293
switch_get_enable(struct udevice * dev)1294 static int switch_get_enable(struct udevice *dev)
1295 {
1296 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1297 const char *supply_name = { "vcc9-supply"};
1298 int ret = 0, sw = dev->driver_data - 1;
1299 struct udevice *supply;
1300 uint mask = 0;
1301
1302 switch (priv->variant) {
1303 case RK808_ID:
1304 mask = 1 << (sw + 5);
1305 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
1306 break;
1307 case RK817_ID:
1308 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1309 dev_get_parent(dev),
1310 supply_name,
1311 &supply)) {
1312 ret = regulator_get_enable(supply);
1313 if (ret) {
1314 sw = 0;
1315 mask = 1 << (sw + 2);
1316 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
1317 } else
1318 ret = 0;
1319 }
1320 break;
1321 case RK809_ID:
1322 mask = 1 << (sw + 2);
1323 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
1324 break;
1325 case RK818_ID:
1326 mask = 1 << 6;
1327 ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
1328 break;
1329 }
1330
1331 if (ret < 0)
1332 return ret;
1333
1334 return ret & mask ? true : false;
1335 }
1336
switch_set_suspend_value(struct udevice * dev,int uvolt)1337 static int switch_set_suspend_value(struct udevice *dev, int uvolt)
1338 {
1339 return 0;
1340 }
1341
switch_get_suspend_value(struct udevice * dev)1342 static int switch_get_suspend_value(struct udevice *dev)
1343 {
1344 return 0;
1345 }
1346
switch_set_suspend_enable(struct udevice * dev,bool enable)1347 static int switch_set_suspend_enable(struct udevice *dev, bool enable)
1348 {
1349 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1350 const char *supply_name = { "vcc9-supply"};
1351 int ret = 0, sw = dev->driver_data - 1;
1352 struct udevice *supply;
1353 uint mask = 0;
1354
1355 switch (priv->variant) {
1356 case RK808_ID:
1357 mask = 1 << (sw + 5);
1358 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
1359 enable ? 0 : mask);
1360 break;
1361 case RK817_ID:
1362 sw = 0;
1363 mask = 1 << (sw + 6);
1364 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
1365 enable ? mask : 0);
1366 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1367 dev_get_parent(dev),
1368 supply_name,
1369 &supply))
1370 ret = regulator_set_suspend_enable(supply, enable);
1371 break;
1372 case RK809_ID:
1373 mask = 1 << (sw + 6);
1374 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
1375 enable ? mask : 0);
1376 break;
1377 case RK818_ID:
1378 mask = 1 << 6;
1379 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
1380 enable ? 0 : mask);
1381 break;
1382 }
1383
1384 debug("%s: switch%d, enable=%d, mask=0x%x\n",
1385 __func__, sw + 1, enable, mask);
1386
1387 return ret;
1388 }
1389
switch_get_suspend_enable(struct udevice * dev)1390 static int switch_get_suspend_enable(struct udevice *dev)
1391 {
1392 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1393 const char *supply_name = { "vcc9-supply"};
1394 int val, ret = 0, sw = dev->driver_data - 1;
1395 struct udevice *supply;
1396 uint mask = 0;
1397
1398 switch (priv->variant) {
1399 case RK808_ID:
1400 mask = 1 << (sw + 5);
1401 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
1402 if (val < 0)
1403 return val;
1404 ret = val & mask ? 0 : 1;
1405 break;
1406 case RK809_ID:
1407 mask = 1 << (sw + 6);
1408 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
1409 if (val < 0)
1410 return val;
1411 ret = val & mask ? 1 : 0;
1412 break;
1413 case RK817_ID:
1414 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1415 dev_get_parent(dev),
1416 supply_name,
1417 &supply)) {
1418 ret = regulator_get_suspend_enable(supply);
1419 if (ret) {
1420 sw = 0;
1421 mask = 1 << (sw + 6);
1422 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
1423 if (val < 0)
1424 return val;
1425 ret = val & mask ? 1 : 0;
1426 }
1427 }
1428 break;
1429 case RK818_ID:
1430 mask = 1 << 6;
1431 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
1432 if (val < 0)
1433 return val;
1434 ret = val & mask ? 0 : 1;
1435 break;
1436 }
1437
1438 return ret;
1439 }
1440
1441 /*
1442 * RK8xx switch does not need to set the voltage,
1443 * but if dts set regulator-min-microvolt/regulator-max-microvolt,
1444 * will cause regulator set value fail and not to enable this switch.
1445 * So add an empty function to return success.
1446 */
switch_get_value(struct udevice * dev)1447 static int switch_get_value(struct udevice *dev)
1448 {
1449 const char *supply_name[] = { "vcc9-supply", "vcc8-supply", };
1450 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1451 struct udevice *supply;
1452 int id = dev->driver_data - 1;
1453
1454 if (!switch_get_enable(dev))
1455 return 0;
1456
1457 /* note: rk817 only contains switch0 */
1458 if ((priv->variant == RK809_ID) || (priv->variant == RK817_ID)) {
1459 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
1460 dev_get_parent(dev),
1461 supply_name[id],
1462 &supply))
1463 return regulator_get_value(supply);
1464 }
1465
1466 return 0;
1467 }
1468
switch_set_value(struct udevice * dev,int uvolt)1469 static int switch_set_value(struct udevice *dev, int uvolt)
1470 {
1471 return 0;
1472 }
1473
get_pldo_reg(struct udevice * pmic,int num,int uvolt)1474 static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic,
1475 int num, int uvolt)
1476 {
1477 struct rk8xx_priv *priv = dev_get_priv(pmic);
1478
1479 switch (priv->variant) {
1480 case RK806_ID:
1481 if (uvolt < 3400000)
1482 return &rk806_pldo[num * 2];
1483 else
1484 return &rk806_pldo[num * 2 + 1];
1485 default:
1486 return &rk806_pldo[num * 2];
1487 }
1488 }
1489
_pldo_get_enable(struct udevice * pmic,int pldo)1490 static int _pldo_get_enable(struct udevice *pmic, int pldo)
1491 {
1492 struct rk8xx_priv *priv = dev_get_priv(pmic);
1493 uint mask = 0, en_reg;
1494 int ret = 0;
1495
1496 switch (priv->variant) {
1497 case RK806_ID:
1498 if ((pldo < 3) || (pldo == 5)) {
1499 en_reg = RK806_PLDO_EN(0);
1500 mask = RK806_PLDO0_2_SET(pldo);
1501 if (pldo == 5)
1502 mask = (1 << 0);
1503 ret = pmic_reg_read(pmic, en_reg);
1504 } else if ((pldo == 3) || (pldo == 4)) {
1505 en_reg = RK806_PLDO_EN(1);
1506 if (pldo == 3)
1507 mask = (1 << 0);
1508 else
1509 mask = (1 << 1);
1510 ret = pmic_reg_read(pmic, en_reg);
1511 }
1512 break;
1513
1514 default:
1515 return -EINVAL;
1516 }
1517
1518 if (ret < 0)
1519 return ret;
1520
1521 return ret & mask ? true : false;
1522 }
1523
_pldo_set_enable(struct udevice * pmic,int pldo,bool enable)1524 static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable)
1525 {
1526 struct rk8xx_priv *priv = dev_get_priv(pmic);
1527 uint value, en_reg;
1528 int ret = 0;
1529
1530 switch (priv->variant) {
1531 case RK806_ID:
1532 if (pldo < 3) {
1533 en_reg = RK806_PLDO_EN(0);
1534 if (enable)
1535 value = RK806_PLDO0_2_SET(pldo);
1536 else
1537 value = RK806_PLDO0_2_CLR(pldo);
1538 ret = pmic_reg_write(pmic, en_reg, value);
1539 } else if (pldo == 3) {
1540 en_reg = RK806_PLDO_EN(1);
1541 if (enable)
1542 value = ((1 << 0) | (1 << 4));
1543 else
1544 value = (1 << 4);
1545 ret = pmic_reg_write(pmic, en_reg, value);
1546 } else if (pldo == 4) {
1547 en_reg = RK806_PLDO_EN(1);
1548 if (enable)
1549 value = ((1 << 1) | (1 << 5));
1550 else
1551 value = ((0 << 1) | (1 << 5));
1552 ret = pmic_reg_write(pmic, en_reg, value);
1553 } else if (pldo == 5) {
1554 en_reg = RK806_PLDO_EN(0);
1555 if (enable)
1556 value = ((1 << 0) | (1 << 4));
1557 else
1558 value = ((0 << 0) | (1 << 4));
1559 ret = pmic_reg_write(pmic, en_reg, value);
1560 }
1561
1562 break;
1563 default:
1564 return -EINVAL;
1565 }
1566
1567 return ret;
1568 }
1569
pldo_get_value(struct udevice * dev)1570 static int pldo_get_value(struct udevice *dev)
1571 {
1572 int ldo = dev->driver_data - 1;
1573 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
1574 int mask = info->vsel_mask;
1575 int ret, val;
1576
1577 if (info->vsel_reg == NA)
1578 return -EINVAL;
1579
1580 ret = pmic_reg_read(dev->parent, info->vsel_reg);
1581 if (ret < 0)
1582 return ret;
1583 val = ret & mask;
1584
1585 return info->min_uv + val * info->step_uv;
1586 }
1587
pldo_set_value(struct udevice * dev,int uvolt)1588 static int pldo_set_value(struct udevice *dev, int uvolt)
1589 {
1590 int ldo = dev->driver_data - 1;
1591 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);
1592 int mask = info->vsel_mask;
1593 int val;
1594
1595 if (info->vsel_reg == NA)
1596 return -EINVAL;
1597
1598 if (info->step_uv == 0)
1599 val = info->min_sel;
1600 else
1601 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1602
1603 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
1604 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
1605
1606 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
1607 }
1608
pldo_set_enable(struct udevice * dev,bool enable)1609 static int pldo_set_enable(struct udevice *dev, bool enable)
1610 {
1611 int ldo = dev->driver_data - 1;
1612
1613 return _pldo_set_enable(dev->parent, ldo, enable);
1614 }
1615
pldo_get_enable(struct udevice * dev)1616 static int pldo_get_enable(struct udevice *dev)
1617 {
1618 int ldo = dev->driver_data - 1;
1619
1620 return _pldo_get_enable(dev->parent, ldo);
1621 }
1622
pldo_set_suspend_value(struct udevice * dev,int uvolt)1623 static int pldo_set_suspend_value(struct udevice *dev, int uvolt)
1624 {
1625 int ldo = dev->driver_data - 1;
1626 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);;
1627 int mask = info->vsel_mask;
1628 int val;
1629
1630 if (info->vsel_sleep_reg == NA)
1631 return -EINVAL;
1632
1633 if (info->step_uv == 0)
1634 val = info->min_sel;
1635 else
1636 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1637
1638 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
1639 }
1640
pldo_get_suspend_value(struct udevice * dev)1641 static int pldo_get_suspend_value(struct udevice *dev)
1642 {
1643 int ldo = dev->driver_data - 1;
1644 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0);
1645 int mask = info->vsel_mask;
1646 int val, ret;
1647
1648 if (info->vsel_sleep_reg == NA)
1649 return -EINVAL;
1650
1651 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
1652 if (ret < 0)
1653 return ret;
1654
1655 val = ret & mask;
1656
1657 return info->min_uv + val * info->step_uv;
1658 }
1659
_pldo_set_suspend_enable(struct udevice * pmic,int ldo,bool enable)1660 static int _pldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
1661 {
1662 uint mask;
1663 int ret;
1664
1665 if (ldo < 5)
1666 mask = 1 << (ldo + 1);
1667 else
1668 mask = 1;
1669 ret = pmic_clrsetbits(pmic, RK806_PLDO_SUSPEND_EN, mask,
1670 enable ? mask : 0);
1671
1672 return ret;
1673 }
1674
_pldo_get_suspend_enable(struct udevice * pmic,int ldo)1675 static int _pldo_get_suspend_enable(struct udevice *pmic, int ldo)
1676 {
1677 uint mask, val;
1678 int ret;
1679
1680 if (ldo < 5)
1681 mask = 1 << (ldo + 1);
1682 else
1683 mask = 1;
1684 val = pmic_reg_read(pmic, RK806_PLDO_SUSPEND_EN);
1685
1686 if (val < 0)
1687 return val;
1688 ret = val & mask ? 1 : 0;
1689
1690 return ret;
1691 }
pldo_set_suspend_enable(struct udevice * dev,bool enable)1692 static int pldo_set_suspend_enable(struct udevice *dev, bool enable)
1693 {
1694 int ldo = dev->driver_data - 1;
1695
1696 return _pldo_set_suspend_enable(dev->parent, ldo, enable);
1697 }
1698
pldo_get_suspend_enable(struct udevice * dev)1699 static int pldo_get_suspend_enable(struct udevice *dev)
1700 {
1701 int ldo = dev->driver_data - 1;
1702
1703 return _pldo_get_suspend_enable(dev->parent, ldo);
1704 }
1705
get_boost_reg(struct udevice * pmic,int num,int uvolt)1706 static const struct rk8xx_reg_info *get_boost_reg(struct udevice *pmic,
1707 int num,
1708 int uvolt)
1709 {
1710 struct rk8xx_priv *priv = dev_get_priv(pmic);
1711
1712 switch (priv->variant) {
1713 case RK817_ID:
1714 return &rk817_boost[0];
1715 }
1716
1717 return NULL;
1718 }
1719
boost_set_enable(struct udevice * dev,bool enable)1720 static int boost_set_enable(struct udevice *dev, bool enable)
1721 {
1722 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1723 uint mask = 0;
1724 int ret = 0;
1725
1726 switch (priv->variant) {
1727 case RK817_ID:
1728 mask = 0x22;
1729 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
1730 enable ? 0x22 : 0x20);
1731 break;
1732 }
1733
1734 debug("%s: boost enable=%d, mask=0x%x\n",
1735 __func__, enable, mask);
1736
1737 return ret;
1738 }
1739
boost_get_enable(struct udevice * dev)1740 static int boost_get_enable(struct udevice *dev)
1741 {
1742 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1743 uint mask = 0;
1744 int ret = 0;
1745
1746 switch (priv->variant) {
1747 case RK817_ID:
1748 mask = 0x02;
1749 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
1750 break;
1751 }
1752
1753 if (ret < 0)
1754 return ret;
1755
1756 return ret & mask ? true : false;
1757 }
1758
boost_set_suspend_value(struct udevice * dev,int uvolt)1759 static int boost_set_suspend_value(struct udevice *dev, int uvolt)
1760 {
1761 int boost = dev->driver_data - 1;
1762 const struct rk8xx_reg_info *info = get_boost_reg(dev->parent, boost, 0);
1763 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1764 int mask = info->vsel_mask;
1765 int val;
1766
1767 switch (priv->variant) {
1768 case RK817_ID:
1769 if (!info)
1770 return -ENOSYS;
1771 if (info->vsel_sleep_reg == NA)
1772 return -ENOSYS;
1773
1774 if (info->step_uv == 0)
1775 val = info->min_sel;
1776 else
1777 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1778
1779 debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
1780 __func__, uvolt, info->vsel_sleep_reg, mask, val);
1781
1782 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
1783 }
1784 return 0;
1785 }
1786
boost_get_suspend_value(struct udevice * dev)1787 static int boost_get_suspend_value(struct udevice *dev)
1788 {
1789 int boost = dev->driver_data - 1;
1790 const struct rk8xx_reg_info *info = get_boost_reg(dev->parent, boost, 0);
1791 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1792 int mask = info->vsel_mask;
1793 int ret, val;
1794
1795 switch (priv->variant) {
1796 case RK817_ID:
1797 if (info->vsel_reg == NA)
1798 return -ENOSYS;
1799 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
1800 if (ret < 0)
1801 return ret;
1802 val = ret & mask;
1803
1804 return info->min_uv + val * info->step_uv;
1805 }
1806 return 0;
1807 }
1808
boost_set_suspend_enable(struct udevice * dev,bool enable)1809 static int boost_set_suspend_enable(struct udevice *dev, bool enable)
1810 {
1811 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1812 uint mask = 0;
1813 int ret = 0;
1814
1815 switch (priv->variant) {
1816 case RK817_ID:
1817 mask = 1 << 5;
1818 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
1819 enable ? mask : 0);
1820 break;
1821 }
1822
1823 debug("%s: boost enable=%d, mask=0x%x\n",
1824 __func__, enable, mask);
1825
1826 return ret;
1827 }
1828
boost_get_suspend_enable(struct udevice * dev)1829 static int boost_get_suspend_enable(struct udevice *dev)
1830 {
1831 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1832 int val, ret = 0;
1833 uint mask = 0;
1834
1835 switch (priv->variant) {
1836 case RK817_ID:
1837 mask = 1 << 5;
1838 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
1839 if (val < 0)
1840 return val;
1841 ret = val & mask ? 1 : 0;
1842 break;
1843 }
1844
1845 return ret;
1846 }
1847
boost_get_value(struct udevice * dev)1848 static int boost_get_value(struct udevice *dev)
1849 {
1850 int boost = dev->driver_data - 1;
1851 const struct rk8xx_reg_info *info = get_boost_reg(dev->parent, boost, 0);
1852 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1853 int mask = info->vsel_mask;
1854 int ret, val;
1855
1856 switch (priv->variant) {
1857 case RK817_ID:
1858 if (info->vsel_reg == NA)
1859 return -ENOSYS;
1860 ret = pmic_reg_read(dev->parent, info->vsel_reg);
1861 if (ret < 0)
1862 return ret;
1863 val = ret & mask;
1864
1865 return info->min_uv + val * info->step_uv;
1866 }
1867
1868 return 0;
1869 }
1870
boost_set_value(struct udevice * dev,int uvolt)1871 static int boost_set_value(struct udevice *dev, int uvolt)
1872 {
1873 int boost = dev->driver_data - 1;
1874 const struct rk8xx_reg_info *info = get_boost_reg(dev->parent, boost, 0);
1875 struct rk8xx_priv *priv = dev_get_priv(dev->parent);
1876 int mask = info->vsel_mask;
1877 int val;
1878
1879 switch (priv->variant) {
1880 case RK817_ID:
1881 if (!info)
1882 return -ENOSYS;
1883
1884 if (info->vsel_reg == NA)
1885 return -ENOSYS;
1886
1887 if (info->step_uv == 0)
1888 val = info->min_sel;
1889 else
1890 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
1891
1892 debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
1893 __func__, uvolt, info->vsel_reg, mask, val);
1894
1895 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
1896 }
1897
1898 return 0;
1899 }
1900
rk8xx_buck_probe(struct udevice * dev)1901 static int rk8xx_buck_probe(struct udevice *dev)
1902 {
1903 struct dm_regulator_uclass_platdata *uc_pdata;
1904
1905 uc_pdata = dev_get_uclass_platdata(dev);
1906
1907 uc_pdata->type = REGULATOR_TYPE_BUCK;
1908 uc_pdata->mode_count = 0;
1909
1910 return 0;
1911 }
1912
rk8xx_ldo_probe(struct udevice * dev)1913 static int rk8xx_ldo_probe(struct udevice *dev)
1914 {
1915 struct dm_regulator_uclass_platdata *uc_pdata;
1916
1917 uc_pdata = dev_get_uclass_platdata(dev);
1918
1919 uc_pdata->type = REGULATOR_TYPE_LDO;
1920 uc_pdata->mode_count = 0;
1921
1922 return 0;
1923 }
1924
rk8xx_switch_probe(struct udevice * dev)1925 static int rk8xx_switch_probe(struct udevice *dev)
1926 {
1927 struct dm_regulator_uclass_platdata *uc_pdata;
1928
1929 uc_pdata = dev_get_uclass_platdata(dev);
1930
1931 uc_pdata->type = REGULATOR_TYPE_FIXED;
1932 uc_pdata->mode_count = 0;
1933
1934 return 0;
1935 }
1936
rk8xx_pldo_probe(struct udevice * dev)1937 static int rk8xx_pldo_probe(struct udevice *dev)
1938 {
1939 struct dm_regulator_uclass_platdata *uc_pdata;
1940
1941 uc_pdata = dev_get_uclass_platdata(dev);
1942 uc_pdata->type = REGULATOR_TYPE_LDO;
1943 uc_pdata->mode_count = 0;
1944
1945 return 0;
1946 }
1947
rk8xx_boost_probe(struct udevice * dev)1948 static int rk8xx_boost_probe(struct udevice *dev)
1949 {
1950 struct dm_regulator_uclass_platdata *uc_pdata;
1951
1952 uc_pdata = dev_get_uclass_platdata(dev);
1953
1954 uc_pdata->type = REGULATOR_TYPE_FIXED;
1955 uc_pdata->mode_count = 0;
1956
1957 return 0;
1958 }
1959
1960 static const struct dm_regulator_ops rk8xx_buck_ops = {
1961 .get_value = buck_get_value,
1962 .set_value = buck_set_value,
1963 .set_suspend_value = buck_set_suspend_value,
1964 .get_suspend_value = buck_get_suspend_value,
1965 .get_enable = buck_get_enable,
1966 .set_enable = buck_set_enable,
1967 .set_suspend_enable = buck_set_suspend_enable,
1968 .get_suspend_enable = buck_get_suspend_enable,
1969 .set_ramp_delay = buck_set_ramp_delay,
1970 };
1971
1972 static const struct dm_regulator_ops rk8xx_ldo_ops = {
1973 .get_value = ldo_get_value,
1974 .set_value = ldo_set_value,
1975 .set_suspend_value = ldo_set_suspend_value,
1976 .get_suspend_value = ldo_get_suspend_value,
1977 .get_enable = ldo_get_enable,
1978 .set_enable = ldo_set_enable,
1979 .set_suspend_enable = ldo_set_suspend_enable,
1980 .get_suspend_enable = ldo_get_suspend_enable,
1981 };
1982
1983 static const struct dm_regulator_ops rk8xx_switch_ops = {
1984 .get_value = switch_get_value,
1985 .set_value = switch_set_value,
1986 .get_enable = switch_get_enable,
1987 .set_enable = switch_set_enable,
1988 .set_suspend_enable = switch_set_suspend_enable,
1989 .get_suspend_enable = switch_get_suspend_enable,
1990 .set_suspend_value = switch_set_suspend_value,
1991 .get_suspend_value = switch_get_suspend_value,
1992 };
1993
1994 static const struct dm_regulator_ops rk8xx_pldo_ops = {
1995 .get_value = pldo_get_value,
1996 .set_value = pldo_set_value,
1997 .set_suspend_value = pldo_set_suspend_value,
1998 .get_suspend_value = pldo_get_suspend_value,
1999 .get_enable = pldo_get_enable,
2000 .set_enable = pldo_set_enable,
2001 .set_suspend_enable = pldo_set_suspend_enable,
2002 .get_suspend_enable = pldo_get_suspend_enable,
2003 };
2004
2005 static const struct dm_regulator_ops rk8xx_boost_ops = {
2006 .get_value = boost_get_value,
2007 .set_value = boost_set_value,
2008 .get_enable = boost_get_enable,
2009 .set_enable = boost_set_enable,
2010 .set_suspend_enable = boost_set_suspend_enable,
2011 .get_suspend_enable = boost_get_suspend_enable,
2012 .set_suspend_value = boost_set_suspend_value,
2013 .get_suspend_value = boost_get_suspend_value,
2014 };
2015
2016 U_BOOT_DRIVER(rk8xx_buck) = {
2017 .name = "rk8xx_buck",
2018 .id = UCLASS_REGULATOR,
2019 .ops = &rk8xx_buck_ops,
2020 .probe = rk8xx_buck_probe,
2021 };
2022
2023 U_BOOT_DRIVER(rk8xx_ldo) = {
2024 .name = "rk8xx_ldo",
2025 .id = UCLASS_REGULATOR,
2026 .ops = &rk8xx_ldo_ops,
2027 .probe = rk8xx_ldo_probe,
2028 };
2029
2030 U_BOOT_DRIVER(rk8xx_switch) = {
2031 .name = "rk8xx_switch",
2032 .id = UCLASS_REGULATOR,
2033 .ops = &rk8xx_switch_ops,
2034 .probe = rk8xx_switch_probe,
2035 };
2036
2037 U_BOOT_DRIVER(rk8xx_spi_pldo) = {
2038 .name = "rk8xx_pldo",
2039 .id = UCLASS_REGULATOR,
2040 .ops = &rk8xx_pldo_ops,
2041 .probe = rk8xx_pldo_probe,
2042 };
2043
2044 U_BOOT_DRIVER(rk8xx_boost) = {
2045 .name = "rk8xx_boost",
2046 .id = UCLASS_REGULATOR,
2047 .ops = &rk8xx_boost_ops,
2048 .probe = rk8xx_boost_probe,
2049 };
2050 #endif
2051
rk8xx_spl_configure_buck(struct udevice * pmic,int buck,int uvolt)2052 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
2053 {
2054 int ret;
2055
2056 ret = _buck_set_value(pmic, buck, uvolt);
2057 if (ret)
2058 return ret;
2059
2060 return _buck_set_enable(pmic, buck, true);
2061 }
2062
rk818_spl_configure_usb_input_current(struct udevice * pmic,int current_ma)2063 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
2064 {
2065 uint i;
2066
2067 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
2068 if (current_ma <= rk818_chrg_cur_input_array[i])
2069 break;
2070
2071 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
2072 }
2073
rk818_spl_configure_usb_chrg_shutdown(struct udevice * pmic,int uvolt)2074 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
2075 {
2076 uint i;
2077
2078 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
2079 if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
2080 break;
2081
2082 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
2083 i);
2084 }
2085