1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 12 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 13 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 14 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 15 16 #define ZYNQ_I2C_BASEADDR0 0xFF020000 17 #define ZYNQ_I2C_BASEADDR1 0xFF030000 18 19 #define ARASAN_NAND_BASEADDR 0xFF100000 20 21 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 22 #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 23 24 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 25 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 26 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 27 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 28 29 #define PS_MODE0 BIT(0) 30 #define PS_MODE1 BIT(1) 31 #define PS_MODE2 BIT(2) 32 #define PS_MODE3 BIT(3) 33 34 struct crlapb_regs { 35 u32 reserved0[36]; 36 u32 cpu_r5_ctrl; /* 0x90 */ 37 u32 reserved1[37]; 38 u32 timestamp_ref_ctrl; /* 0x128 */ 39 u32 reserved2[53]; 40 u32 boot_mode; /* 0x200 */ 41 u32 reserved3[14]; 42 u32 rst_lpd_top; /* 0x23C */ 43 u32 reserved4[4]; 44 u32 boot_pin_ctrl; /* 0x250 */ 45 u32 reserved5[21]; 46 }; 47 48 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 49 50 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 51 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 52 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 53 54 struct iou_scntr_secure { 55 u32 counter_control_register; 56 u32 reserved0[7]; 57 u32 base_frequency_id_register; 58 }; 59 60 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 61 62 /* Bootmode setting values */ 63 #define BOOT_MODES_MASK 0x0000000F 64 #define QSPI_MODE_24BIT 0x00000001 65 #define QSPI_MODE_32BIT 0x00000002 66 #define SD_MODE 0x00000003 /* sd 0 */ 67 #define SD_MODE1 0x00000005 /* sd 1 */ 68 #define NAND_MODE 0x00000004 69 #define EMMC_MODE 0x00000006 70 #define USB_MODE 0x00000007 71 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 72 #define JTAG_MODE 0x00000000 73 #define BOOT_MODE_USE_ALT 0x100 74 #define BOOT_MODE_ALT_SHIFT 12 75 /* SW secondary boot modes 0xa - 0xd */ 76 #define SW_USBHOST_MODE 0x0000000A 77 #define SW_SATA_MODE 0x0000000B 78 79 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 80 81 struct iou_slcr_regs { 82 u32 mio_pin[78]; 83 u32 reserved[442]; 84 }; 85 86 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 87 88 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 89 90 struct rpu_regs { 91 u32 rpu_glbl_ctrl; 92 u32 reserved0[63]; 93 u32 rpu0_cfg; /* 0x100 */ 94 u32 reserved1[63]; 95 u32 rpu1_cfg; /* 0x200 */ 96 }; 97 98 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 99 100 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 101 102 struct crfapb_regs { 103 u32 reserved0[65]; 104 u32 rst_fpd_apu; /* 0x104 */ 105 u32 reserved1; 106 }; 107 108 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 109 110 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 111 112 struct apu_regs { 113 u32 reserved0[16]; 114 u32 rvbar_addr0_l; /* 0x40 */ 115 u32 rvbar_addr0_h; /* 0x44 */ 116 u32 reserved1[20]; 117 }; 118 119 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 120 121 /* Board version value */ 122 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 123 #define ZYNQMP_CSU_VERSION_SILICON 0x0 124 #define ZYNQMP_CSU_VERSION_EP108 0x1 125 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 126 #define ZYNQMP_CSU_VERSION_QEMU 0x3 127 128 #define ZYNQMP_SILICON_VER_MASK 0xF000 129 #define ZYNQMP_SILICON_VER_SHIFT 12 130 131 struct csu_regs { 132 u32 reserved0[17]; 133 u32 version; 134 }; 135 136 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 137 138 #define ZYNQMP_PMU_BASEADDR 0xFFD80000 139 140 struct pmu_regs { 141 u32 reserved[18]; 142 u32 gen_storage6; /* 0x48 */ 143 }; 144 145 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 146 147 #define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 148 #define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 149 150 #endif /* _ASM_ARCH_HARDWARE_H */ 151