1 /* 2 * Texas Instruments System Control Interface (TISCI) Protocol 3 * 4 * Communication protocol with TI SCI hardware 5 * The system works in a message response protocol 6 * See: http://processors.wiki.ti.com/index.php/TISCI for details 7 * 8 * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ 9 * 10 * SPDX-License-Identifier: BSD-3-Clause 11 */ 12 13 #ifndef TI_SCI_PROTOCOL_H 14 #define TI_SCI_PROTOCOL_H 15 16 #include <stdint.h> 17 18 /* Generic Messages */ 19 #define TI_SCI_MSG_ENABLE_WDT 0x0000 20 #define TI_SCI_MSG_WAKE_RESET 0x0001 21 #define TI_SCI_MSG_VERSION 0x0002 22 #define TI_SCI_MSG_WAKE_REASON 0x0003 23 #define TI_SCI_MSG_GOODBYE 0x0004 24 #define TI_SCI_MSG_SYS_RESET 0x0005 25 #define TI_SCI_MSG_BOOT_NOTIFICATION 0x000A 26 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 27 28 /* Device requests */ 29 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 30 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 31 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 32 33 /* Low Power Mode Requests */ 34 #define TI_SCI_MSG_ENTER_SLEEP 0x0301 35 #define TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE 0x030d 36 #define TISCI_MSG_LPM_ENCRYPT_TFA 0x030F 37 38 /* Clock requests */ 39 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 40 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 41 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 42 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 43 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 44 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 45 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 46 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 47 48 /* Processor Control Messages */ 49 #define TISCI_MSG_PROC_REQUEST 0xc000 50 #define TISCI_MSG_PROC_RELEASE 0xc001 51 #define TISCI_MSG_PROC_HANDOVER 0xc005 52 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100 53 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101 54 #define TISCI_MSG_PROC_AUTH_BOOT_IMAGE 0xc120 55 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400 56 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401 57 58 /* Security Management Messages */ 59 #define TI_SCI_MSG_FWL_SET 0x9000 60 #define TI_SCI_MSG_FWL_GET 0x9001 61 #define TI_SCI_MSG_FWL_CHANGE_OWNER 0x9002 62 63 /** 64 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent 65 * via secure transport. 66 * @checksum: crc16 checksum for the entire message 67 * @reserved: Reserved for future use. 68 */ 69 struct ti_sci_secure_msg_hdr { 70 uint16_t checksum; 71 uint16_t reserved; 72 } __packed; 73 74 /** 75 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 76 * @type: Type of messages: One of TI_SCI_MSG* values 77 * @host: Host of the message 78 * @seq: Message identifier indicating a transfer sequence 79 * @flags: Flag for the message 80 */ 81 struct ti_sci_msg_hdr { 82 struct ti_sci_secure_msg_hdr sec_hdr; 83 uint16_t type; 84 uint8_t host; 85 uint8_t seq; 86 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 87 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 88 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 89 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 90 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 91 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 92 /* Additional Flags */ 93 uint32_t flags; 94 } __packed; 95 96 /** 97 * struct ti_sci_msg_version_req - Request for firmware version information 98 * @hdr: Generic header 99 * 100 * Request for TI_SCI_MSG_VERSION 101 */ 102 struct ti_sci_msg_req_version { 103 struct ti_sci_msg_hdr hdr; 104 } __packed; 105 106 /** 107 * struct ti_sci_msg_resp_version - Response for firmware version information 108 * @hdr: Generic header 109 * @firmware_description: String describing the firmware 110 * @firmware_revision: Firmware revision 111 * @abi_major: Major version of the ABI that firmware supports 112 * @abi_minor: Minor version of the ABI that firmware supports 113 * @sub_version: Sub-version number of the firmware 114 * @patch_version: Patch-version number of the firmware. 115 * 116 * In general, ABI version changes follow the rule that minor version increments 117 * are backward compatible. Major revision changes in ABI may not be 118 * backward compatible. 119 * 120 * Response to request TI_SCI_MSG_VERSION 121 */ 122 struct ti_sci_msg_resp_version { 123 struct ti_sci_msg_hdr hdr; 124 #define FIRMWARE_DESCRIPTION_LENGTH 32 125 char firmware_description[FIRMWARE_DESCRIPTION_LENGTH]; 126 uint16_t firmware_revision; 127 uint8_t abi_major; 128 uint8_t abi_minor; 129 uint8_t sub_version; 130 uint8_t patch_version; 131 } __packed; 132 133 /** 134 * struct ti_sci_msg_req_reboot - Reboot the SoC 135 * @hdr: Generic Header 136 * @domain: Domain to be reset, 0 for full SoC reboot 137 * 138 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 139 * ACK/NACK message. 140 */ 141 struct ti_sci_msg_req_reboot { 142 struct ti_sci_msg_hdr hdr; 143 #define TI_SCI_DOMAIN_FULL_SOC_RESET 0x0 144 uint8_t domain; 145 } __packed; 146 147 /** 148 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 149 * @hdr: Generic header 150 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 151 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 152 * MSG_FLAG_CAPS_LPM_DEEP_SLEEP: Deep Sleep LPM 153 * MSG_FLAG_CAPS_LPM_MCU_ONLY: MCU only LPM 154 * MSG_FLAG_CAPS_LPM_STANDBY: Standby LPM 155 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 156 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 157 * 158 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 159 * providing currently available SOC/firmware capabilities. SoC that don't 160 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 161 */ 162 struct ti_sci_msg_resp_query_fw_caps { 163 struct ti_sci_msg_hdr hdr; 164 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 165 #define MSG_FLAG_CAPS_LPM_DEEP_SLEEP TI_SCI_MSG_FLAG(1) 166 #define MSG_FLAG_CAPS_LPM_MCU_ONLY TI_SCI_MSG_FLAG(2) 167 #define MSG_FLAG_CAPS_LPM_STANDBY TI_SCI_MSG_FLAG(3) 168 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 169 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 170 #define MSG_FLAG_CAPS_LPM_ENCRYPT_IMAGE TI_SCI_MSG_FLAG(11) 171 #define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12) 172 uint64_t fw_caps; 173 } __packed; 174 175 /** 176 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 177 * @hdr: Generic header 178 * @id: Indicates which device to modify 179 * @reserved: Reserved space in message, must be 0 for backward compatibility 180 * @state: The desired state of the device. 181 * 182 * Certain flags can also be set to alter the device state: 183 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 184 * The meaning of this flag will vary slightly from device to device and from 185 * SoC to SoC but it generally allows the device to wake the SoC out of deep 186 * suspend states. 187 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 188 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 189 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 190 * If another host already has this device set to STATE_RETENTION or STATE_ON, 191 * the message will fail. Once successful, other hosts attempting to set 192 * STATE_RETENTION or STATE_ON will fail. 193 * 194 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 195 * ACK/NACK message. 196 */ 197 struct ti_sci_msg_req_set_device_state { 198 /* Additional hdr->flags options */ 199 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 200 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 201 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 202 struct ti_sci_msg_hdr hdr; 203 uint32_t id; 204 uint32_t reserved; 205 206 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 207 #define MSG_DEVICE_SW_STATE_RETENTION 1 208 #define MSG_DEVICE_SW_STATE_ON 2 209 uint8_t state; 210 } __packed; 211 212 /** 213 * struct ti_sci_msg_req_get_device_state - Request to get device. 214 * @hdr: Generic header 215 * @id: Device Identifier 216 * 217 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 218 * information 219 */ 220 struct ti_sci_msg_req_get_device_state { 221 struct ti_sci_msg_hdr hdr; 222 uint32_t id; 223 } __packed; 224 225 /** 226 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 227 * @hdr: Generic header 228 * @context_loss_count: Indicates how many times the device has lost context. A 229 * driver can use this monotonic counter to determine if the device has 230 * lost context since the last time this message was exchanged. 231 * @resets: Programmed state of the reset lines. 232 * @programmed_state: The state as programmed by set_device. 233 * - Uses the MSG_DEVICE_SW_* macros 234 * @current_state: The actual state of the hardware. 235 * 236 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 237 */ 238 struct ti_sci_msg_resp_get_device_state { 239 struct ti_sci_msg_hdr hdr; 240 uint32_t context_loss_count; 241 uint32_t resets; 242 uint8_t programmed_state; 243 #define MSG_DEVICE_HW_STATE_OFF 0 244 #define MSG_DEVICE_HW_STATE_ON 1 245 #define MSG_DEVICE_HW_STATE_TRANS 2 246 uint8_t current_state; 247 } __packed; 248 249 /** 250 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 251 * configuration of the device 252 * @hdr: Generic header 253 * @id: Indicates which device to modify 254 * @resets: A bit field of resets for the device. The meaning, behavior, 255 * and usage of the reset flags are device specific. 0 for a bit 256 * indicates releasing the reset represented by that bit while 1 257 * indicates keeping it held. 258 * 259 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 260 * ACK/NACK message. 261 */ 262 struct ti_sci_msg_req_set_device_resets { 263 struct ti_sci_msg_hdr hdr; 264 uint32_t id; 265 uint32_t resets; 266 } __packed; 267 268 /** 269 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 270 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 271 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 272 * via spread spectrum clocking. 273 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 274 * frequency to be changed while it is running so long as it 275 * is within the min/max limits. 276 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 277 * is only applicable to clock inputs on the SoC pseudo-device. 278 * @dev_id: Device identifier this request is for 279 * @clk_id: Clock identifier for the device for this request. 280 * Each device has it's own set of clock inputs. This indexes 281 * which clock input to modify. 282 * @request_state: Request the state for the clock to be set to. 283 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 284 * it can be disabled, regardless of the state of the device 285 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 286 * automatically manage the state of this clock. If the device 287 * is enabled, then the clock is enabled. If the device is set 288 * to off or retention, then the clock is internally set as not 289 * being required by the device.(default) 290 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 291 * regardless of the state of the device. 292 * 293 * Normally, all required clocks are managed by TISCI entity, this is used 294 * only for specific control *IF* required. Auto managed state is 295 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 296 * will explicitly control. 297 * 298 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 299 * ACK or NACK message. 300 */ 301 struct ti_sci_msg_req_set_clock_state { 302 /* Additional hdr->flags options */ 303 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 304 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 305 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 306 struct ti_sci_msg_hdr hdr; 307 uint32_t dev_id; 308 uint8_t clk_id; 309 #define MSG_CLOCK_SW_STATE_UNREQ 0 310 #define MSG_CLOCK_SW_STATE_AUTO 1 311 #define MSG_CLOCK_SW_STATE_REQ 2 312 uint8_t request_state; 313 } __packed; 314 315 /** 316 * struct ti_sci_msg_req_get_clock_state - Request for clock state 317 * @hdr: Generic Header 318 * @dev_id: Device identifier this request is for 319 * @clk_id: Clock identifier for the device for this request. 320 * Each device has it's own set of clock inputs. This indexes 321 * which clock input to get state of. 322 * 323 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 324 * of the clock 325 */ 326 struct ti_sci_msg_req_get_clock_state { 327 struct ti_sci_msg_hdr hdr; 328 uint32_t dev_id; 329 uint8_t clk_id; 330 } __packed; 331 332 /** 333 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 334 * @hdr: Generic Header 335 * @programmed_state: Any programmed state of the clock. This is one of 336 * MSG_CLOCK_SW_STATE* values. 337 * @current_state: Current state of the clock. This is one of: 338 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 339 * MSG_CLOCK_HW_STATE_READY: Clock is ready 340 * 341 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 342 */ 343 struct ti_sci_msg_resp_get_clock_state { 344 struct ti_sci_msg_hdr hdr; 345 uint8_t programmed_state; 346 #define MSG_CLOCK_HW_STATE_NOT_READY 0 347 #define MSG_CLOCK_HW_STATE_READY 1 348 uint8_t current_state; 349 } __packed; 350 351 /** 352 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 353 * @hdr: Generic Header 354 * @dev_id: Device identifier this request is for 355 * @clk_id: Clock identifier for the device for this request. 356 * Each device has it's own set of clock inputs. This indexes 357 * which clock input to modify. 358 * @parent_id: The new clock parent is selectable by an index via this 359 * parameter. 360 * 361 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 362 * ACK / NACK message. 363 */ 364 struct ti_sci_msg_req_set_clock_parent { 365 struct ti_sci_msg_hdr hdr; 366 uint32_t dev_id; 367 uint8_t clk_id; 368 uint8_t parent_id; 369 } __packed; 370 371 /** 372 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 373 * @hdr: Generic Header 374 * @dev_id: Device identifier this request is for 375 * @clk_id: Clock identifier for the device for this request. 376 * Each device has it's own set of clock inputs. This indexes 377 * which clock input to get the parent for. 378 * 379 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 380 */ 381 struct ti_sci_msg_req_get_clock_parent { 382 struct ti_sci_msg_hdr hdr; 383 uint32_t dev_id; 384 uint8_t clk_id; 385 } __packed; 386 387 /** 388 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 389 * @hdr: Generic Header 390 * @parent_id: The current clock parent 391 * 392 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 393 */ 394 struct ti_sci_msg_resp_get_clock_parent { 395 struct ti_sci_msg_hdr hdr; 396 uint8_t parent_id; 397 } __packed; 398 399 /** 400 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 401 * @hdr: Generic header 402 * @dev_id: Device identifier this request is for 403 * @clk_id: Clock identifier for the device for this request. 404 * 405 * This request provides information about how many clock parent options 406 * are available for a given clock to a device. This is typically used 407 * for input clocks. 408 * 409 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 410 * message, or NACK in case of inability to satisfy request. 411 */ 412 struct ti_sci_msg_req_get_clock_num_parents { 413 struct ti_sci_msg_hdr hdr; 414 uint32_t dev_id; 415 uint8_t clk_id; 416 } __packed; 417 418 /** 419 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 420 * @hdr: Generic header 421 * @num_parents: Number of clock parents 422 * 423 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 424 */ 425 struct ti_sci_msg_resp_get_clock_num_parents { 426 struct ti_sci_msg_hdr hdr; 427 uint8_t num_parents; 428 } __packed; 429 430 /** 431 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 432 * @hdr: Generic Header 433 * @dev_id: Device identifier this request is for 434 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 435 * allowable programmed frequency and does not account for clock 436 * tolerances and jitter. 437 * @target_freq_hz: The target clock frequency. A frequency will be found 438 * as close to this target frequency as possible. 439 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 440 * allowable programmed frequency and does not account for clock 441 * tolerances and jitter. 442 * @clk_id: Clock identifier for the device for this request. 443 * 444 * NOTE: Normally clock frequency management is automatically done by TISCI 445 * entity. In case of specific requests, TISCI evaluates capability to achieve 446 * requested frequency within provided range and responds with 447 * result message. 448 * 449 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 450 * or NACK in case of inability to satisfy request. 451 */ 452 struct ti_sci_msg_req_query_clock_freq { 453 struct ti_sci_msg_hdr hdr; 454 uint32_t dev_id; 455 uint64_t min_freq_hz; 456 uint64_t target_freq_hz; 457 uint64_t max_freq_hz; 458 uint8_t clk_id; 459 } __packed; 460 461 /** 462 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 463 * @hdr: Generic Header 464 * @freq_hz: Frequency that is the best match in Hz. 465 * 466 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 467 * cannot be satisfied, the message will be of type NACK. 468 */ 469 struct ti_sci_msg_resp_query_clock_freq { 470 struct ti_sci_msg_hdr hdr; 471 uint64_t freq_hz; 472 } __packed; 473 474 /** 475 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 476 * @hdr: Generic Header 477 * @dev_id: Device identifier this request is for 478 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 479 * allowable programmed frequency and does not account for clock 480 * tolerances and jitter. 481 * @target_freq_hz: The target clock frequency. The clock will be programmed 482 * at a rate as close to this target frequency as possible. 483 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 484 * allowable programmed frequency and does not account for clock 485 * tolerances and jitter. 486 * @clk_id: Clock identifier for the device for this request. 487 * 488 * NOTE: Normally clock frequency management is automatically done by TISCI 489 * entity. In case of specific requests, TISCI evaluates capability to achieve 490 * requested range and responds with success/failure message. 491 * 492 * This sets the desired frequency for a clock within an allowable 493 * range. This message will fail on an enabled clock unless 494 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 495 * if other clocks have their frequency modified due to this message, 496 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 497 * 498 * Calling set frequency on a clock input to the SoC pseudo-device will 499 * inform the PMMC of that clock's frequency. Setting a frequency of 500 * zero will indicate the clock is disabled. 501 * 502 * Calling set frequency on clock outputs from the SoC pseudo-device will 503 * function similarly to setting the clock frequency on a device. 504 * 505 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 506 * message. 507 */ 508 struct ti_sci_msg_req_set_clock_freq { 509 struct ti_sci_msg_hdr hdr; 510 uint32_t dev_id; 511 uint64_t min_freq_hz; 512 uint64_t target_freq_hz; 513 uint64_t max_freq_hz; 514 uint8_t clk_id; 515 } __packed; 516 517 /** 518 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 519 * @hdr: Generic Header 520 * @dev_id: Device identifier this request is for 521 * @clk_id: Clock identifier for the device for this request. 522 * 523 * NOTE: Normally clock frequency management is automatically done by TISCI 524 * entity. In some cases, clock frequencies are configured by host. 525 * 526 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 527 * that the clock is currently at. 528 */ 529 struct ti_sci_msg_req_get_clock_freq { 530 struct ti_sci_msg_hdr hdr; 531 uint32_t dev_id; 532 uint8_t clk_id; 533 } __packed; 534 535 /** 536 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 537 * @hdr: Generic Header 538 * @freq_hz: Frequency that the clock is currently on, in Hz. 539 * 540 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 541 */ 542 struct ti_sci_msg_resp_get_clock_freq { 543 struct ti_sci_msg_hdr hdr; 544 uint64_t freq_hz; 545 } __packed; 546 547 #define TISCI_ADDR_LOW_MASK 0x00000000ffffffff 548 #define TISCI_ADDR_HIGH_MASK 0xffffffff00000000 549 #define TISCI_ADDR_HIGH_SHIFT 32 550 551 /** 552 * struct ti_sci_msg_req_proc_request - Request a processor 553 * 554 * @hdr: Generic Header 555 * @processor_id: ID of processor 556 * 557 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 558 * message. 559 */ 560 struct ti_sci_msg_req_proc_request { 561 struct ti_sci_msg_hdr hdr; 562 uint8_t processor_id; 563 } __packed; 564 565 /** 566 * struct ti_sci_msg_req_proc_release - Release a processor 567 * 568 * @hdr: Generic Header 569 * @processor_id: ID of processor 570 * 571 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 572 * message. 573 */ 574 struct ti_sci_msg_req_proc_release { 575 struct ti_sci_msg_hdr hdr; 576 uint8_t processor_id; 577 } __packed; 578 579 /** 580 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 581 * 582 * @hdr: Generic Header 583 * @processor_id: ID of processor 584 * @host_id: New Host we want to give control to 585 * 586 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 587 * message. 588 */ 589 struct ti_sci_msg_req_proc_handover { 590 struct ti_sci_msg_hdr hdr; 591 uint8_t processor_id; 592 uint8_t host_id; 593 } __packed; 594 595 /* A53 Config Flags */ 596 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001 597 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002 598 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004 599 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008 600 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100 601 602 /* R5 Config Flags */ 603 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001 604 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002 605 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 606 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200 607 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400 608 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800 609 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 610 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 611 612 /** 613 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration 614 * @hdr: Generic Header 615 * @processor_id: ID of processor 616 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 617 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 618 * @config_flags_set: Optional Processor specific Config Flags to set. 619 * Setting a bit here implies required bit sets to 1. 620 * @config_flags_clear: Optional Processor specific Config Flags to clear. 621 * Setting a bit here implies required bit gets cleared. 622 * 623 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic 624 * ACK/NACK message. 625 */ 626 struct ti_sci_msg_req_set_proc_boot_config { 627 struct ti_sci_msg_hdr hdr; 628 uint8_t processor_id; 629 uint32_t bootvector_low; 630 uint32_t bootvector_high; 631 uint32_t config_flags_set; 632 uint32_t config_flags_clear; 633 } __packed; 634 635 /* ARMV8 Control Flags */ 636 #define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001 637 #define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002 638 #define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100 639 640 /* R5 Control Flags */ 641 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 642 643 /** 644 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags 645 * @hdr: Generic Header 646 * @processor_id: ID of processor 647 * @config_flags_set: Optional Processor specific Config Flags to set. 648 * Setting a bit here implies required bit sets to 1. 649 * @config_flags_clear: Optional Processor specific Config Flags to clear. 650 * Setting a bit here implies required bit gets cleared. 651 * 652 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK 653 * message. 654 */ 655 struct ti_sci_msg_req_set_proc_boot_ctrl { 656 struct ti_sci_msg_hdr hdr; 657 uint8_t processor_id; 658 uint32_t control_flags_set; 659 uint32_t control_flags_clear; 660 } __packed; 661 662 /** 663 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image 664 * @hdr: Generic Header 665 * @processor_id: ID of processor 666 * @cert_addr_low: Lower 32bit (Little Endian) of certificate 667 * @cert_addr_high: Higher 32bit (Little Endian) of certificate 668 * 669 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic 670 * ACK/NACK message. 671 */ 672 struct ti_sci_msg_req_proc_auth_boot_image { 673 struct ti_sci_msg_hdr hdr; 674 uint8_t processor_id; 675 uint32_t cert_addr_low; 676 uint32_t cert_addr_high; 677 } __packed; 678 679 /** 680 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status 681 * @hdr: Generic Header 682 * @processor_id: ID of processor 683 * 684 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate 685 * message, or NACK in case of inability to satisfy request. 686 */ 687 struct ti_sci_msg_req_get_proc_boot_status { 688 struct ti_sci_msg_hdr hdr; 689 uint8_t processor_id; 690 } __packed; 691 692 /* ARMv8 Status Flags */ 693 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001 694 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002 695 #define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010 696 #define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020 697 698 /* R5 Status Flags */ 699 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 700 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 701 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004 702 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100 703 704 /** 705 * \brief Processor Status Response 706 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response 707 * @hdr: Generic Header 708 * @processor_id: ID of processor 709 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 710 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 711 * @config_flags: Optional Processor specific Config Flags set. 712 * @control_flags: Optional Processor specific Control Flags. 713 * @status_flags: Optional Processor specific Status Flags set. 714 * 715 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS. 716 */ 717 struct ti_sci_msg_resp_get_proc_boot_status { 718 struct ti_sci_msg_hdr hdr; 719 uint8_t processor_id; 720 uint32_t bootvector_low; 721 uint32_t bootvector_high; 722 uint32_t config_flags; 723 uint32_t control_flags; 724 uint32_t status_flags; 725 } __packed; 726 727 /** 728 * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor boot status 729 * @hdr: Generic Header 730 * @processor_id: ID of processor 731 * @num_wait_iterations Total number of iterations we will check before 732 * we will timeout and give up 733 * @num_match_iterations How many iterations should we have continued 734 * status to account for status bits glitching. 735 * This is to make sure that match occurs for 736 * consecutive checks. This implies that the 737 * worst case should consider that the stable 738 * time should at the worst be num_wait_iterations 739 * num_match_iterations to prevent timeout. 740 * @delay_per_iteration_us Specifies how long to wait (in micro seconds) 741 * between each status checks. This is the minimum 742 * duration, and overhead of register reads and 743 * checks are on top of this and can vary based on 744 * varied conditions. 745 * @delay_before_iterations_us Specifies how long to wait (in micro seconds) 746 * before the very first check in the first 747 * iteration of status check loop. This is the 748 * minimum duration, and overhead of register 749 * reads and checks are. 750 * @status_flags_1_set_all_wait If non-zero, Specifies that all bits of the 751 * status matching this field requested MUST be 1. 752 * @status_flags_1_set_any_wait If non-zero, Specifies that at least one of the 753 * bits matching this field requested MUST be 1. 754 * @status_flags_1_clr_all_wait If non-zero, Specifies that all bits of the 755 * status matching this field requested MUST be 0. 756 * @status_flags_1_clr_any_wait If non-zero, Specifies that at least one of the 757 * bits matching this field requested MUST be 0. 758 * 759 * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate 760 * message, or NACK in case of inability to satisfy request. 761 */ 762 struct ti_sci_msg_req_wait_proc_boot_status { 763 struct ti_sci_msg_hdr hdr; 764 uint8_t processor_id; 765 uint8_t num_wait_iterations; 766 uint8_t num_match_iterations; 767 uint8_t delay_per_iteration_us; 768 uint8_t delay_before_iterations_us; 769 uint32_t status_flags_1_set_all_wait; 770 uint32_t status_flags_1_set_any_wait; 771 uint32_t status_flags_1_clr_all_wait; 772 uint32_t status_flags_1_clr_any_wait; 773 } __packed; 774 775 /** 776 * struct ti_sci_msg_req_enter_sleep - Request for TI_SCI_MSG_ENTER_SLEEP. 777 * 778 * @hdr Generic Header 779 * @mode Low power mode to enter. 780 * @proc_id Processor id to be restored. 781 * @core_resume_lo Low 32-bits of physical pointer to address for core 782 * to begin execution upon resume. 783 * @core_resume_hi High 32-bits of physical pointer to address for core 784 * to begin execution upon resume. 785 * 786 * This message is to be sent after TI_SCI_MSG_PREPARE_SLEEP is sent from OS 787 * and is what actually triggers entry into the specified low power mode. 788 */ 789 struct ti_sci_msg_req_enter_sleep { 790 struct ti_sci_msg_hdr hdr; 791 #define MSG_VALUE_SLEEP_MODE_DEEP_SLEEP 0x0 792 uint8_t mode; 793 uint8_t processor_id; 794 uint32_t core_resume_lo; 795 uint32_t core_resume_hi; 796 } __packed; 797 798 /** 799 * struct ti_sci_msg_req_lpm_get_next_sys_mode - Request for TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE. 800 * 801 * @hdr Generic Header 802 * 803 * This message is used to enquire DM for selected system wide low power mode. 804 */ 805 struct ti_sci_msg_req_lpm_get_next_sys_mode { 806 struct ti_sci_msg_hdr hdr; 807 } __packed; 808 809 /** 810 * struct ti_sci_msg_resp_lpm_get_next_sys_mode - Response for TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE. 811 * 812 * @hdr Generic Header 813 * @mode The selected system wide low power mode. 814 * 815 * Note: If the mode selection is not yet locked, this API returns "not selected" mode. 816 */ 817 struct ti_sci_msg_resp_lpm_get_next_sys_mode { 818 struct ti_sci_msg_hdr hdr; 819 uint8_t mode; 820 } __packed; 821 822 /** 823 * struct tisci_msg_boot_notification_msg - Response to TIFS boot notification 824 * 825 * This structure is used to consume the self initiated boot notification message 826 * from TIFS(TI Foundation Security) firmware which indicates that it is available. 827 * 828 * @hdr: Standard TISCI message header. 829 * @extboot_status: Status of extended boot. Applicable only for combined image 830 */ 831 struct tisci_msg_boot_notification_msg { 832 struct ti_sci_msg_hdr hdr; 833 uint32_t extboot_status; 834 } __packed; 835 836 /* 837 * struct ti_sci_msg_req_encrypt_tfa - Request for TISCI_MSG_LPM_ENCRYPT_TFA. 838 * 839 * @hdr: Standard TISCI message header. 840 * @src_tfa_addr: Address where the TFA lies unencrypted 841 * @src_tfa_len: Size of the TFA unencrypted 842 * 843 * This message is to be sent when the system is going in suspend, just before 844 * TI_SCI_MSG_ENTER_SLEEP. 845 * The TIFS will then encrypt the TFA and store it in RAM, along with a private 846 * header. 847 * Upon resume, the SPL will ask TIFS to decrypt it back. 848 */ 849 struct ti_sci_msg_req_encrypt_tfa { 850 struct ti_sci_msg_hdr hdr; 851 uint64_t src_tfa_addr; 852 uint32_t src_tfa_len; 853 } __packed; 854 855 /* 856 * struct ti_sci_msg_req_encrypt_tfa - Response for TISCI_MSG_LPM_ENCRYPT_TFA. 857 * 858 * @hdr: Standard TISCI message header. 859 */ 860 struct ti_sci_msg_resp_encrypt_tfa { 861 struct ti_sci_msg_hdr hdr; 862 } __packed; 863 864 /* FWL_MAX_PRIVID_SLOTS must be defined with same value in ti_sci.h */ 865 #define FWL_MAX_PRIVID_SLOTS 3U 866 867 /** 868 * struct ti_sci_msg_req_fwl_set_firewall_region - Set firewall permissions 869 * @hdr: Generic Header 870 * @fwl_id: Firewall ID 871 * @region: Region or channel number to set config info. 872 * This field is unused in case of a simple firewall and 873 * must be initialized to zero. In case of a region based 874 * firewall, this field indicates the region (index 875 * starting from 0). In case of a channel based firewall, 876 * this field indicates the channel (index starting 877 * from 0). 878 * @n_permission_regs: Number of permission registers to set 879 * @control: Contents of the firewall CONTROL register to set 880 * @permissions: Contents of the firewall PERMISSION register to set 881 * @start_address: Contents of the firewall START_ADDRESS register to set 882 * @end_address: Contents of the firewall END_ADDRESS register to set 883 */ 884 struct ti_sci_msg_req_fwl_set_firewall_region { 885 struct ti_sci_msg_hdr hdr; 886 uint16_t fwl_id; 887 uint16_t region; 888 uint32_t n_permission_regs; 889 uint32_t control; 890 uint32_t permissions[FWL_MAX_PRIVID_SLOTS]; 891 uint64_t start_address; 892 uint64_t end_address; 893 } __packed; 894 895 struct ti_sci_msg_resp_fwl_set_firewall_region { 896 struct ti_sci_msg_hdr hdr; 897 } __packed; 898 899 /** 900 * struct ti_sci_msg_req_fwl_get_firewall_region - Retrieve firewall permissions 901 * @hdr: Generic Header 902 * @fwl_id: Firewall ID in question 903 * @region: Region or channel number to get config info. 904 * This field is unused in case of a simple firewall and 905 * must be initialized to zero. In case of a region based 906 * firewall, this field indicates the region (index 907 * starting from 0). In case of a channel based firewall, 908 * this field indicates the channel (index starting 909 * from 0). 910 * @n_permission_regs: Number of permission registers to retrieve 911 */ 912 struct ti_sci_msg_req_fwl_get_firewall_region { 913 struct ti_sci_msg_hdr hdr; 914 uint16_t fwl_id; 915 uint16_t region; 916 uint32_t n_permission_regs; 917 } __packed; 918 919 /** 920 * struct ti_sci_msg_resp_fwl_get_firewall_region - Response for retrieving the 921 * firewall permissions 922 * 923 * @hdr: Generic Header 924 * 925 * @fwl_id: Firewall ID in question 926 * @region: Region or channel number to get config info. 927 * This field is unused in case of a simple firewall and 928 * must be initialized to zero. In case of a region based 929 * firewall, this field indicates the region (index 930 * starting from 0). In case of a channel based firewall, 931 * this field indicates the channel (index starting 932 * from 0). 933 * @n_permission_regs: Number of permission registers retrieved 934 * @control: Contents of the firewall CONTROL register 935 * @permissions: Contents of the firewall PERMISSION registers 936 * @start_address: Contents of the firewall START_ADDRESS register 937 * @end_address: Contents of the firewall END_ADDRESS register 938 */ 939 struct ti_sci_msg_resp_fwl_get_firewall_region { 940 struct ti_sci_msg_hdr hdr; 941 uint16_t fwl_id; 942 uint16_t region; 943 uint32_t n_permission_regs; 944 uint32_t control; 945 uint32_t permissions[FWL_MAX_PRIVID_SLOTS]; 946 uint64_t start_address; 947 uint64_t end_address; 948 } __packed; 949 950 /** 951 * struct ti_sci_msg_req_fwl_change_owner_info - Request change firewall owner 952 * 953 * @hdr: Generic Header 954 * 955 * @fwl_id: Firewall ID in question 956 * @region: Region or channel number if applicable 957 * @owner_index: New owner index to transfer ownership to 958 */ 959 struct ti_sci_msg_req_fwl_change_owner_info { 960 struct ti_sci_msg_hdr hdr; 961 uint16_t fwl_id; 962 uint16_t region; 963 uint8_t owner_index; 964 } __packed; 965 966 /** 967 * struct ti_sci_msg_resp_fwl_change_owner_info - Response for change 968 * firewall owner 969 * 970 * @hdr: Generic Header 971 * 972 * @fwl_id: Firewall ID specified in request 973 * @region: Region or channel number specified in request 974 * @owner_index: Owner index specified in request 975 * @owner_privid: New owner priv-ID returned by DMSC/TIFS. 976 * @owner_permission_bits: New owner permission bits returned by DMSC/TIFS. 977 */ 978 struct ti_sci_msg_resp_fwl_change_owner_info { 979 struct ti_sci_msg_hdr hdr; 980 uint16_t fwl_id; 981 uint16_t region; 982 uint8_t owner_index; 983 uint8_t owner_privid; 984 uint16_t owner_permission_bits; 985 } __packed; 986 987 #endif /* TI_SCI_PROTOCOL_H */ 988