1/* 2 * Copyright (c) 2022-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#include <dsu_macros.S> 15#include <wa_cve_2025_0647_cpprctx.h> 16 17#include <plat_macros.S> 18 19/* Hardware handled coherency */ 20#if HW_ASSISTED_COHERENCY == 0 21#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 22#endif 23 24/* 64-bit only core */ 25#if CTX_INCLUDE_AARCH32_REGS == 1 26#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 27#endif 28 29cpu_reset_prologue cortex_x4 30 31.global check_erratum_cortex_x4_2726228 32.global check_erratum_cortex_x4_3701758 33 34add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228 35 36check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 37 38workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 39 /* dsb before isb of power down sequence */ 40 dsb sy 41workaround_runtime_end cortex_x4, ERRATUM(2740089) 42 43check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 44 45workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 46 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 47workaround_reset_end cortex_x4, ERRATUM(2763018) 48 49check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 50 51workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 52 mrs x1, id_aa64pfr1_el1 53 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 54 cbz x2, #1f 55 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 561: 57workaround_reset_end cortex_x4, ERRATUM(2816013) 58 59check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 60 61workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 62 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 63workaround_reset_end cortex_x4, ERRATUM(2897503) 64 65check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 66 67workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952 68 errata_dsu_2900952_wa_apply 69workaround_reset_end cortex_x4, ERRATUM(2900952) 70 71check_erratum_custom_start cortex_x4, ERRATUM(2900952) 72 check_errata_dsu_2900952_applies 73 ret 74check_erratum_custom_end cortex_x4, ERRATUM(2900952) 75 76workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 77 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 78workaround_reset_end cortex_x4, ERRATUM(2923985) 79 80check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 81 82workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 83 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 84 ldr x0, =0x1 85 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 86 ldr x0, =0xd5380000 87 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 88 ldr x0, =0xFFFFFF40 89 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 90 ldr x0, =0x000080010033f 91 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 92 isb 93workaround_reset_end cortex_x4, ERRATUM(2957258) 94 95check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 96 97workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 98 sysreg_lazy_start CORTEX_X4_CPUACTLR3_EL1 99 sysreg_lazy_set BIT(14) 100 sysreg_lazy_set BIT(13) 101 sysreg_lazy_commit CORTEX_X4_CPUACTLR3_EL1 102 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 103workaround_reset_end cortex_x4, ERRATUM(3076789) 104 105check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 106 107workaround_reset_start cortex_x4, ERRATUM(3133195), ERRATA_X4_3133195 108 ldr x0,=0x2 109 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */ 110 ldr x0,=0xd503225f 111 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */ 112 ldr x0,=0xffffffff 113 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */ 114 ldr x0,=0x00000000404003fd 115 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */ 116workaround_reset_end cortex_x4, ERRATUM(3133195) 117 118check_erratum_range cortex_x4, ERRATUM(3133195), CPU_REV(0, 2), CPU_REV(0, 2) 119 120add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758 121 122check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 123 124workaround_reset_start cortex_x4, ERRATUM(3887999), ERRATA_X4_3887999 125 sysreg_bit_set CORTEX_X4_CPUACTLR2_EL1, BIT(22) 126workaround_reset_end cortex_x4, ERRATUM(3887999) 127 128check_erratum_ls cortex_x4, ERRATUM(3887999), CPU_REV(0, 3) 129 130/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 131workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 132 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 133workaround_reset_end cortex_x4, CVE(2024, 5660) 134 135check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 136 137 /* -------------------------------------------------------------- 138 * CVE-2024-7881 is mitigated for Cortex-X4 using erratum 3692983 139 * workaround by disabling the affected prefetcher setting 140 * CPUACTLR6_EL1[41]. 141 * -------------------------------------------------------------- 142 */ 143workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 144 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 145workaround_reset_end cortex_x4, CVE(2024, 7881) 146 147check_erratum_ls cortex_x4, CVE(2024, 7881), CPU_REV(0, 2) 148 149 /* 150 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 151 * Enables mitigation for CVE-2025-0647. 152 */ 153workaround_reset_start cortex_x4, CVE(2025, 647), WORKAROUND_CVE_2025_0647 154#if IMAGE_BL31 155 mov x0, #WA_PATCH_SLOT(3) 156 bl wa_cve_2025_0647_instruction_patch 157#endif /* IMAGE_BL31 */ 158workaround_reset_end cortex_x4, CVE(2025, 647) 159 160check_erratum_chosen cortex_x4, CVE(2025, 647), WORKAROUND_CVE_2025_0647 161 162#if WORKAROUND_CVE_2025_0647 163func cortex_x4_impl_defined_el3_handler 164 mov x0, #0 165 166 /* See if this call came from trap handler. */ 167 cmp x1, #EC_IMP_DEF_EL3 168 bne wa_cve_2025_0647_do_cpp_wa 169 orr x0, x0, #WA_IS_TRAP_HANDLER 170 b wa_cve_2025_0647_do_cpp_wa 171endfunc cortex_x4_impl_defined_el3_handler 172#endif 173 174cpu_reset_func_start cortex_x4 175 /* Disable speculative loads */ 176 msr SSBS, xzr 177 enable_mpmm 178cpu_reset_func_end cortex_x4 179 180 /* ---------------------------------------------------- 181 * HW will do the cache maintenance while powering down 182 * ---------------------------------------------------- 183 */ 184func cortex_x4_core_pwr_dwn 185 /* --------------------------------------------------- 186 * Enable CPU power down bit in power control register 187 * --------------------------------------------------- 188 */ 189 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 190 191 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 192 193 isb 194 ret 195endfunc cortex_x4_core_pwr_dwn 196 197 /* --------------------------------------------- 198 * This function provides Cortex X4-specific 199 * register information for crash reporting. 200 * It needs to return with x6 pointing to 201 * a list of register names in ascii and 202 * x8 - x15 having values of registers to be 203 * reported. 204 * --------------------------------------------- 205 */ 206.section .rodata.cortex_x4_regs, "aS" 207cortex_x4_regs: /* The ascii list of register names to be reported */ 208 .asciz "cpuectlr_el1", "" 209 210func cortex_x4_cpu_reg_dump 211 adr x6, cortex_x4_regs 212 mrs x8, CORTEX_X4_CPUECTLR_EL1 213 ret 214endfunc cortex_x4_cpu_reg_dump 215 216#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 217declare_cpu_ops_eh cortex_x4, CORTEX_X4_MIDR, \ 218 cortex_x4_reset_func, \ 219 cortex_x4_impl_defined_el3_handler, \ 220 cortex_x4_core_pwr_dwn 221#else 222declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 223 cortex_x4_reset_func, \ 224 cortex_x4_core_pwr_dwn 225#endif 226 227