1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13 14.global check_erratum_cortex_a75_764081 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21cpu_reset_prologue cortex_a75 22 23/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 24add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 25 26check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 27 28workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 29 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 30workaround_reset_end cortex_a75, ERRATUM(764081) 31 32check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 33 34workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 35 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 36workaround_reset_end cortex_a75, ERRATUM(790748) 37 38check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 39 40workaround_reset_start cortex_a75, ERRATUM(798953), ERRATA_DSU_798953 41 errata_dsu_798953_wa_impl 42workaround_reset_end cortex_a75, ERRATUM(798953) 43 44check_erratum_custom_start cortex_a75, ERRATUM(798953) 45 check_errata_dsu_798953_impl 46 ret 47check_erratum_custom_end cortex_a75, ERRATUM(798953) 48 49workaround_reset_start cortex_a75, ERRATUM(936184), ERRATA_DSU_936184 50 errata_dsu_936184_wa_impl 51workaround_reset_end cortex_a75, ERRATUM(936184) 52 53check_erratum_custom_start cortex_a75, ERRATUM(936184) 54 check_errata_dsu_936184_impl 55 ret 56check_erratum_custom_end cortex_a75, ERRATUM(936184) 57 58workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 59#if IMAGE_BL31 60 override_vector_table wa_cve_2017_5715_bpiall_vbar 61#endif /* IMAGE_BL31 */ 62workaround_reset_end cortex_a75, CVE(2017, 5715) 63 64/* r3p0 implements FEAT_CSV2 */ 65check_erratum_ls cortex_a75, CVE(2017, 5715), CPU_REV(3, 0) 66 67workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 68 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 69workaround_reset_end cortex_a75, CVE(2018, 3639) 70 71check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 72 73workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 74#if IMAGE_BL31 75 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 76 adr x0, wa_cve_2017_5715_bpiall_vbar 77 mrs x1, vbar_el3 78 cmp x0, x1 79 b.eq 1f 80 msr vbar_el3, x0 811: 82#endif /* IMAGE_BL31 */ 83workaround_reset_end cortex_a75, CVE(2022, 23960) 84 85check_erratum_custom_start cortex_a75, CVE(2022, 23960) 86#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 87 cpu_check_csv2 x0, 1f 88 mov x0, #ERRATA_APPLIES 89 ret 901: 91# if WORKAROUND_CVE_2022_23960 92 mov x0, #ERRATA_APPLIES 93# else 94 mov x0, #ERRATA_MISSING 95# endif /* WORKAROUND_CVE_2022_23960 */ 96 ret 97#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 98 mov x0, #ERRATA_MISSING 99 ret 100check_erratum_custom_end cortex_a75, CVE(2022, 23960) 101 102 /* ------------------------------------------------- 103 * The CPU Ops reset function for Cortex-A75. 104 * ------------------------------------------------- 105 */ 106 107cpu_reset_func_start cortex_a75 108#if ENABLE_FEAT_AMU 109 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 110 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 111 isb 112 113 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 114 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 115 isb 116 117 /* Enable group0 counters */ 118 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 119 msr CPUAMCNTENSET_EL0, x0 120 isb 121 122 /* Enable group1 counters */ 123 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 124 msr CPUAMCNTENSET_EL0, x0 125 /* isb included in cpu_reset_func_end macro */ 126#endif 127cpu_reset_func_end cortex_a75 128 129 /* --------------------------------------------- 130 * HW will do the cache maintenance while powering down 131 * --------------------------------------------- 132 */ 133func cortex_a75_core_pwr_dwn 134 /* --------------------------------------------- 135 * Enable CPU power down bit in power control register 136 * --------------------------------------------- 137 */ 138 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ 139 CORTEX_A75_CORE_PWRDN_EN_MASK 140 isb 141 ret 142endfunc cortex_a75_core_pwr_dwn 143 144 /* --------------------------------------------- 145 * This function provides cortex_a75 specific 146 * register information for crash reporting. 147 * It needs to return with x6 pointing to 148 * a list of register names in ascii and 149 * x8 - x15 having values of registers to be 150 * reported. 151 * --------------------------------------------- 152 */ 153.section .rodata.cortex_a75_regs, "aS" 154cortex_a75_regs: /* The ascii list of register names to be reported */ 155 .asciz "cpuectlr_el1", "" 156 157func cortex_a75_cpu_reg_dump 158 adr x6, cortex_a75_regs 159 mrs x8, CORTEX_A75_CPUECTLR_EL1 160 ret 161endfunc cortex_a75_cpu_reg_dump 162 163declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 164 cortex_a75_reset_func, \ 165 cortex_a75_core_pwr_dwn 166