1 /*
2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <config.h>
8 #include <common.h>
9 #include <errno.h>
10 #include <malloc.h>
11 #include <fdtdec.h>
12 #include <fdt_support.h>
13 #include <asm/unaligned.h>
14 #include <asm/io.h>
15 #include <linux/list.h>
16 #include <linux/media-bus-format.h>
17 #include <linux/iopoll.h>
18 #include <clk.h>
19 #include <asm/arch/clock.h>
20 #include <linux/err.h>
21 #include <dm/device.h>
22 #include <dm/read.h>
23 #include <syscon.h>
24 #include <regmap.h>
25
26 #include "rockchip_display.h"
27 #include "rockchip_crtc.h"
28 #include "rockchip_connector.h"
29 #include "rockchip_vop.h"
30
us_to_vertical_line(struct drm_display_mode * mode,int us)31 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
32 {
33 return us * mode->clock / mode->htotal / 1000;
34 }
35
set_vop_mcu_rs(struct vop * vop,int v)36 static inline void set_vop_mcu_rs(struct vop *vop, int v)
37 {
38 if (dm_gpio_is_valid(&vop->mcu_rs_gpio))
39 dm_gpio_set_value(&vop->mcu_rs_gpio, v);
40 else
41 VOP_CTRL_SET(vop, mcu_rs, v);
42 }
43
to_vop_csc_mode(enum drm_color_encoding color_encoding,enum drm_color_range color_range)44 static enum vop_csc_format to_vop_csc_mode(enum drm_color_encoding color_encoding,
45 enum drm_color_range color_range)
46 {
47 bool full_range = color_range == DRM_COLOR_YCBCR_FULL_RANGE ? 1 : 0;
48 enum vop_csc_format csc_mode = CSC_BT709L;
49
50 switch (color_encoding) {
51 case DRM_COLOR_YCBCR_BT601:
52 if (full_range)
53 csc_mode = CSC_BT601F;
54 else
55 csc_mode = CSC_BT601L;
56 break;
57
58 case DRM_COLOR_YCBCR_BT709:
59 if (full_range) {
60 csc_mode = CSC_BT601F;
61 printf("Unsupported bt709f at 10bit csc depth, use bt601f instead\n");
62 } else {
63 csc_mode = CSC_BT709L;
64 }
65 break;
66
67 case DRM_COLOR_YCBCR_BT2020:
68 if (full_range) {
69 csc_mode = CSC_BT601F;
70 printf("Unsupported bt2020f at 10bit csc depth, use bt601f instead\n");
71 } else {
72 csc_mode = CSC_BT2020L;
73 }
74 break;
75
76 default:
77 printf("Unsuport color_encoding:%d\n", color_encoding);
78 }
79
80 return csc_mode;
81 }
82
is_yuv_output(uint32_t bus_format)83 static bool is_yuv_output(uint32_t bus_format)
84 {
85 switch (bus_format) {
86 case MEDIA_BUS_FMT_YUV8_1X24:
87 case MEDIA_BUS_FMT_YUV10_1X30:
88 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
89 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
90 case MEDIA_BUS_FMT_YUYV8_2X8:
91 case MEDIA_BUS_FMT_YVYU8_2X8:
92 case MEDIA_BUS_FMT_UYVY8_2X8:
93 case MEDIA_BUS_FMT_VYUY8_2X8:
94 case MEDIA_BUS_FMT_YUYV8_1X16:
95 case MEDIA_BUS_FMT_YVYU8_1X16:
96 case MEDIA_BUS_FMT_UYVY8_1X16:
97 case MEDIA_BUS_FMT_VYUY8_1X16:
98 return true;
99 default:
100 return false;
101 }
102 }
103
is_uv_swap(uint32_t bus_format,uint32_t output_mode)104 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode)
105 {
106 /*
107 * FIXME:
108 *
109 * There is no media type for YUV444 output,
110 * so when out_mode is AAAA or P888, assume output is YUV444 on
111 * yuv format.
112 *
113 * From H/W testing, YUV444 mode need a rb swap.
114 */
115 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
116 bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
117 (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
118 output_mode == ROCKCHIP_OUT_MODE_P888))
119 return true;
120 else
121 return false;
122 }
123
is_rb_swap(uint32_t bus_format,uint32_t output_mode)124 static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
125 {
126 /*
127 * The default component order of serial rgb3x8 formats
128 * is BGR. So it is needed to enable RB swap.
129 */
130 if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
131 bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
132 return true;
133 else
134 return false;
135 }
136
is_yc_swap(uint32_t bus_format)137 static bool is_yc_swap(uint32_t bus_format)
138 {
139 switch (bus_format) {
140 case MEDIA_BUS_FMT_YUYV8_1X16:
141 case MEDIA_BUS_FMT_YVYU8_1X16:
142 case MEDIA_BUS_FMT_YUYV8_2X8:
143 case MEDIA_BUS_FMT_YVYU8_2X8:
144 return true;
145 default:
146 return false;
147 }
148 }
149
rockchip_vop_init_gamma(struct vop * vop,struct display_state * state)150 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state)
151 {
152 struct crtc_state *crtc_state = &state->crtc_state;
153 struct connector_state *conn_state = &state->conn_state;
154 u32 *lut = conn_state->gamma.lut;
155 fdt_size_t lut_size;
156 int i, lut_len;
157 u32 *lut_regs;
158
159 if (!conn_state->gamma.lut)
160 return 0;
161
162 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut");
163 if (i < 0) {
164 printf("Warning: vop not support gamma\n");
165 return 0;
166 }
167 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size);
168 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) {
169 printf("failed to get gamma lut register\n");
170 return 0;
171 }
172 lut_len = lut_size / 4;
173 if (lut_len != 256 && lut_len != 1024) {
174 printf("Warning: unsupport gamma lut table[%d]\n", lut_len);
175 return 0;
176 }
177
178 if (conn_state->gamma.size != lut_len) {
179 int size = conn_state->gamma.size;
180 u32 j, r, g, b, color;
181
182 for (i = 0; i < lut_len; i++) {
183 j = i * size / lut_len;
184 r = lut[j] / size / size * lut_len / size;
185 g = lut[j] / size % size * lut_len / size;
186 b = lut[j] % size * lut_len / size;
187 color = r * lut_len * lut_len + g * lut_len + b;
188
189 writel(color, lut_regs + (i << 2));
190 }
191 } else {
192 for (i = 0; i < lut_len; i++)
193 writel(lut[i], lut_regs + (i << 2));
194 }
195
196 VOP_CTRL_SET(vop, dsp_lut_en, 1);
197 VOP_CTRL_SET(vop, update_gamma_lut, 1);
198
199 return 0;
200 }
201
vop_post_config(struct display_state * state,struct vop * vop)202 static void vop_post_config(struct display_state *state, struct vop *vop)
203 {
204 struct connector_state *conn_state = &state->conn_state;
205 struct drm_display_mode *mode = &conn_state->mode;
206 u16 vtotal = mode->crtc_vtotal;
207 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
208 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
209 u16 hdisplay = mode->crtc_hdisplay;
210 u16 vdisplay = mode->crtc_vdisplay;
211 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200;
212 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200;
213 u16 hact_end, vact_end;
214 u32 val;
215
216 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
217 vsize = round_down(vsize, 2);
218
219 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200;
220 hact_end = hact_st + hsize;
221 val = hact_st << 16;
222 val |= hact_end;
223
224 VOP_CTRL_SET(vop, hpost_st_end, val);
225 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200;
226 vact_end = vact_st + vsize;
227 val = vact_st << 16;
228 val |= vact_end;
229 VOP_CTRL_SET(vop, vpost_st_end, val);
230 val = scl_cal_scale2(vdisplay, vsize) << 16;
231 val |= scl_cal_scale2(hdisplay, hsize);
232 VOP_CTRL_SET(vop, post_scl_factor, val);
233 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
234 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
235 VOP_CTRL_SET(vop, post_scl_ctrl,
236 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) |
237 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
238 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
239 u16 vact_st_f1 = vtotal + vact_st + 1;
240 u16 vact_end_f1 = vact_st_f1 + vsize;
241
242 val = vact_st_f1 << 16 | vact_end_f1;
243 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
244 }
245 }
246
vop_mcu_bypass_mode_setup(struct display_state * state,struct vop * vop)247 static void vop_mcu_bypass_mode_setup(struct display_state *state, struct vop *vop)
248 {
249 /*
250 * If mcu_hold_mode is 1, set 1 to mcu_frame_st will
251 * refresh one frame from ddr. So mcu_frame_st is needed
252 * to be initialized as 0.
253 */
254 VOP_CTRL_SET(vop, mcu_frame_st, 0);
255 VOP_CTRL_SET(vop, mcu_clk_sel, 1);
256 VOP_CTRL_SET(vop, mcu_type, 1);
257
258 VOP_CTRL_SET(vop, mcu_hold_mode, 1);
259 VOP_CTRL_SET(vop, mcu_pix_total, 53);
260 VOP_CTRL_SET(vop, mcu_cs_pst, 6);
261 VOP_CTRL_SET(vop, mcu_cs_pend, 48);
262 VOP_CTRL_SET(vop, mcu_rw_pst, 12);
263 VOP_CTRL_SET(vop, mcu_rw_pend, 30);
264 }
265
vop_mcu_mode_setup(struct display_state * state,struct vop * vop)266 static void vop_mcu_mode_setup(struct display_state *state, struct vop *vop)
267 {
268 struct crtc_state *crtc_state = &state->crtc_state;
269
270 /*
271 * If mcu_hold_mode is 1, set 1 to mcu_frame_st will
272 * refresh one frame from ddr. So mcu_frame_st is needed
273 * to be initialized as 0.
274 */
275 VOP_CTRL_SET(vop, mcu_frame_st, 0);
276 VOP_CTRL_SET(vop, mcu_clk_sel, 1);
277 VOP_CTRL_SET(vop, mcu_type, 1);
278
279 VOP_CTRL_SET(vop, mcu_hold_mode, 1);
280 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total);
281 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst);
282 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend);
283 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst);
284 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend);
285 }
286
rockchip_vop_preinit(struct display_state * state)287 static int rockchip_vop_preinit(struct display_state *state)
288 {
289 const struct vop_data *vop_data = state->crtc_state.crtc->data;
290
291 state->crtc_state.max_output = vop_data->max_output;
292
293 return 0;
294 }
295
vop_mode_done(struct vop * vop)296 static u32 vop_mode_done(struct vop *vop)
297 {
298 return VOP_CTRL_GET(vop, out_mode);
299 }
300
vop_set_out_mode(struct vop * vop,u32 mode)301 static void vop_set_out_mode(struct vop *vop, u32 mode)
302 {
303 int ret;
304 u32 val;
305
306 VOP_CTRL_SET(vop, out_mode, mode);
307 vop_cfg_done(vop);
308 ret = readx_poll_timeout(vop_mode_done, vop, val, val == mode, 1000 * 1000);
309 if (ret)
310 printf("wait for setting mode 0x%x timeout\n", mode);
311 }
312
rockchip_vop_init(struct display_state * state)313 static int rockchip_vop_init(struct display_state *state)
314 {
315 struct crtc_state *crtc_state = &state->crtc_state;
316 struct connector_state *conn_state = &state->conn_state;
317 struct drm_display_mode *mode = &conn_state->mode;
318 const struct rockchip_crtc *crtc = crtc_state->crtc;
319 const struct vop_data *vop_data = crtc->data;
320 struct vop *vop;
321 struct regmap *map;
322 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
323 u16 hdisplay = mode->crtc_hdisplay;
324 u16 htotal = mode->crtc_htotal;
325 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
326 u16 hact_end = hact_st + hdisplay;
327 u16 vdisplay = mode->crtc_vdisplay;
328 u16 vtotal = mode->crtc_vtotal;
329 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
330 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
331 u16 vact_end = vact_st + vdisplay;
332 u32 val, act_end;
333 int ret;
334 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false;
335 u16 post_csc_mode;
336 bool dclk_inv, yc_swap = false;
337 char output_type_name[30] = {0};
338
339 vop = malloc(sizeof(*vop));
340 if (!vop)
341 return -ENOMEM;
342 memset(vop, 0, sizeof(*vop));
343
344 crtc_state->private = vop;
345 vop->data = vop_data;
346 vop->regs = dev_read_addr_ptr(crtc_state->dev);
347 vop->regsbak = malloc(vop_data->reg_len);
348 vop->win = vop_data->win;
349 vop->win_offset = vop_data->win_offset;
350 vop->ctrl = vop_data->ctrl;
351
352 map = syscon_regmap_lookup_by_phandle(crtc_state->dev, "rockchip,grf");
353 if (!IS_ERR_OR_NULL(map)) {
354 vop->grf_ctrl = regmap_get_range(map, 0);
355 if (vop->grf_ctrl <= 0)
356 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, vop->grf_ctrl);
357 }
358 map = syscon_regmap_lookup_by_phandle(crtc_state->dev, "rockchip,vo0-grf");
359 if (!IS_ERR_OR_NULL(map)) {
360 vop->vo0_grf_ctrl = regmap_get_range(map, 0);
361 if (vop->vo0_grf_ctrl <= 0)
362 printf("%s: Get syscon vo0_grf failed (ret=%p)\n", __func__, vop->vo0_grf_ctrl);
363 }
364
365 vop->line_flag = vop_data->line_flag;
366 vop->csc_table = vop_data->csc_table;
367 vop->win_csc = vop_data->win_csc;
368 vop->version = vop_data->version;
369
370 printf("VOP:0x%8p update mode to: %dx%d%s%d, type:%s\n",
371 vop->regs, mode->crtc_hdisplay, mode->vdisplay,
372 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
373 drm_mode_vrefresh(mode),
374 rockchip_get_output_if_name(conn_state->output_if, output_type_name));
375
376 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
377 ret = clk_set_defaults(crtc_state->dev);
378 if (ret)
379 debug("%s clk_set_defaults failed %d\n", __func__, ret);
380
381 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &crtc_state->dclk);
382 if (!ret)
383 ret = clk_set_rate(&crtc_state->dclk, mode->crtc_clock * 1000);
384 if (IS_ERR_VALUE(ret)) {
385 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret);
386 return ret;
387 }
388 printf("VOP:0x%8p set crtc_clock to %dKHz, get %dHz\n", vop->regs, mode->crtc_clock, ret);
389
390 memcpy(vop->regsbak, vop->regs, vop_data->reg_len);
391
392 rockchip_vop_init_gamma(vop, state);
393
394 ret = gpio_request_by_name(crtc_state->dev, "mcu-rs-gpios",
395 0, &vop->mcu_rs_gpio, GPIOD_IS_OUT);
396 if (ret && ret != -ENOENT)
397 printf("%s: Cannot get mcu rs GPIO: %d\n", __func__, ret);
398
399 VOP_CTRL_SET(vop, global_regdone_en, 1);
400 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30);
401 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1);
402 VOP_CTRL_SET(vop, reg_done_frm, 1);
403 VOP_CTRL_SET(vop, win_gate[0], 1);
404 VOP_CTRL_SET(vop, win_gate[1], 1);
405 VOP_CTRL_SET(vop, win_channel[0], 0x12);
406 VOP_CTRL_SET(vop, win_channel[1], 0x34);
407 VOP_CTRL_SET(vop, win_channel[2], 0x56);
408 VOP_CTRL_SET(vop, dsp_blank, 0);
409
410 if (vop->version == VOP_VERSION_RK3576_LITE) {
411 VOP_GRF_SET(vop, grf_ctrl, grf_vopl_sel, 1);
412 VOP_CTRL_SET(vop, enable, 1);
413 }
414
415 dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
416 /* For improving signal quality, dclk need to be inverted by default on rv1106. */
417 if (vop->version == VOP_VERSION_RV1106)
418 dclk_inv = !dclk_inv;
419 VOP_CTRL_SET(vop, dclk_pol, dclk_inv);
420
421 val = 0x8;
422 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
423 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
424 VOP_CTRL_SET(vop, pin_pol, val);
425
426 switch (conn_state->type) {
427 case DRM_MODE_CONNECTOR_LVDS:
428 VOP_CTRL_SET(vop, rgb_en, 1);
429 VOP_CTRL_SET(vop, rgb_pin_pol, val);
430 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv);
431 VOP_CTRL_SET(vop, lvds_en, 1);
432 VOP_CTRL_SET(vop, lvds_pin_pol, val);
433 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv);
434 if (!IS_ERR_OR_NULL(vop->grf_ctrl))
435 VOP_GRF_SET(vop, grf_ctrl, grf_dclk_inv, dclk_inv);
436 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) {
437 VOP_CTRL_SET(vop, bt1120_en, 1);
438 yc_swap = is_yc_swap(conn_state->bus_format);
439 VOP_CTRL_SET(vop, bt1120_yc_swap, yc_swap);
440 VOP_CTRL_SET(vop, yuv_clip, 1);
441 } else if (conn_state->output_if & VOP_OUTPUT_IF_BT656) {
442 VOP_CTRL_SET(vop, bt656_en, 1);
443 yc_swap = is_yc_swap(conn_state->bus_format);
444 VOP_CTRL_SET(vop, bt1120_yc_swap, yc_swap);
445 }
446 break;
447 case DRM_MODE_CONNECTOR_eDP:
448 VOP_CTRL_SET(vop, edp_en, 1);
449 VOP_CTRL_SET(vop, edp_pin_pol, val);
450 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv);
451 VOP_CTRL_SET(vop, inf_out_en, 1);
452 VOP_CTRL_SET(vop, out_dresetn, 1);
453 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_edp_ch_sel, 1);
454 break;
455 case DRM_MODE_CONNECTOR_HDMIA:
456 VOP_CTRL_SET(vop, hdmi_en, 1);
457 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
458 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
459 VOP_CTRL_SET(vop, inf_out_en, 1);
460 VOP_CTRL_SET(vop, out_dresetn, 1);
461 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_hdmi_ch_sel, 1);
462 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_hdmi_pin_pol, val);
463 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_hdmi_1to4_en, 1);
464 break;
465 case DRM_MODE_CONNECTOR_DSI:
466 /*
467 * RK3576 DSI CTRL hsync/vsync polarity is positive and can't update,
468 * so set VOP hsync/vsync polarity as positive by default.
469 */
470 if (vop->version == VOP_VERSION_RK3576_LITE)
471 val = BIT(HSYNC_POSITIVE) | BIT(VSYNC_POSITIVE);
472 VOP_CTRL_SET(vop, mipi_en, 1);
473 VOP_CTRL_SET(vop, mipi_pin_pol, val);
474 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv);
475 VOP_CTRL_SET(vop, mipi_dual_channel_en,
476 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE));
477 VOP_CTRL_SET(vop, data01_swap,
478 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) ||
479 crtc_state->dual_channel_swap);
480 VOP_CTRL_SET(vop, inf_out_en, 1);
481 VOP_CTRL_SET(vop, out_dresetn, 1);
482 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_mipi_ch_sel, 1);
483 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_mipi_mode, 0);
484 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_mipi_pin_pol, val);
485 VOP_GRF_SET(vop, vo0_grf_ctrl, grf_mipi_1to4_en, 1);
486 break;
487 case DRM_MODE_CONNECTOR_DisplayPort:
488 VOP_CTRL_SET(vop, dp_dclk_pol, 0);
489 VOP_CTRL_SET(vop, dp_pin_pol, val);
490 VOP_CTRL_SET(vop, dp_en, 1);
491 break;
492 case DRM_MODE_CONNECTOR_TV:
493 if (vdisplay == CVBS_PAL_VDISPLAY)
494 VOP_CTRL_SET(vop, tve_sw_mode, 1);
495 else
496 VOP_CTRL_SET(vop, tve_sw_mode, 0);
497 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
498 VOP_CTRL_SET(vop, tve_dclk_en, 1);
499 /* use the same pol reg with hdmi */
500 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
501 VOP_CTRL_SET(vop, sw_genlock, 1);
502 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
503 VOP_CTRL_SET(vop, dither_up, 1);
504 break;
505 default:
506 printf("unsupport connector_type[%d]\n", conn_state->type);
507 }
508
509 if ((conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
510 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) ||
511 (vop->version >= VOP_VERSION_RV1106 && vop->version < VOP_VERSION_RK3288 &&
512 conn_state->output_if & VOP_OUTPUT_IF_BT656))
513 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888;
514
515 switch (conn_state->bus_format) {
516 case MEDIA_BUS_FMT_RGB565_1X16:
517 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
518 break;
519 case MEDIA_BUS_FMT_RGB666_1X18:
520 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
521 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
522 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
523 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
524 break;
525 case MEDIA_BUS_FMT_YUV8_1X24:
526 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
527 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
528 break;
529 case MEDIA_BUS_FMT_YUV10_1X30:
530 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
531 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
532 break;
533 case MEDIA_BUS_FMT_RGB888_1X24:
534 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
535 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
536 default:
537 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
538 break;
539 }
540 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA)
541 val |= PRE_DITHER_DOWN_EN(0);
542 else
543 val |= PRE_DITHER_DOWN_EN(1);
544 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
545 VOP_CTRL_SET(vop, dither_down, val);
546
547 VOP_CTRL_SET(vop, dclk_ddr,
548 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
549 VOP_CTRL_SET(vop, hdmi_dclk_out_en,
550 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
551
552 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) ||
553 is_rb_swap(conn_state->bus_format, conn_state->output_mode))
554 VOP_CTRL_SET(vop, dsp_rb_swap, 1);
555 else
556 VOP_CTRL_SET(vop, dsp_data_swap, 0);
557
558 /*
559 * For RK3576 vopl, rg_swap and rb_swap need to be enabled in
560 * YUV444 bus_format.
561 */
562 if (vop->version == VOP_VERSION_RK3576_LITE) {
563 if (conn_state->bus_format == MEDIA_BUS_FMT_YUV8_1X24)
564 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RG_SWAP | DSP_RB_SWAP);
565 }
566
567 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode);
568
569 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) {
570 yuv_overlay = is_yuv_output(conn_state->bus_format);
571 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay);
572 }
573 /*
574 * todo: r2y for win csc
575 */
576 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format));
577
578 if (yuv_overlay) {
579 if (!is_yuv_output(conn_state->bus_format))
580 post_y2r_en = true;
581 } else {
582 if (is_yuv_output(conn_state->bus_format))
583 post_r2y_en = true;
584 }
585
586 crtc_state->yuv_overlay = yuv_overlay;
587 post_csc_mode = to_vop_csc_mode(conn_state->color_encoding, conn_state->color_range);
588 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en);
589 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en);
590 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode);
591 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode);
592
593 /*
594 * Background color is 10bit depth if vop version >= 3.5
595 */
596 if (!is_yuv_output(conn_state->bus_format))
597 val = 0;
598 else if (vop->version == VOP_VERSION_RK3576_LITE)
599 val = 0;
600 else if (vop->version >= VOP_VERSION_RK3399_BIG)
601 val = 0x20010200;
602 else
603 val = 0x801080;
604 VOP_CTRL_SET(vop, dsp_background, val);
605
606 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
607 val = hact_st << 16;
608 val |= hact_end;
609 VOP_CTRL_SET(vop, hact_st_end, val);
610 val = vact_st << 16;
611 val |= vact_end;
612 VOP_CTRL_SET(vop, vact_st_end, val);
613 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
614 u16 vact_st_f1 = vtotal + vact_st + 1;
615 u16 vact_end_f1 = vact_st_f1 + vdisplay;
616
617 val = vact_st_f1 << 16 | vact_end_f1;
618 VOP_CTRL_SET(vop, vact_st_end_f1, val);
619
620 val = vtotal << 16 | (vtotal + vsync_len);
621 VOP_CTRL_SET(vop, vs_st_end_f1, val);
622 VOP_CTRL_SET(vop, dsp_interlace, 1);
623 VOP_CTRL_SET(vop, p2i_en, 1);
624 vtotal += vtotal + 1;
625 act_end = vact_end_f1;
626 } else {
627 VOP_CTRL_SET(vop, dsp_interlace, 0);
628 VOP_CTRL_SET(vop, p2i_en, 0);
629 act_end = vact_end;
630 }
631 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
632 vop_post_config(state, vop);
633 VOP_CTRL_SET(vop, core_dclk_div,
634 !!(mode->flags & DRM_MODE_FLAG_DBLCLK) ||
635 conn_state->output_if & VOP_OUTPUT_IF_BT656);
636
637 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3);
638 VOP_LINE_FLAG_SET(vop, line_flag_num[1],
639 act_end - us_to_vertical_line(mode, 1000));
640
641 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) {
642 if (vop->version >= VOP_VERSION_RK3576_LITE) {
643 VOP_CTRL_SET(vop, standby, 0);
644 vop_set_out_mode(vop, conn_state->output_mode);
645 }
646 vop_mcu_mode_setup(state, vop);
647 }
648
649 vop_cfg_done(vop);
650
651 return 0;
652 }
653
scl_vop_cal_scale(enum scale_mode mode,uint32_t src,uint32_t dst,bool is_horizontal,int vsu_mode,int * vskiplines)654 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
655 uint32_t dst, bool is_horizontal,
656 int vsu_mode, int *vskiplines)
657 {
658 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
659
660 if (is_horizontal) {
661 if (mode == SCALE_UP)
662 val = GET_SCL_FT_BIC(src, dst);
663 else if (mode == SCALE_DOWN)
664 val = GET_SCL_FT_BILI_DN(src, dst);
665 } else {
666 if (mode == SCALE_UP) {
667 if (vsu_mode == SCALE_UP_BIL)
668 val = GET_SCL_FT_BILI_UP(src, dst);
669 else
670 val = GET_SCL_FT_BIC(src, dst);
671 } else if (mode == SCALE_DOWN) {
672 if (vskiplines) {
673 *vskiplines = scl_get_vskiplines(src, dst);
674 val = scl_get_bili_dn_vskip(src, dst,
675 *vskiplines);
676 } else {
677 val = GET_SCL_FT_BILI_DN(src, dst);
678 }
679 }
680 }
681
682 return val;
683 }
684
scl_vop_cal_scl_fac(struct vop * vop,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,uint32_t pixel_format)685 static void scl_vop_cal_scl_fac(struct vop *vop,
686 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
687 uint32_t dst_h, uint32_t pixel_format)
688 {
689 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
690 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
691 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
692 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
693 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
694 bool is_yuv = false;
695 uint16_t cbcr_src_w = src_w / hsub;
696 uint16_t cbcr_src_h = src_h / vsub;
697 uint16_t vsu_mode;
698 uint16_t lb_mode;
699 uint32_t val;
700 int vskiplines = 0;
701
702 if (!vop->win->scl)
703 return;
704
705 if (!vop->win->scl->ext) {
706 VOP_SCL_SET(vop, scale_yrgb_x,
707 scl_cal_scale2(src_w, dst_w));
708 VOP_SCL_SET(vop, scale_yrgb_y,
709 scl_cal_scale2(src_h, dst_h));
710 if (is_yuv) {
711 VOP_SCL_SET(vop, scale_cbcr_x,
712 scl_cal_scale2(src_w, dst_w));
713 VOP_SCL_SET(vop, scale_cbcr_y,
714 scl_cal_scale2(src_h, dst_h));
715 }
716 return;
717 }
718
719 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
720 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
721
722 if (is_yuv) {
723 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
724 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
725 if (cbcr_hor_scl_mode == SCALE_DOWN)
726 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
727 else
728 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
729 } else {
730 if (yrgb_hor_scl_mode == SCALE_DOWN)
731 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
732 else
733 lb_mode = scl_vop_cal_lb_mode(src_w, false);
734 }
735
736 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode);
737 if (lb_mode == LB_RGB_3840X2) {
738 if (yrgb_ver_scl_mode != SCALE_NONE) {
739 printf("ERROR : not allow yrgb ver scale\n");
740 return;
741 }
742 if (cbcr_ver_scl_mode != SCALE_NONE) {
743 printf("ERROR : not allow cbcr ver scale\n");
744 return;
745 }
746 vsu_mode = SCALE_UP_BIL;
747 } else if (lb_mode == LB_RGB_2560X4) {
748 vsu_mode = SCALE_UP_BIL;
749 } else {
750 vsu_mode = SCALE_UP_BIC;
751 }
752
753 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
754 true, 0, NULL);
755 VOP_SCL_SET(vop, scale_yrgb_x, val);
756 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
757 false, vsu_mode, &vskiplines);
758 VOP_SCL_SET(vop, scale_yrgb_y, val);
759
760 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4);
761 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2);
762
763 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
764 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
765 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL);
766 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL);
767 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode);
768 if (is_yuv) {
769 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
770 dst_w, true, 0, NULL);
771 VOP_SCL_SET(vop, scale_cbcr_x, val);
772 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
773 dst_h, false, vsu_mode, &vskiplines);
774 VOP_SCL_SET(vop, scale_cbcr_y, val);
775
776 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4);
777 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2);
778 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
779 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
780 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL);
781 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL);
782 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode);
783 }
784 }
785
vop_load_csc_table(struct vop * vop,u32 offset,const u32 * table)786 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
787 {
788 int i;
789
790 /*
791 * so far the csc offset is not 0 and in the feature the csc offset
792 * impossible be 0, so when the offset is 0, should return here.
793 */
794 if (!table || offset == 0)
795 return;
796
797 for (i = 0; i < 8; i++)
798 vop_writel(vop, offset + i * 4, table[i]);
799 }
800
rockchip_vop_setup_csc_table(struct display_state * state)801 static int rockchip_vop_setup_csc_table(struct display_state *state)
802 {
803 struct crtc_state *crtc_state = &state->crtc_state;
804 struct connector_state *conn_state = &state->conn_state;
805 struct vop *vop = crtc_state->private;
806 const uint32_t *csc_table = NULL;
807
808 if (!vop->csc_table || !crtc_state->yuv_overlay)
809 return 0;
810 /* todo: only implement r2y*/
811 switch (conn_state->color_encoding) {
812 case DRM_COLOR_YCBCR_BT601:
813 if (conn_state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
814 csc_table = vop->csc_table->r2y_bt601_12_235; /* bt601 limit */
815 else
816 csc_table = vop->csc_table->r2y_bt601; /* bt601 full */
817 break;
818 case DRM_COLOR_YCBCR_BT709:
819 csc_table = vop->csc_table->r2y_bt709;
820 break;
821 case DRM_COLOR_YCBCR_BT2020:
822 csc_table = vop->csc_table->r2y_bt2020;
823 break;
824 default:
825 csc_table = vop->csc_table->r2y_bt601; /* bt601 full */
826 break;
827 }
828
829 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table);
830 VOP_WIN_CSC_SET(vop, r2y_en, 1);
831
832 return 0;
833 }
834
rockchip_vop_set_plane(struct display_state * state)835 static int rockchip_vop_set_plane(struct display_state *state)
836 {
837 struct crtc_state *crtc_state = &state->crtc_state;
838 const struct rockchip_crtc *crtc = crtc_state->crtc;
839 const struct vop_data *vop_data = crtc->data;
840 struct connector_state *conn_state = &state->conn_state;
841 struct drm_display_mode *mode = &conn_state->mode;
842 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty;
843 struct vop *vop = crtc_state->private;
844 int src_w = crtc_state->src_rect.w;
845 int src_h = crtc_state->src_rect.h;
846 int crtc_x = crtc_state->crtc_rect.x;
847 int crtc_y = crtc_state->crtc_rect.y;
848 int crtc_w = crtc_state->crtc_rect.w;
849 int crtc_h = crtc_state->crtc_rect.h;
850 int xvir = crtc_state->xvir;
851 int x_mirror = 0, y_mirror = 0;
852
853 if (crtc_w > crtc_state->max_output.width) {
854 printf("ERROR: output w[%d] exceeded max width[%d]\n",
855 crtc_w, crtc_state->max_output.width);
856 return -EINVAL;
857 }
858
859 if ((vop->version == VOP_VERSION_RK3036 || vop->version >= VOP_VERSION_RK3576_LITE) &&
860 (mode->flags & DRM_MODE_FLAG_INTERLACE))
861 crtc_h = crtc_h / 2;
862
863 act_info = (src_h - 1) << 16;
864 act_info |= (src_w - 1) & 0xffff;
865
866 dsp_info = (crtc_h - 1) << 16;
867 dsp_info |= (crtc_w - 1) & 0xffff;
868
869 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start;
870 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start;
871 if ((vop->version == VOP_VERSION_RK3036 || vop->version >= VOP_VERSION_RK3576_LITE) &&
872 (mode->flags & DRM_MODE_FLAG_INTERLACE))
873 dsp_sty = crtc_y / 2 + mode->crtc_vtotal - mode->crtc_vsync_start;
874 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
875 /*
876 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround
877 */
878 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3)
879 crtc_state->rb_swap = !crtc_state->rb_swap;
880
881 if (mode->flags & DRM_MODE_FLAG_YMIRROR)
882 y_mirror = 1;
883 else
884 y_mirror = 0;
885 if (mode->flags & DRM_MODE_FLAG_XMIRROR)
886 x_mirror = 1;
887 else
888 x_mirror = 0;
889 if (crtc_state->ymirror ^ y_mirror)
890 y_mirror = 1;
891 else
892 y_mirror = 0;
893 if (y_mirror) {
894 if (VOP_CTRL_SUPPORT(vop, ymirror))
895 crtc_state->dma_addr += (src_h - 1) * xvir * 4;
896 else
897 y_mirror = 0;
898 }
899 VOP_CTRL_SET(vop, ymirror, y_mirror);
900 VOP_CTRL_SET(vop, xmirror, x_mirror);
901
902 VOP_WIN_SET(vop, format, crtc_state->format);
903
904 VOP_WIN_SET(vop, interlace_read, (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
905
906 VOP_WIN_SET(vop, yrgb_vir, xvir);
907 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr);
908
909 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h,
910 crtc_state->format);
911
912 VOP_WIN_SET(vop, act_info, act_info);
913 VOP_WIN_SET(vop, dsp_info, dsp_info);
914 VOP_WIN_SET(vop, dsp_st, dsp_st);
915 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap);
916
917 VOP_WIN_SET(vop, src_alpha_ctl, 0);
918
919 rockchip_vop_setup_csc_table(state);
920 VOP_WIN_SET(vop, enable, 1);
921 VOP_WIN_SET(vop, gate, 1);
922 vop_cfg_done(vop);
923
924 printf("VOP:0x%8p set plane [%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n",
925 vop->regs, crtc_state->src_rect.w, crtc_state->src_rect.h,
926 crtc_state->crtc_rect.w, crtc_state->crtc_rect.h,
927 crtc_state->crtc_rect.x, crtc_state->crtc_rect.y,
928 crtc_state->format, crtc_state->dma_addr);
929
930 return 0;
931 }
932
rockchip_vop_prepare(struct display_state * state)933 static int rockchip_vop_prepare(struct display_state *state)
934 {
935 return 0;
936 }
937
rockchip_vop_enable(struct display_state * state)938 static int rockchip_vop_enable(struct display_state *state)
939 {
940 struct crtc_state *crtc_state = &state->crtc_state;
941 struct vop *vop = crtc_state->private;
942
943 VOP_CTRL_SET(vop, standby, 0);
944 vop_cfg_done(vop);
945 if (crtc_state->mcu_timing.mcu_pix_total > 0)
946 VOP_CTRL_SET(vop, mcu_hold_mode, 0);
947
948 return 0;
949 }
950
rockchip_vop_disable(struct display_state * state)951 static int rockchip_vop_disable(struct display_state *state)
952 {
953 struct crtc_state *crtc_state = &state->crtc_state;
954 struct vop *vop = crtc_state->private;
955
956 VOP_CTRL_SET(vop, standby, 1);
957 vop_cfg_done(vop);
958 return 0;
959 }
960
rockchip_vop_fixup_dts(struct display_state * state,void * blob)961 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob)
962 {
963 #if 0
964 struct crtc_state *crtc_state = &state->crtc_state;
965 struct panel_state *pstate = &state->panel_state;
966 uint32_t phandle;
967 char path[100];
968 int ret, dsp_lut_node;
969
970 if (!ofnode_valid(pstate->dsp_lut_node))
971 return 0;
972 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path));
973 if (ret < 0) {
974 printf("failed to get dsp_lut path[%s], ret=%d\n",
975 path, ret);
976 return ret;
977 }
978
979 dsp_lut_node = fdt_path_offset(blob, path);
980 phandle = fdt_get_phandle(blob, dsp_lut_node);
981 if (!phandle) {
982 phandle = fdt_alloc_phandle(blob);
983 if (!phandle) {
984 printf("failed to alloc phandle\n");
985 return -ENOMEM;
986 }
987
988 fdt_set_phandle(blob, dsp_lut_node, phandle);
989 }
990
991 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path));
992 if (ret < 0) {
993 printf("failed to get route path[%s], ret=%d\n",
994 path, ret);
995 return ret;
996 }
997
998 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1);
999 #endif
1000 return 0;
1001 }
1002
rockchip_vop_send_mcu_cmd(struct display_state * state,u32 type,u32 value)1003 static int rockchip_vop_send_mcu_cmd(struct display_state *state, u32 type, u32 value)
1004 {
1005 struct crtc_state *crtc_state = &state->crtc_state;
1006 struct connector_state *conn_state = &state->conn_state;
1007 struct drm_display_mode *mode = &conn_state->mode;
1008 struct vop *vop = crtc_state->private;
1009 int ret;
1010
1011 if (vop->version >= VOP_VERSION_RK3576_LITE) {
1012 /*
1013 * 1.set mcu bypass mode timing.
1014 * 2.set dclk rate to 150M.
1015 */
1016 if ((type == MCU_SETBYPASS) && value) {
1017 vop_mcu_bypass_mode_setup(state, vop);
1018 ret = clk_set_rate(&crtc_state->dclk, 150000000);
1019 if (IS_ERR_VALUE(ret)) {
1020 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret);
1021 return ret;
1022 }
1023 }
1024 }
1025
1026 if (vop) {
1027 switch (type) {
1028 case MCU_WRCMD:
1029 VOP_CTRL_SET(vop, mcu_force_rdn, 1);
1030 set_vop_mcu_rs(vop, 0);
1031 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value);
1032 set_vop_mcu_rs(vop, 1);
1033 break;
1034 case MCU_WRDATA:
1035 VOP_CTRL_SET(vop, mcu_force_rdn, 1);
1036 set_vop_mcu_rs(vop, 1);
1037 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value);
1038 break;
1039 case MCU_SETBYPASS:
1040 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0);
1041 if (!value)
1042 VOP_CTRL_SET(vop, mcu_force_rdn, 1);
1043 break;
1044 default:
1045 break;
1046 }
1047 }
1048
1049 if (vop->version >= VOP_VERSION_RK3576_LITE) {
1050 /*
1051 * 1.restore mcu data mode timing.
1052 * 2.restore dclk rate to crtc_clock.
1053 */
1054 if ((type == MCU_SETBYPASS) && !value) {
1055 vop_mcu_mode_setup(state, vop);
1056 ret = clk_set_rate(&crtc_state->dclk, mode->crtc_clock * 1000);
1057 if (IS_ERR_VALUE(ret)) {
1058 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret);
1059 return ret;
1060 }
1061 }
1062 }
1063
1064 return 0;
1065 }
1066
rockchip_vop_mode_valid(struct display_state * state)1067 static int rockchip_vop_mode_valid(struct display_state *state)
1068 {
1069 struct connector_state *conn_state = &state->conn_state;
1070 struct drm_display_mode *mode = &conn_state->mode;
1071 struct videomode vm;
1072
1073 drm_display_mode_to_videomode(mode, &vm);
1074
1075 if (vm.hactive < 32 || vm.vactive < 32 ||
1076 (vm.hfront_porch * vm.hsync_len * vm.hback_porch *
1077 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) {
1078 printf("ERROR: unsupported display timing\n");
1079 return -EINVAL;
1080 }
1081
1082 return 0;
1083 }
1084
rockchip_vop_plane_check(struct display_state * state)1085 static int rockchip_vop_plane_check(struct display_state *state)
1086 {
1087 struct crtc_state *crtc_state = &state->crtc_state;
1088 const struct rockchip_crtc *crtc = crtc_state->crtc;
1089 const struct vop_data *vop_data = crtc->data;
1090 const struct vop_win *win = vop_data->win;
1091 struct display_rect *src = &crtc_state->src_rect;
1092 struct display_rect *dst = &crtc_state->crtc_rect;
1093 int min_scale, max_scale;
1094 int hscale, vscale;
1095
1096 min_scale = win->scl ? FRAC_16_16(1, 8) : VOP_PLANE_NO_SCALING;
1097 max_scale = win->scl ? FRAC_16_16(8, 1) : VOP_PLANE_NO_SCALING;
1098
1099 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale);
1100 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale);
1101 if (hscale < 0 || vscale < 0) {
1102 printf("ERROR: scale factor is out of range\n");
1103 return -ERANGE;
1104 }
1105
1106 return 0;
1107 }
1108
rockchip_vop_mode_fixup(struct display_state * state)1109 static int rockchip_vop_mode_fixup(struct display_state *state)
1110 {
1111 struct crtc_state *crtc_state = &state->crtc_state;
1112 const struct rockchip_crtc *crtc = crtc_state->crtc;
1113 const struct vop_data *vop_data = crtc->data;
1114 struct connector_state *conn_state = &state->conn_state;
1115 struct drm_display_mode *mode = &conn_state->mode;
1116
1117 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1118
1119 /*
1120 * Dclk need to be double if BT656 interface and vop version >= 2.12.
1121 */
1122 if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
1123 (vop_data->version >= VOP_VERSION_RV1106 && vop_data->version < VOP_VERSION_RK3288 &&
1124 conn_state->output_if & VOP_OUTPUT_IF_BT656))
1125 mode->crtc_clock *= 2;
1126
1127 mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(conn_state->bus_format);
1128 if (crtc_state->mcu_timing.mcu_pix_total)
1129 mode->crtc_clock *= crtc_state->mcu_timing.mcu_pix_total + 1;
1130
1131 return 0;
1132 }
1133
1134 const struct rockchip_crtc_funcs rockchip_vop_funcs = {
1135 .preinit = rockchip_vop_preinit,
1136 .init = rockchip_vop_init,
1137 .set_plane = rockchip_vop_set_plane,
1138 .prepare = rockchip_vop_prepare,
1139 .enable = rockchip_vop_enable,
1140 .disable = rockchip_vop_disable,
1141 .fixup_dts = rockchip_vop_fixup_dts,
1142 .send_mcu_cmd = rockchip_vop_send_mcu_cmd,
1143 .mode_valid = rockchip_vop_mode_valid,
1144 .plane_check = rockchip_vop_plane_check,
1145 .mode_fixup = rockchip_vop_mode_fixup,
1146 };
1147