1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright 2018-2021 NXP
4 *
5 * Brief CAAM Random Number Generator Hardware Abstration Layer.
6 * Implementation of primitives to access HW.
7 */
8 #include <caam_hal_ctrl.h>
9 #include <caam_hal_rng.h>
10 #include <caam_io.h>
11 #include <caam_status.h>
12 #include <registers/rng_regs.h>
13 #include <registers/version_regs.h>
14
caam_hal_rng_instantiated(vaddr_t baseaddr)15 enum caam_status __weak caam_hal_rng_instantiated(vaddr_t baseaddr)
16 {
17 uint32_t vid = 0;
18 uint32_t nb_sh = 0;
19 uint32_t status = 0;
20
21 /* RNG version < 4 and RNG state handle is already instantiated */
22 if (caam_hal_ctrl_era(baseaddr) < 10) {
23 vid = io_caam_read32(baseaddr + CHAVID_LS);
24
25 if (GET_CHAVID_LS_RNGVID(vid) < 4)
26 return CAAM_NO_ERROR;
27 } else {
28 vid = io_caam_read32(baseaddr + RNG_VERSION);
29
30 if (GET_RNG_VERSION_VID(vid) < 4)
31 return CAAM_NO_ERROR;
32 }
33
34 /* Get the Number of State Handles */
35 nb_sh = caam_hal_rng_get_nb_sh(baseaddr);
36
37 /* Read the RNG Status and checks if all channels are instantiatied */
38 status = caam_hal_rng_get_sh_status(baseaddr);
39
40 if (status != GENMASK_32(nb_sh - 1, 0))
41 return CAAM_NOT_INIT;
42
43 return CAAM_NO_ERROR;
44 }
45
caam_hal_rng_get_nb_sh(vaddr_t baseaddr)46 uint32_t caam_hal_rng_get_nb_sh(vaddr_t baseaddr)
47 {
48 uint32_t reg = 0;
49
50 reg = io_caam_read32(baseaddr + CTPR_MS);
51
52 return GET_CTPR_MS_RNG_I(reg);
53 }
54
caam_hal_rng_get_sh_status(vaddr_t baseaddr)55 uint32_t caam_hal_rng_get_sh_status(vaddr_t baseaddr)
56 {
57 return io_caam_read32(baseaddr + RNG_STA) & (RNG_STA_IF1 | RNG_STA_IF0);
58 }
59
caam_hal_rng_key_loaded(vaddr_t baseaddr)60 bool caam_hal_rng_key_loaded(vaddr_t baseaddr)
61 {
62 return io_caam_read32(baseaddr + RNG_STA) & RNG_STA_SKVN;
63 }
64
65 /*
66 * This function will be overridden for i.MX8QX and i.MX8DX platforms.
67 */
caam_hal_rng_pr_enabled(vaddr_t baseaddr)68 bool __weak caam_hal_rng_pr_enabled(vaddr_t baseaddr)
69 {
70 uint32_t bitmask = RNG_STA_PR0;
71
72 if (caam_hal_rng_get_nb_sh(baseaddr) > 1)
73 bitmask |= RNG_STA_PR1;
74
75 return (io_caam_read32(baseaddr + RNG_STA) & bitmask) == bitmask;
76 }
77
caam_hal_rng_kick(vaddr_t baseaddr,uint32_t inc_delay)78 enum caam_status caam_hal_rng_kick(vaddr_t baseaddr, uint32_t inc_delay)
79 {
80 uint32_t val = 0;
81 uint32_t ent_delay = TRNG_SDCTL_ENT_DLY_MIN + inc_delay;
82
83 if (ent_delay > TRNG_SDCTL_ENT_DLY_MAX)
84 return CAAM_OUT_OF_BOUND;
85
86 /*
87 * Switch RNG in program mode
88 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
89 * properly invalidate the entropy in the entropy register and
90 * force re-generation
91 */
92 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_PRGM | TRNG_MCTL_ACC);
93
94 /*
95 * Configure the RNG Entropy Delay
96 * Performance-wise, it does not make sense to
97 * set the delay to a value that is lower
98 * than the last one that worked (i.e. the state handles
99 * were instantiated correctly). Thus, instead of wasting
100 * time trying to set the values controlling the sample
101 * frequency, the function simply returns.
102 */
103 val = io_caam_read32(baseaddr + TRNG_SDCTL);
104 val = GET_TRNG_SDCTL_ENT_DLY(val);
105
106 if (ent_delay < val) {
107 /*
108 * In this case do the programmation anyway because on some
109 * device the other registers value can be wrong.
110 */
111 ent_delay = val;
112 }
113
114 io_caam_write32(baseaddr + TRNG_SDCTL, TRNG_SDCTL_ENT_DLY(ent_delay) |
115 TRNG_SDCTL_SAMP_SIZE(512));
116
117 /* min. freq. count, equal to 1/4 of the entropy sample length */
118 io_caam_write32(baseaddr + TRNG_FRQMIN, ent_delay >> 2);
119
120 /* max. freq. count, equal to 16 times the entropy sample length */
121 io_caam_write32(baseaddr + TRNG_FRQMAX, ent_delay << 4);
122
123 io_caam_write32(baseaddr + TRNG_RTSCMISC,
124 TRNG_RTSCMISC_RTY_CNT(2) | TRNG_RTSCMISC_LRUN_MAX(32));
125 io_caam_write32(baseaddr + TRNG_RTPKRRNG, TRNG_RTPKRRNG_PKR_RNG(570));
126 io_caam_write32(baseaddr + TRNG_RTPKRMAX, TRNG_RTPKRMAX_PKR_MAX(1600));
127 io_caam_write32(baseaddr + TRNG_RTSCML,
128 TRNG_RTSCML_MONO_RNG(122) | TRNG_RTSCML_MONO_MAX(317));
129 io_caam_write32(baseaddr + TRNG_RTSCR1L,
130 TRNG_RTSCR1L_RUN1_RNG(80) | TRNG_RTSCR1L_RUN1_MAX(107));
131 io_caam_write32(baseaddr + TRNG_RTSCR2L,
132 TRNG_RTSCR2L_RUN2_RNG(57) | TRNG_RTSCR2L_RUN2_MAX(62));
133 io_caam_write32(baseaddr + TRNG_RTSCR3L,
134 TRNG_RTSCR3L_RUN3_RNG(39) | TRNG_RTSCR3L_RUN3_MAX(39));
135 io_caam_write32(baseaddr + TRNG_RTSCR4L,
136 TRNG_RTSCR4L_RUN4_RNG(27) | TRNG_RTSCR4L_RUN4_MAX(26));
137 io_caam_write32(baseaddr + TRNG_RTSCR5L,
138 TRNG_RTSCR5L_RUN5_RNG(19) | TRNG_RTSCR5L_RUN5_MAX(18));
139 io_caam_write32(baseaddr + TRNG_RTSCR6PL,
140 TRNG_RTSCR5L_RUN5_RNG(18) | TRNG_RTSCR5L_RUN5_MAX(17));
141
142 val = io_caam_read32(baseaddr + TRNG_MCTL);
143 /*
144 * Select raw sampling in both entropy shifter
145 * and statistical checker
146 */
147 val &= ~BM_TRNG_MCTL_SAMP_MODE;
148 val |= TRNG_MCTL_SAMP_MODE_RAW_ES_SC;
149 /* Put RNG4 into run mode with handling CAAM/RNG4-TRNG Errata */
150 val &= ~(TRNG_MCTL_PRGM | TRNG_MCTL_ACC);
151 io_caam_write32(baseaddr + TRNG_MCTL, val);
152
153 /*
154 * Clear the ERR bit in RTMCTL if set. The TRNG error can occur when
155 * the RNG clock is not within 1/2x to 8x the system clock.
156 * This error is possible if ROM code does not initialize the system
157 * PLLs immediately after PoR.
158 */
159 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_ERR);
160
161 return CAAM_NO_ERROR;
162 }
163