1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44cpu_reset_func_start c1_pro 45 /* ---------------------------------------------------- 46 * Disable speculative loads 47 * ---------------------------------------------------- 48 */ 49 msr SSBS, xzr 50 /* model bug: not cleared on reset */ 51 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 52 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 53 enable_mpmm 54cpu_reset_func_end c1_pro 55 56 /* ---------------------------------------------------- 57 * HW will do the cache maintenance while powering down 58 * ---------------------------------------------------- 59 */ 60func c1_pro_core_pwr_dwn 61 /* --------------------------------------------------- 62 * Flip CPU power down bit in power control register. 63 * It will be set on powerdown and cleared on wakeup 64 * --------------------------------------------------- 65 */ 66 sysreg_bit_set C1_PRO_IMP_CPUPWRCTLR_EL1, \ 67 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 68 isb 69 signal_pabandon_handled 70 ret 71endfunc c1_pro_core_pwr_dwn 72 73 /* --------------------------------------------- 74 * This function provides Arm C1-Pro specific 75 * register information for crash reporting. 76 * It needs to return with x6 pointing to 77 * a list of register names in ascii and 78 * x8 - x15 having values of registers to be 79 * reported. 80 * --------------------------------------------- 81 */ 82.section .rodata.c1_pro_regs, "aS" 83c1_pro_regs: /* The ASCII list of register names to be reported */ 84 .asciz "imp_cpuectlr_el1", "" 85 86func c1_pro_cpu_reg_dump 87 adr x6, c1_pro_regs 88 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 89 ret 90endfunc c1_pro_cpu_reg_dump 91 92declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 93 c1_pro_reset_func, \ 94 c1_pro_core_pwr_dwn 95