1/* 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <common/bl_common.h> 9#include <el3_common_macros.S> 10 11 .globl bl1_entrypoint 12 .globl bl1_run_bl2_in_root 13 14 15 /* ----------------------------------------------------- 16 * bl1_entrypoint() is the entry point into the trusted 17 * firmware code when a cpu is released from warm or 18 * cold reset. 19 * ----------------------------------------------------- 20 */ 21 22func bl1_entrypoint 23 /* --------------------------------------------------------------------- 24 * If the reset address is programmable then bl1_entrypoint() is 25 * executed only on the cold boot path. Therefore, we can skip the warm 26 * boot mailbox mechanism. 27 * --------------------------------------------------------------------- 28 */ 29 el3_entrypoint_common \ 30 _init_sctlr=1 \ 31 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 32 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 33 _init_memory=1 \ 34 _init_c_runtime=1 \ 35 _exception_vectors=bl1_exceptions \ 36 _pie_fixup_size=0 37 38 /* -------------------------------------------------------------------- 39 * Initialize platform and jump to our c-entry point 40 * for this type of reset. 41 * -------------------------------------------------------------------- 42 */ 43 bl bl1_main 44 45 /* -------------------------------------------------- 46 * Do the transition to next boot image. 47 * -------------------------------------------------- 48 */ 49#if ENABLE_RME 50 b bl1_run_bl2_in_root 51#else 52 b el3_exit 53#endif 54endfunc bl1_entrypoint 55 56 /* ----------------------------------------------------- 57 * void bl1_run_bl2_in_root(); 58 * This function runs BL2 in root/EL3 when RME is enabled. 59 * ----------------------------------------------------- 60 */ 61 62func bl1_run_bl2_in_root 63 /* read bl2_ep_info */ 64 adrp x20, bl2_ep_info 65 add x20, x20, :lo12:bl2_ep_info 66 ldr x20, [x20] 67 68 /* --------------------------------------------- 69 * MMU needs to be disabled because BL2 executes 70 * in EL3. It will initialize the address space 71 * according to its own requirements. 72 * --------------------------------------------- 73 */ 74 bl disable_mmu_icache_el3 75 tlbi alle3 76 77 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 78 msr elr_el3, x0 79 msr spsr_el3, x1 80 81 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 82 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 83 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 84 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 85 exception_return 86endfunc bl1_run_bl2_in_root 87