1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * aw_bin_parse.c
4 *
5 * Copyright (c) 2020 AWINIC Technology CO., LTD
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/i2c.h>
16 #include <linux/of_gpio.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/firmware.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/input.h>
23 #include <linux/interrupt.h>
24 #include <linux/debugfs.h>
25 #include <linux/miscdevice.h>
26 #include <linux/uaccess.h>
27 #include <linux/regmap.h>
28 #include <linux/timer.h>
29 #include <linux/workqueue.h>
30 #include <linux/hrtimer.h>
31 #include <linux/mutex.h>
32 #include <linux/cdev.h>
33 #include <linux/list.h>
34 #include <linux/string.h>
35 #include "aw_bin_parse.h"
36 #include "aw_log.h"
37
38 /* "code version"-"excel version" */
39 #define AWINIC_CODE_VERSION "V0.0.8-V1.0.4"
40
41 #define DEBUG_LOG_LEVEL
42 #ifdef DEBUG_LOG_LEVEL
43 #define DBG(fmt, arg...) do {\
44 pr_debug("AWINIC_BIN %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
45 } while (0)
46 #define DBG_ERR(fmt, arg...) do {\
47 pr_err("AWINIC_BIN_ERR %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
48 } while (0)
49 #else
50 #define DBG(fmt, arg...) do {} while (0)
51 #define DBG_ERR(fmt, arg...) do {} while (0)
52 #endif
53
54 #define printing_data_code
55
56 typedef unsigned short int aw_uint16;
57 typedef unsigned long int aw_uint32;
58
59 #define BigLittleSwap16(A) ((((aw_uint16)(A) & 0xff00) >> 8) | \
60 (((aw_uint16)(A) & 0x00ff) << 8))
61
62 #define BigLittleSwap32(A) ((((aw_uint32)(A) & 0xff000000) >> 24) | \
63 (((aw_uint32)(A) & 0x00ff0000) >> 8) | \
64 (((aw_uint32)(A) & 0x0000ff00) << 8) | \
65 (((aw_uint32)(A) & 0x000000ff) << 24))
66
67 static char *profile_name[AW_PROFILE_MAX] = {"Music", "Voice", "Voip", "Ringtone", "Ringtone_hs", "Lowpower",
68 "Bypass", "Mmi", "Fm", "Notification", "Receiver"};
69
70 /**
71 *
72 * Interface function
73 *
74 * return value:
75 * value = 0 :success;
76 * value = -1 :check bin header version
77 * value = -2 :check bin data type
78 * value = -3 :check sum or check bin data len error
79 * value = -4 :check data version
80 * value = -5 :check register num
81 * value = -6 :check dsp reg num
82 * value = -7 :check soc app num
83 * value = -8 :bin is NULL point
84 *
85 */
86
87 /********************************************************
88 *
89 * check sum data
90 *
91 ********************************************************/
aw_check_sum(struct aw_bin * bin,int bin_num)92 static int aw_check_sum(struct aw_bin *bin, int bin_num)
93 {
94 unsigned int i = 0;
95 unsigned int sum_data = 0;
96 unsigned int check_sum = 0;
97 char *p_check_sum = NULL;
98
99 DBG("enter\n");
100 p_check_sum = &(bin->info.data[(bin->header_info[bin_num].
101 valid_data_addr - bin->header_info[bin_num].header_len)]);
102 DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
103 check_sum = GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2),
104 *(p_check_sum + 1), *(p_check_sum));
105
106 for (i = 4; i < bin->header_info[bin_num].bin_data_len + bin->
107 header_info[bin_num].header_len; i++) {
108 sum_data += *(p_check_sum + i);
109 }
110 DBG("aw_bin_parse bin_num = %d, check_sum = 0x%x, sum_data = 0x%x\n",
111 bin_num, check_sum, sum_data);
112 if (sum_data != check_sum) {
113 p_check_sum = NULL;
114 DBG_ERR("aw_bin_parse check sum or check bin data len error\n");
115 DBG_ERR("aw_bin_parse bin_num = %d\n", bin_num);
116 DBG_ERR("aw_bin_parse check_sum = 0x%x\n", check_sum);
117 DBG_ERR("aw_bin_parse sum_data = 0x%x\n", sum_data);
118 return -BIN_DATA_LEN_ERR;
119 }
120 p_check_sum = NULL;
121
122 return 0;
123 }
124
aw_check_data_version(struct aw_bin * bin,int bin_num)125 static int aw_check_data_version(struct aw_bin *bin, int bin_num)
126 {
127 int i = 0;
128
129 DBG("enter\n");
130 for (i = DATA_VERSION_V1; i < DATA_VERSION_MAX; i++) {
131 if (bin->header_info[bin_num].bin_data_ver == i)
132 return 0;
133 }
134 DBG_ERR("aw_bin_parse Unrecognized this bin data version\n");
135 return -DATA_VER_ERR;
136 }
137
aw_check_register_num_v1(struct aw_bin * bin,int bin_num)138 static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
139 {
140 unsigned int check_register_num = 0;
141 unsigned int parse_register_num = 0;
142 char *p_check_sum = NULL;
143
144 DBG("enter\n");
145 p_check_sum = &(bin->info.data[(bin->header_info[bin_num].
146 valid_data_addr)]);
147 DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
148 parse_register_num = GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2),
149 *(p_check_sum + 1), *(p_check_sum));
150 check_register_num = (bin->header_info[bin_num].bin_data_len - 4) /
151 (bin->header_info[bin_num].reg_byte_len +
152 bin->header_info[bin_num].data_byte_len);
153 DBG("aw_bin_parse bin_num = %d\n", bin_num);
154 DBG("aw_bin_parse parse_register_num = 0x%x\n", parse_register_num);
155 DBG("aw_bin_parse check_register_num = 0x%x\n", check_register_num);
156 if (parse_register_num != check_register_num) {
157 p_check_sum = NULL;
158 DBG_ERR("aw_bin_parse check register num error\n");
159 DBG_ERR("aw_bin_parse bin_num = %d\n", bin_num);
160 DBG_ERR("aw_bin_parse parse_register_num = 0x%x\n",
161 parse_register_num);
162 DBG_ERR("aw_bin_parse check_register_num = 0x%x\n",
163 check_register_num);
164 return -REG_NUM_ERR;
165 }
166 bin->header_info[bin_num].reg_num = parse_register_num;
167 bin->header_info[bin_num].valid_data_len = bin->header_info[bin_num].
168 bin_data_len - 4;
169 p_check_sum = NULL;
170 bin->header_info[bin_num].valid_data_addr = bin->header_info[bin_num].
171 valid_data_addr + 4;
172 return 0;
173 }
174
aw_check_dsp_reg_num_v1(struct aw_bin * bin,int bin_num)175 static int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
176 {
177 unsigned int check_dsp_reg_num = 0;
178 unsigned int parse_dsp_reg_num = 0;
179 char *p_check_sum = NULL;
180
181 DBG("enter\n");
182 p_check_sum = &(bin->info.data[(bin->header_info[bin_num].
183 valid_data_addr)]);
184 DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
185 parse_dsp_reg_num = GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6),
186 *(p_check_sum + 5), *(p_check_sum + 4));
187 bin->header_info[bin_num].reg_data_byte_len =
188 GET_32_DATA(*(p_check_sum + 11), *(p_check_sum + 10),
189 *(p_check_sum + 9), *(p_check_sum + 8));
190 check_dsp_reg_num = (bin->header_info[bin_num].bin_data_len - 12) /
191 bin->header_info[bin_num].reg_data_byte_len;
192 DBG("aw_bin_parse bin_num = %d\n", bin_num);
193 DBG("aw_bin_parse parse_dsp_reg_num = 0x%x\n", parse_dsp_reg_num);
194 DBG("aw_bin_parse check_dsp_reg_num = 0x%x\n", check_dsp_reg_num);
195 if (parse_dsp_reg_num != check_dsp_reg_num) {
196 p_check_sum = NULL;
197 DBG_ERR("aw_bin_parse check dsp reg num error\n");
198 DBG_ERR("aw_bin_parse bin_num = %d\n", bin_num);
199 DBG_ERR("aw_bin_parse parse_dsp_reg_num = 0x%x\n",
200 parse_dsp_reg_num);
201 DBG_ERR("aw_bin_parse check_dsp_reg_num = 0x%x\n",
202 check_dsp_reg_num);
203 return -DSP_REG_NUM_ERR;
204 }
205 bin->header_info[bin_num].download_addr =
206 GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2),
207 *(p_check_sum + 1), *(p_check_sum));
208 bin->header_info[bin_num].reg_num = parse_dsp_reg_num;
209 bin->header_info[bin_num].valid_data_len = bin->header_info[bin_num].
210 bin_data_len - 12;
211 p_check_sum = NULL;
212 bin->header_info[bin_num].valid_data_addr = bin->header_info[bin_num].
213 valid_data_addr + 12;
214 return 0;
215 }
216
aw_check_soc_app_num_v1(struct aw_bin * bin,int bin_num)217 static int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
218 {
219 unsigned int check_soc_app_num = 0;
220 unsigned int parse_soc_app_num = 0;
221 char *p_check_sum = NULL;
222
223 DBG("enter\n");
224 p_check_sum = &(bin->info.data[(bin->header_info[bin_num].
225 valid_data_addr)]);
226 DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
227 bin->header_info[bin_num].app_version = GET_32_DATA(*(p_check_sum + 3),
228 *(p_check_sum + 2), *(p_check_sum + 1), *(p_check_sum));
229 parse_soc_app_num = GET_32_DATA(*(p_check_sum + 11),
230 *(p_check_sum + 10), *(p_check_sum + 9), *(p_check_sum + 8));
231 check_soc_app_num = bin->header_info[bin_num].bin_data_len - 12;
232 DBG("aw_bin_parse bin_num = %d\n", bin_num);
233 DBG("aw_bin_parse parse_soc_app_num = 0x%x\n", parse_soc_app_num);
234 DBG("aw_bin_parse check_soc_app_num = 0x%x\n", check_soc_app_num);
235 if (parse_soc_app_num != check_soc_app_num) {
236 p_check_sum = NULL;
237 DBG_ERR("aw_bin_parse check soc app num error\n");
238 DBG_ERR("aw_bin_parse bin_num = %d\n", bin_num);
239 DBG_ERR("aw_bin_parse parse_soc_app_num = 0x%x\n",
240 parse_soc_app_num);
241 DBG_ERR("aw_bin_parse check_soc_app_num = 0x%x\n",
242 check_soc_app_num);
243 return -SOC_APP_NUM_ERR;
244 }
245 bin->header_info[bin_num].reg_num = parse_soc_app_num;
246 bin->header_info[bin_num].download_addr =
247 GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6),
248 *(p_check_sum + 5), *(p_check_sum + 4));
249 bin->header_info[bin_num].valid_data_len = bin->header_info[bin_num].
250 bin_data_len - 12;
251 p_check_sum = NULL;
252 bin->header_info[bin_num].valid_data_addr = bin->header_info[bin_num].
253 valid_data_addr + 12;
254 return 0;
255 }
256 /********************************************************
257 *
258 * bin header 1_0_0
259 *
260 ********************************************************/
aw_get_single_bin_header_1_0_0(struct aw_bin * bin)261 static void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
262 {
263 int i;
264
265 DBG("enter %s\n", __func__);
266 bin->header_info[bin->all_bin_parse_num].header_len = 60;
267 bin->header_info[bin->all_bin_parse_num].check_sum =
268 GET_32_DATA(*(bin->p_addr + 3), *(bin->p_addr + 2),
269 *(bin->p_addr + 1), *(bin->p_addr));
270 bin->header_info[bin->all_bin_parse_num].header_ver =
271 GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6),
272 *(bin->p_addr + 5), *(bin->p_addr + 4));
273 bin->header_info[bin->all_bin_parse_num].bin_data_type =
274 GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10),
275 *(bin->p_addr + 9), *(bin->p_addr + 8));
276 bin->header_info[bin->all_bin_parse_num].bin_data_ver =
277 GET_32_DATA(*(bin->p_addr + 15), *(bin->p_addr + 14),
278 *(bin->p_addr + 13), *(bin->p_addr + 12));
279 bin->header_info[bin->all_bin_parse_num].bin_data_len =
280 GET_32_DATA(*(bin->p_addr + 19), *(bin->p_addr + 18),
281 *(bin->p_addr + 17), *(bin->p_addr + 16));
282 bin->header_info[bin->all_bin_parse_num].ui_ver =
283 GET_32_DATA(*(bin->p_addr + 23), *(bin->p_addr + 22),
284 *(bin->p_addr + 21), *(bin->p_addr + 20));
285 bin->header_info[bin->all_bin_parse_num].reg_byte_len =
286 GET_32_DATA(*(bin->p_addr + 35), *(bin->p_addr + 34),
287 *(bin->p_addr + 33), *(bin->p_addr + 32));
288 bin->header_info[bin->all_bin_parse_num].data_byte_len =
289 GET_32_DATA(*(bin->p_addr + 39), *(bin->p_addr + 38),
290 *(bin->p_addr + 37), *(bin->p_addr + 36));
291 bin->header_info[bin->all_bin_parse_num].device_addr =
292 GET_32_DATA(*(bin->p_addr + 43), *(bin->p_addr + 42),
293 *(bin->p_addr + 41), *(bin->p_addr + 40));
294 for (i = 0; i < 8; i++) {
295 bin->header_info[bin->all_bin_parse_num].chip_type[i] =
296 *(bin->p_addr + 24 + i);
297 }
298 bin->header_info[bin->all_bin_parse_num].reg_num = 0x00000000;
299 bin->header_info[bin->all_bin_parse_num].reg_data_byte_len = 0x00000000;
300 bin->header_info[bin->all_bin_parse_num].download_addr = 0x00000000;
301 bin->header_info[bin->all_bin_parse_num].app_version = 0x00000000;
302 bin->header_info[bin->all_bin_parse_num].valid_data_len = 0x00000000;
303 bin->all_bin_parse_num += 1;
304 }
305
aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num,int bin_serial_num,struct aw_bin * bin)306 static int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
307 struct aw_bin *bin)
308 {
309 int ret = 0;
310 unsigned int bin_start_addr = 0;
311 unsigned int valid_data_len = 0;
312
313 DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
314 if (!bin_serial_num) {
315 bin_start_addr = GET_32_DATA(*(bin->p_addr + 67), *(bin->p_addr
316 + 66), *(bin->p_addr + 65), *(bin->p_addr + 64));
317 bin->p_addr += (60 + bin_start_addr);
318 bin->header_info[bin->all_bin_parse_num].valid_data_addr =
319 bin->header_info[bin->all_bin_parse_num - 1].
320 valid_data_addr + 4 + 8 * bin_num + 60;
321 } else {
322 valid_data_len = bin->header_info[bin->all_bin_parse_num - 1].
323 bin_data_len;
324 bin->p_addr += (60 + valid_data_len);
325 bin->header_info[bin->all_bin_parse_num].valid_data_addr =
326 bin->header_info[bin->all_bin_parse_num - 1].valid_data_addr
327 + bin->header_info[bin->all_bin_parse_num - 1].bin_data_len
328 + 60;
329 }
330
331 ret = aw_parse_bin_header_1_0_0(bin);
332 return ret;
333 }
334
335 /* Get the number of bins in multi bins, and set a for loop,
336 * loop processing each bin data
337 */
aw_get_multi_bin_header_1_0_0(struct aw_bin * bin)338 static int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
339 {
340 int i = 0;
341 int ret = 0;
342 unsigned int bin_num = 0;
343
344 DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
345 bin_num = GET_32_DATA(*(bin->p_addr + 63), *(bin->p_addr + 62),
346 *(bin->p_addr + 61), *(bin->p_addr + 60));
347 if (bin->multi_bin_parse_num == 1)
348 bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
349 aw_get_single_bin_header_1_0_0(bin);
350
351 for (i = 0; i < bin_num; i++) {
352 DBG("aw_bin_parse enter multi bin for is %d\n", i);
353 ret = aw_parse_each_of_multi_bins_1_0_0(bin_num, i, bin);
354 if (ret < 0)
355 return ret;
356 }
357 return 0;
358 }
359
360 /********************************************************
361 *
362 * If the bin framework header version is 1.0.0,
363 * determine the data type of bin, and then perform different processing
364 * according to the data type
365 * If it is a single bin data type, write the data directly
366 * into the structure array
367 * If it is a multi-bin data type, first obtain the number of bins,
368 * and then recursively call the bin frame header processing function
369 * according to the bin number to process the frame header information
370 * of each bin separately
371 *
372 ********************************************************/
aw_parse_bin_header_1_0_0(struct aw_bin * bin)373 int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
374 {
375 int ret = 0;
376 unsigned int bin_data_type;
377
378 DBG("enter %s\n", __func__);
379 bin_data_type = GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10),
380 *(bin->p_addr + 9), *(bin->p_addr + 8));
381 DBG("aw_bin_parse bin_data_type 0x%x\n", bin_data_type);
382 switch (bin_data_type) {
383 case DATA_TYPE_REGISTER:
384 case DATA_TYPE_DSP_REG:
385 case DATA_TYPE_SOC_APP:
386 /* Divided into two processing methods,
387 * one is single bin processing,
388 * and the other is single bin processing in multi bin
389 */
390 DBG("aw_bin_parse enter single bin branch\n");
391 bin->single_bin_parse_num += 1;
392 DBG("%s bin->single_bin_parse_num is %d\n", __func__,
393 bin->single_bin_parse_num);
394 if (!bin->multi_bin_parse_num) {
395 bin->header_info[bin->all_bin_parse_num].
396 valid_data_addr = 60;
397 }
398 aw_get_single_bin_header_1_0_0(bin);
399 break;
400 case DATA_TYPE_MULTI_BINS:
401 /* Get the number of times to enter multi bins */
402 DBG("aw_bin_parse enter multi bin branch\n");
403 bin->multi_bin_parse_num += 1;
404 DBG("%s bin->multi_bin_parse_num is %d\n", __func__,
405 bin->multi_bin_parse_num);
406 ret = aw_get_multi_bin_header_1_0_0(bin);
407 if (ret < 0)
408 return ret;
409 break;
410 }
411 return 0;
412 }
413
414 /* get the bin's header version */
aw_check_bin_header_version(struct aw_bin * bin)415 static int aw_check_bin_header_version(struct aw_bin *bin)
416 {
417 int ret = 0;
418 unsigned int header_version = 0;
419
420 header_version = GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6),
421 *(bin->p_addr + 5), *(bin->p_addr + 4));
422 DBG("aw_bin_parse header_version 0x%x\n", header_version);
423 /* Write data to the corresponding structure array
424 * according to different formats of the bin frame header version
425 */
426 switch (header_version) {
427 case HEADER_VERSION_1_0_0:
428 ret = aw_parse_bin_header_1_0_0(bin);
429 return ret;
430 default:
431 DBG_ERR("aw_bin_parse Unrecognized this bin header version\n");
432 return -BIN_HEADER_VER_ERR;
433 }
434 }
435
aw_parsing_bin_file(struct aw_bin * bin)436 int aw_parsing_bin_file(struct aw_bin *bin)
437 {
438 int i = 0;
439 int ret = 0;
440
441 DBG("aw_bin_parse code version:%s\n", AWINIC_CODE_VERSION);
442 if (!bin) {
443 DBG_ERR("aw_bin_parse bin is NULL\n");
444 return -BIN_IS_NULL;
445 }
446 bin->p_addr = bin->info.data;
447 bin->all_bin_parse_num = 0;
448 bin->multi_bin_parse_num = 0;
449 bin->single_bin_parse_num = 0;
450
451 /* filling bins header info */
452 ret = aw_check_bin_header_version(bin);
453 if (ret < 0) {
454 DBG_ERR("aw_bin_parse check bin header version error\n");
455 return ret;
456 }
457 bin->p_addr = NULL;
458
459 /* check bin header info */
460 for (i = 0; i < bin->all_bin_parse_num; i++) {
461 /* check sum */
462 ret = aw_check_sum(bin, i);
463 if (ret < 0) {
464 DBG_ERR("aw_bin_parse check sum data error\n");
465 return ret;
466 }
467 /* check bin data version */
468 ret = aw_check_data_version(bin, i);
469 if (ret < 0) {
470 DBG_ERR("aw_bin_parse check data version error\n");
471 return ret;
472 }
473 /* check valid data */
474 if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) {
475 /* check register num */
476 if (bin->header_info[i].bin_data_type ==
477 DATA_TYPE_REGISTER) {
478 ret = aw_check_register_num_v1(bin, i);
479 if (ret < 0)
480 return ret;
481 /* check dsp reg num */
482 } else if (bin->header_info[i].bin_data_type ==
483 DATA_TYPE_DSP_REG) {
484 ret = aw_check_dsp_reg_num_v1(bin, i);
485 if (ret < 0)
486 return ret;
487 /* check soc app num */
488 } else if (bin->header_info[i].bin_data_type ==
489 DATA_TYPE_SOC_APP) {
490 ret = aw_check_soc_app_num_v1(bin, i);
491 if (ret < 0)
492 return ret;
493 } else {
494 bin->header_info[i].valid_data_len = bin->
495 header_info[i].bin_data_len;
496 }
497 }
498 }
499 DBG("aw_bin_parse parsing success\n");
500
501 return 0;
502 }
503
aw_dev_dsp_data_order(struct aw_device * aw_dev,uint8_t * data,uint32_t data_len)504 int aw_dev_dsp_data_order(struct aw_device *aw_dev,
505 uint8_t *data, uint32_t data_len)
506 {
507 int i = 0;
508 uint8_t tmp_val = 0;
509
510 aw_dev_dbg(aw_dev->dev, "enter");
511
512 if (data_len % 2 != 0) {
513 aw_dev_dbg(aw_dev->dev, "data_len:%d unsupported", data_len);
514 return -EINVAL;
515 }
516
517 for (i = 0; i < data_len; i += 2) {
518 tmp_val = data[i];
519 data[i] = data[i + 1];
520 data[i + 1] = tmp_val;
521 }
522
523 return 0;
524 }
525
aw_dev_parse_raw_reg(struct aw_device * aw_dev,uint8_t * data,uint32_t data_len,struct aw_prof_desc * prof_desc)526 static int aw_dev_parse_raw_reg(struct aw_device *aw_dev,
527 uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
528 {
529 aw_dev_info(aw_dev->dev, "data_size:%d enter", data_len);
530
531 prof_desc->sec_desc[AW_DATA_TYPE_REG].data = data;
532 prof_desc->sec_desc[AW_DATA_TYPE_REG].len = data_len;
533
534 prof_desc->prof_st = AW_PROFILE_OK;
535
536 return 0;
537 }
538
aw_dev_parse_raw_dsp_cfg(struct aw_device * aw_dev,uint8_t * data,uint32_t data_len,struct aw_prof_desc * prof_desc)539 static int aw_dev_parse_raw_dsp_cfg(struct aw_device *aw_dev,
540 uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
541 {
542 int ret;
543
544 aw_dev_info(aw_dev->dev, "data_size:%d enter", data_len);
545
546 ret = aw_dev_dsp_data_order(aw_dev, data, data_len);
547 if (ret < 0)
548 return ret;
549
550 prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data = data;
551 prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len = data_len;
552
553 prof_desc->prof_st = AW_PROFILE_OK;
554
555 return 0;
556 }
557
aw_dev_parse_raw_dsp_fw(struct aw_device * aw_dev,uint8_t * data,uint32_t data_len,struct aw_prof_desc * prof_desc)558 static int aw_dev_parse_raw_dsp_fw(struct aw_device *aw_dev,
559 uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
560 {
561 int ret;
562
563 aw_dev_info(aw_dev->dev, "data_size:%d enter", data_len);
564
565 ret = aw_dev_dsp_data_order(aw_dev, data, data_len);
566 if (ret < 0)
567 return ret;
568
569 prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data = data;
570 prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len = data_len;
571
572 prof_desc->prof_st = AW_PROFILE_OK;
573
574 return 0;
575 }
576
aw_dev_prof_parse_multi_bin(struct aw_device * aw_dev,uint8_t * data,uint32_t data_len,struct aw_prof_desc * prof_desc)577 static int aw_dev_prof_parse_multi_bin(struct aw_device *aw_dev,
578 uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
579 {
580 struct aw_bin *aw_bin = NULL;
581 int i;
582 int ret;
583
584 aw_bin = devm_kzalloc(aw_dev->dev, data_len + sizeof(struct aw_bin), GFP_KERNEL);
585 if (aw_bin == NULL) {
586 aw_dev_err(aw_dev->dev, "kzalloc aw_bin failed");
587 return -ENOMEM;
588 }
589
590 aw_bin->info.len = data_len;
591 memcpy(aw_bin->info.data, data, data_len);
592
593 ret = aw_parsing_bin_file(aw_bin);
594 if (ret < 0) {
595 aw_dev_err(aw_dev->dev, "parse bin failed");
596 goto parse_bin_failed;
597 }
598
599 for (i = 0; i < aw_bin->all_bin_parse_num; i++) {
600 if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_REGISTER) {
601 prof_desc->sec_desc[AW_DATA_TYPE_REG].len = aw_bin->header_info[i].valid_data_len;
602 prof_desc->sec_desc[AW_DATA_TYPE_REG].data = data + aw_bin->header_info[i].valid_data_addr;
603 } else if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_DSP_REG) {
604 ret = aw_dev_dsp_data_order(aw_dev, data + aw_bin->header_info[i].valid_data_addr,
605 aw_bin->header_info[i].valid_data_len);
606 if (ret < 0)
607 return ret;
608
609 prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len = aw_bin->header_info[i].valid_data_len;
610 prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data = data + aw_bin->header_info[i].valid_data_addr;
611 } else if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_DSP_FW) {
612 ret = aw_dev_dsp_data_order(aw_dev, data + aw_bin->header_info[i].valid_data_addr,
613 aw_bin->header_info[i].valid_data_len);
614 if (ret < 0)
615 return ret;
616
617 prof_desc->fw_ver = aw_bin->header_info[i].app_version;
618 prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len = aw_bin->header_info[i].valid_data_len;
619 prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data = data + aw_bin->header_info[i].valid_data_addr;
620 }
621 }
622 devm_kfree(aw_dev->dev, aw_bin);
623 aw_bin = NULL;
624 prof_desc->prof_st = AW_PROFILE_OK;
625 return 0;
626
627 parse_bin_failed:
628 devm_kfree(aw_dev->dev, aw_bin);
629 aw_bin = NULL;
630 return ret;
631 }
632
aw_dev_parse_data_by_sec_type(struct aw_device * aw_dev,struct aw_cfg_hdr * cfg_hdr,struct aw_cfg_dde * cfg_dde,struct aw_prof_desc * scene_prof_desc)633 static int aw_dev_parse_data_by_sec_type(struct aw_device *aw_dev, struct aw_cfg_hdr *cfg_hdr,
634 struct aw_cfg_dde *cfg_dde, struct aw_prof_desc *scene_prof_desc)
635 {
636
637 switch (cfg_dde->data_type) {
638 case ACF_SEC_TYPE_REG:
639 return aw_dev_parse_raw_reg(aw_dev,
640 (uint8_t *)cfg_hdr + cfg_dde->data_offset,
641 cfg_dde->data_size, scene_prof_desc);
642 case ACF_SEC_TYPE_DSP_CFG:
643 return aw_dev_parse_raw_dsp_cfg(aw_dev,
644 (uint8_t *)cfg_hdr + cfg_dde->data_offset,
645 cfg_dde->data_size, scene_prof_desc);
646 case ACF_SEC_TYPE_DSP_FW:
647 return aw_dev_parse_raw_dsp_fw(aw_dev,
648 (uint8_t *)cfg_hdr + cfg_dde->data_offset,
649 cfg_dde->data_size, scene_prof_desc);
650 case ACF_SEC_TYPE_MUTLBIN:
651 return aw_dev_prof_parse_multi_bin(aw_dev,
652 (uint8_t *)cfg_hdr + cfg_dde->data_offset,
653 cfg_dde->data_size, scene_prof_desc);
654 }
655 return 0;
656 }
657
aw_dev_parse_dev_type(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr,struct aw_all_prof_info * all_prof_info)658 static int aw_dev_parse_dev_type(struct aw_device *aw_dev,
659 struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
660 {
661 int i = 0;
662 int ret;
663 int sec_num = 0;
664 struct aw_cfg_dde *cfg_dde =
665 (struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
666
667 aw_dev_info(aw_dev->dev, "enter");
668
669 for (i = 0; i < prof_hdr->a_ddt_num; i++) {
670 if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
671 (aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
672 (cfg_dde[i].type == AW_DEV_TYPE_ID)) {
673 if (cfg_dde[i].data_type == ACF_SEC_TYPE_MONITOR) {
674 ret = aw_monitor_parse_fw(&aw_dev->monitor_desc,
675 (uint8_t *)prof_hdr + cfg_dde[i].data_offset,
676 cfg_dde[i].data_size);
677 if (ret < 0) {
678 aw_dev_err(aw_dev->dev, "parse monitor failed");
679 return ret;
680 }
681 } else {
682 if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
683 aw_dev_err(aw_dev->dev, "dev_profile [%d] overflow",
684 cfg_dde[i].dev_profile);
685 return -EINVAL;
686 }
687 ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
688 &all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
689 if (ret < 0) {
690 aw_dev_err(aw_dev->dev, "parse failed");
691 return ret;
692 }
693 sec_num++;
694 }
695 }
696 }
697
698 if (sec_num == 0) {
699 aw_dev_info(aw_dev->dev, "get dev type num is %d, please use default",
700 sec_num);
701 return AW_DEV_TYPE_NONE;
702 }
703
704 return AW_DEV_TYPE_OK;
705 }
706
aw_dev_parse_dev_default_type(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr,struct aw_all_prof_info * all_prof_info)707 static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev,
708 struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
709 {
710 int i = 0;
711 int ret;
712 int sec_num = 0;
713 struct aw_cfg_dde *cfg_dde =
714 (struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
715
716 aw_dev_info(aw_dev->dev, "enter");
717
718 for (i = 0; i < prof_hdr->a_ddt_num; i++) {
719 if ((aw_dev->channel == cfg_dde[i].dev_index) &&
720 (cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)) {
721 if (cfg_dde[i].data_type == ACF_SEC_TYPE_MONITOR) {
722 ret = aw_monitor_parse_fw(&aw_dev->monitor_desc,
723 (uint8_t *)prof_hdr + cfg_dde[i].data_offset,
724 cfg_dde[i].data_size);
725 if (ret < 0) {
726 aw_dev_err(aw_dev->dev, "parse monitor failed");
727 return ret;
728 }
729 } else {
730 if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
731 aw_dev_err(aw_dev->dev, "dev_profile [%d] overflow",
732 cfg_dde[i].dev_profile);
733 return -EINVAL;
734 }
735 ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
736 &all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
737 if (ret < 0) {
738 aw_dev_err(aw_dev->dev, "parse failed");
739 return ret;
740 }
741 sec_num++;
742 }
743 }
744 }
745
746 if (sec_num == 0) {
747 aw_dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num);
748 return -EINVAL;
749 }
750
751 return 0;
752 }
753
aw_dev_cfg_get_vaild_prof(struct aw_device * aw_dev,struct aw_all_prof_info all_prof_info)754 static int aw_dev_cfg_get_vaild_prof(struct aw_device *aw_dev,
755 struct aw_all_prof_info all_prof_info)
756 {
757 int i;
758 int num = 0;
759 struct aw_sec_data_desc *sec_desc = NULL;
760 struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
761 struct aw_prof_info *prof_info = &aw_dev->prof_info;
762
763 for (i = 0; i < AW_PROFILE_MAX; i++) {
764 if (prof_desc[i].prof_st == AW_PROFILE_OK) {
765 sec_desc = prof_desc[i].sec_desc;
766 if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
767 (sec_desc[AW_DATA_TYPE_REG].len != 0) &&
768 (sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
769 (sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
770 (sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
771 (sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
772 prof_info->count++;
773 }
774 }
775 }
776
777 aw_dev_info(aw_dev->dev, "get vaild profile:%d", aw_dev->prof_info.count);
778
779 if (!prof_info->count) {
780 aw_dev_err(aw_dev->dev, "no profile data");
781 return -EPERM;
782 }
783
784 prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
785 prof_info->count * sizeof(struct aw_prof_desc),
786 GFP_KERNEL);
787 if (prof_info->prof_desc == NULL) {
788 aw_dev_err(aw_dev->dev, "prof_desc kzalloc failed");
789 return -ENOMEM;
790 }
791
792 for (i = 0; i < AW_PROFILE_MAX; i++) {
793 if (prof_desc[i].prof_st == AW_PROFILE_OK) {
794 sec_desc = prof_desc[i].sec_desc;
795 if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
796 (sec_desc[AW_DATA_TYPE_REG].len != 0) &&
797 (sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
798 (sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
799 (sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
800 (sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
801 if (num >= prof_info->count) {
802 aw_dev_err(aw_dev->dev, "get scene num[%d] overflow count[%d]",
803 num, prof_info->count);
804 return -ENOMEM;
805 }
806 prof_info->prof_desc[num] = prof_desc[i];
807 prof_info->prof_desc[num].id = i;
808 num++;
809 }
810 }
811 }
812
813 return 0;
814 }
815
aw_dev_load_cfg_by_hdr(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr)816 static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev,
817 struct aw_cfg_hdr *prof_hdr)
818 {
819 int ret;
820 struct aw_all_prof_info all_prof_info;
821
822 memset(&all_prof_info, 0, sizeof(struct aw_all_prof_info));
823
824 ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, &all_prof_info);
825 if (ret < 0) {
826 return ret;
827 } else if (ret == AW_DEV_TYPE_NONE) {
828 aw_dev_info(aw_dev->dev, "get dev type num is 0, parse default dev");
829 ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, &all_prof_info);
830 if (ret < 0)
831 return ret;
832 }
833
834 ret = aw_dev_cfg_get_vaild_prof(aw_dev, all_prof_info);
835 if (ret < 0)
836 return ret;
837
838 aw_dev->prof_info.prof_name_list = profile_name;
839
840 return 0;
841 }
842
aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device * aw_dev)843 static int aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device *aw_dev)
844 {
845 struct aw_prof_info *prof_info = &aw_dev->prof_info;
846 struct aw_prof_desc *prof_desc = prof_info->prof_desc;
847 int i;
848
849 if (prof_desc == NULL) {
850 aw_dev_err(aw_dev->dev, "prof_desc is NULL");
851 return -EINVAL;
852 }
853
854 prof_info->prof_name_list = devm_kzalloc(aw_dev->dev,
855 prof_info->count * PROFILE_STR_MAX,
856 GFP_KERNEL);
857 if (prof_info->prof_name_list == NULL) {
858 aw_dev_err(aw_dev->dev, "prof_name_list devm_kzalloc failed");
859 return -ENOMEM;
860 }
861
862 for (i = 0; i < prof_info->count; i++) {
863 prof_desc[i].id = i;
864 prof_info->prof_name_list[i] = prof_desc[i].prf_str;
865 aw_dev_info(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]);
866 }
867
868 return 0;
869 }
870
aw_get_dde_type_info(struct aw_device * aw_dev,struct aw_container * aw_cfg)871 static int aw_get_dde_type_info(struct aw_device *aw_dev, struct aw_container *aw_cfg)
872 {
873 int i;
874 int dev_num = 0;
875 int default_num = 0;
876 struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
877 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
878 (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
879
880 for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
881 if (cfg_dde[i].type == AW_DEV_TYPE_ID)
882 dev_num++;
883
884 if (cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)
885 default_num++;
886 }
887
888 if (!(dev_num || default_num)) {
889 aw_dev_err(aw_dev->dev, "can't find scene");
890 return -EINVAL;
891 }
892
893 if (dev_num != 0) {
894 aw_dev->prof_info.prof_type = AW_DEV_TYPE_ID;
895 } else {
896 aw_dev->prof_info.prof_type = AW_DEV_DEFAULT_TYPE_ID;
897 }
898
899 return 0;
900 }
901
aw_get_dev_scene_count_v_1_0_0_0(struct aw_device * aw_dev,struct aw_container * aw_cfg,uint32_t * scene_num)902 static int aw_get_dev_scene_count_v_1_0_0_0(struct aw_device *aw_dev,
903 struct aw_container *aw_cfg,
904 uint32_t *scene_num)
905 {
906 int i;
907 struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
908 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
909 (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
910
911 for (i = 0; i < cfg_hdr->a_ddt_num; ++i) {
912 if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) &&
913 (aw_dev->chip_id == cfg_dde[i].chip_id) &&
914 ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
915 (aw_dev->i2c->addr == cfg_dde[i].dev_addr)))
916 (*scene_num)++;
917 }
918
919 return 0;
920 }
921
aw_get_default_scene_count_v_1_0_0_0(struct aw_device * aw_dev,struct aw_container * aw_cfg,uint32_t * scene_num)922 static int aw_get_default_scene_count_v_1_0_0_0(struct aw_device *aw_dev,
923 struct aw_container *aw_cfg,
924 uint32_t *scene_num)
925 {
926 int i;
927 struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
928 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
929 (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
930
931 for (i = 0; i < cfg_hdr->a_ddt_num; ++i) {
932 if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) &&
933 (aw_dev->chip_id == cfg_dde[i].chip_id) &&
934 (aw_dev->channel == cfg_dde[i].dev_index))
935 (*scene_num)++;
936 }
937
938 return 0;
939 }
940
aw_dev_parse_scene_count_v_1_0_0_0(struct aw_device * aw_dev,struct aw_container * aw_cfg,uint32_t * count)941 static int aw_dev_parse_scene_count_v_1_0_0_0(struct aw_device *aw_dev,
942 struct aw_container *aw_cfg,
943 uint32_t *count)
944 {
945 int ret;
946
947 ret = aw_get_dde_type_info(aw_dev, aw_cfg);
948 if (ret < 0)
949 return ret;
950
951 if (aw_dev->prof_info.prof_type == AW_DEV_TYPE_ID) {
952 aw_get_dev_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count);
953 } else if (aw_dev->prof_info.prof_type == AW_DEV_DEFAULT_TYPE_ID) {
954 aw_get_default_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count);
955 } else {
956 aw_dev_err(aw_dev->dev, "unsupported prof_type[%x]",
957 aw_dev->prof_info.prof_type);
958 return -EINVAL;
959 }
960
961 aw_dev_info(aw_dev->dev, "scene count is %d", (*count));
962 return 0;
963 }
964
aw_dev_parse_data_by_sec_type_v_1_0_0_0(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr,struct aw_cfg_dde_v_1_0_0_0 * cfg_dde,int * cur_scene_id)965 static int aw_dev_parse_data_by_sec_type_v_1_0_0_0(struct aw_device *aw_dev,
966 struct aw_cfg_hdr *prof_hdr,
967 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde,
968 int *cur_scene_id)
969 {
970 int ret;
971 struct aw_prof_info *prof_info = &aw_dev->prof_info;
972
973 switch (cfg_dde->data_type) {
974 case ACF_SEC_TYPE_MUTLBIN:
975 ret = aw_dev_prof_parse_multi_bin(aw_dev,
976 (uint8_t *)prof_hdr + cfg_dde->data_offset,
977 cfg_dde->data_size, &prof_info->prof_desc[*cur_scene_id]);
978 if (ret < 0) {
979 aw_dev_err(aw_dev->dev, "parse multi bin failed");
980 return ret;
981 }
982 prof_info->prof_desc[*cur_scene_id].prf_str = cfg_dde->dev_profile_str;
983 prof_info->prof_desc[*cur_scene_id].id = cfg_dde->dev_profile;
984 (*cur_scene_id)++;
985 break;
986 case ACF_SEC_TYPE_MONITOR:
987 return aw_monitor_parse_fw(&aw_dev->monitor_desc,
988 (uint8_t *)prof_hdr + cfg_dde->data_offset,
989 cfg_dde->data_size);
990 default:
991 aw_pr_err("unsupported SEC_TYPE [%d]", cfg_dde->data_type);
992 return -EINVAL;
993 }
994
995 return 0;
996 }
997
aw_dev_parse_dev_type_v_1_0_0_0(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr)998 static int aw_dev_parse_dev_type_v_1_0_0_0(struct aw_device *aw_dev,
999 struct aw_cfg_hdr *prof_hdr)
1000 {
1001 int i = 0;
1002 int ret;
1003 int cur_scene_id = 0;
1004 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
1005 (struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
1006
1007 aw_dev_info(aw_dev->dev, "enter");
1008
1009 for (i = 0; i < prof_hdr->a_ddt_num; i++) {
1010 if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
1011 (aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
1012 (aw_dev->chip_id == cfg_dde[i].chip_id)) {
1013 ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr,
1014 &cfg_dde[i], &cur_scene_id);
1015 if (ret < 0) {
1016 aw_dev_err(aw_dev->dev, "parse failed");
1017 return ret;
1018 }
1019 }
1020 }
1021
1022 if (cur_scene_id == 0) {
1023 aw_dev_info(aw_dev->dev, "get dev type failed, get num [%d]", cur_scene_id);
1024 return -EINVAL;
1025 }
1026
1027 return 0;
1028 }
1029
aw_dev_parse_default_type_v_1_0_0_0(struct aw_device * aw_dev,struct aw_cfg_hdr * prof_hdr)1030 static int aw_dev_parse_default_type_v_1_0_0_0(struct aw_device *aw_dev,
1031 struct aw_cfg_hdr *prof_hdr)
1032 {
1033 int i = 0;
1034 int ret;
1035 int cur_scene_id = 0;
1036 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
1037 (struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
1038
1039 aw_dev_info(aw_dev->dev, "enter");
1040
1041 for (i = 0; i < prof_hdr->a_ddt_num; i++) {
1042 if ((aw_dev->channel == cfg_dde[i].dev_index) &&
1043 (aw_dev->chip_id == cfg_dde[i].chip_id)) {
1044 ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr,
1045 &cfg_dde[i], &cur_scene_id);
1046 if (ret < 0) {
1047 aw_dev_err(aw_dev->dev, "parse failed");
1048 return ret;
1049 }
1050 }
1051 }
1052
1053 if (cur_scene_id == 0) {
1054 aw_dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", cur_scene_id);
1055 return -EINVAL;
1056 }
1057
1058 return 0;
1059 }
1060
aw_dev_parse_by_hdr_v_1_0_0_0(struct aw_device * aw_dev,struct aw_cfg_hdr * cfg_hdr)1061 static int aw_dev_parse_by_hdr_v_1_0_0_0(struct aw_device *aw_dev,
1062 struct aw_cfg_hdr *cfg_hdr)
1063 {
1064 int ret;
1065
1066 if (aw_dev->prof_info.prof_type == AW_DEV_TYPE_ID) {
1067 ret = aw_dev_parse_dev_type_v_1_0_0_0(aw_dev, cfg_hdr);
1068 if (ret < 0)
1069 return ret;
1070 } else if (aw_dev->prof_info.prof_type == AW_DEV_DEFAULT_TYPE_ID) {
1071 ret = aw_dev_parse_default_type_v_1_0_0_0(aw_dev, cfg_hdr);
1072 if (ret < 0)
1073 return ret;
1074 } else {
1075 aw_dev_err(aw_dev->dev, "prof type matched failed, get num[%d]",
1076 aw_dev->prof_info.prof_type);
1077 return -EINVAL;
1078 }
1079
1080 return 0;
1081 }
1082
aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device * aw_dev,struct aw_container * aw_cfg)1083 static int aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device *aw_dev, struct aw_container *aw_cfg)
1084 {
1085 struct aw_prof_info *prof_info = &aw_dev->prof_info;
1086 struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
1087 int ret;
1088
1089 ret = aw_dev_parse_scene_count_v_1_0_0_0(aw_dev, aw_cfg, &prof_info->count);
1090 if (ret < 0) {
1091 aw_dev_err(aw_dev->dev, "get scene count failed");
1092 return ret;
1093 }
1094
1095 prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
1096 prof_info->count * sizeof(struct aw_prof_desc),
1097 GFP_KERNEL);
1098 if (prof_info->prof_desc == NULL) {
1099 aw_dev_err(aw_dev->dev, "prof_desc devm_kzalloc failed");
1100 return -ENOMEM;
1101 }
1102
1103 ret = aw_dev_parse_by_hdr_v_1_0_0_0(aw_dev, cfg_hdr);
1104 if (ret < 0) {
1105 aw_dev_err(aw_dev->dev, " failed");
1106 return ret;
1107 }
1108
1109 ret = aw_dev_create_prof_name_list_v_1_0_0_0(aw_dev);
1110 if (ret < 0) {
1111 aw_dev_err(aw_dev->dev, "create prof name list failed");
1112 return ret;
1113 }
1114
1115 return 0;
1116 }
1117
aw_dev_cfg_load(struct aw_device * aw_dev,struct aw_container * aw_cfg)1118 int aw_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg)
1119 {
1120 struct aw_cfg_hdr *cfg_hdr = NULL;
1121 int ret;
1122
1123 aw_dev_info(aw_dev->dev, "enter");
1124
1125 cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
1126 switch (cfg_hdr->a_hdr_version) {
1127 case AW_CFG_HDR_VER_0_0_0_1:
1128 ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr);
1129 if (ret < 0) {
1130 aw_dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
1131 cfg_hdr->a_hdr_version);
1132 return ret;
1133 }
1134 break;
1135 case AW_CFG_HDR_VER_1_0_0_0:
1136 ret = aw_dev_load_cfg_by_hdr_v_1_0_0_0(aw_dev, aw_cfg);
1137 if (ret < 0) {
1138 aw_dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
1139 cfg_hdr->a_hdr_version);
1140 return ret;
1141 }
1142 break;
1143 default:
1144 aw_pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
1145 return -EINVAL;
1146 }
1147
1148 aw_dev->fw_status = AW_DEV_FW_OK;
1149 aw_dev_info(aw_dev->dev, "parse cfg success");
1150 return 0;
1151 }
1152
aw_dev_crc8_check(unsigned char * data,uint32_t data_size)1153 static uint8_t aw_dev_crc8_check(unsigned char *data, uint32_t data_size)
1154 {
1155 uint8_t crc_value = 0x00;
1156 uint8_t pdatabuf = 0;
1157 int i;
1158
1159 while (data_size--) {
1160 pdatabuf = *data++;
1161 for (i = 0; i < 8; i++) {
1162 /*if the lowest bit is 1*/
1163 if ((crc_value ^ (pdatabuf)) & 0x01) {
1164 /*Xor multinomial*/
1165 crc_value ^= 0x18;
1166 crc_value >>= 1;
1167 crc_value |= 0x80;
1168 } else {
1169 crc_value >>= 1;
1170 }
1171 pdatabuf >>= 1;
1172 }
1173 }
1174 return crc_value;
1175 }
1176
aw_dev_check_cfg_by_hdr(struct aw_container * aw_cfg)1177 static int aw_dev_check_cfg_by_hdr(struct aw_container *aw_cfg)
1178 {
1179 struct aw_cfg_hdr *cfg_hdr = NULL;
1180 struct aw_cfg_dde *cfg_dde = NULL;
1181 unsigned int end_data_offset = 0;
1182 unsigned int act_data = 0;
1183 unsigned int hdr_ddt_len = 0;
1184 uint8_t act_crc8 = 0;
1185 int i;
1186
1187 cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
1188
1189 /*check file type id is awinic acf file*/
1190 if (cfg_hdr->a_id != ACF_FILE_ID) {
1191 aw_pr_err("not acf type file");
1192 return -EINVAL;
1193 }
1194
1195 hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
1196 if (hdr_ddt_len > aw_cfg->len) {
1197 aw_pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
1198 cfg_hdr->a_hdr_offset, aw_cfg->len);
1199 return -EINVAL;
1200 }
1201
1202 /*check data size*/
1203 cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
1204 act_data += hdr_ddt_len;
1205 for (i = 0; i < cfg_hdr->a_ddt_num; i++)
1206 act_data += cfg_dde[i].data_size;
1207
1208 if (act_data != aw_cfg->len) {
1209 aw_pr_err("act_data[%d] not equal to file size[%d]!",
1210 act_data, aw_cfg->len);
1211 return -EINVAL;
1212 }
1213
1214 for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
1215 /* data check */
1216 end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
1217 if (end_data_offset > aw_cfg->len) {
1218 aw_pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
1219 i, end_data_offset, aw_cfg->len);
1220 return -EINVAL;
1221 }
1222
1223 /* crc check */
1224 act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset, cfg_dde[i].data_size);
1225 if (act_crc8 != cfg_dde[i].data_crc) {
1226 aw_pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
1227 i, (uint32_t)act_crc8, cfg_dde[i].data_crc);
1228 return -EINVAL;
1229 }
1230 }
1231
1232 aw_pr_info("project name [%s]", cfg_hdr->a_project);
1233 aw_pr_info("custom name [%s]", cfg_hdr->a_custom);
1234 aw_pr_info("version name [%d.%d.%d.%d]", cfg_hdr->a_version[3], cfg_hdr->a_version[2],
1235 cfg_hdr->a_version[1], cfg_hdr->a_version[0]);
1236 aw_pr_info("author id %d", cfg_hdr->a_author_id);
1237
1238 return 0;
1239 }
1240
aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container * aw_cfg)1241 static int aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container *aw_cfg)
1242 {
1243 struct aw_cfg_hdr *cfg_hdr = NULL;
1244 struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = NULL;
1245 unsigned int end_data_offset = 0;
1246 unsigned int act_data = 0;
1247 unsigned int hdr_ddt_len = 0;
1248 uint8_t act_crc8 = 0;
1249 int i;
1250
1251 cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
1252
1253 /*check file type id is awinic acf file*/
1254 if (cfg_hdr->a_id != ACF_FILE_ID) {
1255 aw_pr_err("not acf type file");
1256 return -EINVAL;
1257 }
1258
1259 hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
1260 if (hdr_ddt_len > aw_cfg->len) {
1261 aw_pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
1262 cfg_hdr->a_hdr_offset, aw_cfg->len);
1263 return -EINVAL;
1264 }
1265
1266 /*check data size*/
1267 cfg_dde = (struct aw_cfg_dde_v_1_0_0_0 *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
1268 act_data += hdr_ddt_len;
1269 for (i = 0; i < cfg_hdr->a_ddt_num; i++)
1270 act_data += cfg_dde[i].data_size;
1271
1272 if (act_data != aw_cfg->len) {
1273 aw_pr_err("act_data[%d] not equal to file size[%d]!",
1274 act_data, aw_cfg->len);
1275 return -EINVAL;
1276 }
1277
1278 for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
1279 /* data check */
1280 end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
1281 if (end_data_offset > aw_cfg->len) {
1282 aw_pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
1283 i, end_data_offset, aw_cfg->len);
1284 return -EINVAL;
1285 }
1286
1287 /* crc check */
1288 act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset, cfg_dde[i].data_size);
1289 if (act_crc8 != cfg_dde[i].data_crc) {
1290 aw_pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
1291 i, (uint32_t)act_crc8, cfg_dde[i].data_crc);
1292 return -EINVAL;
1293 }
1294 }
1295
1296 aw_pr_info("project name [%s]", cfg_hdr->a_project);
1297 aw_pr_info("custom name [%s]", cfg_hdr->a_custom);
1298 aw_pr_info("version name [%d.%d.%d.%d]", cfg_hdr->a_version[3], cfg_hdr->a_version[2],
1299 cfg_hdr->a_version[1], cfg_hdr->a_version[0]);
1300 aw_pr_info("author id %d", cfg_hdr->a_author_id);
1301
1302 return 0;
1303
1304 }
1305
aw_dev_load_acf_check(struct aw_container * aw_cfg)1306 int aw_dev_load_acf_check(struct aw_container *aw_cfg)
1307 {
1308 struct aw_cfg_hdr *cfg_hdr = NULL;
1309
1310 if (aw_cfg == NULL) {
1311 aw_pr_err("aw_prof is NULL");
1312 return -ENOMEM;
1313 }
1314
1315 if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) {
1316 aw_pr_err("cfg hdr size[%d] overflow file size[%d]",
1317 aw_cfg->len, (int)sizeof(struct aw_cfg_hdr));
1318 return -EINVAL;
1319 }
1320
1321 cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
1322 switch (cfg_hdr->a_hdr_version) {
1323 case AW_CFG_HDR_VER_0_0_0_1:
1324 return aw_dev_check_cfg_by_hdr(aw_cfg);
1325 case AW_CFG_HDR_VER_1_0_0_0:
1326 return aw_dev_check_acf_by_hdr_v_1_0_0_0(aw_cfg);
1327 default:
1328 aw_pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
1329 return -EINVAL;
1330 }
1331
1332 return 0;
1333 }
1334
aw_dev_get_profile_count(struct aw_device * aw_dev)1335 int aw_dev_get_profile_count(struct aw_device *aw_dev)
1336 {
1337 if (aw_dev == NULL) {
1338 aw_pr_err("aw_dev is NULL");
1339 return -ENOMEM;
1340 }
1341
1342 return aw_dev->prof_info.count;
1343 }
1344
aw_dev_check_profile_index(struct aw_device * aw_dev,int index)1345 int aw_dev_check_profile_index(struct aw_device *aw_dev, int index)
1346 {
1347 if ((index >= aw_dev->prof_info.count) || (index < 0))
1348 return -EINVAL;
1349 else
1350 return 0;
1351 }
1352
aw_dev_get_profile_index(struct aw_device * aw_dev)1353 int aw_dev_get_profile_index(struct aw_device *aw_dev)
1354 {
1355 return aw_dev->set_prof;
1356 }
1357
aw_dev_set_profile_index(struct aw_device * aw_dev,int index)1358 int aw_dev_set_profile_index(struct aw_device *aw_dev, int index)
1359 {
1360 struct aw_prof_desc *prof_desc = NULL;
1361
1362 if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1363 return -EINVAL;
1364 } else {
1365 aw_dev->set_prof = index;
1366 prof_desc = &aw_dev->prof_info.prof_desc[index];
1367
1368 aw_dev_info(aw_dev->dev, "set prof[%s]",
1369 aw_dev->prof_info.prof_name_list[prof_desc->id]);
1370 }
1371
1372 return 0;
1373 }
1374
aw_dev_get_prof_name(struct aw_device * aw_dev,int index)1375 char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index)
1376 {
1377 struct aw_prof_desc *prof_desc = NULL;
1378 struct aw_prof_info *prof_info = &aw_dev->prof_info;
1379
1380 if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1381 aw_dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
1382 index, aw_dev->prof_info.count);
1383 return NULL;
1384 }
1385
1386 prof_desc = &aw_dev->prof_info.prof_desc[index];
1387
1388 return prof_info->prof_name_list[prof_desc->id];
1389 }
1390
aw_dev_get_prof_data(struct aw_device * aw_dev,int index,struct aw_prof_desc ** prof_desc)1391 int aw_dev_get_prof_data(struct aw_device *aw_dev, int index,
1392 struct aw_prof_desc **prof_desc)
1393 {
1394 if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1395 aw_dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
1396 __func__, index, aw_dev->prof_info.count);
1397 return -EINVAL;
1398 }
1399
1400 *prof_desc = &aw_dev->prof_info.prof_desc[index];
1401
1402 return 0;
1403 }
1404
1405