1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 #ifndef __PHYDMANTDIV_H__ 17 #define __PHYDMANTDIV_H__ 18 19 /*#define ANTDIV_VERSION "2.0" //2014.11.04*/ 20 /*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ 21 /*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ 22 /*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ 23 /*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ 24 /*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, 25 because antenna diversity only works when BT is disable or radio off*/ 26 /*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ 27 /*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ 28 /*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ 29 /*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ 30 /*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ 31 /*#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ 32 #define ANTDIV_VERSION "4.0" /*2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */ 33 34 /* 1 ============================================================ 35 * 1 Definition 36 * 1 ============================================================ */ 37 38 #define ANTDIV_INIT 0xff 39 #define MAIN_ANT 1 /*ant A or ant Main or S1*/ 40 #define AUX_ANT 2 /*AntB or ant Aux or S0*/ 41 #define MAX_ANT 3 /* 3 for AP using*/ 42 43 #define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ 44 #define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ 45 /*smart antenna*/ 46 #define SUPPORT_RF_PATH_NUM 4 47 #define SUPPORT_BEAM_PATTERN_NUM 4 48 #define NUM_ANTENNA_8821A 2 49 50 #define SUPPORT_BEAM_SET_PATTERN_NUM 16 51 52 #define NO_FIX_TX_ANT 0 53 #define FIX_TX_AT_MAIN 1 54 #define FIX_AUX_AT_MAIN 2 55 56 /* Antenna Diversty Control type */ 57 #define ODM_AUTO_ANT 0 58 #define ODM_FIX_MAIN_ANT 1 59 #define ODM_FIX_AUX_ANT 2 60 61 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A) 62 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B) 63 #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT) 64 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) 65 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) 66 67 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D) 68 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C) 69 70 #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) 71 72 #define ODM_ANTDIV_2G BIT(0) 73 #define ODM_ANTDIV_5G BIT(1) 74 75 #define ANTDIV_ON 1 76 #define ANTDIV_OFF 0 77 78 #define FAT_ON 1 79 #define FAT_OFF 0 80 81 #define TX_BY_DESC 1 82 #define TX_BY_REG 0 83 84 #define RSSI_METHOD 0 85 #define EVM_METHOD 1 86 #define CRC32_METHOD 2 87 #define TP_METHOD 3 88 89 #define INIT_ANTDIV_TIMMER 0 90 #define CANCEL_ANTDIV_TIMMER 1 91 #define RELEASE_ANTDIV_TIMMER 2 92 93 #define CRC32_FAIL 1 94 #define CRC32_OK 0 95 96 #define evm_rssi_th_high 25 97 #define evm_rssi_th_low 20 98 99 #define NORMAL_STATE_MIAN 1 100 #define NORMAL_STATE_AUX 2 101 #define TRAINING_STATE 3 102 103 #define FORCE_RSSI_DIFF 10 104 105 #define CSI_ON 1 106 #define CSI_OFF 0 107 108 #define DIVON_CSIOFF 1 109 #define DIVOFF_CSION 2 110 111 #define BDC_DIV_TRAIN_STATE 0 112 #define bdc_bfer_train_state 1 113 #define BDC_DECISION_STATE 2 114 #define BDC_BF_HOLD_STATE 3 115 #define BDC_DIV_HOLD_STATE 4 116 117 #define BDC_MODE_1 1 118 #define BDC_MODE_2 2 119 #define BDC_MODE_3 3 120 #define BDC_MODE_4 4 121 #define BDC_MODE_NULL 0xff 122 123 /*SW S0S1 antenna diversity*/ 124 #define SWAW_STEP_INIT 0xff 125 #define SWAW_STEP_PEEK 0 126 #define SWAW_STEP_DETERMINE 1 127 128 #define RSSI_CHECK_RESET_PERIOD 10 129 #define RSSI_CHECK_THRESHOLD 50 130 131 /*Hong Lin Smart antenna*/ 132 #define HL_SMTANT_2WIRE_DATA_LEN 24 133 134 /* 1 ============================================================ 135 * 1 structure 136 * 1 ============================================================ */ 137 138 139 struct _sw_antenna_switch_ { 140 u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ 141 u8 try_flag; 142 s32 pre_rssi; 143 u8 cur_antenna; 144 u8 pre_antenna; 145 u8 rssi_trying; 146 u8 reset_idx; 147 u8 train_time; 148 u8 train_time_flag; /*base on RSSI difference between two antennas*/ 149 struct timer_list phydm_sw_antenna_switch_timer; 150 u32 pkt_cnt_sw_ant_div_by_ctrl_frame; 151 boolean is_sw_ant_div_by_ctrl_frame; 152 153 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 154 #if USE_WORKITEM 155 RT_WORK_ITEM phydm_sw_antenna_switch_workitem; 156 #endif 157 #endif 158 159 /* AntDect (Before link Antenna Switch check) need to be moved*/ 160 u16 single_ant_counter; 161 u16 dual_ant_counter; 162 u16 aux_fail_detec_counter; 163 u16 retry_counter; 164 u8 swas_no_link_state; 165 u32 swas_no_link_bk_reg948; 166 boolean ANTA_ON; /*To indicate ant A is or not*/ 167 boolean ANTB_ON; /*To indicate ant B is on or not*/ 168 boolean pre_aux_fail_detec; 169 boolean rssi_ant_dect_result; 170 u8 ant_5g; 171 u8 ant_2g; 172 173 174 }; 175 176 177 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 178 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 179 struct _BF_DIV_COEX_ { 180 boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; 181 boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; 182 u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; 183 u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; 184 185 u8 bd_ccoex_type_wbfer; 186 u8 num_txbfee_client; 187 u8 num_txbfer_client; 188 u8 bdc_try_counter; 189 u8 bdc_hold_counter; 190 u8 bdc_mode; 191 u8 bdc_active_mode; 192 u8 BDC_state; 193 u8 bdc_rx_idle_update_counter; 194 u8 num_client; 195 u8 pre_num_client; 196 u8 num_bf_tar; 197 u8 num_div_tar; 198 199 boolean is_all_div_sta_idle; 200 boolean is_all_bf_sta_idle; 201 boolean bdc_try_flag; 202 boolean BF_pass; 203 boolean DIV_pass; 204 }; 205 #endif 206 #endif 207 208 209 struct phydm_fat_struct { 210 u8 bssid[6]; 211 u8 antsel_rx_keep_0; 212 u8 antsel_rx_keep_1; 213 u8 antsel_rx_keep_2; 214 u8 antsel_rx_keep_3; 215 u32 ant_sum_rssi[7]; 216 u32 ant_rssi_cnt[7]; 217 u32 ant_ave_rssi[7]; 218 u8 fat_state; 219 u8 fat_state_cnt; 220 u32 train_idx; 221 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 222 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 223 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 224 u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; 225 u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; 226 u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 227 u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 228 u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 229 u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 230 u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 231 u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 232 u8 rx_idle_ant; 233 u8 rvrt_val; 234 u8 ant_div_on_off; 235 boolean is_become_linked; 236 u32 min_max_rssi; 237 u8 idx_ant_div_counter_2g; 238 u8 idx_ant_div_counter_5g; 239 u8 ant_div_2g_5g; 240 241 #ifdef ODM_EVM_ENHANCE_ANTDIV 242 /*For 1SS RX phy rate*/ 243 u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 244 u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 245 u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 246 u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 247 248 /*For 2SS RX phy rate*/ 249 u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/ 250 u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A2+B*/ 251 u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 252 u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 253 254 boolean EVM_method_enable; 255 u8 target_ant_evm; 256 u8 target_ant_crc32; 257 u8 target_ant_tp; 258 u8 target_ant_enhance; 259 u8 pre_target_ant_enhance; 260 u16 main_mpdu_ok_cnt; 261 u16 aux_mpdu_ok_cnt; 262 263 u32 crc32_ok_cnt; 264 u32 crc32_fail_cnt; 265 u32 main_crc32_ok_cnt; 266 u32 aux_crc32_ok_cnt; 267 u32 main_crc32_fail_cnt; 268 u32 aux_crc32_fail_cnt; 269 270 u32 antdiv_tp_main; 271 u32 antdiv_tp_aux; 272 u32 antdiv_tp_main_cnt; 273 u32 antdiv_tp_aux_cnt; 274 275 u8 pre_antdiv_rssi; 276 u8 pre_antdiv_tp; 277 #endif 278 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 279 u32 cck_ctrl_frame_cnt_main; 280 u32 cck_ctrl_frame_cnt_aux; 281 u32 ofdm_ctrl_frame_cnt_main; 282 u32 ofdm_ctrl_frame_cnt_aux; 283 u32 main_ant_ctrl_frame_sum; 284 u32 aux_ant_ctrl_frame_sum; 285 u32 main_ant_ctrl_frame_cnt; 286 u32 aux_ant_ctrl_frame_cnt; 287 #endif 288 u8 b_fix_tx_ant; 289 boolean fix_ant_bfee; 290 boolean enable_ctrl_frame_antdiv; 291 boolean use_ctrl_frame_antdiv; 292 u8 hw_antsw_occur; 293 u8 *p_force_tx_ant_by_desc; 294 u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/ 295 u8 *p_default_s0_s1; 296 u8 default_s0_s1; 297 }; 298 299 300 /* 1 ============================================================ 301 * 1 enumeration 302 * 1 ============================================================ */ 303 304 305 306 enum fat_state_e /*Fast antenna training*/ 307 { 308 FAT_BEFORE_LINK_STATE = 0, 309 FAT_PREPARE_STATE = 1, 310 FAT_TRAINING_STATE = 2, 311 FAT_DECISION_STATE = 3 312 }; 313 314 enum ant_div_type_e { 315 NO_ANTDIV = 0xFF, 316 CG_TRX_HW_ANTDIV = 0x01, 317 CGCS_RX_HW_ANTDIV = 0x02, 318 FIXED_HW_ANTDIV = 0x03, 319 CG_TRX_SMART_ANTDIV = 0x04, 320 CGCS_RX_SW_ANTDIV = 0x05, 321 S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ 322 S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ 323 HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/ 324 HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ 325 }; 326 327 328 /* 1 ============================================================ 329 * 1 function prototype 330 * 1 ============================================================ */ 331 332 333 void 334 odm_stop_antenna_switch_dm( 335 void *p_dm_void 336 ); 337 338 void 339 phydm_enable_antenna_diversity( 340 void *p_dm_void 341 ); 342 343 void 344 odm_set_ant_config( 345 void *p_dm_void, 346 u8 ant_setting /* 0=A, 1=B, 2=C, .... */ 347 ); 348 349 350 #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link 351 352 void odm_sw_ant_div_rest_after_link( 353 void *p_dm_void 354 ); 355 356 void 357 odm_ant_div_on_off( 358 void *p_dm_void, 359 u8 swch 360 ); 361 362 void 363 odm_tx_by_tx_desc_or_reg( 364 void *p_dm_void, 365 u8 swch 366 ); 367 368 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 369 370 void 371 phydm_antdiv_reset_statistic( 372 void *p_dm_void, 373 u32 macid 374 ); 375 376 void 377 odm_update_rx_idle_ant( 378 void *p_dm_void, 379 u8 ant 380 ); 381 382 void 383 phydm_set_antdiv_val( 384 void *p_dm_void, 385 u32 *val_buf, 386 u8 val_len 387 ); 388 389 #if (RTL8723B_SUPPORT == 1) 390 void 391 odm_update_rx_idle_ant_8723b( 392 void *p_dm_void, 393 u8 ant, 394 u32 default_ant, 395 u32 optional_ant 396 ); 397 #endif 398 399 #if (RTL8188F_SUPPORT == 1) 400 void 401 phydm_update_rx_idle_antenna_8188F( 402 void *p_dm_void, 403 u32 default_ant 404 ); 405 #endif 406 407 #if (RTL8723D_SUPPORT == 1) 408 409 void 410 phydm_set_tx_ant_pwr_8723d( 411 void *p_dm_void, 412 u8 ant 413 ); 414 415 void 416 odm_update_rx_idle_ant_8723d( 417 void *p_dm_void, 418 u8 ant, 419 u32 default_ant, 420 u32 optional_ant 421 ); 422 423 #endif 424 425 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY 426 427 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 428 void 429 odm_sw_antdiv_callback( 430 struct timer_list *p_timer 431 ); 432 433 void 434 odm_sw_antdiv_workitem_callback( 435 void *p_context 436 ); 437 438 439 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 440 441 void 442 odm_sw_antdiv_workitem_callback( 443 void *p_context 444 ); 445 446 void 447 odm_sw_antdiv_callback( 448 void *function_context 449 ); 450 451 #endif 452 453 void 454 odm_s0s1_sw_ant_div_by_ctrl_frame( 455 void *p_dm_void, 456 u8 step 457 ); 458 459 void 460 odm_antsel_statistics_of_ctrl_frame( 461 void *p_dm_void, 462 u8 antsel_tr_mux, 463 u32 rx_pwdb_all 464 ); 465 466 void 467 odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( 468 void *p_dm_void, 469 void *p_phy_info_void, 470 void *p_pkt_info_void 471 ); 472 473 #endif 474 475 #ifdef ODM_EVM_ENHANCE_ANTDIV 476 VOID 477 phydm_evm_sw_antdiv_init( 478 void *p_dm_void 479 ); 480 481 void 482 odm_evm_fast_ant_training_callback( 483 void *p_dm_void 484 ); 485 #endif 486 487 void 488 odm_hw_ant_div( 489 void *p_dm_void 490 ); 491 492 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) 493 void 494 odm_fast_ant_training( 495 void *p_dm_void 496 ); 497 498 void 499 odm_fast_ant_training_callback( 500 void *p_dm_void 501 ); 502 503 void 504 odm_fast_ant_training_work_item_callback( 505 void *p_dm_void 506 ); 507 #endif 508 509 void 510 odm_ant_div_init( 511 void *p_dm_void 512 ); 513 514 void 515 odm_ant_div( 516 void *p_dm_void 517 ); 518 519 void 520 odm_antsel_statistics( 521 void *p_dm_void, 522 void *p_phy_info_void, 523 u8 antsel_tr_mux, 524 u32 mac_id, 525 u32 utility, 526 u8 method, 527 u8 is_cck_rate 528 ); 529 530 void 531 odm_process_rssi_for_ant_div( 532 void *p_dm_void, 533 void *p_phy_info_void, 534 void *p_pkt_info_void 535 ); 536 537 538 539 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 540 void 541 odm_set_tx_ant_by_tx_info( 542 void *p_dm_void, 543 u8 *p_desc, 544 u8 mac_id 545 ); 546 547 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) 548 549 struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/ 550 551 void 552 odm_set_tx_ant_by_tx_info( 553 struct rtl8192cd_priv *priv, 554 struct tx_desc *pdesc, 555 unsigned short aid 556 ); 557 558 #if 1/*def def CONFIG_WLAN_HAL*/ 559 void 560 odm_set_tx_ant_by_tx_info_hal( 561 struct rtl8192cd_priv *priv, 562 void *pdesc_data, 563 u16 aid 564 ); 565 #endif /*#ifdef CONFIG_WLAN_HAL*/ 566 #endif 567 568 569 void 570 odm_ant_div_config( 571 void *p_dm_void 572 ); 573 574 void 575 odm_ant_div_timers( 576 void *p_dm_void, 577 u8 state 578 ); 579 580 void 581 phydm_antdiv_debug( 582 void *p_dm_void, 583 u32 *const dm_value, 584 u32 *_used, 585 char *output, 586 u32 *_out_len 587 ); 588 589 #endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ 590 591 void 592 odm_ant_div_reset( 593 void *p_dm_void 594 ); 595 596 void 597 odm_antenna_diversity_init( 598 void *p_dm_void 599 ); 600 601 void 602 odm_antenna_diversity( 603 void *p_dm_void 604 ); 605 606 #endif /*#ifndef __ODMANTDIV_H__*/ 607