1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H264E_VEPU541_REG_L2_H__ 18 #define __HAL_H264E_VEPU541_REG_L2_H__ 19 20 #include "rk_type.h" 21 22 /* 23 * L2CFG_ADDR 24 * Address offset: 0x3F0 Access type: read and write 25 * Level2 configuration address 26 */ 27 /* 28 * L2CFG_WDATA 29 * Address offset: 0x3F4 Access type: read and write 30 * L2 configuration write data 31 */ 32 /* 33 * L2 configuration write data. 34 * 35 * Single access: 36 * write address to VEPU_L2CFG_ADDR then write data to VEPU_L2CFG_WDATA. 37 * 38 * Burst access: 39 * write the start address to VEPU_L2CFG_ADDR then write datas 40 * (to VEPU_L2CFG_WDATA) consecutively. 41 * Address will be auto increased after write VEPU_L2CFG_WDATA, 42 * no need to configure VEPU_L2CFG_ADDR. 43 */ 44 45 /* 46 * L2CFG_RDATA 47 * Address offset: 0x3F8 Access type: read and write 48 * L2 configuration read data 49 */ 50 struct { 51 /* 52 * L2 configuration read data. 53 * 54 * Single access: 55 * write address to VEPU_L2CFG_ADDR then read data from VEPU_L2CFG_RDATA. 56 * 57 * Burst access: 58 * write the start address to VEPU_L2CFG_ADDR then read datas 59 * (from VEPU_L2CFG_RDATA) consecutively. 60 * Address will be auto increased after read VEPU_L2CFG_RDATA, 61 * no need to configure VEPU_L2CFG_ADDR. 62 */ 63 RK_U32 l2cfg_rdata; 64 } reg254; 65 66 /* reg gap 255 */ 67 RK_U32 reg_255; 68 69 70 typedef struct Vepu541H264eRegL2Set_t { 71 /* 72 * IPRD_TTHDY4_0_H264 ~ IPRD_TTHDY4_1_H264 73 * Address: 0x0004~0x0008 Access type: read and write 74 * The texture thredsholds for H.264 LUMA 4x4 intra prediction 75 */ 76 RK_U16 iprd_tthdy4[4]; 77 78 /* 79 * IPRD_TTHDC8_0_H264 ~ IPRD_TTHDC8_1_H264 80 * Address: 0x000C~0x0010 Access type: read and write 81 * The texture threshold for H.264 CHROMA 8x8 intra prediction. 82 */ 83 RK_U16 iprd_tthdc8[4]; 84 85 /* 86 * IPRD_TTHDY8_0_H264 ~ IPRD_TTHDY8_1_H264 87 * Address: 0x0014~0x0018 Access type: read and write 88 * The texture thredsholds for H.264 LUMA 8x8 intra prediction 89 */ 90 RK_U16 iprd_tthdy8[4]; 91 92 /* 93 * IPRD_TTHD_UL_H264 94 * Address: 0x001C Access type: read and write 95 * Texture thredsholds of up and left MB for H.264 LUMA intra prediction. 96 */ 97 RK_U32 iprd_tthd_ul; 98 99 /* 100 * IPRD_WGTY8_H264 101 * Address: 0x0020 Access type: read and write 102 * Weights of the cost for H.264 LUMA 8x8 intra prediction 103 */ 104 RK_U8 iprd_wgty8[4]; 105 106 /* 107 * IPRD_WGTY4_H264 108 * Address: 0x0024 Access type: read and write 109 * Weights of the cost for H.264 LUMA 4x4 intra prediction 110 */ 111 RK_U8 iprd_wgty4[4]; 112 113 /* 114 * IPRD_WGTY16_H264 115 * Address: 0x0028 Access type: read and write 116 * Weights of the cost for H.264 LUMA 16x16 intra prediction 117 */ 118 RK_U8 iprd_wgty16[4]; 119 120 /* 121 * IPRD_WGTC8_H264 122 * Address: 0x002C Access type: read and write 123 * Weights of the cost for H.264 CHROMA 8x8 intra prediction 124 */ 125 RK_U8 iprd_wgtc8[4]; 126 127 /* 128 * QNT_BIAS_COMB 129 * Address: 0x0030 Access type: read and write 130 * Quantization bias for H.264 and HEVC. 131 */ 132 struct { 133 /* Quantization bias for HEVC and H.264 I frame. */ 134 RK_U32 qnt_bias_i : 10; 135 /* Quantization bias for HEVC and H.264 P frame. */ 136 RK_U32 qnt_bias_p : 10; 137 RK_U32 reserved : 12; 138 } qnt_bias_comb; 139 140 /* 141 * ATR_THD0_H264 142 * Address: 0x0034 Access type: read and write 143 * H.264 anti ringing noise threshold configuration0. 144 */ 145 struct { 146 /* The 1st threshold for H.264 anti-ringing-noise. */ 147 RK_U32 atr_thd0 : 12; 148 RK_U32 reserved0 : 4; 149 /* The 2nd threshold for H.264 anti-ringing-noise. */ 150 RK_U32 atr_thd1 : 12; 151 RK_U32 reserved1 : 4; 152 } atr_thd0_h264; 153 154 /* 155 * ATR_THD1_H264 156 * Address: 0x0038 Access type: read and write 157 * H.264 anti ringing noise threshold configuration1. 158 */ 159 struct { 160 /* The 3rd threshold for H.264 anti-ringing-noise. */ 161 RK_U32 atr_thd2 : 12; 162 RK_U32 reserved0 : 4; 163 /* QP threshold of P frame for H.264 anti-ringing-nois. */ 164 RK_U32 atr_qp : 6; 165 RK_U32 reserved1 : 10; 166 } atr_thd1_h264; 167 168 /* 169 * ATR_WGT16_H264 170 * Address: 0x003C Access type: read and write 171 * Weights of 16x16 cost for H.264 anti ringing noise. 172 */ 173 struct { 174 /* The 1st weight for H.264 16x16 anti-ringing-noise. */ 175 RK_U32 atr_lv16_wgt0 : 8; 176 /* The 2nd weight for H.264 16x16 anti-ringing-noise. */ 177 RK_U32 atr_lv16_wgt1 : 8; 178 /* The 3rd weight for H.264 16x16 anti-ringing-noise. */ 179 RK_U32 atr_lv16_wgt2 : 8; 180 RK_U32 reserved : 8; 181 } atr_wgt16_h264; 182 183 /* 184 * ATR_WGT8_H264 185 * Address: 0x0040 Access type: read and write 186 * Weights of 8x8 cost for H.264 anti ringing noise. 187 */ 188 struct { 189 /* The 1st weight for H.264 8x8 anti-ringing-noise. */ 190 RK_U32 atr_lv8_wgt0 : 8; 191 /* The 2nd weight for H.264 8x8 anti-ringing-noise. */ 192 RK_U32 atr_lv8_wgt1 : 8; 193 /* The 3rd weight for H.264 8x8 anti-ringing-noise. */ 194 RK_U32 atr_lv8_wgt2 : 8; 195 RK_U32 reserved : 8; 196 } atr_wgt8_h264; 197 198 /* 199 * ATR_WGT4_H264 200 * Address: 0x0044 Access type: read and write 201 * Weights of 4x4 cost for H.264 anti ringing noise. 202 */ 203 struct { 204 /* The 1st weight for H.264 4x4 anti-ringing-noise. */ 205 RK_U32 atr_lv4_wgt0 : 8; 206 /* The 2nd weight for H.264 4x4 anti-ringing-noise. */ 207 RK_U32 atr_lv4_wgt1 : 8; 208 /* The 3rd weight for H.264 4x4 anti-ringing-noise. */ 209 RK_U32 atr_lv4_wgt2 : 8; 210 RK_U32 reserved : 8; 211 } atr_wgt4_h264; 212 213 /* 214 * ATF_TTHD0_H264 ~ ATF_TTHD1_H264 215 * Address: 0x0048~0x004C Access type: read and write 216 * Texture threshold configuration for H.264 anti-flicker 217 */ 218 RK_U16 atf_tthd[4]; 219 220 /* 221 * ATF_STHD0_H264 222 * Address: 0x0050 Access type: read and write 223 * (CME) SAD threshold configuration1 for H.264 anti-flicker. 224 */ 225 struct { 226 /* (CME) SAD threshold0 of texture interval1 for H.264 anti-flicker. */ 227 RK_U32 atf_sthd_10 : 14; 228 RK_U32 reserved0 : 2; 229 /* Max (CME) SAD threshold for H.264 anti-flicker. */ 230 RK_U32 atf_sthd_max : 14; 231 RK_U32 reserved1 : 2; 232 } atf_sthd0_h264; 233 234 /* 235 * ATF_STHD1_H264 236 * Address: 0x0054 Access type: read and write 237 * (CME) SAD threshold configuration1 for H.264 anti-flicker. 238 */ 239 struct { 240 /* (CME) SAD threshold1 of texture interval1 for H.264 anti-flicker. */ 241 RK_U32 atf_sthd_11 : 14; 242 RK_U32 reserved0 : 2; 243 /* (CME) SAD threshold0 of texture interval2 for H.264 anti-flicker. */ 244 RK_U32 atf_sthd_20 : 14; 245 RK_U32 reserved1 : 2; 246 } atf_sthd1_h264; 247 248 /* 249 * ATF_WGT0_H264 250 * Address: 0x0058 Access type: read and write 251 * Weight configuration0 for H.264 anti-flicker. 252 */ 253 struct { 254 /* The 1st weight in texture interval1 for H.264 anti-flicker. */ 255 RK_U32 atf_wgt10 : 9; 256 RK_U32 reserved0 : 7; 257 /* The 2nd weight in texture interval1 for H.264 anti-flicker. */ 258 RK_U32 atf_wgt11 : 9; 259 RK_U32 reserved1 : 7; 260 } atf_wgt0_h264; 261 262 /* 263 * ATF_WGT1_H264 264 * Address: 0x005C Access type: read and write 265 * Weight configuration1 for H.264 anti-flicker. 266 */ 267 struct { 268 /* The 3rd weight in texture interval1 for H.264 anti-flicker. */ 269 RK_U32 atf_wgt12 : 9; 270 RK_U32 reserved0 : 7; 271 /* The 1st weight in texture interval2 for H.264 anti-flicker. */ 272 RK_U32 atf_wgt20 : 9; 273 RK_U32 reserved1 : 7; 274 } atf_wgt1_h264; 275 276 /* 277 * ATF_WGT2_H264 278 * Address: 0x0060 Access type: read and write 279 * Weight configuration2 for H.264 anti-flicker. 280 */ 281 struct { 282 /* The 2nd weight in texture interval2 for H.264 anti-flicker. */ 283 RK_U32 atf_wgt21 : 9; 284 RK_U32 reserved0 : 7; 285 /* The weight in texture interval3 for H.264 anti-flicker. */ 286 RK_U32 atf_wgt30 : 9; 287 RK_U32 reserved1 : 7; 288 } atf_wgt2_h264; 289 290 /* 291 * ATF_OFST0_H264 292 * Address: 0x0064 Access type: read and write 293 * Offset configuration0 for H.264 anti-flicker. 294 */ 295 struct { 296 /* The 1st offset in texture interval1 for H.264 anti-flicker. */ 297 RK_U32 atf_ofst10 : 14; 298 RK_U32 reserved0 : 2; 299 /* The 2nd offset in texture interval1 for H.264 anti-flicker. */ 300 RK_U32 atf_ofst11 : 14; 301 RK_U32 reserved1 : 2; 302 } atf_ofst0_h264; 303 304 /* 305 * ATF_OFST1_H264 306 * Address: 0x0068 Access type: read and write 307 * Offset configuration1 for H.264 anti-flicker. 308 */ 309 struct { 310 /* The 3rd offset in texture interval1 for H.264 anti-flicker. */ 311 RK_U32 atf_ofst12 : 14; 312 RK_U32 reserved0 : 2; 313 /* The 1st offset in texture interval2 for H.264 anti-flicker. */ 314 RK_U32 atf_ofst20 : 14; 315 RK_U32 reserved1 : 2; 316 } atf_ofst1_h264; 317 318 /* 319 * ATF_OFST2_H264 320 * Address: 0x006C Access type: read and write 321 * Offset configuration2 for H.264 anti-flicker. 322 */ 323 struct { 324 /* The 2nd offset in texture interval1 for H.264 anti-flicker. */ 325 RK_U32 atf_ofst21 : 14; 326 RK_U32 reserved0 : 2; 327 /* The offset in texture interval3 for H.264 anti-flicker. */ 328 RK_U32 atf_ofst30 : 14; 329 RK_U32 reserved1 : 2; 330 } atf_ofst2_h264; 331 332 /* 333 * IPRD_WGT_QP0_HEVC ~ IPRD_WGT_QP51_HEVC 334 * Address: 0x0070 ~ 0x013C Access type: read and write 335 * Weight of SATD cost when QP is 0~51 for HEVC intra prediction. 336 */ 337 RK_U32 iprd_wgt_qp[52]; 338 339 /* 340 * RDO_WGTA_QP0_COMB ~ RDO_WGTA_QP51_COMB 341 * Address: 0x0140 ~ 0x020C Access type: read and write 342 * Weight of group A for HEVC and H.264 RDO mode decision when QP is 0~51. 343 */ 344 RK_U32 wgt_qp_grpa[52]; 345 346 /* 347 * RDO_WGTB_QP0_COMB ~ RDO_WGTB_QP51_COMB 348 * Address: 0x0210 ~ 0x02DC Access type: read and write 349 * Weight of group B for HEVC and H.264 RDO mode decision when QP is 0~51. 350 */ 351 RK_U32 wgt_qp_grpb[52]; 352 353 /* 354 * MADI_CFG 355 * Address: 0x02E0 Access type: read and write 356 * MADI configuration for CU32 and CU64. 357 */ 358 /* 359 * MADI generation mode for CU32 and CU64. 360 * 1'h0: Follow 32x32 and 64x64 MADI functions. 361 * 1'h1: Calculated by the mean of corresponding CU16 MADIs. 362 */ 363 RK_U32 madi_mode; 364 365 /* 366 * AQ_TTHD0 ~ AQ_TTHD3 367 * Address: 0x02E4 ~ 0x02F0 Access type: read and write 368 * Texture threshold configuration for adaptive QP adjustment. 369 */ 370 /* Texture threshold for adaptive QP adjustment. */ 371 RK_U8 aq_tthd[16]; 372 373 /* 374 * AQ_STP0 ~ AQ_STP3 375 * Address: 0x02F4 ~ 0x300 Access type: read and write 376 * Adjustment step configuration0 for adaptive QP adjustment. 377 */ 378 /* 379 * MADI generation mode for CU32 and CU64. 380 * 1'h0: Follow 32x32 and 64x64 MADI functions. 381 * 1'h1: Calculated by the mean of corresponding CU16 MADIs. 382 */ 383 /* QP adjust step when current texture strength is between n-1 and n step. */ 384 RK_S8 aq_step[16]; 385 386 /* 387 * RME_MVD_PNSH_H264 388 * Address: 0x0304 Access type: read and write 389 * RME MVD(motion vector difference) cost penalty, H.264 only. 390 */ 391 struct { 392 /* MVD cost penalty enable. */ 393 RK_U32 mvd_pnlt_e : 1; 394 /* MVD cost penalty coefficienc. */ 395 RK_U32 mvd_pnlt_coef : 5; 396 /* MVD cost penalty constant. */ 397 RK_U32 mvd_pnlt_cnst : 14; 398 /* Low threshold of the MVs which should be punished. */ 399 RK_U32 mvd_pnlt_lthd : 4; 400 /* High threshold of the MVs which should be punished. */ 401 RK_U32 mvd_pnlt_hthd : 4; 402 RK_U32 reserved : 4; 403 } rme_mvd_penalty; 404 405 /* 406 * ATR1_THD0_H264 407 * Address: 0x0308 Access type: read and write 408 * H.264 anti ringing noise threshold configuration0 of group1. 409 */ 410 struct { 411 /* The 1st threshold for H.264 anti-ringing-noise of group1. */ 412 RK_U32 atr1_thd0 : 12; 413 RK_U32 reserved0 : 4; 414 /* The 2nd threshold for H.264 anti-ringing-noise of group1. */ 415 RK_U32 atr1_thd1 : 12; 416 RK_U32 reserved1 : 4; 417 } atr1_thd0_h264; 418 419 /* 420 * ATR1_THD0_H264 421 * Address: 0x030C Access type: read and write 422 * H.264 anti ringing noise threshold configuration1 of group1. 423 */ 424 struct { 425 /* The 3rd threshold for H.264 anti-ringing-noise of group1. */ 426 RK_U32 atr1_thd2 : 12; 427 RK_U32 reserved0 : 20; 428 } atr1_thd1_h264; 429 } Vepu541H264eRegL2Set; 430 431 #endif /* __HAL_H264E_VEPU541_REG_L2_H__ */ 432