1 /*
2 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <common/debug.h>
11 #include <common/runtime_svc.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <tools_share/uuid.h>
15
16 #include "lib/utils/alignment_utils.h"
17 #include "socfpga_fcs.h"
18 #include "socfpga_mailbox.h"
19 #include "socfpga_plat_def.h"
20 #include "socfpga_reset_manager.h"
21 #include "socfpga_sip_svc.h"
22 #include "socfpga_system_manager.h"
23
24 /* Total buffer the driver can hold */
25 #define FPGA_CONFIG_BUFFER_SIZE 4
26
27 static config_type request_type = NO_REQUEST;
28 static int current_block, current_buffer;
29 static int read_block, max_blocks;
30 static uint32_t send_id, rcv_id;
31 static uint32_t bytes_per_block, blocks_submitted;
32 static bool bridge_disable;
33 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
34 static uint32_t g_remapper_bypass;
35 #endif
36
37 /* RSU static variables */
38 static uint32_t rsu_dcmf_ver[4] = {0};
39 static uint16_t rsu_dcmf_stat[4] = {0};
40 static uint32_t rsu_max_retry;
41
42 /* SiP Service UUID */
43 DEFINE_SVC_UUID2(intl_svc_uid,
44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
46
socfpga_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)47 static uint64_t socfpga_sip_handler(uint32_t smc_fid,
48 uint64_t x1,
49 uint64_t x2,
50 uint64_t x3,
51 uint64_t x4,
52 void *cookie,
53 void *handle,
54 uint64_t flags)
55 {
56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
57 SMC_RET1(handle, SMC_UNK);
58 }
59
60 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
61
intel_fpga_sdm_write_buffer(struct fpga_config_info * buffer)62 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
63 {
64 uint32_t args[3];
65
66 while (max_blocks > 0 && buffer->size > buffer->size_written) {
67 args[0] = (1<<8);
68 args[1] = buffer->addr + buffer->size_written;
69 if (buffer->size - buffer->size_written <= bytes_per_block) {
70 args[2] = buffer->size - buffer->size_written;
71 current_buffer++;
72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
73 } else {
74 args[2] = bytes_per_block;
75 }
76
77 buffer->size_written += args[2];
78 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
79 3U, CMD_INDIRECT);
80
81 buffer->subblocks_sent++;
82 max_blocks--;
83 }
84
85 return !max_blocks;
86 }
87
intel_fpga_sdm_write_all(void)88 static int intel_fpga_sdm_write_all(void)
89 {
90 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
91 if (intel_fpga_sdm_write_buffer(
92 &fpga_config_buffers[current_buffer])) {
93 break;
94 }
95 }
96 return 0;
97 }
98
intel_mailbox_fpga_config_isdone(uint32_t * err_states)99 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states)
100 {
101 uint32_t ret;
102
103 if (err_states == NULL)
104 return INTEL_SIP_SMC_STATUS_REJECTED;
105
106 switch (request_type) {
107 case RECONFIGURATION:
108 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
109 true, err_states);
110 break;
111 case BITSTREAM_AUTH:
112 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
113 false, err_states);
114 break;
115 default:
116 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
117 false, err_states);
118 break;
119 }
120
121 if (ret != 0U) {
122 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
123 return INTEL_SIP_SMC_STATUS_BUSY;
124 } else {
125 request_type = NO_REQUEST;
126 return INTEL_SIP_SMC_STATUS_ERROR;
127 }
128 }
129
130 if (bridge_disable != 0U) {
131 socfpga_bridges_enable(~0); /* Enable bridge */
132 bridge_disable = false;
133 }
134 request_type = NO_REQUEST;
135
136 return INTEL_SIP_SMC_STATUS_OK;
137 }
138
mark_last_buffer_xfer_completed(uint32_t * buffer_addr_completed)139 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
140 {
141 int i;
142
143 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
144 if (fpga_config_buffers[i].block_number == current_block) {
145 fpga_config_buffers[i].subblocks_sent--;
146 if (fpga_config_buffers[i].subblocks_sent == 0
147 && fpga_config_buffers[i].size <=
148 fpga_config_buffers[i].size_written) {
149 fpga_config_buffers[i].write_requested = 0;
150 current_block++;
151 *buffer_addr_completed =
152 fpga_config_buffers[i].addr;
153 return 0;
154 }
155 }
156 }
157
158 return -1;
159 }
160
intel_fpga_config_completed_write(uint32_t * completed_addr,uint32_t * count,uint32_t * job_id)161 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
162 uint32_t *count, uint32_t *job_id)
163 {
164 uint32_t resp[5];
165 unsigned int resp_len = ARRAY_SIZE(resp);
166 int status = INTEL_SIP_SMC_STATUS_OK;
167 int all_completed = 1;
168 *count = 0;
169
170 while (*count < 3) {
171
172 status = mailbox_read_response(job_id,
173 resp, &resp_len);
174
175 if (status < 0) {
176 break;
177 }
178
179 max_blocks++;
180
181 if (mark_last_buffer_xfer_completed(
182 &completed_addr[*count]) == 0) {
183 *count = *count + 1;
184 } else {
185 break;
186 }
187 }
188
189 if (*count <= 0) {
190 if (status != MBOX_NO_RESPONSE &&
191 status != MBOX_TIMEOUT && resp_len != 0) {
192 mailbox_clear_response();
193 request_type = NO_REQUEST;
194 return INTEL_SIP_SMC_STATUS_ERROR;
195 }
196
197 *count = 0;
198 }
199
200 intel_fpga_sdm_write_all();
201
202 if (*count > 0) {
203 status = INTEL_SIP_SMC_STATUS_OK;
204 } else if (*count == 0) {
205 status = INTEL_SIP_SMC_STATUS_BUSY;
206 }
207
208 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
209 if (fpga_config_buffers[i].write_requested != 0) {
210 all_completed = 0;
211 break;
212 }
213 }
214
215 if (all_completed == 1) {
216 return INTEL_SIP_SMC_STATUS_OK;
217 }
218
219 return status;
220 }
221
intel_fpga_config_start(uint32_t flag)222 static int intel_fpga_config_start(uint32_t flag)
223 {
224 uint32_t argument = 0x1;
225 uint32_t response[3];
226 int status = 0;
227 unsigned int size = 0;
228 unsigned int resp_len = ARRAY_SIZE(response);
229
230 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
231 /*
232 * To trigger isolation
233 * FPGA configuration complete signal should be de-asserted
234 */
235 INFO("SOCFPGA: Request SDM to trigger isolation\n");
236 status = mailbox_send_fpga_config_comp();
237
238 if (status < 0) {
239 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n");
240 }
241 #endif
242
243 request_type = RECONFIGURATION;
244
245 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
246 bridge_disable = true;
247 }
248
249 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
250 size = 1;
251 bridge_disable = false;
252 request_type = BITSTREAM_AUTH;
253 }
254
255 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
256 intel_smmu_hps_remapper_init(0U);
257 #endif
258
259 mailbox_clear_response();
260
261 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
262 CMD_CASUAL, NULL, NULL);
263
264 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
265 CMD_CASUAL, response, &resp_len);
266
267 if (status < 0) {
268 bridge_disable = false;
269 request_type = NO_REQUEST;
270 return INTEL_SIP_SMC_STATUS_ERROR;
271 }
272
273 max_blocks = response[0];
274 bytes_per_block = response[1];
275
276 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
277 fpga_config_buffers[i].size = 0;
278 fpga_config_buffers[i].size_written = 0;
279 fpga_config_buffers[i].addr = 0;
280 fpga_config_buffers[i].write_requested = 0;
281 fpga_config_buffers[i].block_number = 0;
282 fpga_config_buffers[i].subblocks_sent = 0;
283 }
284
285 blocks_submitted = 0;
286 current_block = 0;
287 read_block = 0;
288 current_buffer = 0;
289
290 /* Disable bridge on full reconfiguration */
291 if (bridge_disable) {
292 socfpga_bridges_disable(~0);
293 }
294
295 return INTEL_SIP_SMC_STATUS_OK;
296 }
297
is_fpga_config_buffer_full(void)298 static bool is_fpga_config_buffer_full(void)
299 {
300 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
301 if (!fpga_config_buffers[i].write_requested) {
302 return false;
303 }
304 }
305 return true;
306 }
307
is_address_in_ddr_range(uint64_t addr,uint64_t size)308 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
309 {
310 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE;
311 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size;
312
313 if (!addr && !size) {
314 return true;
315 }
316 if (size > (UINT64_MAX - addr)) {
317 return false;
318 }
319 if (addr < BL31_LIMIT) {
320 return false;
321 }
322 if (dram_region_end > dram_max_sz) {
323 return false;
324 }
325
326 return true;
327 }
328
intel_fpga_config_write(uint64_t mem,uint64_t size)329 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
330 {
331 int i;
332
333 intel_fpga_sdm_write_all();
334
335 if (!is_address_in_ddr_range(mem, size) ||
336 is_fpga_config_buffer_full()) {
337 return INTEL_SIP_SMC_STATUS_REJECTED;
338 }
339
340 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
341 intel_smmu_hps_remapper_init(&mem);
342 #endif
343
344 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
345 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
346
347 if (!fpga_config_buffers[j].write_requested) {
348 fpga_config_buffers[j].addr = mem;
349 fpga_config_buffers[j].size = size;
350 fpga_config_buffers[j].size_written = 0;
351 fpga_config_buffers[j].write_requested = 1;
352 fpga_config_buffers[j].block_number =
353 blocks_submitted++;
354 fpga_config_buffers[j].subblocks_sent = 0;
355 break;
356 }
357 }
358
359 if (is_fpga_config_buffer_full()) {
360 return INTEL_SIP_SMC_STATUS_BUSY;
361 }
362
363 return INTEL_SIP_SMC_STATUS_OK;
364 }
365
is_out_of_sec_range(uint64_t reg_addr)366 static int is_out_of_sec_range(uint64_t reg_addr)
367 {
368 #if DEBUG
369 return 0;
370 #endif
371
372 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
373 switch (reg_addr) {
374 case(0xF8011100): /* ECCCTRL1 */
375 case(0xF8011104): /* ECCCTRL2 */
376 case(0xF8011110): /* ERRINTEN */
377 case(0xF8011114): /* ERRINTENS */
378 case(0xF8011118): /* ERRINTENR */
379 case(0xF801111C): /* INTMODE */
380 case(0xF8011120): /* INTSTAT */
381 case(0xF8011124): /* DIAGINTTEST */
382 case(0xF801112C): /* DERRADDRA */
383 case(0xFA000000): /* SMMU SCR0 */
384 case(0xFA000004): /* SMMU SCR1 */
385 case(0xFA000400): /* SMMU NSCR0 */
386 case(0xFA004000): /* SMMU SSD0_REG */
387 case(0xFA000820): /* SMMU SMR8 */
388 case(0xFA000c20): /* SMMU SCR8 */
389 case(0xFA028000): /* SMMU CB8_SCTRL */
390 case(0xFA001020): /* SMMU CBAR8 */
391 case(0xFA028030): /* SMMU TCR_LPAE */
392 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
393 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
394 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
395 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
396 case(0xFA028010): /* SMMU_CB8)TCR2 */
397 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
398 case(0xFA001820): /* SMMU_CBA2R8 */
399 case(0xFA000074): /* SMMU_STLBGSTATUS */
400 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
401 case(0xFA000060): /* SMMU_STLBIALL */
402 case(0xFA000070): /* SMMU_STLBGSYNC */
403 case(0xFA028618): /* CB8_TLBALL */
404 case(0xFA0287F0): /* CB8_TLBSYNC */
405 case(0xFFD12028): /* SDMMCGRP_CTRL */
406 case(0xFFD12044): /* EMAC0 */
407 case(0xFFD12048): /* EMAC1 */
408 case(0xFFD1204C): /* EMAC2 */
409 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
410 case(0xFFD12094): /* ECC_INT_MASK_SET */
411 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
412 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
413 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
414 case(0xFFD120C0): /* NOC_TIMEOUT */
415 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
416 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
417 case(0xFFD120D0): /* NOC_IDLEACK */
418 case(0xFFD120D4): /* NOC_IDLESTATUS */
419 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
420 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
421 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
422 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
423 return 0;
424 #else
425 switch (reg_addr) {
426
427 case(0xF8011104): /* ECCCTRL2 */
428 case(0xFFD12028): /* SDMMCGRP_CTRL */
429 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
430 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
431 case(0xFFD120D0): /* NOC_IDLEACK */
432
433
434 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */
435 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */
436 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */
437 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */
438 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */
439 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */
440 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
441 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
442
443 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */
444 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
445 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
446 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
447 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
449 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
450 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
451 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */
452 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */
453 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */
454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */
455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
457 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
458 #endif
459 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
460 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
461 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
462 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */
463 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */
464 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */
465 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */
466 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */
467 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
468 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
469 return 0;
470
471 default:
472 break;
473 }
474
475 return -1;
476 }
477
478 /* Secure register access */
479 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
480 {
481 if (is_out_of_sec_range(reg_addr)) {
482 return INTEL_SIP_SMC_STATUS_ERROR;
483 }
484
485 *retval = mmio_read_32(reg_addr);
486
487 return INTEL_SIP_SMC_STATUS_OK;
488 }
489
490 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
491 uint32_t *retval)
492 {
493 if (is_out_of_sec_range(reg_addr)) {
494 return INTEL_SIP_SMC_STATUS_ERROR;
495 }
496
497 switch (reg_addr) {
498 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
499 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
500 mmio_write_16(reg_addr, val);
501 break;
502 default:
503 mmio_write_32(reg_addr, val);
504 break;
505 }
506
507 return intel_secure_reg_read(reg_addr, retval);
508 }
509
510 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
511 uint32_t val, uint32_t *retval)
512 {
513 if (!intel_secure_reg_read(reg_addr, retval)) {
514 *retval &= ~mask;
515 *retval |= val & mask;
516 return intel_secure_reg_write(reg_addr, *retval, retval);
517 }
518
519 return INTEL_SIP_SMC_STATUS_ERROR;
520 }
521
522 /* Intel Remote System Update (RSU) services */
523 uint64_t intel_rsu_update_address;
524
525 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
526 {
527 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
528 return INTEL_SIP_SMC_RSU_ERROR;
529 }
530
531 return INTEL_SIP_SMC_STATUS_OK;
532 }
533
534 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf,
535 unsigned int respbuf_sz)
536 {
537 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) {
538 return INTEL_SIP_SMC_RSU_ERROR;
539 }
540
541 return INTEL_SIP_SMC_STATUS_OK;
542 }
543
544 uint32_t intel_rsu_update(uint64_t update_address)
545 {
546 if (update_address > SIZE_MAX) {
547 return INTEL_SIP_SMC_STATUS_REJECTED;
548 }
549
550 intel_rsu_update_address = update_address;
551 return INTEL_SIP_SMC_STATUS_OK;
552 }
553
554 static uint32_t intel_rsu_notify(uint32_t execution_stage)
555 {
556 if (mailbox_hps_stage_notify(execution_stage) < 0) {
557 return INTEL_SIP_SMC_RSU_ERROR;
558 }
559
560 return INTEL_SIP_SMC_STATUS_OK;
561 }
562
563 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
564 uint32_t *ret_stat)
565 {
566 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
567 return INTEL_SIP_SMC_RSU_ERROR;
568 }
569
570 *ret_stat = respbuf[8];
571 return INTEL_SIP_SMC_STATUS_OK;
572 }
573
574 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
575 uint64_t dcmf_ver_3_2)
576 {
577 rsu_dcmf_ver[0] = dcmf_ver_1_0;
578 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
579 rsu_dcmf_ver[2] = dcmf_ver_3_2;
580 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
581
582 return INTEL_SIP_SMC_STATUS_OK;
583 }
584
585 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
586 {
587 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
588 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
589 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
590 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
591
592 return INTEL_SIP_SMC_STATUS_OK;
593 }
594
595 /* Intel HWMON services */
596 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
597 {
598 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
599 return INTEL_SIP_SMC_STATUS_ERROR;
600 }
601
602 return INTEL_SIP_SMC_STATUS_OK;
603 }
604
605 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
606 {
607 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
608 return INTEL_SIP_SMC_STATUS_ERROR;
609 }
610
611 return INTEL_SIP_SMC_STATUS_OK;
612 }
613
614 /* Mailbox services */
615 static uint32_t intel_smc_fw_version(uint32_t *fw_version)
616 {
617 int status;
618 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
619 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
620
621 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
622 CMD_CASUAL, resp_data, &resp_len);
623
624 if (status < 0) {
625 return INTEL_SIP_SMC_STATUS_ERROR;
626 }
627
628 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
629 return INTEL_SIP_SMC_STATUS_ERROR;
630 }
631
632 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
633
634 return INTEL_SIP_SMC_STATUS_OK;
635 }
636
637 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
638 unsigned int len, uint32_t urgent, uint64_t response,
639 unsigned int resp_len, int *mbox_status,
640 unsigned int *len_in_resp)
641 {
642 *len_in_resp = 0;
643 *mbox_status = GENERIC_RESPONSE_ERROR;
644
645 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
646 return INTEL_SIP_SMC_STATUS_REJECTED;
647 }
648
649 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
650 (uint32_t *) response, &resp_len);
651
652 if (status < 0) {
653 *mbox_status = -status;
654 return INTEL_SIP_SMC_STATUS_ERROR;
655 }
656
657 *mbox_status = 0;
658 *len_in_resp = resp_len;
659
660 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
661
662 return INTEL_SIP_SMC_STATUS_OK;
663 }
664
665 static int intel_smc_get_usercode(uint32_t *user_code)
666 {
667 int status;
668 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
669
670 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
671 0U, CMD_CASUAL, user_code, &resp_len);
672
673 if (status < 0) {
674 return INTEL_SIP_SMC_STATUS_ERROR;
675 }
676
677 return INTEL_SIP_SMC_STATUS_OK;
678 }
679
680 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
681 uint32_t mode, uint32_t *job_id,
682 uint32_t *ret_size, uint32_t *mbox_error)
683 {
684 int status = 0;
685 uint32_t resp_len = size / MBOX_WORD_BYTE;
686
687 if (resp_len > MBOX_DATA_MAX_LEN) {
688 return INTEL_SIP_SMC_STATUS_REJECTED;
689 }
690
691 if (!is_address_in_ddr_range(addr, size)) {
692 return INTEL_SIP_SMC_STATUS_REJECTED;
693 }
694
695 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
696 status = mailbox_read_response_async(job_id,
697 NULL, (uint32_t *) addr, &resp_len, 0);
698 } else {
699 status = mailbox_read_response(job_id,
700 (uint32_t *) addr, &resp_len);
701
702 if (status == MBOX_NO_RESPONSE) {
703 status = MBOX_BUSY;
704 }
705 }
706
707 if (status == MBOX_NO_RESPONSE) {
708 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
709 }
710
711 if (status == MBOX_BUSY) {
712 return INTEL_SIP_SMC_STATUS_BUSY;
713 }
714
715 *ret_size = resp_len * MBOX_WORD_BYTE;
716 flush_dcache_range(addr, *ret_size);
717
718 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
719 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
720 *mbox_error = -status;
721 } else if (status != MBOX_RET_OK) {
722 *mbox_error = -status;
723 return INTEL_SIP_SMC_STATUS_ERROR;
724 }
725
726 return INTEL_SIP_SMC_STATUS_OK;
727 }
728
729 /* Miscellaneous HPS services */
730 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
731 {
732 int status = 0;
733
734 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
735 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
736 status = socfpga_bridges_enable((uint32_t)mask);
737 } else {
738 status = socfpga_bridges_enable(~0);
739 }
740 } else {
741 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
742 status = socfpga_bridges_disable((uint32_t)mask);
743 } else {
744 status = socfpga_bridges_disable(~0);
745 }
746 }
747
748 if (status < 0) {
749 return INTEL_SIP_SMC_STATUS_ERROR;
750 }
751
752 return INTEL_SIP_SMC_STATUS_OK;
753 }
754
755 /* SDM SEU Error services */
756 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
757 {
758 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
759 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
760 }
761
762 return INTEL_SIP_SMC_STATUS_OK;
763 }
764
765 /* SDM SAFE SEU Error inject services */
766 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
767 {
768 if (mailbox_safe_inject_seu_err(command, len) < 0) {
769 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
770 }
771
772 return INTEL_SIP_SMC_STATUS_OK;
773 }
774
775 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
776 /* SMMU HPS Remapper */
777 void intel_smmu_hps_remapper_init(uint64_t *mem)
778 {
779 /* Read out Bit 1 value */
780 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02);
781
782 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) {
783 /* Update DRAM Base address for SDM SMMU */
784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
785 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
786 *mem = *mem - DRAM_BASE;
787 } else {
788 *mem = *mem - DRAM_BASE;
789 }
790 }
791
792 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass)
793 {
794 /* Read out the JTAG-ID from boot scratch register */
795 if (is_agilex5_A5F0() || is_agilex5_A5F4()) {
796 if (remapper_bypass == 0x01) {
797 g_remapper_bypass = remapper_bypass;
798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0);
799 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0);
800 }
801 }
802 return INTEL_SIP_SMC_STATUS_OK;
803 }
804
805 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
806 {
807 volatile uint64_t atf_ddr_buffer;
808 volatile uint64_t val;
809
810 mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
811 mmio_write_32(IOSSM_CMD_TRIG_OP, command);
812 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
813 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */
814 memcpy_s((void *)&val, sizeof(val),
815 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
816
817 /* Clear response_ready BIT0 of status_register before sending next command. */
818 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
819 }
820 #endif
821
822 #if SIP_SVC_V3
823 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
824 {
825 uint8_t ret_args_len = 0U;
826 sdm_response_t *resp = (sdm_response_t *)resp_desc;
827 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
828
829 (void)cmd;
830 /* Returns 3 SMC arguments for SMC_RET3 */
831 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
832 ret_args[ret_args_len++] = resp->err_code;
833
834 return ret_args_len;
835 }
836
837 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
838 {
839 uint8_t ret_args_len = 0U;
840 sdm_response_t *resp = (sdm_response_t *)resp_desc;
841 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
842
843 (void)cmd;
844 /* Returns 3 SMC arguments for SMC_RET3 */
845 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
846 ret_args[ret_args_len++] = resp->err_code;
847 ret_args[ret_args_len++] = resp->resp_data[0];
848
849 return ret_args_len;
850 }
851
852 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
853 {
854 uint8_t ret_args_len = 0U;
855 sdm_response_t *resp = (sdm_response_t *)resp_desc;
856 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
857
858 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n",
859 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
860
861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
862 ret_args[ret_args_len++] = resp->err_code;
863 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
864
865 /* Flush the response data buffer. */
866 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE);
867
868 return ret_args_len;
869 }
870
871 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
872 {
873 uint8_t ret_args_len = 0U;
874 sdm_response_t *resp = (sdm_response_t *)resp_desc;
875 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
876
877 (void)cmd;
878 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n",
879 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]);
880
881 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
882 ret_args[ret_args_len++] = resp->err_code;
883 ret_args[ret_args_len++] = resp->resp_data[0];
884 ret_args[ret_args_len++] = resp->resp_data[1];
885
886 return ret_args_len;
887 }
888
889 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
890 {
891 uint8_t ret_args_len = 0U;
892 uint32_t retry_counter = ~0U;
893 uint32_t failure_source = 0U;
894 sdm_response_t *resp = (sdm_response_t *)resp_desc;
895 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
896
897 (void)cmd;
898 /* Get the failure source and current image retry counter value from the response. */
899 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
900 retry_counter = resp->resp_data[8];
901
902 if ((retry_counter != ~0U) && (failure_source == 0U))
903 resp->resp_data[5] |= RSU_VERSION_ACMF;
904
905 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
906 ret_args[ret_args_len++] = resp->err_code;
907 /* Current CMF */
908 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
909 /* Last Failing CMF Address */
910 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
911 /* Config State */
912 ret_args[ret_args_len++] = resp->resp_data[4];
913 /* Version */
914 ret_args[ret_args_len++] = resp->resp_data[5];
915 /* Failure Source */
916 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
917 /* Error location */
918 ret_args[ret_args_len++] = resp->resp_data[6];
919 /* Error details */
920 ret_args[ret_args_len++] = resp->resp_data[7];
921 /* Current image retry counter */
922 ret_args[ret_args_len++] = resp->resp_data[8];
923
924 return ret_args_len;
925 }
926
927 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
928 {
929 uint8_t ret_args_len = 0U;
930 sdm_response_t *resp = (sdm_response_t *)resp_desc;
931 sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
932
933 (void)cmd;
934
935 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
936 ret_args[ret_args_len++] = resp->err_code;
937 /* Sub Partition Table (SPT) 0 address */
938 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
939 /* Sub Partition Table (SPT) 1 address */
940 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
941
942 return ret_args_len;
943 }
944
945 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
946 {
947
948 switch (ret_args_len) {
949 case SMC_RET_ARGS_ONE:
950 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
951 SMC_RET1(handle, ret_args[0]);
952 break;
953
954 case SMC_RET_ARGS_TWO:
955 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
956 SMC_RET2(handle, ret_args[0], ret_args[1]);
957 break;
958
959 case SMC_RET_ARGS_THREE:
960 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
961 __func__, ret_args[0], ret_args[1], ret_args[2]);
962 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
963 break;
964
965 case SMC_RET_ARGS_FOUR:
966 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
967 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
968 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
969 break;
970
971 case SMC_RET_ARGS_FIVE:
972 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
973 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
974 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
975 break;
976
977 case SMC_RET_ARGS_SIX:
978 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
979 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
980 ret_args[5]);
981 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
982 ret_args[5]);
983 break;
984
985 case SMC_RET_ARGS_SEVEN:
986 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
987 "x6 0x%lx\n",
988 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
989 ret_args[5], ret_args[6]);
990 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
991 ret_args[5], ret_args[6]);
992 break;
993
994 case SMC_RET_ARGS_EIGHT:
995 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
996 "x6 0x%lx, x7 0x%lx\n",
997 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
998 ret_args[5], ret_args[6], ret_args[7]);
999 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
1000 ret_args[5], ret_args[6], ret_args[7]);
1001 break;
1002
1003 case SMC_RET_ARGS_NINE:
1004 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
1005 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
1006 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
1007 ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
1008 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
1009 ret_args[5], ret_args[6], ret_args[7], ret_args[8],
1010 0, 0, 0, 0, 0, 0, 0, 0, 0);
1011 break;
1012
1013 case SMC_RET_ARGS_TEN:
1014 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
1015 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
1016 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
1017 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
1018 ret_args[9], ret_args[10]);
1019 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
1020 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
1021 0, 0, 0, 0, 0, 0, 0, 0);
1022 break;
1023
1024 default:
1025 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
1026 __func__, ret_args_len);
1027 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
1028 break;
1029 }
1030 }
1031
1032 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
1033 {
1034 /* Check if the command is allowed to be executed in generic mbox format */
1035 bool is_cmd_allowed = false;
1036
1037 switch (cmd) {
1038 case MBOX_FCS_OPEN_CS_SESSION:
1039 case MBOX_FCS_CLOSE_CS_SESSION:
1040 case MBOX_FCS_IMPORT_CS_KEY:
1041 case MBOX_FCS_EXPORT_CS_KEY:
1042 case MBOX_FCS_REMOVE_CS_KEY:
1043 case MBOX_FCS_GET_CS_KEY_INFO:
1044 case MBOX_FCS_CREATE_CS_KEY:
1045 case MBOX_FCS_GET_DIGEST_REQ:
1046 case MBOX_FCS_MAC_VERIFY_REQ:
1047 case MBOX_FCS_ECDSA_HASH_SIGN_REQ:
1048 case MBOX_FCS_GET_PROVISION:
1049 case MBOX_FCS_CNTR_SET_PREAUTH:
1050 case MBOX_FCS_ENCRYPT_REQ:
1051 case MBOX_FCS_DECRYPT_REQ:
1052 case MBOX_FCS_RANDOM_GEN:
1053 case MBOX_FCS_AES_CRYPT_REQ:
1054 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ:
1055 case MBOX_FCS_ECDSA_HASH_SIG_VERIFY:
1056 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY:
1057 case MBOX_FCS_ECDSA_GET_PUBKEY:
1058 case MBOX_FCS_ECDH_REQUEST:
1059 case MBOX_FCS_HKDF_REQUEST:
1060 /* These mailbox commands are not supported in the generic mailbox format. */
1061 break;
1062
1063 default:
1064 is_cmd_allowed = true;
1065 break;
1066 } /* switch */
1067
1068 return is_cmd_allowed;
1069 }
1070
1071 /*
1072 * This function is responsible for handling all SiP SVC V3 calls from the
1073 * non-secure world.
1074 */
1075 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid,
1076 u_register_t x1,
1077 u_register_t x2,
1078 u_register_t x3,
1079 u_register_t x4,
1080 void *cookie,
1081 void *handle,
1082 u_register_t flags)
1083 {
1084 int status = 0;
1085 uint32_t mbox_error = 0U;
1086 u_register_t x5, x6, x7, x8, x9, x10, x11;
1087
1088 /* Get all the SMC call arguments */
1089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1090 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1091 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1092 x8 = SMC_GET_GP(handle, CTX_GPREG_X8);
1093 x9 = SMC_GET_GP(handle, CTX_GPREG_X9);
1094 x10 = SMC_GET_GP(handle, CTX_GPREG_X10);
1095 x11 = SMC_GET_GP(handle, CTX_GPREG_X11);
1096
1097 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n",
1098 smc_fid, x1, x2, x3, x4, x5);
1099 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n",
1100 x6, x7, x8, x9, x10, x11);
1101
1102 switch (smc_fid) {
1103 case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
1104 {
1105 uint64_t ret_args[16] = {0};
1106 uint32_t ret_args_len = 0;
1107
1108 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
1109 GET_JOB_ID(x1),
1110 ret_args,
1111 &ret_args_len);
1112 /* Always reserve [0] index for command status. */
1113 ret_args[0] = status;
1114
1115 /* Return SMC call based on the number of return arguments */
1116 return smc_ret(handle, ret_args, ret_args_len);
1117 }
1118
1119 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR:
1120 {
1121 /* TBD: Here now we don't need these CID and JID?? */
1122 uint8_t client_id = 0U;
1123 uint8_t job_id = 0U;
1124 uint64_t trans_id_bitmap[4] = {0U};
1125
1126 status = mailbox_response_poll_on_intr_v3(&client_id,
1127 &job_id,
1128 trans_id_bitmap);
1129
1130 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1],
1131 trans_id_bitmap[2], trans_id_bitmap[3]);
1132 break;
1133 }
1134
1135 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY:
1136 {
1137 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1138 GET_JOB_ID(x1),
1139 MBOX_CMD_GET_DEVICEID,
1140 NULL,
1141 0U,
1142 MBOX_CMD_FLAG_CASUAL,
1143 sip_smc_ret_nbytes_cb,
1144 (uint32_t *)x2,
1145 2);
1146
1147 SMC_RET1(handle, status);
1148 }
1149
1150 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE:
1151 {
1152 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1153 GET_JOB_ID(x1),
1154 MBOX_CMD_GET_IDCODE,
1155 NULL,
1156 0U,
1157 MBOX_CMD_FLAG_CASUAL,
1158 sip_smc_cmd_cb_ret3,
1159 NULL,
1160 0);
1161
1162 SMC_RET1(handle, status);
1163 }
1164
1165 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN:
1166 {
1167 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1168 GET_JOB_ID(x1),
1169 MBOX_CMD_QSPI_OPEN,
1170 NULL,
1171 0U,
1172 MBOX_CMD_FLAG_CASUAL,
1173 sip_smc_cmd_cb_ret2,
1174 NULL,
1175 0U);
1176
1177 SMC_RET1(handle, status);
1178 }
1179
1180 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE:
1181 {
1182 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1183 GET_JOB_ID(x1),
1184 MBOX_CMD_QSPI_CLOSE,
1185 NULL,
1186 0U,
1187 MBOX_CMD_FLAG_CASUAL,
1188 sip_smc_cmd_cb_ret2,
1189 NULL,
1190 0U);
1191
1192 SMC_RET1(handle, status);
1193 }
1194
1195 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS:
1196 {
1197 uint32_t cmd_data = 0U;
1198 uint32_t chip_sel = (uint32_t)x2;
1199 uint32_t comb_addr_mode = (uint32_t)x3;
1200 uint32_t ext_dec_mode = (uint32_t)x4;
1201
1202 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) |
1203 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) |
1204 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET);
1205
1206 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1207 GET_JOB_ID(x1),
1208 MBOX_CMD_QSPI_SET_CS,
1209 &cmd_data,
1210 1U,
1211 MBOX_CMD_FLAG_CASUAL,
1212 sip_smc_cmd_cb_ret2,
1213 NULL,
1214 0U);
1215
1216 SMC_RET1(handle, status);
1217 }
1218
1219 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE:
1220 {
1221 uint32_t qspi_addr = (uint32_t)x2;
1222 uint32_t qspi_nwords = (uint32_t)x3;
1223
1224 /* QSPI address offset to start erase, must be 4K aligned */
1225 if (MBOX_IS_4K_ALIGNED(qspi_addr)) {
1226 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n",
1227 smc_fid);
1228 status = INTEL_SIP_SMC_STATUS_REJECTED;
1229 SMC_RET1(handle, status);
1230 }
1231
1232 /* Number of words to erase, multiples of 0x400 or 4K */
1233 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) {
1234 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n",
1235 smc_fid);
1236 status = INTEL_SIP_SMC_STATUS_REJECTED;
1237 SMC_RET1(handle, status);
1238 }
1239
1240 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
1241
1242 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1243 GET_JOB_ID(x1),
1244 MBOX_CMD_QSPI_ERASE,
1245 cmd_data,
1246 sizeof(cmd_data) / MBOX_WORD_BYTE,
1247 MBOX_CMD_FLAG_CASUAL,
1248 sip_smc_cmd_cb_ret2,
1249 NULL,
1250 0U);
1251
1252 SMC_RET1(handle, status);
1253 }
1254
1255 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE:
1256 {
1257 uint32_t *qspi_payload = (uint32_t *)x2;
1258 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE);
1259 uint32_t qspi_addr = qspi_payload[0];
1260 uint32_t qspi_nwords = qspi_payload[1];
1261
1262 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) {
1263 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n",
1264 smc_fid);
1265 status = INTEL_SIP_SMC_STATUS_REJECTED;
1266 SMC_RET1(handle, status);
1267 }
1268
1269 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
1270 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
1271 smc_fid);
1272 status = INTEL_SIP_SMC_STATUS_REJECTED;
1273 SMC_RET1(handle, status);
1274 }
1275
1276 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1277 GET_JOB_ID(x1),
1278 MBOX_CMD_QSPI_WRITE,
1279 qspi_payload,
1280 qspi_total_nwords,
1281 MBOX_CMD_FLAG_CASUAL,
1282 sip_smc_cmd_cb_ret2,
1283 NULL,
1284 0U);
1285
1286 SMC_RET1(handle, status);
1287 }
1288
1289 case ALTERA_SIP_SMC_ASYNC_QSPI_READ:
1290 {
1291 uint32_t qspi_addr = (uint32_t)x2;
1292 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE);
1293
1294 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
1295 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
1296 smc_fid);
1297 status = INTEL_SIP_SMC_STATUS_REJECTED;
1298 SMC_RET1(handle, status);
1299 }
1300
1301 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
1302
1303 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1304 GET_JOB_ID(x1),
1305 MBOX_CMD_QSPI_READ,
1306 cmd_data,
1307 sizeof(cmd_data) / MBOX_WORD_BYTE,
1308 MBOX_CMD_FLAG_CASUAL,
1309 sip_smc_ret_nbytes_cb,
1310 (uint32_t *)x3,
1311 2);
1312
1313 SMC_RET1(handle, status);
1314 }
1315
1316 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO:
1317 {
1318 uint32_t *dst_addr = (uint32_t *)x2;
1319
1320 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1321 GET_JOB_ID(x1),
1322 MBOX_CMD_QSPI_GET_DEV_INFO,
1323 NULL,
1324 0U,
1325 MBOX_CMD_FLAG_CASUAL,
1326 sip_smc_ret_nbytes_cb,
1327 (uint32_t *)dst_addr,
1328 2);
1329
1330 SMC_RET1(handle, status);
1331 }
1332
1333 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT:
1334 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP:
1335 {
1336 uint32_t channel = (uint32_t)x2;
1337 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ?
1338 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP);
1339
1340 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1341 GET_JOB_ID(x1),
1342 mbox_cmd,
1343 &channel,
1344 1U,
1345 MBOX_CMD_FLAG_CASUAL,
1346 sip_smc_cmd_cb_ret3,
1347 NULL,
1348 0);
1349
1350 SMC_RET1(handle, status);
1351 }
1352
1353 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
1354 {
1355 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1356 GET_JOB_ID(x1),
1357 MBOX_GET_SUBPARTITION_TABLE,
1358 NULL,
1359 0,
1360 MBOX_CMD_FLAG_CASUAL,
1361 sip_smc_cmd_cb_rsu_spt,
1362 NULL,
1363 0);
1364
1365 SMC_RET1(handle, status);
1366 }
1367
1368 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
1369 {
1370 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1371 GET_JOB_ID(x1),
1372 MBOX_RSU_STATUS,
1373 NULL,
1374 0,
1375 MBOX_CMD_FLAG_CASUAL,
1376 sip_smc_cmd_cb_rsu_status,
1377 NULL,
1378 0);
1379
1380 SMC_RET1(handle, status);
1381 }
1382
1383 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
1384 {
1385 uint32_t notify_code = (uint32_t)x2;
1386
1387 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1388 GET_JOB_ID(x1),
1389 MBOX_HPS_STAGE_NOTIFY,
1390 ¬ify_code,
1391 1U,
1392 MBOX_CMD_FLAG_CASUAL,
1393 sip_smc_cmd_cb_ret2,
1394 NULL,
1395 0);
1396
1397 SMC_RET1(handle, status);
1398 }
1399
1400 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
1401 {
1402 /* Collect all the args passed in, and send the mailbox command. */
1403 uint32_t mbox_cmd = (uint32_t)x2;
1404 uint32_t *cmd_payload_addr = NULL;
1405 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
1406 uint32_t *resp_payload_addr = NULL;
1407 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
1408
1409 /* Filter the required commands here. */
1410 if (!is_gen_mbox_cmd_allowed(mbox_cmd)) {
1411 status = INTEL_SIP_SMC_STATUS_REJECTED;
1412 SMC_RET1(handle, status);
1413 }
1414
1415 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
1416 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
1417 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
1418 smc_fid);
1419 status = INTEL_SIP_SMC_STATUS_REJECTED;
1420 SMC_RET1(handle, status);
1421 }
1422
1423 /* Make sure we have valid command payload length and buffer */
1424 if (cmd_payload_len != 0U) {
1425 cmd_payload_addr = (uint32_t *)x3;
1426 if (cmd_payload_addr == NULL) {
1427 ERROR("MBOX: 0x%x: Command payload address is NULL\n",
1428 smc_fid);
1429 status = INTEL_SIP_SMC_STATUS_REJECTED;
1430 SMC_RET1(handle, status);
1431 }
1432 }
1433
1434 /* Make sure we have valid response payload length and buffer */
1435 if (resp_payload_len != 0U) {
1436 resp_payload_addr = (uint32_t *)x5;
1437 if (resp_payload_addr == NULL) {
1438 ERROR("MBOX: 0x%x: Response payload address is NULL\n",
1439 smc_fid);
1440 status = INTEL_SIP_SMC_STATUS_REJECTED;
1441 SMC_RET1(handle, status);
1442 }
1443 }
1444
1445 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1446 GET_JOB_ID(x1),
1447 mbox_cmd,
1448 (uint32_t *)cmd_payload_addr,
1449 cmd_payload_len,
1450 MBOX_CMD_FLAG_CASUAL,
1451 sip_smc_ret_nbytes_cb,
1452 (uint32_t *)resp_payload_addr,
1453 resp_payload_len);
1454
1455 SMC_RET1(handle, status);
1456 }
1457
1458 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
1459 {
1460 uint32_t session_id = (uint32_t)x2;
1461 uint32_t context_id = (uint32_t)x3;
1462 uint64_t ret_random_addr = (uint64_t)x4;
1463 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
1464 uint32_t crypto_header = 0U;
1465
1466 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) ||
1467 (random_len == 0U) ||
1468 (!is_size_4_bytes_aligned(random_len))) {
1469 ERROR("MBOX: 0x%x is rejected\n", smc_fid);
1470 status = INTEL_SIP_SMC_STATUS_REJECTED;
1471 SMC_RET1(handle, status);
1472 }
1473
1474 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) <<
1475 FCS_CS_FIELD_FLAG_OFFSET);
1476 fcs_rng_payload payload = {session_id, context_id,
1477 crypto_header, random_len};
1478
1479 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1480 GET_JOB_ID(x1),
1481 MBOX_FCS_RANDOM_GEN,
1482 (uint32_t *)&payload,
1483 sizeof(payload) / MBOX_WORD_BYTE,
1484 MBOX_CMD_FLAG_CASUAL,
1485 sip_smc_ret_nbytes_cb,
1486 (uint32_t *)ret_random_addr,
1487 2);
1488 SMC_RET1(handle, status);
1489 }
1490
1491 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA:
1492 {
1493 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1494 GET_JOB_ID(x1),
1495 MBOX_FCS_GET_PROVISION,
1496 NULL,
1497 0U,
1498 MBOX_CMD_FLAG_CASUAL,
1499 sip_smc_ret_nbytes_cb,
1500 (uint32_t *)x2,
1501 2);
1502 SMC_RET1(handle, status);
1503 }
1504
1505 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH:
1506 {
1507 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3,
1508 x4, &mbox_error);
1509 SMC_RET1(handle, status);
1510 }
1511
1512 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID:
1513 {
1514 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1515 GET_JOB_ID(x1),
1516 MBOX_CMD_GET_CHIPID,
1517 NULL,
1518 0U,
1519 MBOX_CMD_FLAG_CASUAL,
1520 sip_smc_get_chipid_cb,
1521 NULL,
1522 0);
1523 SMC_RET1(handle, status);
1524 }
1525
1526 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT:
1527 {
1528 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
1529 (uint32_t *) &x4, &mbox_error);
1530 SMC_RET1(handle, status);
1531 }
1532
1533 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD:
1534 {
1535 status = intel_fcs_create_cert_on_reload(smc_fid, x1,
1536 x2, &mbox_error);
1537 SMC_RET1(handle, status);
1538 }
1539
1540 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
1541 {
1542 if (x4 == FCS_MODE_ENCRYPT) {
1543 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3,
1544 x5, x6, x7, (uint32_t *) &x8,
1545 &mbox_error, x10, x11);
1546 } else if (x4 == FCS_MODE_DECRYPT) {
1547 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3,
1548 x5, x6, x7, (uint32_t *) &x8,
1549 &mbox_error, x9, x10, x11);
1550 } else {
1551 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid);
1552 status = INTEL_SIP_SMC_STATUS_REJECTED;
1553 }
1554 SMC_RET1(handle, status);
1555 }
1556
1557 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE:
1558 {
1559 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error);
1560 SMC_RET1(handle, status);
1561 }
1562
1563 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
1564 {
1565 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1566 GET_JOB_ID(x1),
1567 MBOX_FCS_OPEN_CS_SESSION,
1568 NULL,
1569 0U,
1570 MBOX_CMD_FLAG_CASUAL,
1571 sip_smc_cmd_cb_ret3,
1572 NULL,
1573 0);
1574 SMC_RET1(handle, status);
1575 }
1576
1577 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
1578 {
1579 uint32_t session_id = (uint32_t)x2;
1580
1581 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1582 GET_JOB_ID(x1),
1583 MBOX_FCS_CLOSE_CS_SESSION,
1584 &session_id,
1585 1U,
1586 MBOX_CMD_FLAG_CASUAL,
1587 sip_smc_cmd_cb_ret2,
1588 NULL,
1589 0);
1590 SMC_RET1(handle, status);
1591 }
1592
1593 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
1594 {
1595 uint64_t key_addr = x2;
1596 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
1597
1598 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) ||
1599 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) {
1600 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n",
1601 smc_fid);
1602 status = INTEL_SIP_SMC_STATUS_REJECTED;
1603 SMC_RET1(handle, status);
1604 }
1605
1606 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1607 GET_JOB_ID(x1),
1608 MBOX_FCS_IMPORT_CS_KEY,
1609 (uint32_t *)key_addr,
1610 key_len_words,
1611 MBOX_CMD_FLAG_CASUAL,
1612 sip_smc_cmd_cb_ret3,
1613 NULL,
1614 0);
1615 SMC_RET1(handle, status);
1616 }
1617
1618 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
1619 {
1620 uint64_t key_addr = x2;
1621 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
1622
1623 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) {
1624 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
1625 status = INTEL_SIP_SMC_STATUS_REJECTED;
1626 SMC_RET1(handle, status);
1627 }
1628
1629 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1630 GET_JOB_ID(x1),
1631 MBOX_FCS_CREATE_CS_KEY,
1632 (uint32_t *)key_addr,
1633 key_len_words,
1634 MBOX_CMD_FLAG_CASUAL,
1635 sip_smc_cmd_cb_ret3,
1636 NULL,
1637 0);
1638 SMC_RET1(handle, status);
1639 }
1640
1641 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
1642 {
1643 uint32_t session_id = (uint32_t)x2;
1644 uint32_t key_uid = (uint32_t)x3;
1645 uint64_t ret_key_addr = (uint64_t)x4;
1646 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
1647
1648 if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
1649 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
1650 status = INTEL_SIP_SMC_STATUS_REJECTED;
1651 SMC_RET1(handle, status);
1652 }
1653
1654 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
1655 RESERVED_AS_ZERO, key_uid};
1656
1657 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1658 GET_JOB_ID(x1),
1659 MBOX_FCS_EXPORT_CS_KEY,
1660 (uint32_t *)&payload,
1661 sizeof(payload) / MBOX_WORD_BYTE,
1662 MBOX_CMD_FLAG_CASUAL,
1663 sip_smc_ret_nbytes_cb,
1664 (uint32_t *)ret_key_addr,
1665 2);
1666 SMC_RET1(handle, status);
1667 }
1668
1669 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
1670 {
1671 uint32_t session_id = (uint32_t)x2;
1672 uint32_t key_uid = (uint32_t)x3;
1673
1674 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
1675 RESERVED_AS_ZERO, key_uid};
1676
1677 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1678 GET_JOB_ID(x1),
1679 MBOX_FCS_REMOVE_CS_KEY,
1680 (uint32_t *)&payload,
1681 sizeof(payload) / MBOX_WORD_BYTE,
1682 MBOX_CMD_FLAG_CASUAL,
1683 sip_smc_cmd_cb_ret3,
1684 NULL,
1685 0);
1686 SMC_RET1(handle, status);
1687 }
1688
1689 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
1690 {
1691 uint32_t session_id = (uint32_t)x2;
1692 uint32_t key_uid = (uint32_t)x3;
1693 uint64_t ret_key_addr = (uint64_t)x4;
1694 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
1695
1696 if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
1697 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
1698 status = INTEL_SIP_SMC_STATUS_REJECTED;
1699 SMC_RET1(handle, status);
1700 }
1701
1702 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
1703 RESERVED_AS_ZERO, key_uid};
1704
1705 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1706 GET_JOB_ID(x1),
1707 MBOX_FCS_GET_CS_KEY_INFO,
1708 (uint32_t *)&payload,
1709 sizeof(payload) / MBOX_WORD_BYTE,
1710 MBOX_CMD_FLAG_CASUAL,
1711 sip_smc_ret_nbytes_cb,
1712 (uint32_t *)ret_key_addr,
1713 2);
1714 SMC_RET1(handle, status);
1715 }
1716
1717 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT:
1718 {
1719 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
1720 x6, &mbox_error);
1721 SMC_RET1(handle, status);
1722 }
1723
1724 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE:
1725 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE:
1726 {
1727 uint32_t job_id = 0U;
1728 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ?
1729 true : false;
1730
1731 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2,
1732 x3, x4, x5, x6, x7, x8, is_final,
1733 &job_id, x9, x10);
1734 SMC_RET1(handle, status);
1735 }
1736
1737 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
1738 {
1739 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
1740 &mbox_error);
1741 SMC_RET1(handle, status);
1742 }
1743
1744 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
1745 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
1746 {
1747 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ?
1748 true : false;
1749
1750 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2,
1751 x3, x4, x5, x6, (uint32_t *) &x7,
1752 is_final, &mbox_error, x8);
1753
1754 SMC_RET1(handle, status);
1755 }
1756
1757 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
1758 {
1759 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6,
1760 &mbox_error);
1761 SMC_RET1(handle, status);
1762 }
1763
1764 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
1765 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
1766 {
1767 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ?
1768 true : false;
1769
1770 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2,
1771 x3, x4, x5, x6, (uint32_t *) &x7, x8,
1772 is_final, &mbox_error, x9);
1773 SMC_RET1(handle, status);
1774 }
1775
1776 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
1777 {
1778 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6,
1779 &mbox_error);
1780 SMC_RET1(handle, status);
1781 }
1782
1783 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
1784 {
1785 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3,
1786 x4, x5, x6, (uint32_t *) &x7,
1787 &mbox_error);
1788 SMC_RET1(handle, status);
1789 }
1790
1791 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
1792 {
1793 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6,
1794 &mbox_error);
1795 SMC_RET1(handle, status);
1796 }
1797
1798 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
1799 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
1800 {
1801 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE)
1802 ? true : false;
1803
1804 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
1805 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7,
1806 is_final, &mbox_error, x8);
1807 SMC_RET1(handle, status);
1808 }
1809
1810 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
1811 {
1812 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5,
1813 x6, &mbox_error);
1814 SMC_RET1(handle, status);
1815 }
1816
1817 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1818 {
1819 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1,
1820 x2, x3, x4, x5, x6, (uint32_t *) &x7,
1821 &mbox_error);
1822 SMC_RET1(handle, status);
1823 }
1824
1825 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1826 {
1827 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4,
1828 x5, x6, &mbox_error);
1829 SMC_RET1(handle, status);
1830 }
1831
1832 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1833 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1834 {
1835 bool is_final = (smc_fid ==
1836 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ?
1837 true : false;
1838
1839 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1840 smc_fid, x1, x2, x3, x4, x5, x6,
1841 (uint32_t *) &x7, x8, is_final,
1842 &mbox_error, x9);
1843 SMC_RET1(handle, status);
1844 }
1845
1846 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
1847 {
1848 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6,
1849 &mbox_error);
1850 SMC_RET1(handle, status);
1851 }
1852
1853 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1854 {
1855 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3,
1856 x4, (uint32_t *) &x5, &mbox_error);
1857 SMC_RET1(handle, status);
1858 }
1859
1860 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
1861 {
1862 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6,
1863 &mbox_error);
1864 SMC_RET1(handle, status);
1865 }
1866
1867 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
1868 {
1869 uint32_t dest_size = (uint32_t)x7;
1870
1871 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n",
1872 __func__, __LINE__, (uint32_t)x7, dest_size);
1873
1874 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3,
1875 x4, x5, x6, (uint32_t *) &dest_size,
1876 &mbox_error);
1877 SMC_RET1(handle, status);
1878 }
1879
1880 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG:
1881 {
1882 uint32_t *src_addr = (uint32_t *)x2;
1883 uint32_t src_size = (uint32_t)x3;
1884 uint32_t *dst_addr = (uint32_t *)x4;
1885
1886 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1887 GET_JOB_ID(x1),
1888 MBOX_CMD_MCTP_MSG,
1889 src_addr,
1890 src_size / MBOX_WORD_BYTE,
1891 MBOX_CMD_FLAG_CASUAL,
1892 sip_smc_ret_nbytes_cb,
1893 dst_addr,
1894 2);
1895
1896 SMC_RET1(handle, status);
1897 }
1898
1899 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
1900 {
1901 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6,
1902 x7);
1903 SMC_RET1(handle, status);
1904 }
1905
1906 default:
1907 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1908 cookie, handle, flags);
1909 } /* switch (smc_fid) */
1910 }
1911 #endif
1912
1913 /*
1914 * This function is responsible for handling all SiP calls from the NS world
1915 */
1916
1917 uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
1918 u_register_t x1,
1919 u_register_t x2,
1920 u_register_t x3,
1921 u_register_t x4,
1922 void *cookie,
1923 void *handle,
1924 u_register_t flags)
1925 {
1926 uint32_t retval = 0, completed_addr[3];
1927 uint32_t retval2 = 0;
1928 uint32_t mbox_error = 0;
1929 uint32_t err_states = 0;
1930 uint64_t retval64, rsu_respbuf[9];
1931 uint32_t seu_respbuf[3];
1932 int status = INTEL_SIP_SMC_STATUS_OK;
1933 int mbox_status;
1934 unsigned int len_in_resp = 0;
1935 u_register_t x5, x6, x7;
1936
1937 switch (smc_fid) {
1938 case SIP_SVC_UID:
1939 /* Return UID to the caller */
1940 SMC_UUID_RET(handle, intl_svc_uid);
1941
1942 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
1943 status = intel_mailbox_fpga_config_isdone(&err_states);
1944 SMC_RET4(handle, status, err_states, 0, 0);
1945
1946 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
1947 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1948 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
1949 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
1950 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
1951
1952 case INTEL_SIP_SMC_FPGA_CONFIG_START:
1953 status = intel_fpga_config_start(x1);
1954 SMC_RET4(handle, status, 0, 0, 0);
1955
1956 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
1957 status = intel_fpga_config_write(x1, x2);
1958 SMC_RET4(handle, status, 0, 0, 0);
1959
1960 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
1961 status = intel_fpga_config_completed_write(completed_addr,
1962 &retval, &rcv_id);
1963 switch (retval) {
1964 case 1:
1965 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
1966 completed_addr[0], 0, 0);
1967
1968 case 2:
1969 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
1970 completed_addr[0],
1971 completed_addr[1], 0);
1972
1973 case 3:
1974 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
1975 completed_addr[0],
1976 completed_addr[1],
1977 completed_addr[2]);
1978
1979 case 0:
1980 SMC_RET4(handle, status, 0, 0, 0);
1981
1982 default:
1983 mailbox_clear_response();
1984 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
1985 }
1986
1987 case INTEL_SIP_SMC_REG_READ:
1988 status = intel_secure_reg_read(x1, &retval);
1989 SMC_RET3(handle, status, retval, x1);
1990
1991 case INTEL_SIP_SMC_REG_WRITE:
1992 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
1993 SMC_RET3(handle, status, retval, x1);
1994
1995 case INTEL_SIP_SMC_REG_UPDATE:
1996 status = intel_secure_reg_update(x1, (uint32_t)x2,
1997 (uint32_t)x3, &retval);
1998 SMC_RET3(handle, status, retval, x1);
1999
2000 case INTEL_SIP_SMC_RSU_STATUS:
2001 status = intel_rsu_status(rsu_respbuf,
2002 ARRAY_SIZE(rsu_respbuf));
2003 if (status) {
2004 SMC_RET1(handle, status);
2005 } else {
2006 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
2007 rsu_respbuf[2], rsu_respbuf[3]);
2008 }
2009
2010 case INTEL_SIP_SMC_RSU_UPDATE:
2011 status = intel_rsu_update(x1);
2012 SMC_RET1(handle, status);
2013
2014 case INTEL_SIP_SMC_RSU_NOTIFY:
2015 status = intel_rsu_notify(x1);
2016 SMC_RET1(handle, status);
2017
2018 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
2019 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
2020 ARRAY_SIZE(rsu_respbuf), &retval);
2021 if (status) {
2022 SMC_RET1(handle, status);
2023 } else {
2024 SMC_RET2(handle, status, retval);
2025 }
2026
2027 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
2028 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
2029 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
2030 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
2031
2032 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
2033 status = intel_rsu_copy_dcmf_version(x1, x2);
2034 SMC_RET1(handle, status);
2035
2036 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO:
2037 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf,
2038 ARRAY_SIZE(rsu_respbuf));
2039 if (status) {
2040 SMC_RET1(handle, status);
2041 } else {
2042 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1],
2043 rsu_respbuf[2], rsu_respbuf[3]);
2044 }
2045
2046 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
2047 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
2048 ((uint64_t)rsu_dcmf_stat[3] << 48) |
2049 ((uint64_t)rsu_dcmf_stat[2] << 32) |
2050 ((uint64_t)rsu_dcmf_stat[1] << 16) |
2051 rsu_dcmf_stat[0]);
2052
2053 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
2054 status = intel_rsu_copy_dcmf_status(x1);
2055 SMC_RET1(handle, status);
2056
2057 case INTEL_SIP_SMC_RSU_MAX_RETRY:
2058 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
2059
2060 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
2061 rsu_max_retry = x1;
2062 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
2063
2064 case INTEL_SIP_SMC_ECC_DBE:
2065 status = intel_ecc_dbe_notification(x1);
2066 SMC_RET1(handle, status);
2067
2068 case INTEL_SIP_SMC_SERVICE_COMPLETED:
2069 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
2070 &len_in_resp, &mbox_error);
2071 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
2072
2073 case INTEL_SIP_SMC_FIRMWARE_VERSION:
2074 status = intel_smc_fw_version(&retval);
2075 SMC_RET2(handle, status, retval);
2076
2077 case INTEL_SIP_SMC_MBOX_SEND_CMD:
2078 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2079 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2080 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
2081 &mbox_status, &len_in_resp);
2082 SMC_RET3(handle, status, mbox_status, len_in_resp);
2083
2084 case INTEL_SIP_SMC_GET_USERCODE:
2085 status = intel_smc_get_usercode(&retval);
2086 SMC_RET2(handle, status, retval);
2087
2088 case INTEL_SIP_SMC_FCS_CRYPTION:
2089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2090
2091 if (x1 == FCS_MODE_DECRYPT) {
2092 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
2093 } else if (x1 == FCS_MODE_ENCRYPT) {
2094 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
2095 } else {
2096 status = INTEL_SIP_SMC_STATUS_REJECTED;
2097 }
2098
2099 SMC_RET3(handle, status, x4, x5);
2100
2101 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
2102 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2103 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2104 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2105
2106 if (x3 == FCS_MODE_DECRYPT) {
2107 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
2108 (uint32_t *) &x7, &mbox_error, 0, 0, 0);
2109 } else if (x3 == FCS_MODE_ENCRYPT) {
2110 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
2111 (uint32_t *) &x7, &mbox_error, 0, 0);
2112 } else {
2113 status = INTEL_SIP_SMC_STATUS_REJECTED;
2114 }
2115
2116 SMC_RET4(handle, status, mbox_error, x6, x7);
2117
2118 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
2119 status = intel_fcs_random_number_gen(x1, &retval64,
2120 &mbox_error);
2121 SMC_RET4(handle, status, mbox_error, x1, retval64);
2122
2123 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
2124 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
2125 &send_id);
2126 SMC_RET1(handle, status);
2127
2128 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
2129 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id);
2130 SMC_RET1(handle, status);
2131
2132 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
2133 status = intel_fcs_get_provision_data(&send_id);
2134 SMC_RET1(handle, status);
2135
2136 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
2137 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3,
2138 &mbox_error);
2139 SMC_RET2(handle, status, mbox_error);
2140
2141 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
2142 status = intel_hps_set_bridges(x1, x2);
2143 SMC_RET1(handle, status);
2144
2145 case INTEL_SIP_SMC_HWMON_READTEMP:
2146 status = intel_hwmon_readtemp(x1, &retval);
2147 SMC_RET2(handle, status, retval);
2148
2149 case INTEL_SIP_SMC_HWMON_READVOLT:
2150 status = intel_hwmon_readvolt(x1, &retval);
2151 SMC_RET2(handle, status, retval);
2152
2153 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
2154 status = intel_fcs_sigma_teardown(x1, &mbox_error);
2155 SMC_RET2(handle, status, mbox_error);
2156
2157 case INTEL_SIP_SMC_FCS_CHIP_ID:
2158 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
2159 SMC_RET4(handle, status, mbox_error, retval, retval2);
2160
2161 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
2162 status = intel_fcs_attestation_subkey(x1, x2, x3,
2163 (uint32_t *) &x4, &mbox_error);
2164 SMC_RET4(handle, status, mbox_error, x3, x4);
2165
2166 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
2167 status = intel_fcs_get_measurement(x1, x2, x3,
2168 (uint32_t *) &x4, &mbox_error);
2169 SMC_RET4(handle, status, mbox_error, x3, x4);
2170
2171 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
2172 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2,
2173 (uint32_t *) &x3, &mbox_error);
2174 SMC_RET4(handle, status, mbox_error, x2, x3);
2175
2176 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
2177 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error);
2178 SMC_RET2(handle, status, mbox_error);
2179
2180 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
2181 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
2182 SMC_RET3(handle, status, mbox_error, retval);
2183
2184 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
2185 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
2186 SMC_RET2(handle, status, mbox_error);
2187
2188 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
2189 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
2190 SMC_RET1(handle, status);
2191
2192 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
2193 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
2194 (uint32_t *) &x4, &mbox_error);
2195 SMC_RET4(handle, status, mbox_error, x3, x4);
2196
2197 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
2198 status = intel_fcs_remove_crypto_service_key(x1, x2,
2199 &mbox_error);
2200 SMC_RET2(handle, status, mbox_error);
2201
2202 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
2203 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
2204 (uint32_t *) &x4, &mbox_error);
2205 SMC_RET4(handle, status, mbox_error, x3, x4);
2206
2207 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
2208 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2209 status = intel_fcs_get_digest_init(x1, x2, x3,
2210 x4, x5, &mbox_error);
2211 SMC_RET2(handle, status, mbox_error);
2212
2213 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
2214 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2215 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2216 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
2217 x3, x4, x5, (uint32_t *) &x6, false,
2218 &mbox_error, 0);
2219 SMC_RET4(handle, status, mbox_error, x5, x6);
2220
2221 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
2222 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2223 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2224 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
2225 x3, x4, x5, (uint32_t *) &x6, true,
2226 &mbox_error, 0);
2227 SMC_RET4(handle, status, mbox_error, x5, x6);
2228
2229 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
2230 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2231 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2232 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2233 x4, x5, (uint32_t *) &x6, false,
2234 &mbox_error, &send_id);
2235 SMC_RET4(handle, status, mbox_error, x5, x6);
2236
2237 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
2238 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2239 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2240 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2241 x4, x5, (uint32_t *) &x6, true,
2242 &mbox_error, &send_id);
2243 SMC_RET4(handle, status, mbox_error, x5, x6);
2244
2245 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
2246 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2247 status = intel_fcs_mac_verify_init(x1, x2, x3,
2248 x4, x5, &mbox_error);
2249 SMC_RET2(handle, status, mbox_error);
2250
2251 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
2252 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2253 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2254 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2255 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
2256 x3, x4, x5, (uint32_t *) &x6, x7, false,
2257 &mbox_error, 0);
2258 SMC_RET4(handle, status, mbox_error, x5, x6);
2259
2260 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
2261 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2262 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2263 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2264 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
2265 x3, x4, x5, (uint32_t *) &x6, x7, true,
2266 &mbox_error, 0);
2267 SMC_RET4(handle, status, mbox_error, x5, x6);
2268
2269 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
2270 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2271 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2272 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2273 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2274 x4, x5, (uint32_t *) &x6, x7,
2275 false, &mbox_error, &send_id);
2276 SMC_RET4(handle, status, mbox_error, x5, x6);
2277
2278 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
2279 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2280 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2281 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2282 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2283 x4, x5, (uint32_t *) &x6, x7,
2284 true, &mbox_error, &send_id);
2285 SMC_RET4(handle, status, mbox_error, x5, x6);
2286
2287 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
2288 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2289 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
2290 x4, x5, &mbox_error);
2291 SMC_RET2(handle, status, mbox_error);
2292
2293 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
2294 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2295 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2296 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
2297 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
2298 false, &mbox_error, 0);
2299 SMC_RET4(handle, status, mbox_error, x5, x6);
2300
2301 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
2302 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2303 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2304 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
2305 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
2306 true, &mbox_error, 0);
2307 SMC_RET4(handle, status, mbox_error, x5, x6);
2308
2309 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
2310 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2311 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2312 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
2313 x2, x3, x4, x5, (uint32_t *) &x6, false,
2314 &mbox_error, &send_id);
2315 SMC_RET4(handle, status, mbox_error, x5, x6);
2316
2317 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
2318 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2319 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2320 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
2321 x2, x3, x4, x5, (uint32_t *) &x6, true,
2322 &mbox_error, &send_id);
2323 SMC_RET4(handle, status, mbox_error, x5, x6);
2324
2325 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
2326 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2327 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
2328 x4, x5, &mbox_error);
2329 SMC_RET2(handle, status, mbox_error);
2330
2331 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
2332 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2333 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2334 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2,
2335 x3, x4, x5, (uint32_t *) &x6,
2336 &mbox_error);
2337 SMC_RET4(handle, status, mbox_error, x5, x6);
2338
2339 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
2340 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2341 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
2342 x4, x5, &mbox_error);
2343 SMC_RET2(handle, status, mbox_error);
2344
2345 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
2346 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2347 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2348 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1,
2349 x2, x3, x4, x5, (uint32_t *) &x6,
2350 &mbox_error);
2351 SMC_RET4(handle, status, mbox_error, x5, x6);
2352
2353 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
2354 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2355 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
2356 x4, x5, &mbox_error);
2357 SMC_RET2(handle, status, mbox_error);
2358
2359 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
2360 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2361 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2362 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2363 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
2364 smc_fid, 0, x1, x2, x3, x4, x5,
2365 (uint32_t *) &x6, x7, false,
2366 &mbox_error, 0);
2367 SMC_RET4(handle, status, mbox_error, x5, x6);
2368
2369 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
2370 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2371 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2372 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2373 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
2374 x1, x2, x3, x4, x5, (uint32_t *) &x6,
2375 x7, false, &mbox_error, &send_id);
2376 SMC_RET4(handle, status, mbox_error, x5, x6);
2377
2378 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
2379 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2380 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2381 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2382 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
2383 x1, x2, x3, x4, x5, (uint32_t *) &x6,
2384 x7, true, &mbox_error, &send_id);
2385 SMC_RET4(handle, status, mbox_error, x5, x6);
2386
2387 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
2388 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2389 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2390 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
2391 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
2392 smc_fid, 0, x1, x2, x3, x4, x5,
2393 (uint32_t *) &x6, x7, true,
2394 &mbox_error, 0);
2395 SMC_RET4(handle, status, mbox_error, x5, x6);
2396
2397 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
2398 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2399 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
2400 x4, x5, &mbox_error);
2401 SMC_RET2(handle, status, mbox_error);
2402
2403 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
2404 status = intel_fcs_ecdsa_get_pubkey_finalize(
2405 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0,
2406 x1, x2, x3, (uint32_t *) &x4, &mbox_error);
2407 SMC_RET4(handle, status, mbox_error, x3, x4);
2408
2409 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
2410 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2411 status = intel_fcs_ecdh_request_init(x1, x2, x3,
2412 x4, x5, &mbox_error);
2413 SMC_RET2(handle, status, mbox_error);
2414
2415 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
2416 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2417 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2418 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3,
2419 x4, x5, (uint32_t *) &x6, &mbox_error);
2420 SMC_RET4(handle, status, mbox_error, x5, x6);
2421
2422 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
2423 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2424 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
2425 &mbox_error);
2426 SMC_RET2(handle, status, mbox_error);
2427
2428 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
2429 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2430 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2431 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
2432 x3, x4, x5, x6, 0, false, &send_id, 0, 0);
2433 SMC_RET1(handle, status);
2434
2435 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
2436 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2437 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
2438 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
2439 x3, x4, x5, x6, 0, true, &send_id, 0, 0);
2440 SMC_RET1(handle, status);
2441
2442 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
2443 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG:
2444 status = intel_smmu_hps_remapper_config(x1);
2445 SMC_RET1(handle, status);
2446 #endif
2447
2448 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
2449 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
2450 &mbox_error);
2451 SMC_RET4(handle, status, mbox_error, x1, retval64);
2452
2453 case INTEL_SIP_SMC_SVC_VERSION:
2454 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
2455 SIP_SVC_VERSION_MAJOR,
2456 SIP_SVC_VERSION_MINOR);
2457
2458 case INTEL_SIP_SMC_SEU_ERR_STATUS:
2459 status = intel_sdm_seu_err_read(seu_respbuf,
2460 ARRAY_SIZE(seu_respbuf));
2461 if (status) {
2462 SMC_RET1(handle, status);
2463 } else {
2464 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
2465 }
2466
2467 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
2468 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
2469 SMC_RET1(handle, status);
2470
2471 case INTEL_SIP_SMC_ATF_BUILD_VER:
2472 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
2473 VERSION_MINOR, VERSION_PATCH);
2474
2475 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
2476 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
2477 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
2478 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
2479 #endif
2480
2481 default:
2482 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
2483 cookie, handle, flags);
2484 }
2485 }
2486
2487 uintptr_t sip_smc_handler(uint32_t smc_fid,
2488 u_register_t x1,
2489 u_register_t x2,
2490 u_register_t x3,
2491 u_register_t x4,
2492 void *cookie,
2493 void *handle,
2494 u_register_t flags)
2495 {
2496 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
2497
2498 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
2499 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
2500 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
2501 cookie, handle, flags);
2502 }
2503 #if SIP_SVC_V3
2504 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) &&
2505 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) {
2506 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4,
2507 cookie, handle, flags);
2508 return ret;
2509 }
2510 #endif
2511 else {
2512 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
2513 cookie, handle, flags);
2514 }
2515 }
2516
2517 DECLARE_RT_SVC(
2518 socfpga_sip_svc,
2519 OEN_SIP_START,
2520 OEN_SIP_END,
2521 SMC_TYPE_FAST,
2522 NULL,
2523 sip_smc_handler
2524 );
2525
2526 DECLARE_RT_SVC(
2527 socfpga_sip_svc_std,
2528 OEN_SIP_START,
2529 OEN_SIP_END,
2530 SMC_TYPE_YIELD,
2531 NULL,
2532 sip_smc_handler
2533 );
2534