1 /*
2 * Copyright (c) 2016-2026, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <bl32/sp_min/platform_sp_min.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/console.h>
15 #include <lib/mmio.h>
16 #include <plat/arm/common/plat_arm.h>
17 #include <plat/common/platform.h>
18
19 struct transfer_list_header *secure_tl;
20 struct transfer_list_header *ns_tl __unused;
21
22 static entry_point_info_t bl33_image_ep_info;
23
24 /* Weak definitions may be overridden in specific ARM standard platform */
25 #pragma weak sp_min_platform_setup
26 #pragma weak sp_min_plat_arch_setup
27 #pragma weak plat_arm_sp_min_early_platform_setup
28
29 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \
30 BL32_BASE, \
31 BL32_END - BL32_BASE, \
32 MT_MEMORY | MT_RW | MT_SECURE)
33
34 #define MAP_EL3_FW_HANDOFF \
35 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
36 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
37
38 #define MAP_FW_NS_HANDOFF \
39 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
40 MT_MEMORY | MT_RW | MT_NS)
41
42 /*
43 * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
44 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
45 */
46 #if !RESET_TO_SP_MIN
47 #if TRANSFER_LIST
48 CASSERT(BL32_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl32_base_overflows);
49 #else
50 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
51 #endif
52 #endif
53
54 /*******************************************************************************
55 * Return a pointer to the 'entry_point_info' structure of the next image for the
56 * security state specified. BL33 corresponds to the non-secure image type
57 * while BL32 corresponds to the secure image type. A NULL pointer is returned
58 * if the image does not exist.
59 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)60 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
61 {
62 entry_point_info_t *next_image_info;
63
64 next_image_info = &bl33_image_ep_info;
65
66 /*
67 * None of the images on the ARM development platforms can have 0x0
68 * as the entrypoint
69 */
70 if (next_image_info->pc)
71 return next_image_info;
72 else
73 return NULL;
74 }
75
76 /*******************************************************************************
77 * Utility function to perform early platform setup.
78 ******************************************************************************/
arm_sp_min_early_platform_setup(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)79 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
80 u_register_t arg2, u_register_t arg3)
81 {
82 struct transfer_list_entry *te __unused;
83
84 /* Initialize the console to provide early debug support */
85 arm_console_boot_init();
86
87 #if TRANSFER_LIST
88 secure_tl = (struct transfer_list_header *)arg3;
89
90 te = transfer_list_find(secure_tl, TL_TAG_EXEC_EP_INFO32);
91 assert(te != NULL);
92
93 bl33_image_ep_info =
94 *(struct entry_point_info *)transfer_list_entry_data(te);
95 return;
96 #endif /* TRANSFER_LIST */
97
98 #if RESET_TO_SP_MIN
99 /* Populate entry point information for BL33 */
100 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
101 /*
102 * Tell SP_MIN where the non-trusted software image
103 * is located and the entry state information
104 */
105 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
106 bl33_image_ep_info.spsr = arm_get_spsr(BL33_IMAGE_ID);
107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
108
109 #if ARM_LINUX_KERNEL_AS_BL33
110 /*
111 * According to the file ``Documentation/arm/Booting`` of the Linux
112 * kernel tree, Linux expects:
113 * r0 = 0
114 * r1 = machine type number, optional in DT-only platforms (~0 if so)
115 * r2 = Physical address of the device tree blob
116 */
117 bl33_image_ep_info.args.arg0 = 0U;
118 bl33_image_ep_info.args.arg1 = ~0U;
119 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE;
120 # endif
121
122 #else /* RESET_TO_SP_MIN */
123
124 /*
125 * Check params passed from BL2 should not be NULL,
126 */
127 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
128 assert(params_from_bl2 != NULL);
129 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
130 assert(params_from_bl2->h.version >= VERSION_2);
131
132 bl_params_node_t *bl_params = params_from_bl2->head;
133
134 /*
135 * Copy BL33 entry point information.
136 * They are stored in Secure RAM, in BL2's address space.
137 */
138 while (bl_params) {
139 if (bl_params->image_id == BL33_IMAGE_ID) {
140 bl33_image_ep_info = *bl_params->ep_info;
141 break;
142 }
143
144 bl_params = bl_params->next_params_info;
145 }
146
147 if (bl33_image_ep_info.pc == 0)
148 panic();
149
150 #endif /* RESET_TO_SP_MIN */
151
152 }
153
154 /*******************************************************************************
155 * Default implementation for sp_min_platform_setup2() for ARM platforms
156 ******************************************************************************/
plat_arm_sp_min_early_platform_setup(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)157 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
158 u_register_t arg2, u_register_t arg3)
159 {
160 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
161
162 #if !HW_ASSISTED_COHERENCY
163 /*
164 * Initialize Interconnect for this cluster during cold boot.
165 * No need for locks as no other CPU is active.
166 */
167 plat_arm_interconnect_init();
168
169 /*
170 * Enable Interconnect coherency for the primary CPU's cluster.
171 * Earlier bootloader stages might already do this (e.g. Trusted
172 * Firmware's BL1 does it) but we can't assume so. There is no harm in
173 * executing this code twice anyway.
174 * Platform specific PSCI code will enable coherency for other
175 * clusters.
176 */
177 plat_arm_interconnect_enter_coherency();
178 #endif
179 }
180
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)181 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
182 u_register_t arg2, u_register_t arg3)
183 {
184 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
185 }
186
187 /*******************************************************************************
188 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit.
189 * Common to ARM standard platforms.
190 ******************************************************************************/
arm_sp_min_plat_runtime_setup(void)191 void arm_sp_min_plat_runtime_setup(void)
192 {
193 /* Initialize the runtime console */
194 arm_console_runtime_init();
195
196 #if PLAT_RO_XLAT_TABLES
197 arm_xlat_make_tables_readonly();
198 #endif
199 }
200
201 /*******************************************************************************
202 * Perform platform specific setup for SP_MIN
203 ******************************************************************************/
sp_min_platform_setup(void)204 void sp_min_platform_setup(void)
205 {
206 struct transfer_list_entry *te __unused;
207
208 /* Initialize the GIC driver, cpu and distributor interfaces */
209 unsigned int core_pos = plat_my_core_pos();
210
211 #if USE_GIC_DRIVER == 3
212 gic_set_gicr_frames(arm_gicr_base_addrs);
213 #endif
214 gic_init(core_pos);
215 gic_pcpu_init(core_pos);
216 gic_cpuif_enable(core_pos);
217
218 #if TRANSFER_LIST
219 ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,
220 PLAT_ARM_FW_HANDOFF_SIZE);
221 if (ns_tl == NULL) {
222 ERROR("Non-secure transfer list initialisation failed!\n");
223 panic();
224 }
225
226 te = transfer_list_find(secure_tl, TL_TAG_FDT);
227 if (te != NULL) {
228 te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
229 (void *)transfer_list_entry_data(te));
230 if (te == NULL) {
231 ERROR("Failed to relocate device tree into non-secure memory.\n");
232 panic();
233 }
234 }
235
236 transfer_list_set_handoff_args(ns_tl, &bl33_image_ep_info);
237 #endif
238
239 /*
240 * Do initial security configuration to allow DRAM/device access
241 * (if earlier BL has not already done so).
242 */
243 #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
244 plat_arm_security_setup();
245
246 #if defined(PLAT_ARM_MEM_PROT_ADDR)
247 arm_nor_psci_do_dyn_mem_protect();
248 #endif /* PLAT_ARM_MEM_PROT_ADDR */
249
250 #endif
251
252 /* Enable and initialize the System level generic timer */
253 #ifdef ARM_SYS_CNTCTL_BASE
254 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
255 CNTCR_FCREQ(0U) | CNTCR_EN);
256 #endif
257 #ifdef ARM_SYS_TIMCTL_BASE
258 /* Allow access to the System counter timer module */
259 arm_configure_sys_timer();
260 #endif
261 /* Initialize power controller before setting up topology */
262 plat_arm_pwrc_setup();
263 }
264
sp_min_plat_runtime_setup(void)265 void sp_min_plat_runtime_setup(void)
266 {
267 arm_sp_min_plat_runtime_setup();
268 }
269
270 /*******************************************************************************
271 * Perform the very early platform specific architectural setup here. At the
272 * moment this only initializes the MMU
273 ******************************************************************************/
arm_sp_min_plat_arch_setup(void)274 void arm_sp_min_plat_arch_setup(void)
275 {
276 const mmap_region_t bl_regions[] = {
277 MAP_BL_SP_MIN_TOTAL,
278 ARM_MAP_BL_RO,
279 #if USE_COHERENT_MEM
280 ARM_MAP_BL_COHERENT_RAM,
281 #endif
282 #if TRANSFER_LIST
283 MAP_EL3_FW_HANDOFF,
284 MAP_FW_NS_HANDOFF,
285 #endif
286 {0}
287 };
288
289 setup_page_tables(bl_regions, plat_arm_get_mmap());
290
291 enable_mmu_svc_mon(0);
292 }
293
sp_min_plat_arch_setup(void)294 void sp_min_plat_arch_setup(void)
295 {
296 arm_sp_min_plat_arch_setup();
297 }
298