1 #ifndef __ODY_CSRS_ECAM_H__
2 #define __ODY_CSRS_ECAM_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * ECAM.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration ecam_bar_e
24 *
25 * ECAM Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_ECAM_BAR_E_ECAMX_PF_BAR0(a) (0x87e078000000ll + 0x1000000ll * (a))
29 #define ODY_ECAM_BAR_E_ECAMX_PF_BAR0_SIZE 0x100000ull
30 #define ODY_ECAM_BAR_E_ECAMX_PF_BAR2(a) (0x878000000000ll + 0x1000000000ll * (a))
31 #define ODY_ECAM_BAR_E_ECAMX_PF_BAR2_SIZE 0x1000000000ull
32
33 /**
34 * Structure ecam_cfg_addr_s
35 *
36 * ECAM Configuration Address Structure
37 * ECAM load and store operations form an address with this structure: 8-bit, 16-bit, 32-bit and
38 * 64-bit read and write operations are supported to this region.
39 */
40 union ody_ecam_cfg_addr_s {
41 uint64_t u;
42 struct ody_ecam_cfg_addr_s_s {
43 uint64_t addr : 12;
44 uint64_t func : 8;
45 uint64_t bus : 8;
46 uint64_t dmn : 6;
47 uint64_t bcst : 1;
48 uint64_t setup : 1;
49 uint64_t did : 8;
50 uint64_t node : 2;
51 uint64_t reserved_46 : 1;
52 uint64_t io : 5;
53 uint64_t reserved_52_63 : 12;
54 } s;
55 /* struct ody_ecam_cfg_addr_s_s cn; */
56 };
57
58 /**
59 * Register (RSL) ecam#_const
60 *
61 * ECAM Constants Register
62 * This register contains constants for software discovery.
63 */
64 union ody_ecamx_const {
65 uint64_t u;
66 struct ody_ecamx_const_s {
67 uint64_t ecams : 8;
68 uint64_t domains : 8;
69 uint64_t reserved_16_63 : 48;
70 } s;
71 /* struct ody_ecamx_const_s cn; */
72 };
73 typedef union ody_ecamx_const ody_ecamx_const_t;
74
75 static inline uint64_t ODY_ECAMX_CONST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_ECAMX_CONST(uint64_t a)76 static inline uint64_t ODY_ECAMX_CONST(uint64_t a)
77 {
78 if (a == 0)
79 return 0x87e078000200ll;
80 __ody_csr_fatal("ECAMX_CONST", 1, a, 0, 0, 0, 0, 0);
81 }
82
83 #define typedef_ODY_ECAMX_CONST(a) ody_ecamx_const_t
84 #define bustype_ODY_ECAMX_CONST(a) CSR_TYPE_RSL
85 #define basename_ODY_ECAMX_CONST(a) "ECAMX_CONST"
86 #define device_bar_ODY_ECAMX_CONST(a) 0x0 /* PF_BAR0 */
87 #define busnum_ODY_ECAMX_CONST(a) (a)
88 #define arguments_ODY_ECAMX_CONST(a) (a), -1, -1, -1
89
90 /**
91 * Register (RSL) ecam#_dom#_bus#_permit
92 *
93 * ECAM Domain Bus Permit Registers
94 * This register sets the permissions for an ECAM access to a device
95 * using a given ECAM bus number.
96 *
97 * Index {a} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DMN]).
98 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
99 * implemented; nonimplemented indices are RAZ.
100 *
101 * Index {b} corresponds to the ECAM address's bus number (address's ECAM_CFG_ADDR_S[BUS]).
102 */
103 union ody_ecamx_domx_busx_permit {
104 uint64_t u;
105 struct ody_ecamx_domx_busx_permit_s {
106 uint64_t sec_dis : 1;
107 uint64_t nsec_dis : 1;
108 uint64_t xcp0_dis : 1;
109 uint64_t xcp1_dis : 1;
110 uint64_t xcp2_dis : 1;
111 uint64_t reserved_5_6 : 2;
112 uint64_t kill : 1;
113 uint64_t lock : 1;
114 uint64_t reserved_9_63 : 55;
115 } s;
116 /* struct ody_ecamx_domx_busx_permit_s cn; */
117 };
118 typedef union ody_ecamx_domx_busx_permit ody_ecamx_domx_busx_permit_t;
119
120 static inline uint64_t ODY_ECAMX_DOMX_BUSX_PERMIT(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_ECAMX_DOMX_BUSX_PERMIT(uint64_t a,uint64_t b,uint64_t c)121 static inline uint64_t ODY_ECAMX_DOMX_BUSX_PERMIT(uint64_t a, uint64_t b, uint64_t c)
122 {
123 if ((a == 0) && ((b == 0) || (b == 1) || (b == 2)) && (c <= 255))
124 return 0x87e078020000ll + 0x800ll * ((b) & 0x3) + 8ll * ((c) & 0xff);
125 __ody_csr_fatal("ECAMX_DOMX_BUSX_PERMIT", 3, a, b, c, 0, 0, 0);
126 }
127
128 #define typedef_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) ody_ecamx_domx_busx_permit_t
129 #define bustype_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) CSR_TYPE_RSL
130 #define basename_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) "ECAMX_DOMX_BUSX_PERMIT"
131 #define device_bar_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) 0x0 /* PF_BAR0 */
132 #define busnum_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) (a)
133 #define arguments_ODY_ECAMX_DOMX_BUSX_PERMIT(a, b, c) (a), (b), (c), -1
134
135 /**
136 * Register (RSL) ecam#_dom#_const
137 *
138 * ECAM Constants Register
139 * This register contains constants for software discovery.
140 *
141 * Index {a} indicates the domain for which the attributes are to be returned.
142 */
143 union ody_ecamx_domx_const {
144 uint64_t u;
145 struct ody_ecamx_domx_const_s {
146 uint64_t smmu : 4;
147 uint64_t permit : 1;
148 uint64_t pres : 1;
149 uint64_t reserved_6_63 : 58;
150 } s;
151 /* struct ody_ecamx_domx_const_s cn; */
152 };
153 typedef union ody_ecamx_domx_const ody_ecamx_domx_const_t;
154
155 static inline uint64_t ODY_ECAMX_DOMX_CONST(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_ECAMX_DOMX_CONST(uint64_t a,uint64_t b)156 static inline uint64_t ODY_ECAMX_DOMX_CONST(uint64_t a, uint64_t b)
157 {
158 if ((a == 0) && (b <= 63))
159 return 0x87e078000400ll + 8ll * ((b) & 0x3f);
160 __ody_csr_fatal("ECAMX_DOMX_CONST", 2, a, b, 0, 0, 0, 0);
161 }
162
163 #define typedef_ODY_ECAMX_DOMX_CONST(a, b) ody_ecamx_domx_const_t
164 #define bustype_ODY_ECAMX_DOMX_CONST(a, b) CSR_TYPE_RSL
165 #define basename_ODY_ECAMX_DOMX_CONST(a, b) "ECAMX_DOMX_CONST"
166 #define device_bar_ODY_ECAMX_DOMX_CONST(a, b) 0x0 /* PF_BAR0 */
167 #define busnum_ODY_ECAMX_DOMX_CONST(a, b) (a)
168 #define arguments_ODY_ECAMX_DOMX_CONST(a, b) (a), (b), -1, -1
169
170 /**
171 * Register (RSL) ecam#_dom#_dev#_permit
172 *
173 * ECAM Domain Device Permit Registers
174 * This register sets the permissions for a ECAM access to a bus 0 device.
175 * This register is used when the bus number is 0; i.e. address's ECAM_CFG_ADDR_S[BUS] = 0x0.
176 *
177 * Index {a} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DOMAIN]).
178 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
179 * implemented; nonimplemented indices are RAZ.
180 *
181 * Index {b} corresponds to the bus 0 non-ARI device number (address's
182 * ECAM_CFG_ADDR_S[FUNC]\<7:3\>).
183 *
184 * Also see and program identically to IOBN()_ECAM_DOM()_DEV()_PERMIT.
185 */
186 union ody_ecamx_domx_devx_permit {
187 uint64_t u;
188 struct ody_ecamx_domx_devx_permit_s {
189 uint64_t sec_dis : 1;
190 uint64_t nsec_dis : 1;
191 uint64_t xcp0_dis : 1;
192 uint64_t xcp1_dis : 1;
193 uint64_t xcp2_dis : 1;
194 uint64_t reserved_5_6 : 2;
195 uint64_t kill : 1;
196 uint64_t lock : 1;
197 uint64_t reserved_9_63 : 55;
198 } s;
199 /* struct ody_ecamx_domx_devx_permit_s cn; */
200 };
201 typedef union ody_ecamx_domx_devx_permit ody_ecamx_domx_devx_permit_t;
202
203 static inline uint64_t ODY_ECAMX_DOMX_DEVX_PERMIT(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_ECAMX_DOMX_DEVX_PERMIT(uint64_t a,uint64_t b,uint64_t c)204 static inline uint64_t ODY_ECAMX_DOMX_DEVX_PERMIT(uint64_t a, uint64_t b, uint64_t c)
205 {
206 if ((a == 0) && (b <= 18) && (c <= 31))
207 return 0x87e078040000ll + 0x800ll * ((b) & 0x1f) + 8ll * ((c) & 0x1f);
208 __ody_csr_fatal("ECAMX_DOMX_DEVX_PERMIT", 3, a, b, c, 0, 0, 0);
209 }
210
211 #define typedef_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) ody_ecamx_domx_devx_permit_t
212 #define bustype_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) CSR_TYPE_RSL
213 #define basename_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) "ECAMX_DOMX_DEVX_PERMIT"
214 #define device_bar_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) 0x0 /* PF_BAR0 */
215 #define busnum_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) (a)
216 #define arguments_ODY_ECAMX_DOMX_DEVX_PERMIT(a, b, c) (a), (b), (c), -1
217
218 /**
219 * Register (RSL) ecam#_dom#_rsl#_permit
220 *
221 * ECAM Domain RSL Permit Registers
222 * This register sets the permissions for an ECAM access to an RSL device.
223 * This register is used when the domain and bus point to RSL; i.e.
224 * address's ECAM_CFG_ADDR_S[DOMAIN]=PCC_DEV_CON_E::MRML\<21:16\>,
225 * ECAM_CFG_ADDR_S[BUS] = PCC_DEV_CON_E::MRML\<15:8\>.
226 *
227 * Index {a} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DOMAIN]).
228 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
229 * implemented; nonimplemented indices are RAZ.
230 *
231 * Index {b} bits 9:8 are 0x0 when the RSL device's PCC_DEV_CON_E\<9:8\> value is 0x1
232 * (MRML0).
233 *
234 * Index {b} bits 9:8 are 0x1 when the RSL device's PCC_DEV_CON_E\<9:8\> value is 0x2
235 * (MRML1).
236 *
237 * Index {b} bits 9:8 are 0x2 when the RSL device's PCC_DEV_CON_E\<9:8\> value is 0x3
238 * (MRML2).
239 *
240 * Index {b} bits 9:8 are 0x3 when the RSL device's PCC_DEV_CON_E\<9:8\> value is 0x0
241 * (MRML3).
242 *
243 * Index {b} bits 7:0 corresponds to the RSL device's PCC_DEV_CON_E\<7:0\> value.
244 */
245 union ody_ecamx_domx_rslx_permit {
246 uint64_t u;
247 struct ody_ecamx_domx_rslx_permit_s {
248 uint64_t sec_dis : 1;
249 uint64_t nsec_dis : 1;
250 uint64_t xcp0_dis : 1;
251 uint64_t xcp1_dis : 1;
252 uint64_t xcp2_dis : 1;
253 uint64_t reserved_5_6 : 2;
254 uint64_t kill : 1;
255 uint64_t lock : 1;
256 uint64_t reserved_9_63 : 55;
257 } s;
258 /* struct ody_ecamx_domx_rslx_permit_s cn; */
259 };
260 typedef union ody_ecamx_domx_rslx_permit ody_ecamx_domx_rslx_permit_t;
261
262 static inline uint64_t ODY_ECAMX_DOMX_RSLX_PERMIT(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_ECAMX_DOMX_RSLX_PERMIT(uint64_t a,uint64_t b,uint64_t c)263 static inline uint64_t ODY_ECAMX_DOMX_RSLX_PERMIT(uint64_t a, uint64_t b, uint64_t c)
264 {
265 if ((a == 0) && ((b == 0) || (b == 1) || (b == 2)) && (c <= 1023))
266 return 0x87e078060000ll + 0x2000ll * ((b) & 0x3) + 8ll * ((c) & 0x3ff);
267 __ody_csr_fatal("ECAMX_DOMX_RSLX_PERMIT", 3, a, b, c, 0, 0, 0);
268 }
269
270 #define typedef_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) ody_ecamx_domx_rslx_permit_t
271 #define bustype_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) CSR_TYPE_RSL
272 #define basename_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) "ECAMX_DOMX_RSLX_PERMIT"
273 #define device_bar_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) 0x0 /* PF_BAR0 */
274 #define busnum_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) (a)
275 #define arguments_ODY_ECAMX_DOMX_RSLX_PERMIT(a, b, c) (a), (b), (c), -1
276
277 #endif /* __ODY_CSRS_ECAM_H__ */
278