1 /*
2 * Analogix DP (Display port) core register interface driver.
3 *
4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <config.h>
15 #include <common.h>
16 #include <errno.h>
17 #include <malloc.h>
18 #include <asm/unaligned.h>
19 #include <linux/list.h>
20 #include <dm/device.h>
21 #include <syscon.h>
22 #include <asm/io.h>
23 #include <asm/gpio.h>
24 #include <linux/iopoll.h>
25
26 #include "rockchip_display.h"
27 #include "rockchip_crtc.h"
28 #include "rockchip_connector.h"
29 #include "analogix_dp.h"
30
31 #define COMMON_INT_MASK_1 0
32 #define COMMON_INT_MASK_2 0
33 #define COMMON_INT_MASK_3 0
34 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
35 #define INT_STA_MASK INT_HPD
36
analogix_dp_write(struct analogix_dp_device * dp,u32 reg,u32 val)37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val)
38 {
39 readl(dp->reg_base);
40 writel(val, dp->reg_base + reg);
41 writel(val, dp->reg_base + reg);
42 }
43
analogix_dp_read(struct analogix_dp_device * dp,u32 reg)44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg)
45 {
46 readl(dp->reg_base + reg);
47
48 return readl(dp->reg_base + reg);
49 }
50
analogix_dp_enable_video_mute(struct analogix_dp_device * dp,bool enable)51 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
52 {
53 u32 reg;
54
55 if (enable) {
56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
57 reg |= HDCP_VIDEO_MUTE;
58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
59 } else {
60 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
61 reg &= ~HDCP_VIDEO_MUTE;
62 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
63 }
64 }
65
analogix_dp_stop_video(struct analogix_dp_device * dp)66 void analogix_dp_stop_video(struct analogix_dp_device *dp)
67 {
68 u32 reg;
69
70 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
71 reg &= ~VIDEO_EN;
72 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
73 }
74
analogix_dp_set_lane_map(struct analogix_dp_device * dp)75 static void analogix_dp_set_lane_map(struct analogix_dp_device *dp)
76 {
77 u32 i, reg = 0;
78
79 for (i = 0; i < dp->video_info.max_lane_count; i++)
80 reg |= dp->lane_map[i] << (2 * i);
81
82 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg);
83 }
84
analogix_dp_init_analog_param(struct analogix_dp_device * dp)85 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
86 {
87 u32 reg;
88
89 reg = TX_TERMINAL_CTRL_50_OHM;
90 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg);
91
92 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
93 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg);
94
95 if (dp->plat_data.dev_type == ROCKCHIP_DP) {
96 reg = REF_CLK_24M;
97 if (dp->plat_data.subdev_type == RK3288_DP ||
98 dp->plat_data.subdev_type == RK3368_EDP)
99 reg ^= REF_CLK_MASK;
100
101 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg);
102 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99);
103 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40);
104 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58);
105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22);
106 analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44);
107 }
108
109 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
110 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg);
111
112 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
113 TX_CUR1_2X | TX_CUR_16_MA;
114 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg);
115
116 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
117 CH1_AMP_400_MV | CH0_AMP_400_MV;
118 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg);
119 }
120
analogix_dp_init_interrupt(struct analogix_dp_device * dp)121 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
122 {
123 /* Set interrupt pin assertion polarity as high */
124 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0);
125
126 /* Clear pending regisers */
127 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff);
128 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f);
129 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0);
130 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7);
131 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63);
132
133 /* 0:mask,1: unmask */
134 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00);
135 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00);
136 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00);
137 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00);
138 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00);
139 }
140
analogix_dp_reset(struct analogix_dp_device * dp)141 void analogix_dp_reset(struct analogix_dp_device *dp)
142 {
143 u32 reg;
144
145 analogix_dp_stop_video(dp);
146 analogix_dp_enable_video_mute(dp, 0);
147
148 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
149 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
150 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
151 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
152
153 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
154 SERDES_FIFO_FUNC_EN_N |
155 LS_CLK_DOMAIN_FUNC_EN_N;
156 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
157
158 udelay(30);
159
160 analogix_dp_set_lane_map(dp);
161
162 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0);
163 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40);
164 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0);
165 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0);
166
167 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0);
168 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0);
169
170 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e);
171 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a);
172
173 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10);
174
175 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0);
176
177 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0);
178 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20);
179
180 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4);
181 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2);
182
183 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101);
184 }
185
analogix_dp_swreset(struct analogix_dp_device * dp)186 void analogix_dp_swreset(struct analogix_dp_device *dp)
187 {
188 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX);
189 }
190
analogix_dp_config_interrupt(struct analogix_dp_device * dp)191 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
192 {
193 u32 reg;
194
195 /* 0: mask, 1: unmask */
196 reg = COMMON_INT_MASK_1;
197 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg);
198
199 reg = COMMON_INT_MASK_2;
200 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg);
201
202 reg = COMMON_INT_MASK_3;
203 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg);
204
205 reg = COMMON_INT_MASK_4;
206 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
207
208 reg = INT_STA_MASK;
209 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg);
210 }
211
analogix_dp_mute_hpd_interrupt(struct analogix_dp_device * dp)212 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
213 {
214 u32 reg;
215
216 /* 0: mask, 1: unmask */
217 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4);
218 reg &= ~COMMON_INT_MASK_4;
219 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
220
221 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK);
222 reg &= ~INT_STA_MASK;
223 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg);
224 }
225
analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device * dp)226 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
227 {
228 u32 reg;
229
230 /* 0: mask, 1: unmask */
231 reg = COMMON_INT_MASK_4;
232 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
233
234 reg = INT_STA_MASK;
235 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg);
236 }
237
analogix_dp_get_pll_lock_status(struct analogix_dp_device * dp)238 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
239 {
240 u32 reg;
241
242 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL);
243 if (reg & PLL_LOCK)
244 return PLL_LOCKED;
245 else
246 return PLL_UNLOCKED;
247 }
248
analogix_dp_set_pll_power_down(struct analogix_dp_device * dp,bool enable)249 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
250 {
251 u32 reg;
252
253 if (enable) {
254 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL);
255 reg |= DP_PLL_PD;
256 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg);
257 } else {
258 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL);
259 reg &= ~DP_PLL_PD;
260 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg);
261 }
262 }
263
analogix_dp_set_analog_power_down(struct analogix_dp_device * dp,enum analog_power_block block,bool enable)264 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
265 enum analog_power_block block,
266 bool enable)
267 {
268 u32 reg;
269 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
270
271 if (dp->plat_data.dev_type == ROCKCHIP_DP)
272 phy_pd_addr = ANALOGIX_DP_PD;
273
274 switch (block) {
275 case AUX_BLOCK:
276 if (enable) {
277 reg = analogix_dp_read(dp, phy_pd_addr);
278 reg |= AUX_PD;
279 analogix_dp_write(dp, phy_pd_addr, reg);
280 } else {
281 reg = analogix_dp_read(dp, phy_pd_addr);
282 reg &= ~AUX_PD;
283 analogix_dp_write(dp, phy_pd_addr, reg);
284 }
285 break;
286 case CH0_BLOCK:
287 if (enable) {
288 reg = analogix_dp_read(dp, phy_pd_addr);
289 reg |= CH0_PD;
290 analogix_dp_write(dp, phy_pd_addr, reg);
291 } else {
292 reg = analogix_dp_read(dp, phy_pd_addr);
293 reg &= ~CH0_PD;
294 analogix_dp_write(dp, phy_pd_addr, reg);
295 }
296 break;
297 case CH1_BLOCK:
298 if (enable) {
299 reg = analogix_dp_read(dp, phy_pd_addr);
300 reg |= CH1_PD;
301 analogix_dp_write(dp, phy_pd_addr, reg);
302 } else {
303 reg = analogix_dp_read(dp, phy_pd_addr);
304 reg &= ~CH1_PD;
305 analogix_dp_write(dp, phy_pd_addr, reg);
306 }
307 break;
308 case CH2_BLOCK:
309 if (enable) {
310 reg = analogix_dp_read(dp, phy_pd_addr);
311 reg |= CH2_PD;
312 analogix_dp_write(dp, phy_pd_addr, reg);
313 } else {
314 reg = analogix_dp_read(dp, phy_pd_addr);
315 reg &= ~CH2_PD;
316 analogix_dp_write(dp, phy_pd_addr, reg);
317 }
318 break;
319 case CH3_BLOCK:
320 if (enable) {
321 reg = analogix_dp_read(dp, phy_pd_addr);
322 reg |= CH3_PD;
323 analogix_dp_write(dp, phy_pd_addr, reg);
324 } else {
325 reg = analogix_dp_read(dp, phy_pd_addr);
326 reg &= ~CH3_PD;
327 analogix_dp_write(dp, phy_pd_addr, reg);
328 }
329 break;
330 case ANALOG_TOTAL:
331 if (enable) {
332 reg = analogix_dp_read(dp, phy_pd_addr);
333 reg |= DP_PHY_PD;
334 analogix_dp_write(dp, phy_pd_addr, reg);
335 } else {
336 reg = analogix_dp_read(dp, phy_pd_addr);
337 reg &= ~DP_PHY_PD;
338 analogix_dp_write(dp, phy_pd_addr, reg);
339 }
340 break;
341 case POWER_ALL:
342 if (enable) {
343 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
344 CH1_PD | CH0_PD;
345 analogix_dp_write(dp, phy_pd_addr, reg);
346 } else {
347 analogix_dp_write(dp, phy_pd_addr, 0x00);
348 }
349 break;
350 default:
351 break;
352 }
353 }
354
analogix_dp_init_analog_func(struct analogix_dp_device * dp)355 void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
356 {
357 u32 reg;
358
359 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
360
361 reg = PLL_LOCK_CHG;
362 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg);
363
364 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL);
365 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
366 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg);
367
368 /* Power up PLL */
369 analogix_dp_set_pll_power_down(dp, 0);
370
371 /* Enable Serdes FIFO function and Link symbol clock domain module */
372 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
373 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
374 | AUX_FUNC_EN_N);
375 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
376 }
377
analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device * dp)378 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
379 {
380 u32 reg;
381
382 if (dm_gpio_is_valid(&dp->hpd_gpio))
383 return;
384
385 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
386 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg);
387
388 reg = INT_HPD;
389 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg);
390 }
391
analogix_dp_init_hpd(struct analogix_dp_device * dp)392 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
393 {
394 u32 reg;
395
396 if (dm_gpio_is_valid(&dp->hpd_gpio))
397 return;
398
399 analogix_dp_clear_hotplug_interrupts(dp);
400
401 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
402 reg &= ~(F_HPD | HPD_CTRL);
403 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
404 }
405
analogix_dp_force_hpd(struct analogix_dp_device * dp)406 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
407 {
408 u32 reg;
409
410 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
411 reg |= (F_HPD | HPD_CTRL);
412 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
413 }
414
analogix_dp_get_irq_type(struct analogix_dp_device * dp)415 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
416 {
417 u32 reg;
418
419 if (dm_gpio_is_valid(&dp->hpd_gpio)) {
420 reg = dm_gpio_get_value(&dp->hpd_gpio);
421 if (reg)
422 return DP_IRQ_TYPE_HP_CABLE_IN;
423 else
424 return DP_IRQ_TYPE_HP_CABLE_OUT;
425 } else {
426 /* Parse hotplug interrupt status register */
427 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4);
428
429 if (reg & PLUG)
430 return DP_IRQ_TYPE_HP_CABLE_IN;
431
432 if (reg & HPD_LOST)
433 return DP_IRQ_TYPE_HP_CABLE_OUT;
434
435 if (reg & HOTPLUG_CHG)
436 return DP_IRQ_TYPE_HP_CHANGE;
437
438 return DP_IRQ_TYPE_UNKNOWN;
439 }
440 }
441
analogix_dp_reset_aux(struct analogix_dp_device * dp)442 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
443 {
444 u32 reg;
445
446 /* Disable AUX channel module */
447 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
448 reg |= AUX_FUNC_EN_N;
449 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
450 }
451
analogix_dp_init_aux(struct analogix_dp_device * dp)452 void analogix_dp_init_aux(struct analogix_dp_device *dp)
453 {
454 u32 reg;
455
456 /* Clear inerrupts related to AUX channel */
457 reg = RPLY_RECEIV | AUX_ERR;
458 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg);
459
460 analogix_dp_reset_aux(dp);
461
462 /* Disable AUX transaction H/W retry */
463 if (dp->plat_data.dev_type == ROCKCHIP_DP)
464 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
465 AUX_HW_RETRY_COUNT_SEL(3) |
466 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
467 else
468 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
469 AUX_HW_RETRY_COUNT_SEL(0) |
470 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
471 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg);
472
473 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
474 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
475 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg);
476
477 /* Enable AUX channel module */
478 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
479 reg &= ~AUX_FUNC_EN_N;
480 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
481 }
482
analogix_dp_detect(struct analogix_dp_device * dp)483 int analogix_dp_detect(struct analogix_dp_device *dp)
484 {
485 u32 reg;
486
487 if (dm_gpio_is_valid(&dp->hpd_gpio))
488 return dm_gpio_get_value(&dp->hpd_gpio);
489
490 if (dp->force_hpd)
491 analogix_dp_force_hpd(dp);
492
493 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
494 if (reg & HPD_STATUS)
495 return 1;
496
497 return 0;
498 }
499
analogix_dp_enable_sw_function(struct analogix_dp_device * dp)500 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
501 {
502 u32 reg;
503
504 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
505 reg &= ~SW_FUNC_EN_N;
506 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
507 }
508
analogix_dp_get_plug_in_status(struct analogix_dp_device * dp)509 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
510 {
511 u32 reg;
512
513 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
514 if (reg & HPD_STATUS)
515 return 0;
516
517 return -EINVAL;
518 }
519
analogix_dp_start_aux_transaction(struct analogix_dp_device * dp)520 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
521 {
522 int reg;
523 int retval = 0;
524 int timeout_loop = 0;
525
526 /* Enable AUX CH operation */
527 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2);
528 reg |= AUX_EN;
529 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg);
530
531 /* Is AUX CH command reply received? */
532 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
533 while (!(reg & RPLY_RECEIV)) {
534 timeout_loop++;
535 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
536 dev_err(dp->dev, "AUX CH command reply failed!\n");
537 return -ETIMEDOUT;
538 }
539
540 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
541 udelay(11);
542 }
543
544 /* Clear interrupt source for AUX CH command reply */
545 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg);
546
547 /* Clear interrupt source for AUX CH access error */
548 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
549 if (reg & AUX_ERR) {
550 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR);
551 return -EREMOTEIO;
552 }
553
554 /* Check AUX CH error access status */
555 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA);
556 if ((reg & AUX_STATUS_MASK) != 0) {
557 dev_err(dp->dev,
558 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK);
559 return -EREMOTEIO;
560 }
561
562 return retval;
563 }
564
analogix_dp_write_byte_to_dpcd(struct analogix_dp_device * dp,unsigned int reg_addr,unsigned char data)565 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
566 unsigned int reg_addr,
567 unsigned char data)
568 {
569 u32 reg;
570 int i;
571 int retval;
572
573 for (i = 0; i < 3; i++) {
574 /* Clear AUX CH data buffer */
575 reg = BUF_CLR;
576 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
577
578 /* Select DPCD device address */
579 reg = AUX_ADDR_7_0(reg_addr);
580 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
581 reg = AUX_ADDR_15_8(reg_addr);
582 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
583 reg = AUX_ADDR_19_16(reg_addr);
584 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
585
586 /* Write data buffer */
587 reg = (unsigned int)data;
588 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg);
589
590 /*
591 * Set DisplayPort transaction and write 1 byte
592 * If bit 3 is 1, DisplayPort transaction.
593 * If Bit 3 is 0, I2C transaction.
594 */
595 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
596 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
597
598 /* Start AUX transaction */
599 retval = analogix_dp_start_aux_transaction(dp);
600 if (retval == 0)
601 break;
602 }
603
604 return retval;
605 }
606
analogix_dp_read_byte_from_dpcd(struct analogix_dp_device * dp,unsigned int reg_addr,unsigned char * data)607 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
608 unsigned int reg_addr,
609 unsigned char *data)
610 {
611 u32 reg;
612 int i;
613 int retval;
614
615 for (i = 0; i < 3; i++) {
616 /* Clear AUX CH data buffer */
617 reg = BUF_CLR;
618 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
619
620 /* Select DPCD device address */
621 reg = AUX_ADDR_7_0(reg_addr);
622 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
623 reg = AUX_ADDR_15_8(reg_addr);
624 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
625 reg = AUX_ADDR_19_16(reg_addr);
626 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
627
628 /*
629 * Set DisplayPort transaction and read 1 byte
630 * If bit 3 is 1, DisplayPort transaction.
631 * If Bit 3 is 0, I2C transaction.
632 */
633 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
634 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
635
636 /* Start AUX transaction */
637 retval = analogix_dp_start_aux_transaction(dp);
638 if (retval == 0)
639 break;
640 }
641
642 /* Read data buffer */
643 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0);
644 *data = (unsigned char)(reg & 0xff);
645
646 return retval;
647 }
648
analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device * dp,unsigned int reg_addr,unsigned int count,unsigned char data[])649 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
650 unsigned int reg_addr,
651 unsigned int count,
652 unsigned char data[])
653 {
654 u32 reg;
655 unsigned int start_offset;
656 unsigned int cur_data_count;
657 unsigned int cur_data_idx;
658 int i;
659 int retval = 0;
660
661 /* Clear AUX CH data buffer */
662 reg = BUF_CLR;
663 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
664
665 start_offset = 0;
666 while (start_offset < count) {
667 /* Buffer size of AUX CH is 16 * 4bytes */
668 if ((count - start_offset) > 16)
669 cur_data_count = 16;
670 else
671 cur_data_count = count - start_offset;
672
673 for (i = 0; i < 3; i++) {
674 /* Select DPCD device address */
675 reg = AUX_ADDR_7_0(reg_addr + start_offset);
676 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
677 reg = AUX_ADDR_15_8(reg_addr + start_offset);
678 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
679 reg = AUX_ADDR_19_16(reg_addr + start_offset);
680 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
681
682 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
683 cur_data_idx++) {
684 reg = data[start_offset + cur_data_idx];
685 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 +
686 4 * cur_data_idx, reg);
687 }
688
689 /*
690 * Set DisplayPort transaction and write
691 * If bit 3 is 1, DisplayPort transaction.
692 * If Bit 3 is 0, I2C transaction.
693 */
694 reg = AUX_LENGTH(cur_data_count) |
695 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
696 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
697
698 /* Start AUX transaction */
699 retval = analogix_dp_start_aux_transaction(dp);
700 if (retval == 0)
701 break;
702 }
703
704 start_offset += cur_data_count;
705 }
706
707 return retval;
708 }
709
analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device * dp,unsigned int reg_addr,unsigned int count,unsigned char data[])710 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
711 unsigned int reg_addr,
712 unsigned int count,
713 unsigned char data[])
714 {
715 u32 reg;
716 unsigned int start_offset;
717 unsigned int cur_data_count;
718 unsigned int cur_data_idx;
719 int i;
720 int retval = 0;
721
722 /* Clear AUX CH data buffer */
723 reg = BUF_CLR;
724 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
725
726 start_offset = 0;
727 while (start_offset < count) {
728 /* Buffer size of AUX CH is 16 * 4bytes */
729 if ((count - start_offset) > 16)
730 cur_data_count = 16;
731 else
732 cur_data_count = count - start_offset;
733
734 /* AUX CH Request Transaction process */
735 for (i = 0; i < 3; i++) {
736 /* Select DPCD device address */
737 reg = AUX_ADDR_7_0(reg_addr + start_offset);
738 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
739 reg = AUX_ADDR_15_8(reg_addr + start_offset);
740 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
741 reg = AUX_ADDR_19_16(reg_addr + start_offset);
742 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
743
744 /*
745 * Set DisplayPort transaction and read
746 * If bit 3 is 1, DisplayPort transaction.
747 * If Bit 3 is 0, I2C transaction.
748 */
749 reg = AUX_LENGTH(cur_data_count) |
750 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
751 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
752
753 /* Start AUX transaction */
754 retval = analogix_dp_start_aux_transaction(dp);
755 if (retval == 0)
756 break;
757 }
758
759 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
760 cur_data_idx++) {
761 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0
762 + 4 * cur_data_idx);
763 data[start_offset + cur_data_idx] =
764 (unsigned char)reg;
765 }
766
767 start_offset += cur_data_count;
768 }
769
770 return retval;
771 }
772
analogix_dp_select_i2c_device(struct analogix_dp_device * dp,unsigned int device_addr,unsigned int reg_addr)773 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
774 unsigned int device_addr,
775 unsigned int reg_addr)
776 {
777 u32 reg;
778 int retval;
779
780 /* Set EDID device address */
781 reg = device_addr;
782 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
783 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0);
784 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0);
785
786 /* Set offset from base address of EDID device */
787 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr);
788
789 /*
790 * Set I2C transaction and write address
791 * If bit 3 is 1, DisplayPort transaction.
792 * If Bit 3 is 0, I2C transaction.
793 */
794 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
795 AUX_TX_COMM_WRITE;
796 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
797
798 /* Start AUX transaction */
799 retval = analogix_dp_start_aux_transaction(dp);
800 if (retval < 0)
801 return retval;
802
803 return 0;
804 }
805
analogix_dp_read_byte_from_i2c(struct analogix_dp_device * dp,unsigned int device_addr,unsigned int reg_addr,unsigned int * data)806 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
807 unsigned int device_addr,
808 unsigned int reg_addr,
809 unsigned int *data)
810 {
811 u32 reg;
812 int i;
813 int retval;
814
815 for (i = 0; i < 3; i++) {
816 /* Clear AUX CH data buffer */
817 reg = BUF_CLR;
818 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
819
820 /* Select EDID device */
821 retval = analogix_dp_select_i2c_device(dp, device_addr,
822 reg_addr);
823 if (retval != 0)
824 continue;
825
826 /*
827 * Set I2C transaction and read data
828 * If bit 3 is 1, DisplayPort transaction.
829 * If Bit 3 is 0, I2C transaction.
830 */
831 reg = AUX_TX_COMM_I2C_TRANSACTION |
832 AUX_TX_COMM_READ;
833 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
834
835 /* Start AUX transaction */
836 retval = analogix_dp_start_aux_transaction(dp);
837 if (retval == 0)
838 break;
839 }
840
841 /* Read data */
842 if (retval == 0)
843 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0);
844
845 return retval;
846 }
847
analogix_dp_read_bytes_from_i2c(struct analogix_dp_device * dp,unsigned int device_addr,unsigned int reg_addr,unsigned int count,unsigned char edid[])848 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
849 unsigned int device_addr,
850 unsigned int reg_addr,
851 unsigned int count,
852 unsigned char edid[])
853 {
854 u32 reg;
855 unsigned int i, j;
856 unsigned int cur_data_idx;
857 unsigned int defer = 0;
858 int retval = 0;
859
860 for (i = 0; i < count; i += 16) {
861 for (j = 0; j < 3; j++) {
862 /* Clear AUX CH data buffer */
863 reg = BUF_CLR;
864 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
865
866 /* Set normal AUX CH command */
867 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2);
868 reg &= ~ADDR_ONLY;
869 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg);
870
871 /*
872 * If Rx sends defer, Tx sends only reads
873 * request without sending address
874 */
875 if (!defer)
876 retval = analogix_dp_select_i2c_device(dp,
877 device_addr, reg_addr + i);
878 else
879 defer = 0;
880
881 if (retval == 0) {
882 /*
883 * Set I2C transaction and write data
884 * If bit 3 is 1, DisplayPort transaction.
885 * If Bit 3 is 0, I2C transaction.
886 */
887 reg = AUX_LENGTH(16) |
888 AUX_TX_COMM_I2C_TRANSACTION |
889 AUX_TX_COMM_READ;
890 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1,
891 reg);
892
893 /* Start AUX transaction */
894 retval = analogix_dp_start_aux_transaction(dp);
895 if (retval == 0)
896 break;
897 }
898 /* Check if Rx sends defer */
899 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM);
900 if (reg == AUX_RX_COMM_AUX_DEFER ||
901 reg == AUX_RX_COMM_I2C_DEFER) {
902 dev_dbg(dp->dev, "Defer: %d\n\n", reg);
903 defer = 1;
904 }
905 }
906
907 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
908 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0
909 + 4 * cur_data_idx);
910 edid[i + cur_data_idx] = (unsigned char)reg;
911 }
912 }
913
914 return retval;
915 }
916
analogix_dp_ssc_supported(struct analogix_dp_device * dp)917 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp)
918 {
919 /* Check if SSC is supported by both sides */
920 return dp->plat_data.ssc && dp->link_train.ssc;
921 }
922
analogix_dp_set_link_bandwidth(struct analogix_dp_device * dp,u32 bwtype)923 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
924 {
925 union phy_configure_opts phy_cfg;
926 u32 status;
927 int ret;
928
929 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype);
930
931 phy_cfg.dp.lanes = dp->link_train.lane_count;
932 phy_cfg.dp.link_rate =
933 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
934 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
935 phy_cfg.dp.set_lanes = false;
936 phy_cfg.dp.set_rate = true;
937 phy_cfg.dp.set_voltages = false;
938 ret = generic_phy_configure(&dp->phy, &phy_cfg);
939 if (ret) {
940 dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
941 __func__, ret);
942 return;
943 }
944
945 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
946 status != PLL_UNLOCKED,
947 120 * DP_TIMEOUT_LOOP_COUNT);
948 if (ret) {
949 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret);
950 return;
951 }
952 }
953
analogix_dp_get_link_bandwidth(struct analogix_dp_device * dp,u32 * bwtype)954 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
955 {
956 u32 reg;
957
958 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET);
959 *bwtype = reg;
960 }
961
analogix_dp_set_lane_count(struct analogix_dp_device * dp,u32 count)962 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
963 {
964 union phy_configure_opts phy_cfg;
965 u32 reg;
966 int ret;
967
968 reg = count;
969 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg);
970
971 phy_cfg.dp.lanes = dp->link_train.lane_count;
972 phy_cfg.dp.set_lanes = true;
973 phy_cfg.dp.set_rate = false;
974 phy_cfg.dp.set_voltages = false;
975 ret = generic_phy_configure(&dp->phy, &phy_cfg);
976 if (ret) {
977 dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
978 __func__, ret);
979 return;
980 }
981 }
982
analogix_dp_get_lane_count(struct analogix_dp_device * dp,u32 * count)983 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
984 {
985 u32 reg;
986
987 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET);
988 *count = reg;
989 }
990
analogix_dp_set_lane_link_training(struct analogix_dp_device * dp)991 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
992 {
993 union phy_configure_opts phy_cfg;
994 u8 lane;
995 int ret;
996
997 for (lane = 0; lane < dp->link_train.lane_count; lane++) {
998 u8 training_lane = dp->link_train.training_lane[lane];
999 u8 vs, pe;
1000
1001 analogix_dp_write(dp,
1002 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane,
1003 dp->link_train.training_lane[lane]);
1004
1005 vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
1006 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1007 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
1008 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1009 phy_cfg.dp.voltage[lane] = vs;
1010 phy_cfg.dp.pre[lane] = pe;
1011 }
1012
1013 phy_cfg.dp.lanes = dp->link_train.lane_count;
1014 phy_cfg.dp.link_rate =
1015 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
1016 phy_cfg.dp.set_lanes = false;
1017 phy_cfg.dp.set_rate = false;
1018 phy_cfg.dp.set_voltages = true;
1019 ret = generic_phy_configure(&dp->phy, &phy_cfg);
1020 if (ret) {
1021 dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
1022 __func__, ret);
1023 return;
1024 }
1025 }
1026
analogix_dp_get_lane_link_training(struct analogix_dp_device * dp,u8 lane)1027 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)
1028 {
1029 return analogix_dp_read(dp,
1030 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);
1031 }
1032
analogix_dp_enable_enhanced_mode(struct analogix_dp_device * dp,bool enable)1033 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
1034 bool enable)
1035 {
1036 u32 reg;
1037
1038 if (enable) {
1039 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1040 reg |= ENHANCED;
1041 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1042 } else {
1043 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1044 reg &= ~ENHANCED;
1045 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1046 }
1047 }
1048
analogix_dp_set_training_pattern(struct analogix_dp_device * dp,enum pattern_set pattern)1049 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
1050 enum pattern_set pattern)
1051 {
1052 u32 reg;
1053
1054 switch (pattern) {
1055 case PRBS7:
1056 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
1057 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1058 break;
1059 case D10_2:
1060 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
1061 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1062 break;
1063 case TRAINING_PTN1:
1064 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
1065 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1066 break;
1067 case TRAINING_PTN2:
1068 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
1069 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1070 break;
1071 case TRAINING_PTN3:
1072 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3;
1073 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1074 break;
1075 case DP_NONE:
1076 reg = SCRAMBLING_ENABLE |
1077 LINK_QUAL_PATTERN_SET_DISABLE |
1078 SW_TRAINING_PATTERN_SET_NORMAL;
1079 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1080 break;
1081 default:
1082 break;
1083 }
1084 }
1085
analogix_dp_reset_macro(struct analogix_dp_device * dp)1086 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
1087 {
1088 u32 reg;
1089
1090 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST);
1091 reg |= MACRO_RST;
1092 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg);
1093
1094 /* 10 us is the minimum reset time. */
1095 udelay(20);
1096
1097 reg &= ~MACRO_RST;
1098 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg);
1099 }
1100
analogix_dp_init_video(struct analogix_dp_device * dp)1101 void analogix_dp_init_video(struct analogix_dp_device *dp)
1102 {
1103 u32 reg;
1104
1105 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1106 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg);
1107
1108 reg = 0x0;
1109 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg);
1110
1111 reg = CHA_CRI(4) | CHA_CTRL;
1112 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
1113
1114 if (dp->video_info.force_stream_valid) {
1115 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
1116 reg |= VALID_CTRL | F_VALID;
1117 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
1118 }
1119
1120 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1121 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg);
1122 }
1123
analogix_dp_set_video_color_format(struct analogix_dp_device * dp)1124 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
1125 {
1126 u32 reg;
1127
1128 /* Configure the input color depth, color space, dynamic range */
1129 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
1130 (dp->video_info.color_depth << IN_BPC_SHIFT) |
1131 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
1132 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg);
1133
1134 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1135 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3);
1136 reg &= ~IN_YC_COEFFI_MASK;
1137 if (dp->video_info.ycbcr_coeff)
1138 reg |= IN_YC_COEFFI_ITU709;
1139 else
1140 reg |= IN_YC_COEFFI_ITU601;
1141 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg);
1142 }
1143
analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device * dp)1144 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
1145 {
1146 u32 reg;
1147
1148 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1);
1149 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg);
1150
1151 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1);
1152
1153 if (!(reg & DET_STA))
1154 return -EINVAL;
1155
1156 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2);
1157 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
1158
1159 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2);
1160
1161 if (reg & CHA_STA)
1162 return -EINVAL;
1163
1164 return 0;
1165 }
1166
analogix_dp_set_video_cr_mn(struct analogix_dp_device * dp,enum clock_recovery_m_value_type type,u32 m_value,u32 n_value)1167 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
1168 enum clock_recovery_m_value_type type,
1169 u32 m_value, u32 n_value)
1170 {
1171 u32 reg;
1172
1173 if (type == REGISTER_M) {
1174 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1175 reg |= FIX_M_VID;
1176 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1177 reg = m_value & 0xff;
1178 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg);
1179 reg = (m_value >> 8) & 0xff;
1180 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg);
1181 reg = (m_value >> 16) & 0xff;
1182 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg);
1183
1184 reg = n_value & 0xff;
1185 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg);
1186 reg = (n_value >> 8) & 0xff;
1187 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg);
1188 reg = (n_value >> 16) & 0xff;
1189 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg);
1190 } else {
1191 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1192 reg &= ~FIX_M_VID;
1193 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1194
1195 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00);
1196 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80);
1197 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00);
1198 }
1199 }
1200
analogix_dp_set_video_timing_mode(struct analogix_dp_device * dp,u32 type)1201 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
1202 {
1203 u32 reg;
1204
1205 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1206 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1207 reg &= ~FORMAT_SEL;
1208 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1209 } else {
1210 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1211 reg |= FORMAT_SEL;
1212 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1213 }
1214 }
1215
analogix_dp_enable_video_master(struct analogix_dp_device * dp,bool enable)1216 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
1217 {
1218 u32 reg;
1219
1220 if (enable) {
1221 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL);
1222 reg &= ~VIDEO_MODE_MASK;
1223 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1224 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
1225 } else {
1226 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL);
1227 reg &= ~VIDEO_MODE_MASK;
1228 reg |= VIDEO_MODE_SLAVE_MODE;
1229 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
1230 }
1231 }
1232
analogix_dp_start_video(struct analogix_dp_device * dp)1233 void analogix_dp_start_video(struct analogix_dp_device *dp)
1234 {
1235 u32 reg;
1236
1237 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
1238 reg |= VIDEO_EN;
1239 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
1240 }
1241
analogix_dp_is_video_stream_on(struct analogix_dp_device * dp)1242 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
1243 {
1244 u32 reg;
1245
1246 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
1247 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
1248
1249 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
1250 if (!(reg & STRM_VALID))
1251 return -EINVAL;
1252
1253 return 0;
1254 }
1255
analogix_dp_config_video_slave_mode(struct analogix_dp_device * dp)1256 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
1257 {
1258 u32 reg;
1259
1260 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
1261 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
1262 reg |= MASTER_VID_FUNC_EN_N;
1263 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
1264
1265 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1266 reg &= ~INTERACE_SCAN_CFG;
1267 reg |= (dp->video_info.interlaced << 2);
1268 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1269
1270 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1271 reg &= ~VSYNC_POLARITY_CFG;
1272 reg |= (dp->video_info.v_sync_polarity << 1);
1273 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1274
1275 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1276 reg &= ~HSYNC_POLARITY_CFG;
1277 reg |= (dp->video_info.h_sync_polarity << 0);
1278 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1279
1280 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1281 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
1282 }
1283
analogix_dp_enable_scrambling(struct analogix_dp_device * dp)1284 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
1285 {
1286 u32 reg;
1287
1288 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET);
1289 reg &= ~SCRAMBLING_DISABLE;
1290 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1291 }
1292
analogix_dp_disable_scrambling(struct analogix_dp_device * dp)1293 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
1294 {
1295 u32 reg;
1296
1297 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET);
1298 reg |= SCRAMBLING_DISABLE;
1299 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
1300 }
1301
analogix_dp_set_video_format(struct analogix_dp_device * dp,const struct drm_display_mode * mode)1302 void analogix_dp_set_video_format(struct analogix_dp_device *dp,
1303 const struct drm_display_mode *mode)
1304 {
1305 unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
1306
1307 dp->video_info.interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1308
1309 if (dp->plat_data.subdev_type == RK3588_EDP) {
1310 dp->video_info.v_sync_polarity = true;
1311 dp->video_info.h_sync_polarity = true;
1312 } else {
1313 dp->video_info.v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1314 dp->video_info.h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1315 }
1316
1317 hsw = mode->hsync_end - mode->hsync_start;
1318 hfp = mode->hsync_start - mode->hdisplay;
1319 hbp = mode->htotal - mode->hsync_end;
1320 vsw = mode->vsync_end - mode->vsync_start;
1321 vfp = mode->vsync_start - mode->vdisplay;
1322 vbp = mode->vtotal - mode->vsync_end;
1323
1324 /* Set Video Format Parameters */
1325 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_L,
1326 TOTAL_LINE_CFG_L(mode->vtotal));
1327 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_H,
1328 TOTAL_LINE_CFG_H(mode->vtotal >> 8));
1329 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_L,
1330 ACTIVE_LINE_CFG_L(mode->vdisplay));
1331 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_H,
1332 ACTIVE_LINE_CFG_H(mode->vdisplay >> 8));
1333 analogix_dp_write(dp, ANALOGIX_DP_V_F_PORCH_CFG,
1334 V_F_PORCH_CFG(vfp));
1335 analogix_dp_write(dp, ANALOGIX_DP_V_SYNC_WIDTH_CFG,
1336 V_SYNC_WIDTH_CFG(vsw));
1337 analogix_dp_write(dp, ANALOGIX_DP_V_B_PORCH_CFG,
1338 V_B_PORCH_CFG(vbp));
1339 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_L,
1340 TOTAL_PIXEL_CFG_L(mode->htotal));
1341 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_H,
1342 TOTAL_PIXEL_CFG_H(mode->htotal >> 8));
1343 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_L,
1344 ACTIVE_PIXEL_CFG_L(mode->hdisplay));
1345 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_H,
1346 ACTIVE_PIXEL_CFG_H(mode->hdisplay >> 8));
1347 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_L,
1348 H_F_PORCH_CFG_L(hfp));
1349 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_H,
1350 H_F_PORCH_CFG_H(hfp >> 8));
1351 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_L,
1352 H_SYNC_CFG_L(hsw));
1353 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_H,
1354 H_SYNC_CFG_H(hsw >> 8));
1355 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_L,
1356 H_B_PORCH_CFG_L(hbp));
1357 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_H,
1358 H_B_PORCH_CFG_H(hbp >> 8));
1359 }
1360
analogix_dp_video_bist_enable(struct analogix_dp_device * dp)1361 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp)
1362 {
1363 u32 reg;
1364
1365 /* Enable Video BIST */
1366 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_4, BIST_EN);
1367
1368 /*
1369 * Note that if BIST_EN is set to 1, F_SEL must be cleared to 0
1370 * although video format information comes from registers set by user.
1371 */
1372 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1373 reg &= ~FORMAT_SEL;
1374 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1375 }
1376