1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Analogix DP (Display port) core register interface driver.
4 *
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/phy/phy.h>
15
16 #include <drm/bridge/analogix_dp.h>
17 #include <drm/drm_probe_helper.h>
18
19 #include "analogix_dp_core.h"
20 #include "analogix_dp_reg.h"
21
analogix_dp_write(struct analogix_dp_device * dp,u32 reg,u32 val)22 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val)
23 {
24 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
25 readl(dp->reg_base);
26 writel(val, dp->reg_base + reg);
27 }
28
29 writel(val, dp->reg_base + reg);
30 }
31
analogix_dp_read(struct analogix_dp_device * dp,u32 reg)32 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg)
33 {
34 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
35 readl(dp->reg_base + reg);
36
37 return readl(dp->reg_base + reg);
38 }
39
analogix_dp_enable_video_mute(struct analogix_dp_device * dp,bool enable)40 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
41 {
42 u32 reg;
43
44 if (enable) {
45 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
46 reg |= HDCP_VIDEO_MUTE;
47 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
48 } else {
49 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
50 reg &= ~HDCP_VIDEO_MUTE;
51 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
52 }
53 }
54
analogix_dp_stop_video(struct analogix_dp_device * dp)55 void analogix_dp_stop_video(struct analogix_dp_device *dp)
56 {
57 u32 reg;
58
59 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
60 reg &= ~VIDEO_EN;
61 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
62 }
63
analogix_dp_set_lane_map(struct analogix_dp_device * dp)64 static void analogix_dp_set_lane_map(struct analogix_dp_device *dp)
65 {
66 struct video_info *video_info = &dp->video_info;
67 u32 i, reg = 0;
68
69 for (i = 0; i < video_info->max_lane_count; i++)
70 reg |= video_info->lane_map[i] << (2 * i);
71
72 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg);
73 }
74
analogix_dp_init_analog_param(struct analogix_dp_device * dp)75 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
76 {
77 u32 reg;
78
79 reg = TX_TERMINAL_CTRL_50_OHM;
80 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg);
81
82 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
83 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg);
84
85 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
86 reg = REF_CLK_24M;
87 if (dp->plat_data->dev_type == RK3288_DP)
88 reg ^= REF_CLK_MASK;
89
90 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg);
91 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99);
92 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40);
93 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58);
94 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22);
95 analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44);
96 }
97
98 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
99 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg);
100
101 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
102 TX_CUR1_2X | TX_CUR_16_MA;
103 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg);
104
105 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
106 CH1_AMP_400_MV | CH0_AMP_400_MV;
107 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg);
108 }
109
analogix_dp_init_interrupt(struct analogix_dp_device * dp)110 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
111 {
112 /* Set interrupt pin assertion polarity as high */
113 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0);
114
115 /* Clear pending regisers */
116 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff);
117 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f);
118 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0);
119 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7);
120 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63);
121
122 /* 0:mask,1: unmask */
123 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00);
124 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00);
125 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00);
126 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00);
127 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00);
128 }
129
analogix_dp_reset(struct analogix_dp_device * dp)130 void analogix_dp_reset(struct analogix_dp_device *dp)
131 {
132 u32 reg;
133
134 analogix_dp_stop_video(dp);
135 analogix_dp_enable_video_mute(dp, 0);
136
137 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
138 reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N |
139 SW_FUNC_EN_N;
140 else
141 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
142 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
143 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
144
145 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
146
147 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
148 SERDES_FIFO_FUNC_EN_N |
149 LS_CLK_DOMAIN_FUNC_EN_N;
150 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
151
152 usleep_range(20, 30);
153
154 analogix_dp_set_lane_map(dp);
155
156 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0);
157 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40);
158 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0);
159 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0);
160
161 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0);
162 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0);
163
164 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10);
165
166 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0);
167
168 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0);
169 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20);
170
171 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4);
172 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2);
173
174 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101);
175 }
176
analogix_dp_swreset(struct analogix_dp_device * dp)177 void analogix_dp_swreset(struct analogix_dp_device *dp)
178 {
179 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX);
180 }
181
analogix_dp_config_interrupt(struct analogix_dp_device * dp)182 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
183 {
184 /* 0: mask, 1: unmask */
185 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0);
186 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0);
187 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0);
188
189 if (dp->force_hpd || dp->hpd_gpiod)
190 analogix_dp_mute_hpd_interrupt(dp);
191 else
192 analogix_dp_unmute_hpd_interrupt(dp);
193 }
194
analogix_dp_mute_hpd_interrupt(struct analogix_dp_device * dp)195 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
196 {
197 u32 reg;
198
199 /* 0: mask, 1: unmask */
200 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4);
201 reg &= ~HOTPLUG_CHG;
202 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
203
204 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK);
205 reg &= ~INT_HPD;
206 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg);
207 }
208
analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device * dp)209 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
210 {
211 u32 reg;
212
213 /* 0: mask, 1: unmask */
214 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4);
215 reg |= HOTPLUG_CHG;
216 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
217
218 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK);
219 reg |= INT_HPD;
220 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg);
221 }
222
analogix_dp_get_pll_lock_status(struct analogix_dp_device * dp)223 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
224 {
225 u32 reg;
226
227 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL);
228 if (reg & PLL_LOCK)
229 return PLL_LOCKED;
230 else
231 return PLL_UNLOCKED;
232 }
233
analogix_dp_set_pll_power_down(struct analogix_dp_device * dp,bool enable)234 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
235 {
236 u32 reg;
237 u32 mask = DP_PLL_PD;
238 u32 pd_addr = ANALOGIX_DP_PLL_CTL;
239
240 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
241 pd_addr = ANALOGIX_DP_PD;
242 mask = RK_PLL_PD;
243 }
244
245 reg = analogix_dp_read(dp, pd_addr);
246 if (enable)
247 reg |= mask;
248 else
249 reg &= ~mask;
250 analogix_dp_write(dp, pd_addr, reg);
251 }
252
analogix_dp_set_analog_power_down(struct analogix_dp_device * dp,enum analog_power_block block,bool enable)253 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
254 enum analog_power_block block,
255 bool enable)
256 {
257 u32 reg;
258 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
259 u32 mask;
260
261 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
262 phy_pd_addr = ANALOGIX_DP_PD;
263
264 switch (block) {
265 case AUX_BLOCK:
266 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
267 mask = RK_AUX_PD;
268 else
269 mask = AUX_PD;
270
271 reg = analogix_dp_read(dp, phy_pd_addr);
272 if (enable) {
273 reg &= ~(DP_INC_BG | DP_EXP_BG);
274 reg |= mask;
275 } else {
276 reg &= ~mask;
277 }
278 analogix_dp_write(dp, phy_pd_addr, reg);
279 break;
280 case CH0_BLOCK:
281 mask = CH0_PD;
282 reg = analogix_dp_read(dp, phy_pd_addr);
283
284 if (enable)
285 reg |= mask;
286 else
287 reg &= ~mask;
288 analogix_dp_write(dp, phy_pd_addr, reg);
289 break;
290 case CH1_BLOCK:
291 mask = CH1_PD;
292 reg = analogix_dp_read(dp, phy_pd_addr);
293
294 if (enable)
295 reg |= mask;
296 else
297 reg &= ~mask;
298 analogix_dp_write(dp, phy_pd_addr, reg);
299 break;
300 case CH2_BLOCK:
301 mask = CH2_PD;
302 reg = analogix_dp_read(dp, phy_pd_addr);
303
304 if (enable)
305 reg |= mask;
306 else
307 reg &= ~mask;
308 analogix_dp_write(dp, phy_pd_addr, reg);
309 break;
310 case CH3_BLOCK:
311 mask = CH3_PD;
312 reg = analogix_dp_read(dp, phy_pd_addr);
313
314 if (enable)
315 reg |= mask;
316 else
317 reg &= ~mask;
318 analogix_dp_write(dp, phy_pd_addr, reg);
319 break;
320 case ANALOG_TOTAL:
321 /*
322 * There is no bit named DP_PHY_PD, so We used DP_INC_BG
323 * to power off everything instead of DP_PHY_PD in
324 * Rockchip
325 */
326 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
327 mask = DP_INC_BG;
328 else
329 mask = DP_PHY_PD;
330
331 reg = analogix_dp_read(dp, phy_pd_addr);
332 if (enable)
333 reg |= mask;
334 else
335 reg &= ~mask;
336
337 analogix_dp_write(dp, phy_pd_addr, reg);
338 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
339 usleep_range(10, 15);
340 break;
341 case POWER_ALL:
342 if (enable) {
343 reg = DP_ALL_PD;
344 analogix_dp_write(dp, phy_pd_addr, reg);
345 } else {
346 reg = DP_ALL_PD;
347 analogix_dp_write(dp, phy_pd_addr, reg);
348 usleep_range(10, 15);
349 reg &= ~DP_INC_BG;
350 analogix_dp_write(dp, phy_pd_addr, reg);
351 usleep_range(10, 15);
352
353 analogix_dp_write(dp, phy_pd_addr, 0x00);
354 }
355 break;
356 default:
357 break;
358 }
359 }
360
analogix_dp_init_analog_func(struct analogix_dp_device * dp)361 int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
362 {
363 u32 reg;
364
365 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
366
367 reg = PLL_LOCK_CHG;
368 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg);
369
370 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL);
371 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
372 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg);
373
374 /* Power up PLL */
375 analogix_dp_set_pll_power_down(dp, 0);
376
377 /* Enable Serdes FIFO function and Link symbol clock domain module */
378 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
379 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
380 | AUX_FUNC_EN_N);
381 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
382 return 0;
383 }
384
analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device * dp)385 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
386 {
387 u32 reg;
388
389 if (dp->hpd_gpiod)
390 return;
391
392 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
393 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg);
394
395 reg = INT_HPD;
396 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg);
397 }
398
analogix_dp_init_hpd(struct analogix_dp_device * dp)399 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
400 {
401 u32 reg;
402
403 if (dp->hpd_gpiod)
404 return;
405
406 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0xbb);
407 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x80);
408
409 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
410 reg &= ~(F_HPD | HPD_CTRL);
411 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
412 }
413
analogix_dp_force_hpd(struct analogix_dp_device * dp)414 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
415 {
416 u32 reg;
417
418 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
419 reg |= (F_HPD | HPD_CTRL);
420 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
421 }
422
analogix_dp_handle_hpd_event(struct analogix_dp_device * dp)423 static void analogix_dp_handle_hpd_event(struct analogix_dp_device *dp)
424 {
425 bool changed = false;
426 u32 reg;
427
428 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
429 if (reg & INT_HPD) {
430 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, INT_HPD);
431
432 memset(&dp->compliance, 0, sizeof(dp->compliance));
433
434 analogix_dp_check_device_service_irq(dp);
435
436 if (dp->compliance.test_active &&
437 dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
438 analogix_dp_phy_test(dp);
439 return;
440 }
441 }
442
443 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4);
444 if (reg & HOTPLUG_CHG) {
445 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, HOTPLUG_CHG);
446 changed = true;
447 }
448
449 if (changed)
450 drm_helper_hpd_irq_event(dp->drm_dev);
451 }
452
analogix_dp_irq_handler(struct analogix_dp_device * dp)453 void analogix_dp_irq_handler(struct analogix_dp_device *dp)
454 {
455 analogix_dp_handle_hpd_event(dp);
456 }
457
analogix_dp_reset_aux(struct analogix_dp_device * dp)458 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
459 {
460 u32 reg;
461
462 /* Disable AUX channel module */
463 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
464 reg |= AUX_FUNC_EN_N;
465 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
466 }
467
analogix_dp_init_aux(struct analogix_dp_device * dp)468 void analogix_dp_init_aux(struct analogix_dp_device *dp)
469 {
470 u32 reg;
471
472 /* Clear inerrupts related to AUX channel */
473 reg = RPLY_RECEIV | AUX_ERR;
474 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg);
475
476 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true);
477 usleep_range(10, 11);
478 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false);
479
480 analogix_dp_reset_aux(dp);
481
482 /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
483 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
484 reg = 0;
485 else
486 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
487
488 /* Disable AUX transaction H/W retry */
489 reg |= AUX_HW_RETRY_COUNT_SEL(0) |
490 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
491
492 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg);
493
494 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
495 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
496 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg);
497
498 /* Enable AUX channel module */
499 analogix_dp_enable_sw_function(dp);
500 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
501 reg &= ~AUX_FUNC_EN_N;
502 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg);
503 }
504
analogix_dp_get_plug_in_status(struct analogix_dp_device * dp)505 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
506 {
507 u32 reg;
508
509 if (dp->hpd_gpiod) {
510 if (gpiod_get_value(dp->hpd_gpiod))
511 return 0;
512 } else {
513 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
514 if (reg & HPD_STATUS)
515 return 0;
516 }
517
518 return -EINVAL;
519 }
520
analogix_dp_enable_sw_function(struct analogix_dp_device * dp)521 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
522 {
523 u32 reg;
524
525 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
526 reg &= ~SW_FUNC_EN_N;
527 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
528 }
529
analogix_dp_ssc_enable(struct analogix_dp_device * dp)530 static void analogix_dp_ssc_enable(struct analogix_dp_device *dp)
531 {
532 u32 reg;
533
534 /* 4500ppm */
535 writel(0x19, dp->reg_base + ANALOIGX_DP_SSC_REG);
536 /*
537 * To apply updated SSC parameters into SSC operation,
538 * firmware must disable and enable this bit.
539 */
540 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
541 reg |= SSC_FUNC_EN_N;
542 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
543 reg &= ~SSC_FUNC_EN_N;
544 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
545 }
546
analogix_dp_ssc_disable(struct analogix_dp_device * dp)547 static void analogix_dp_ssc_disable(struct analogix_dp_device *dp)
548 {
549 u32 reg;
550
551 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
552 reg |= SSC_FUNC_EN_N;
553 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
554 }
555
analogix_dp_ssc_supported(struct analogix_dp_device * dp)556 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp)
557 {
558 /* Check if SSC is supported by both sides */
559 return dp->plat_data->ssc && dp->link_train.ssc;
560 }
561
analogix_dp_set_link_bandwidth(struct analogix_dp_device * dp,u32 bwtype)562 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
563 {
564 u32 status;
565 int ret;
566
567 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype);
568
569 if (dp->phy) {
570 union phy_configure_opts phy_cfg = {0};
571
572 phy_cfg.dp.lanes = dp->link_train.lane_count;
573 phy_cfg.dp.link_rate =
574 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
575 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
576 phy_cfg.dp.set_lanes = false;
577 phy_cfg.dp.set_rate = true;
578 phy_cfg.dp.set_voltages = false;
579 ret = phy_configure(dp->phy, &phy_cfg);
580 if (ret && ret != -EOPNOTSUPP) {
581 dev_err(dp->dev, "%s: phy_configure failed: %d\n",
582 __func__, ret);
583 return;
584 }
585 } else {
586 if (analogix_dp_ssc_supported(dp))
587 analogix_dp_ssc_enable(dp);
588 else
589 analogix_dp_ssc_disable(dp);
590 }
591
592 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
593 status != PLL_UNLOCKED, 120,
594 120 * DP_TIMEOUT_LOOP_COUNT);
595 if (ret) {
596 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret);
597 return;
598 }
599 }
600
analogix_dp_get_link_bandwidth(struct analogix_dp_device * dp,u32 * bwtype)601 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
602 {
603 u32 reg;
604
605 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET);
606 *bwtype = reg;
607 }
608
analogix_dp_set_lane_count(struct analogix_dp_device * dp,u32 count)609 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
610 {
611 u32 reg;
612 int ret;
613
614 reg = count;
615 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg);
616
617 if (dp->phy) {
618 union phy_configure_opts phy_cfg = {0};
619
620 phy_cfg.dp.lanes = dp->link_train.lane_count;
621 phy_cfg.dp.set_lanes = true;
622 phy_cfg.dp.set_rate = false;
623 phy_cfg.dp.set_voltages = false;
624 ret = phy_configure(dp->phy, &phy_cfg);
625 if (ret && ret != -EOPNOTSUPP) {
626 dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
627 __func__, ret);
628 return;
629 }
630 }
631 }
632
analogix_dp_get_lane_count(struct analogix_dp_device * dp,u32 * count)633 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
634 {
635 u32 reg;
636
637 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET);
638 *count = reg;
639 }
640
analogix_dp_set_lane_link_training(struct analogix_dp_device * dp)641 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
642 {
643 u8 lane;
644 int ret;
645
646 for (lane = 0; lane < dp->link_train.lane_count; lane++)
647 analogix_dp_write(dp,
648 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane,
649 dp->link_train.training_lane[lane]);
650
651 if (dp->phy) {
652 union phy_configure_opts phy_cfg = {0};
653
654 for (lane = 0; lane < dp->link_train.lane_count; lane++) {
655 u8 training_lane = dp->link_train.training_lane[lane];
656 u8 vs, pe;
657
658 vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
659 DP_TRAIN_VOLTAGE_SWING_SHIFT;
660 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
661 DP_TRAIN_PRE_EMPHASIS_SHIFT;
662 phy_cfg.dp.voltage[lane] = vs;
663 phy_cfg.dp.pre[lane] = pe;
664 }
665
666 phy_cfg.dp.lanes = dp->link_train.lane_count;
667 phy_cfg.dp.link_rate =
668 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
669 phy_cfg.dp.set_lanes = false;
670 phy_cfg.dp.set_rate = false;
671 phy_cfg.dp.set_voltages = true;
672 ret = phy_configure(dp->phy, &phy_cfg);
673 if (ret && ret != -EOPNOTSUPP) {
674 dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
675 __func__, ret);
676 return;
677 }
678 }
679 }
680
analogix_dp_get_lane_link_training(struct analogix_dp_device * dp,u8 lane)681 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)
682 {
683 return analogix_dp_read(dp,
684 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);
685 }
686
analogix_dp_enable_enhanced_mode(struct analogix_dp_device * dp,bool enable)687 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
688 bool enable)
689 {
690 u32 reg;
691
692 if (enable) {
693 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
694 reg |= ENHANCED;
695 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
696 } else {
697 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
698 reg &= ~ENHANCED;
699 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
700 }
701 }
702
analogix_dp_get_enhanced_mode(struct analogix_dp_device * dp)703 bool analogix_dp_get_enhanced_mode(struct analogix_dp_device *dp)
704 {
705 u32 reg;
706
707 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
708
709 return !!(reg & ENHANCED);
710 }
711
analogix_dp_set_training_pattern(struct analogix_dp_device * dp,enum pattern_set pattern)712 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
713 enum pattern_set pattern)
714 {
715 u32 reg;
716
717 switch (pattern) {
718 case PRBS7:
719 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
720 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
721 break;
722 case D10_2:
723 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
724 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
725 break;
726 case TRAINING_PTN1:
727 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
728 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
729 break;
730 case TRAINING_PTN2:
731 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
732 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
733 break;
734 case TRAINING_PTN3:
735 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3;
736 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
737 break;
738 case TEST_PATTERN_80BIT:
739 reg = 0x3e0f83e0;
740 analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN0, reg);
741 reg = 0x0f83e0f8;
742 analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN1, reg);
743 reg = 0x0000f83e;
744 analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN2, reg);
745 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_80BIT;
746 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
747 break;
748 case TEST_PATTERN_HBR2:
749 reg = 0xfb;
750 analogix_dp_write(dp, ANALOGIX_DP_TEST_HBR2_PATTERN, reg);
751 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_HBR2;
752 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
753 break;
754 case DP_NONE:
755 reg = SCRAMBLING_ENABLE |
756 LINK_QUAL_PATTERN_SET_DISABLE |
757 SW_TRAINING_PATTERN_SET_NORMAL;
758 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
759 break;
760 default:
761 break;
762 }
763 }
764
analogix_dp_reset_macro(struct analogix_dp_device * dp)765 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
766 {
767 u32 reg;
768
769 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST);
770 reg |= MACRO_RST;
771 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg);
772
773 /* 10 us is the minimum reset time. */
774 usleep_range(10, 20);
775
776 reg &= ~MACRO_RST;
777 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg);
778 }
779
analogix_dp_init_video(struct analogix_dp_device * dp)780 void analogix_dp_init_video(struct analogix_dp_device *dp)
781 {
782 u32 reg;
783
784 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
785 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg);
786
787 reg = 0x0;
788 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg);
789
790 reg = CHA_CRI(4) | CHA_CTRL;
791 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
792
793 if (dp->video_info.force_stream_valid) {
794 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
795 reg |= VALID_CTRL | F_VALID;
796 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
797 }
798
799 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
800 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg);
801 }
802
analogix_dp_set_video_color_format(struct analogix_dp_device * dp)803 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
804 {
805 u32 reg;
806
807 /* Configure the input color depth, color space, dynamic range */
808 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
809 (dp->video_info.color_depth << IN_BPC_SHIFT) |
810 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
811 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg);
812
813 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
814 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3);
815 reg &= ~IN_YC_COEFFI_MASK;
816 if (dp->video_info.ycbcr_coeff)
817 reg |= IN_YC_COEFFI_ITU709;
818 else
819 reg |= IN_YC_COEFFI_ITU601;
820 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg);
821 }
822
analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device * dp)823 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
824 {
825 u32 reg;
826
827 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1);
828 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg);
829
830 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1);
831
832 if (!(reg & DET_STA)) {
833 dev_dbg(dp->dev, "Input stream clock not detected.\n");
834 return -EINVAL;
835 }
836
837 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2);
838 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
839
840 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2);
841 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
842
843 if (reg & CHA_STA) {
844 dev_dbg(dp->dev, "Input stream clk is changing\n");
845 return -EINVAL;
846 }
847
848 return 0;
849 }
850
analogix_dp_set_video_cr_mn(struct analogix_dp_device * dp,enum clock_recovery_m_value_type type,u32 m_value,u32 n_value)851 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
852 enum clock_recovery_m_value_type type,
853 u32 m_value, u32 n_value)
854 {
855 u32 reg;
856
857 if (type == REGISTER_M) {
858 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
859 reg |= FIX_M_VID;
860 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
861 reg = m_value & 0xff;
862 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg);
863 reg = (m_value >> 8) & 0xff;
864 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg);
865 reg = (m_value >> 16) & 0xff;
866 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg);
867
868 reg = n_value & 0xff;
869 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg);
870 reg = (n_value >> 8) & 0xff;
871 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg);
872 reg = (n_value >> 16) & 0xff;
873 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg);
874 } else {
875 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
876 reg &= ~FIX_M_VID;
877 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
878
879 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00);
880 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80);
881 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00);
882 }
883 }
884
analogix_dp_set_video_timing_mode(struct analogix_dp_device * dp,u32 type)885 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
886 {
887 u32 reg;
888
889 if (type == VIDEO_TIMING_FROM_CAPTURE) {
890 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
891 reg &= ~FORMAT_SEL;
892 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
893 } else {
894 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
895 reg |= FORMAT_SEL;
896 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
897 }
898 }
899
analogix_dp_enable_video_master(struct analogix_dp_device * dp,bool enable)900 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
901 {
902 u32 reg;
903
904 if (enable) {
905 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL);
906 reg &= ~VIDEO_MODE_MASK;
907 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
908 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
909 } else {
910 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL);
911 reg &= ~VIDEO_MODE_MASK;
912 reg |= VIDEO_MODE_SLAVE_MODE;
913 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
914 }
915 }
916
analogix_dp_start_video(struct analogix_dp_device * dp)917 void analogix_dp_start_video(struct analogix_dp_device *dp)
918 {
919 u32 reg;
920
921 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1);
922 reg |= VIDEO_EN;
923 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
924 }
925
analogix_dp_is_video_stream_on(struct analogix_dp_device * dp)926 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
927 {
928 u32 reg;
929
930 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
931 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
932
933 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
934 if (!(reg & STRM_VALID)) {
935 dev_dbg(dp->dev, "Input video stream is not detected.\n");
936 return -EINVAL;
937 }
938
939 return 0;
940 }
941
analogix_dp_config_video_slave_mode(struct analogix_dp_device * dp)942 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
943 {
944 u32 reg;
945
946 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
947 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
948 reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
949 } else {
950 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
951 reg |= MASTER_VID_FUNC_EN_N;
952 }
953 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
954
955 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
956 reg &= ~INTERACE_SCAN_CFG;
957 reg |= (dp->video_info.interlaced << 2);
958 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
959
960 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
961 reg &= ~VSYNC_POLARITY_CFG;
962 reg |= (dp->video_info.v_sync_polarity << 1);
963 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
964
965 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
966 reg &= ~HSYNC_POLARITY_CFG;
967 reg |= (dp->video_info.h_sync_polarity << 0);
968 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
969
970 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
971 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg);
972 }
973
analogix_dp_enable_scrambling(struct analogix_dp_device * dp)974 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
975 {
976 u32 reg;
977
978 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET);
979 reg &= ~SCRAMBLING_DISABLE;
980 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
981 }
982
analogix_dp_disable_scrambling(struct analogix_dp_device * dp)983 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
984 {
985 u32 reg;
986
987 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET);
988 reg |= SCRAMBLING_DISABLE;
989 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
990 }
991
analogix_dp_enable_psr_crc(struct analogix_dp_device * dp)992 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
993 {
994 analogix_dp_write(dp, ANALOGIX_DP_CRC_CON, PSR_VID_CRC_ENABLE);
995 }
996
analogix_dp_get_psr_status(struct analogix_dp_device * dp)997 static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp)
998 {
999 ssize_t val;
1000 u8 status;
1001
1002 val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
1003 if (val < 0) {
1004 dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val);
1005 return val;
1006 }
1007 return status;
1008 }
1009
analogix_dp_reuse_spd(struct analogix_dp_device * dp)1010 static void analogix_dp_reuse_spd(struct analogix_dp_device *dp)
1011 {
1012 u32 reg, val;
1013
1014 switch (dp->plat_data->dev_type) {
1015 case RK3588_EDP:
1016 reg = ANALOGIX_DP_SPDIF_AUDIO_CTL_0;
1017 break;
1018 default:
1019 reg = ANALOGIX_DP_VIDEO_CTL_3;
1020 break;
1021 }
1022
1023 val = analogix_dp_read(dp, reg);
1024 val |= REUSE_SPD_EN;
1025 analogix_dp_write(dp, reg, val);
1026 }
1027
analogix_dp_send_psr_spd(struct analogix_dp_device * dp,struct dp_sdp * vsc,bool blocking)1028 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
1029 struct dp_sdp *vsc, bool blocking)
1030 {
1031 unsigned int val;
1032 int ret;
1033 ssize_t psr_status;
1034
1035 /* don't send info frame */
1036 val = analogix_dp_read(dp, ANALOGIX_DP_PKT_SEND_CTL);
1037 val &= ~IF_EN;
1038 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, val);
1039
1040 /* configure single frame update mode */
1041 analogix_dp_write(dp, ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL,
1042 PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE);
1043
1044 /* configure VSC HB0~HB3 */
1045 analogix_dp_write(dp, ANALOGIX_DP_SPD_HB0, vsc->sdp_header.HB0);
1046 analogix_dp_write(dp, ANALOGIX_DP_SPD_HB1, vsc->sdp_header.HB1);
1047 analogix_dp_write(dp, ANALOGIX_DP_SPD_HB2, vsc->sdp_header.HB2);
1048 analogix_dp_write(dp, ANALOGIX_DP_SPD_HB3, vsc->sdp_header.HB3);
1049
1050 /* configure reused VSC PB0~PB3, magic number from vendor */
1051 analogix_dp_write(dp, ANALOGIX_DP_SPD_PB0, 0x00);
1052 analogix_dp_write(dp, ANALOGIX_DP_SPD_PB1, 0x16);
1053 analogix_dp_write(dp, ANALOGIX_DP_SPD_PB2, 0xCE);
1054 analogix_dp_write(dp, ANALOGIX_DP_SPD_PB3, 0x5D);
1055
1056 /* configure DB0 / DB1 values */
1057 analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB0, vsc->db[0]);
1058 analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB1, vsc->db[1]);
1059
1060 /* configure PB0 / PB1 values */
1061 analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_PB0,
1062 vsc->db[1] ? 0x8d : 0x00);
1063 analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_PB1, 0x00);
1064
1065 /* set reuse spd inforframe */
1066 analogix_dp_reuse_spd(dp);
1067
1068 /* mark info frame update */
1069 val = analogix_dp_read(dp, ANALOGIX_DP_PKT_SEND_CTL);
1070 val = (val | IF_UP) & ~IF_EN;
1071 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, val);
1072
1073 /* send info frame */
1074 val = analogix_dp_read(dp, ANALOGIX_DP_PKT_SEND_CTL);
1075 val |= IF_EN;
1076 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, val);
1077
1078 if (!blocking)
1079 return 0;
1080
1081 /*
1082 * db[1]!=0: entering PSR, wait for fully active remote frame buffer.
1083 * db[1]==0: exiting PSR, wait for either
1084 * (a) ACTIVE_RESYNC - the sink "must display the
1085 * incoming active frames from the Source device with no visible
1086 * glitches and/or artifacts", even though timings may still be
1087 * re-synchronizing; or
1088 * (b) INACTIVE - the transition is fully complete.
1089 */
1090 ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
1091 psr_status >= 0 &&
1092 ((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
1093 (!vsc->db[1] && (psr_status == DP_PSR_SINK_ACTIVE_RESYNC ||
1094 psr_status == DP_PSR_SINK_INACTIVE))),
1095 1500, DP_TIMEOUT_PSR_LOOP_MS * 1000);
1096 if (ret) {
1097 dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
1098 return ret;
1099 }
1100 return 0;
1101 }
1102
analogix_dp_phy_power_on(struct analogix_dp_device * dp)1103 int analogix_dp_phy_power_on(struct analogix_dp_device *dp)
1104 {
1105 int ret;
1106
1107 ret = phy_set_mode(dp->phy, PHY_MODE_DP);
1108 if (ret) {
1109 dev_err(dp->dev, "phy_set_mode failed: %d\n", ret);
1110 return ret;
1111 }
1112
1113 ret = phy_power_on(dp->phy);
1114 if (ret) {
1115 dev_err(dp->dev, "phy_power_on failed: %d\n", ret);
1116 return ret;
1117 }
1118
1119 return ret;
1120 }
1121
analogix_dp_phy_power_off(struct analogix_dp_device * dp)1122 void analogix_dp_phy_power_off(struct analogix_dp_device *dp)
1123 {
1124 phy_power_off(dp->phy);
1125 }
1126
1127 enum {
1128 AUX_STATUS_OK,
1129 AUX_STATUS_NACK_ERROR,
1130 AUX_STATUS_TIMEOUT_ERROR,
1131 AUX_STATUS_UNKNOWN_ERROR,
1132 AUX_STATUS_MUCH_DEFER_ERROR,
1133 AUX_STATUS_TX_SHORT_ERROR,
1134 AUX_STATUS_RX_SHORT_ERROR,
1135 AUX_STATUS_NACK_WITHOUT_M_ERROR,
1136 AUX_STATUS_I2C_NACK_ERROR
1137 };
1138
analogix_dp_transfer(struct analogix_dp_device * dp,struct drm_dp_aux_msg * msg)1139 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
1140 struct drm_dp_aux_msg *msg)
1141 {
1142 u32 reg;
1143 u8 *buffer = msg->buffer;
1144 unsigned int i;
1145 int num_transferred = 0;
1146 int ret;
1147
1148 /* Buffer size of AUX CH is 16 bytes */
1149 if (WARN_ON(msg->size > 16))
1150 return -E2BIG;
1151
1152 /* Clear AUX CH data buffer */
1153 reg = BUF_CLR;
1154 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
1155
1156 switch (msg->request & ~DP_AUX_I2C_MOT) {
1157 case DP_AUX_I2C_WRITE:
1158 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION;
1159 if (msg->request & DP_AUX_I2C_MOT)
1160 reg |= AUX_TX_COMM_MOT;
1161 break;
1162
1163 case DP_AUX_I2C_READ:
1164 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION;
1165 if (msg->request & DP_AUX_I2C_MOT)
1166 reg |= AUX_TX_COMM_MOT;
1167 break;
1168
1169 case DP_AUX_NATIVE_WRITE:
1170 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION;
1171 break;
1172
1173 case DP_AUX_NATIVE_READ:
1174 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION;
1175 break;
1176
1177 default:
1178 return -EINVAL;
1179 }
1180
1181 reg |= AUX_LENGTH(msg->size);
1182 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
1183
1184 /* Select DPCD device address */
1185 reg = AUX_ADDR_7_0(msg->address);
1186 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
1187 reg = AUX_ADDR_15_8(msg->address);
1188 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
1189 reg = AUX_ADDR_19_16(msg->address);
1190 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
1191
1192 if (!(msg->request & DP_AUX_I2C_READ)) {
1193 for (i = 0; i < msg->size; i++) {
1194 reg = buffer[i];
1195 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 4 * i,
1196 reg);
1197 num_transferred++;
1198 }
1199 }
1200
1201 /* Enable AUX CH operation */
1202 reg = AUX_EN;
1203
1204 /* Zero-sized messages specify address-only transactions. */
1205 if (msg->size < 1)
1206 reg |= ADDR_ONLY;
1207
1208 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg);
1209
1210 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2,
1211 reg, !(reg & AUX_EN), 25, 500 * 1000);
1212 if (ret) {
1213 dev_err(dp->dev, "AUX CH enable timeout!\n");
1214 goto aux_error;
1215 }
1216
1217 /* TODO: Wait for an interrupt instead of looping? */
1218 /* Is AUX CH command reply received? */
1219 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA,
1220 reg, reg & RPLY_RECEIV, 10, 20 * 1000);
1221 if (ret) {
1222 dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
1223 goto aux_error;
1224 }
1225
1226 /* Clear interrupt source for AUX CH command reply */
1227 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, RPLY_RECEIV);
1228
1229 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA);
1230 if ((reg & AUX_STATUS_MASK) == AUX_STATUS_TIMEOUT_ERROR)
1231 return -ETIMEDOUT;
1232
1233 if (msg->request & DP_AUX_I2C_READ) {
1234 size_t buf_data_count;
1235
1236 reg = analogix_dp_read(dp, ANALOGIX_DP_BUFFER_DATA_CTL);
1237 buf_data_count = BUF_DATA_COUNT(reg);
1238
1239 if (buf_data_count != msg->size)
1240 return -EBUSY;
1241
1242 for (i = 0; i < msg->size; i++) {
1243 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 +
1244 4 * i);
1245 buffer[i] = (unsigned char)reg;
1246 num_transferred++;
1247 }
1248 }
1249
1250 /* Check if Rx sends defer */
1251 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM);
1252 if (reg == AUX_RX_COMM_AUX_DEFER)
1253 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1254 else if (reg == AUX_RX_COMM_I2C_DEFER)
1255 msg->reply = DP_AUX_I2C_REPLY_DEFER;
1256 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
1257 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
1258 msg->reply = DP_AUX_I2C_REPLY_ACK;
1259 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
1260 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
1261 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1262
1263 return (num_transferred == msg->size) ? num_transferred : -EBUSY;
1264
1265 aux_error:
1266 /* if aux err happen, reset aux */
1267 analogix_dp_init_aux(dp);
1268
1269 return -EREMOTEIO;
1270 }
1271
analogix_dp_set_video_format(struct analogix_dp_device * dp)1272 void analogix_dp_set_video_format(struct analogix_dp_device *dp)
1273 {
1274 struct video_info *video = &dp->video_info;
1275 const struct drm_display_mode *mode = &video->mode;
1276 unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
1277
1278 hsw = mode->hsync_end - mode->hsync_start;
1279 hfp = mode->hsync_start - mode->hdisplay;
1280 hbp = mode->htotal - mode->hsync_end;
1281 vsw = mode->vsync_end - mode->vsync_start;
1282 vfp = mode->vsync_start - mode->vdisplay;
1283 vbp = mode->vtotal - mode->vsync_end;
1284
1285 /* Set Video Format Parameters */
1286 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_L,
1287 TOTAL_LINE_CFG_L(mode->vtotal));
1288 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_H,
1289 TOTAL_LINE_CFG_H(mode->vtotal >> 8));
1290 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_L,
1291 ACTIVE_LINE_CFG_L(mode->vdisplay));
1292 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_H,
1293 ACTIVE_LINE_CFG_H(mode->vdisplay >> 8));
1294 analogix_dp_write(dp, ANALOGIX_DP_V_F_PORCH_CFG,
1295 V_F_PORCH_CFG(vfp));
1296 analogix_dp_write(dp, ANALOGIX_DP_V_SYNC_WIDTH_CFG,
1297 V_SYNC_WIDTH_CFG(vsw));
1298 analogix_dp_write(dp, ANALOGIX_DP_V_B_PORCH_CFG,
1299 V_B_PORCH_CFG(vbp));
1300 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_L,
1301 TOTAL_PIXEL_CFG_L(mode->htotal));
1302 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_H,
1303 TOTAL_PIXEL_CFG_H(mode->htotal >> 8));
1304 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_L,
1305 ACTIVE_PIXEL_CFG_L(mode->hdisplay));
1306 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_H,
1307 ACTIVE_PIXEL_CFG_H(mode->hdisplay >> 8));
1308 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_L,
1309 H_F_PORCH_CFG_L(hfp));
1310 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_H,
1311 H_F_PORCH_CFG_H(hfp >> 8));
1312 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_L,
1313 H_SYNC_CFG_L(hsw));
1314 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_H,
1315 H_SYNC_CFG_H(hsw >> 8));
1316 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_L,
1317 H_B_PORCH_CFG_L(hbp));
1318 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_H,
1319 H_B_PORCH_CFG_H(hbp >> 8));
1320 }
1321
analogix_dp_video_bist_enable(struct analogix_dp_device * dp)1322 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp)
1323 {
1324 u32 reg;
1325
1326 /* Enable Video BIST */
1327 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_4, BIST_EN);
1328
1329 /*
1330 * Note that if BIST_EN is set to 1, F_SEL must be cleared to 0
1331 * although video format information comes from registers set by user.
1332 */
1333 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10);
1334 reg &= ~FORMAT_SEL;
1335 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg);
1336 }
1337
analogix_dp_audio_config_i2s(struct analogix_dp_device * dp)1338 void analogix_dp_audio_config_i2s(struct analogix_dp_device *dp)
1339 {
1340 u32 reg;
1341
1342 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1343 reg &= ~FIX_M_AUD;
1344 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1345
1346 reg = analogix_dp_read(dp, ANALOGIX_DP_I2S_CTRL);
1347 reg |= I2S_EN;
1348 analogix_dp_write(dp, ANALOGIX_DP_I2S_CTRL, reg);
1349 }
1350
analogix_dp_audio_config_spdif(struct analogix_dp_device * dp)1351 void analogix_dp_audio_config_spdif(struct analogix_dp_device *dp)
1352 {
1353 u32 reg;
1354
1355 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
1356 reg &= ~FIX_M_AUD;
1357 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg);
1358
1359 reg = analogix_dp_read(dp, ANALOGIX_DP_SPDIF_AUDIO_CTL_0);
1360 reg |= AUD_SPDIF_EN;
1361 analogix_dp_write(dp, ANALOGIX_DP_SPDIF_AUDIO_CTL_0, reg);
1362 }
1363
analogix_dp_audio_enable(struct analogix_dp_device * dp)1364 void analogix_dp_audio_enable(struct analogix_dp_device *dp)
1365 {
1366 u32 reg;
1367
1368 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
1369 reg &= ~(AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N);
1370 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
1371
1372 reg = analogix_dp_read(dp, ANALOGIX_DP_AUD_CTL);
1373 reg |= MISC_CTRL_RESET | DP_AUDIO_EN;
1374 analogix_dp_write(dp, ANALOGIX_DP_AUD_CTL, reg);
1375 }
1376
analogix_dp_audio_disable(struct analogix_dp_device * dp)1377 void analogix_dp_audio_disable(struct analogix_dp_device *dp)
1378 {
1379 u32 reg;
1380
1381 analogix_dp_write(dp, ANALOGIX_DP_AUD_CTL, 0);
1382
1383 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1);
1384 reg |= AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N;
1385 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
1386 }
1387
analogix_dp_init(struct analogix_dp_device * dp)1388 void analogix_dp_init(struct analogix_dp_device *dp)
1389 {
1390 analogix_dp_init_interrupt(dp);
1391 analogix_dp_config_interrupt(dp);
1392 analogix_dp_init_hpd(dp);
1393 analogix_dp_init_aux(dp);
1394 }
1395