1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Analogix DP (Display Port) core interface driver.
4 *
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/err.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22
23 #include <drm/bridge/analogix_dp.h>
24 #include <drm/drm_atomic.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_bridge.h>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_device.h>
29 #include <drm/drm_panel.h>
30 #include <drm/drm_print.h>
31 #include <drm/drm_probe_helper.h>
32
33 #include "analogix_dp_core.h"
34 #include "analogix_dp_reg.h"
35 #include "../../rockchip/rockchip_drm_drv.h"
36
37 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
38
39 static const bool verify_fast_training;
40
41 #ifdef CONFIG_NO_GKI
42 #undef EXTCON_DISP_DP
43 #define EXTCON_DISP_DP EXTCON_DISP_EDP
44 #endif
45
46 static const unsigned int analogix_dp_cable[] = {
47 EXTCON_DISP_DP,
48 EXTCON_NONE,
49 };
50
51 struct bridge_init {
52 struct i2c_client *client;
53 struct device_node *node;
54 };
55
56 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
57 const struct drm_display_mode *adj_mode);
58
analogix_dp_bandwidth_ok(struct analogix_dp_device * dp,const struct drm_display_mode * mode,unsigned int rate,unsigned int lanes)59 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp,
60 const struct drm_display_mode *mode,
61 unsigned int rate, unsigned int lanes)
62 {
63 const struct drm_display_info *info;
64 u32 max_bw, req_bw, bpp = 24;
65
66 if (dp->plat_data->skip_connector)
67 return true;
68
69 info = &dp->connector.display_info;
70 if (info->bpc)
71 bpp = 3 * info->bpc;
72
73 req_bw = mode->clock * bpp / 8;
74 max_bw = lanes * rate;
75 if (req_bw > max_bw)
76 return false;
77
78 return true;
79 }
80
analogix_dp_init_dp(struct analogix_dp_device * dp)81 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
82 {
83 int ret;
84
85 analogix_dp_reset(dp);
86
87 analogix_dp_swreset(dp);
88
89 analogix_dp_init_analog_param(dp);
90 analogix_dp_init_interrupt(dp);
91
92 /* SW defined function Normal operation */
93 analogix_dp_enable_sw_function(dp);
94
95 analogix_dp_config_interrupt(dp);
96 ret = analogix_dp_init_analog_func(dp);
97 if (ret)
98 return ret;
99
100 analogix_dp_init_hpd(dp);
101 analogix_dp_init_aux(dp);
102 return 0;
103 }
104
analogix_dp_panel_prepare(struct analogix_dp_device * dp)105 static int analogix_dp_panel_prepare(struct analogix_dp_device *dp)
106 {
107 int ret;
108
109 mutex_lock(&dp->panel_lock);
110
111 if (dp->panel_is_prepared)
112 goto out;
113
114 ret = drm_panel_prepare(dp->plat_data->panel);
115 if (ret)
116 goto out;
117
118 dp->panel_is_prepared = true;
119
120 out:
121 mutex_unlock(&dp->panel_lock);
122 return 0;
123 }
124
analogix_dp_panel_unprepare(struct analogix_dp_device * dp)125 static int analogix_dp_panel_unprepare(struct analogix_dp_device *dp)
126 {
127 int ret;
128
129 mutex_lock(&dp->panel_lock);
130
131 if (!dp->panel_is_prepared)
132 goto out;
133
134 ret = drm_panel_unprepare(dp->plat_data->panel);
135 if (ret)
136 goto out;
137
138 dp->panel_is_prepared = false;
139
140 out:
141 mutex_unlock(&dp->panel_lock);
142 return 0;
143 }
144
analogix_dp_detect_hpd(struct analogix_dp_device * dp)145 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
146 {
147 if (dp->force_hpd)
148 analogix_dp_force_hpd(dp);
149
150 if (analogix_dp_get_plug_in_status(dp) != 0) {
151 dev_err(dp->dev, "failed to get hpd plug in status\n");
152 return -EINVAL;
153 }
154
155 return 0;
156 }
157
analogix_dp_detect_sink_psr(struct analogix_dp_device * dp)158 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
159 {
160 unsigned char psr_version;
161 int ret;
162
163 if (!device_property_read_bool(dp->dev, "support-psr"))
164 return 0;
165
166 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
167 if (ret != 1) {
168 dev_err(dp->dev, "failed to get PSR version, disable it\n");
169 return false;
170 }
171
172 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
173 return psr_version & DP_PSR_IS_SUPPORTED;
174 }
175
analogix_dp_enable_sink_psr(struct analogix_dp_device * dp)176 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
177 {
178 unsigned char psr_en;
179 int ret;
180
181 /* Disable psr function */
182 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
183 if (ret != 1) {
184 dev_err(dp->dev, "failed to get psr config\n");
185 goto end;
186 }
187
188 psr_en &= ~DP_PSR_ENABLE;
189 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
190 if (ret != 1) {
191 dev_err(dp->dev, "failed to disable panel psr\n");
192 goto end;
193 }
194
195 /* Main-Link transmitter remains active during PSR active states */
196 psr_en = DP_PSR_CRC_VERIFICATION;
197 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
198 if (ret != 1) {
199 dev_err(dp->dev, "failed to set panel psr\n");
200 goto end;
201 }
202
203 /* Enable psr function */
204 psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
205 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
206 if (ret != 1) {
207 dev_err(dp->dev, "failed to set panel psr\n");
208 goto end;
209 }
210
211 analogix_dp_enable_psr_crc(dp);
212
213 dp->psr_supported = true;
214
215 return 0;
216 end:
217 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
218
219 return ret;
220 }
221
222 static int
analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device * dp,bool enable)223 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
224 bool enable)
225 {
226 u8 data;
227 int ret;
228
229 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
230 if (ret != 1)
231 return ret;
232
233 if (enable)
234 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
235 DP_LANE_COUNT_ENHANCED_FRAME_EN |
236 DPCD_LANE_COUNT_SET(data));
237 else
238 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
239 DPCD_LANE_COUNT_SET(data));
240
241 return ret < 0 ? ret : 0;
242 }
243
analogix_dp_is_enhanced_mode_available(struct analogix_dp_device * dp,u8 * enhanced_mode_support)244 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
245 u8 *enhanced_mode_support)
246 {
247 u8 data;
248 int ret;
249
250 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
251 if (ret != 1) {
252 *enhanced_mode_support = 0;
253 return ret;
254 }
255
256 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
257
258 return 0;
259 }
260
analogix_dp_set_enhanced_mode(struct analogix_dp_device * dp)261 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
262 {
263 u8 data;
264 int ret;
265
266 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
267 if (ret < 0)
268 return ret;
269
270 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
271 if (ret < 0)
272 return ret;
273
274 if (!data) {
275 /*
276 * A setting of 1 indicates that this is an eDP device that
277 * uses only Enhanced Framing, independently of the setting by
278 * the source of ENHANCED_FRAME_EN
279 */
280 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP,
281 &data);
282 if (ret < 0)
283 return ret;
284
285 data = !!(data & DP_FRAMING_CHANGE_CAP);
286 }
287
288 analogix_dp_enable_enhanced_mode(dp, data);
289
290 dp->link_train.enhanced_framing = data;
291
292 return 0;
293 }
294
analogix_dp_training_pattern_dis(struct analogix_dp_device * dp)295 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
296 {
297 int ret;
298
299 analogix_dp_set_training_pattern(dp, DP_NONE);
300
301 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
302 DP_TRAINING_PATTERN_DISABLE);
303
304 return ret < 0 ? ret : 0;
305 }
306
analogix_dp_get_vrr_capable(struct analogix_dp_device * dp)307 static bool analogix_dp_get_vrr_capable(struct analogix_dp_device *dp)
308 {
309 struct drm_connector *connector = &dp->connector;
310 struct drm_display_info *info = &connector->display_info;
311
312 if (!info->monitor_range.max_vfreq)
313 return false;
314 if (!info->monitor_range.min_vfreq)
315 return false;
316 if (info->monitor_range.max_vfreq < info->monitor_range.min_vfreq)
317 return false;
318 if (!drm_dp_sink_can_do_video_without_timing_msa(dp->dpcd))
319 return false;
320
321 return true;
322 }
323
analogix_dp_link_start(struct analogix_dp_device * dp)324 static int analogix_dp_link_start(struct analogix_dp_device *dp)
325 {
326 u8 buf[4];
327 int lane, lane_count, retval;
328
329 lane_count = dp->link_train.lane_count;
330
331 dp->link_train.lt_state = CLOCK_RECOVERY;
332 dp->link_train.eq_loop = 0;
333
334 for (lane = 0; lane < lane_count; lane++)
335 dp->link_train.cr_loop[lane] = 0;
336
337 /* Set link rate and count as you want to establish*/
338 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
339 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
340
341 /* Setup RX configuration */
342 buf[0] = dp->link_train.link_rate;
343 buf[1] = dp->link_train.lane_count;
344 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
345 if (retval < 0)
346 return retval;
347
348 /* Spread AMP if required, enable 8b/10b coding */
349 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0;
350 if (analogix_dp_get_vrr_capable(dp))
351 buf[0] |= DP_MSA_TIMING_PAR_IGNORE_EN;
352 buf[1] = DP_SET_ANSI_8B10B;
353 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2);
354 if (retval < 0)
355 return retval;
356
357 /* set enhanced mode if available */
358 retval = analogix_dp_set_enhanced_mode(dp);
359 if (retval < 0) {
360 dev_err(dp->dev, "failed to set enhance mode\n");
361 return retval;
362 }
363
364 /* Set TX voltage-swing and pre-emphasis to minimum */
365 for (lane = 0; lane < lane_count; lane++)
366 dp->link_train.training_lane[lane] =
367 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
368 DP_TRAIN_PRE_EMPH_LEVEL_0;
369 analogix_dp_set_lane_link_training(dp);
370
371 /* Set training pattern 1 */
372 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
373
374 /* Set RX training pattern */
375 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
376 DP_LINK_SCRAMBLING_DISABLE |
377 DP_TRAINING_PATTERN_1);
378 if (retval < 0)
379 return retval;
380
381 for (lane = 0; lane < lane_count; lane++)
382 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
383 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
384
385 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
386 lane_count);
387 if (retval < 0)
388 return retval;
389
390 return 0;
391 }
392
analogix_dp_get_lane_status(u8 link_status[2],int lane)393 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
394 {
395 int shift = (lane & 1) * 4;
396 u8 link_value = link_status[lane >> 1];
397
398 return (link_value >> shift) & 0xf;
399 }
400
analogix_dp_clock_recovery_ok(u8 link_status[2],int lane_count)401 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
402 {
403 int lane;
404 u8 lane_status;
405
406 for (lane = 0; lane < lane_count; lane++) {
407 lane_status = analogix_dp_get_lane_status(link_status, lane);
408 if ((lane_status & DP_LANE_CR_DONE) == 0)
409 return -EINVAL;
410 }
411 return 0;
412 }
413
analogix_dp_channel_eq_ok(u8 link_status[2],u8 link_align,int lane_count)414 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
415 int lane_count)
416 {
417 int lane;
418 u8 lane_status;
419
420 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
421 return -EINVAL;
422
423 for (lane = 0; lane < lane_count; lane++) {
424 lane_status = analogix_dp_get_lane_status(link_status, lane);
425 lane_status &= DP_CHANNEL_EQ_BITS;
426 if (lane_status != DP_CHANNEL_EQ_BITS)
427 return -EINVAL;
428 }
429
430 return 0;
431 }
432
433 static unsigned char
analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],int lane)434 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
435 {
436 int shift = (lane & 1) * 4;
437 u8 link_value = adjust_request[lane >> 1];
438
439 return (link_value >> shift) & 0x3;
440 }
441
analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[2],int lane)442 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
443 u8 adjust_request[2],
444 int lane)
445 {
446 int shift = (lane & 1) * 4;
447 u8 link_value = adjust_request[lane >> 1];
448
449 return ((link_value >> shift) & 0xc) >> 2;
450 }
451
analogix_dp_reduce_link_rate(struct analogix_dp_device * dp)452 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
453 {
454 analogix_dp_training_pattern_dis(dp);
455 analogix_dp_set_enhanced_mode(dp);
456
457 dp->link_train.lt_state = FAILED;
458 }
459
analogix_dp_get_adjust_training_lane(struct analogix_dp_device * dp,u8 adjust_request[2])460 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
461 u8 adjust_request[2])
462 {
463 int lane, lane_count;
464 u8 voltage_swing, pre_emphasis, training_lane;
465
466 lane_count = dp->link_train.lane_count;
467 for (lane = 0; lane < lane_count; lane++) {
468 voltage_swing = analogix_dp_get_adjust_request_voltage(
469 adjust_request, lane);
470 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
471 adjust_request, lane);
472 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
473 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
474
475 if (voltage_swing == VOLTAGE_LEVEL_3)
476 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
477 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
478 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
479
480 dp->link_train.training_lane[lane] = training_lane;
481 }
482 }
483
analogix_dp_tps3_supported(struct analogix_dp_device * dp)484 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp)
485 {
486 bool source_tps3_supported, sink_tps3_supported;
487 u8 dpcd = 0;
488
489 source_tps3_supported =
490 dp->video_info.max_link_rate == DP_LINK_BW_5_4;
491 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd);
492 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED;
493
494 return source_tps3_supported && sink_tps3_supported;
495 }
496
analogix_dp_process_clock_recovery(struct analogix_dp_device * dp)497 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
498 {
499 int lane, lane_count, retval;
500 u8 voltage_swing, pre_emphasis, training_lane;
501 u8 link_status[2], adjust_request[2];
502 u8 training_pattern = TRAINING_PTN2;
503
504 drm_dp_link_train_clock_recovery_delay(dp->dpcd);
505
506 lane_count = dp->link_train.lane_count;
507
508 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
509 if (retval < 0)
510 return retval;
511
512 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
513 if (analogix_dp_tps3_supported(dp))
514 training_pattern = TRAINING_PTN3;
515
516 /* set training pattern for EQ */
517 analogix_dp_set_training_pattern(dp, training_pattern);
518
519 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
520 DP_LINK_SCRAMBLING_DISABLE |
521 (training_pattern == TRAINING_PTN3 ?
522 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2));
523 if (retval < 0)
524 return retval;
525
526 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
527 dp->link_train.lt_state = EQUALIZER_TRAINING;
528
529 return 0;
530 } else {
531 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
532 adjust_request, 2);
533 if (retval < 0)
534 return retval;
535
536 for (lane = 0; lane < lane_count; lane++) {
537 training_lane = analogix_dp_get_lane_link_training(
538 dp, lane);
539 voltage_swing = analogix_dp_get_adjust_request_voltage(
540 adjust_request, lane);
541 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
542 adjust_request, lane);
543
544 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
545 voltage_swing &&
546 DPCD_PRE_EMPHASIS_GET(training_lane) ==
547 pre_emphasis)
548 dp->link_train.cr_loop[lane]++;
549
550 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
551 voltage_swing == VOLTAGE_LEVEL_3 ||
552 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
553 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
554 dp->link_train.cr_loop[lane],
555 voltage_swing, pre_emphasis);
556 analogix_dp_reduce_link_rate(dp);
557 return -EIO;
558 }
559 }
560 }
561
562 analogix_dp_get_adjust_training_lane(dp, adjust_request);
563 analogix_dp_set_lane_link_training(dp);
564
565 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
566 dp->link_train.training_lane, lane_count);
567 if (retval < 0)
568 return retval;
569
570 return 0;
571 }
572
analogix_dp_process_equalizer_training(struct analogix_dp_device * dp)573 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
574 {
575 int lane_count, retval;
576 u32 reg;
577 u8 link_align, link_status[2], adjust_request[2];
578
579 drm_dp_link_train_channel_eq_delay(dp->dpcd);
580
581 lane_count = dp->link_train.lane_count;
582
583 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
584 if (retval < 0)
585 return retval;
586
587 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
588 analogix_dp_reduce_link_rate(dp);
589 return -EIO;
590 }
591
592 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
593 &link_align);
594 if (retval < 0)
595 return retval;
596
597 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
598 /* traing pattern Set to Normal */
599 retval = analogix_dp_training_pattern_dis(dp);
600 if (retval < 0)
601 return retval;
602
603 dev_dbg(dp->dev, "Link Training success!\n");
604 analogix_dp_get_link_bandwidth(dp, ®);
605 dp->link_train.link_rate = reg;
606 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
607 dp->link_train.link_rate);
608
609 analogix_dp_get_lane_count(dp, ®);
610 dp->link_train.lane_count = reg;
611 dev_dbg(dp->dev, "final lane count = %.2x\n",
612 dp->link_train.lane_count);
613
614 dp->link_train.lt_state = FINISHED;
615
616 return 0;
617 }
618
619 /* not all locked */
620 dp->link_train.eq_loop++;
621
622 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
623 dev_err(dp->dev, "EQ Max loop\n");
624 analogix_dp_reduce_link_rate(dp);
625 return -EIO;
626 }
627
628 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
629 adjust_request, 2);
630 if (retval < 0)
631 return retval;
632
633 analogix_dp_get_adjust_training_lane(dp, adjust_request);
634 analogix_dp_set_lane_link_training(dp);
635
636 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
637 dp->link_train.training_lane, lane_count);
638 if (retval < 0)
639 return retval;
640
641 return 0;
642 }
643
analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device * dp,u8 * bandwidth)644 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
645 u8 *bandwidth)
646 {
647 u8 data;
648 int ret;
649
650 /*
651 * For DP rev.1.1, Maximum link rate of Main Link lanes
652 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
653 * For DP rev.1.2, Maximum link rate of Main Link lanes
654 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
655 */
656 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
657 if (ret < 0)
658 return ret;
659
660 *bandwidth = data;
661
662 return 0;
663 }
664
analogix_dp_get_max_rx_lane_count(struct analogix_dp_device * dp,u8 * lane_count)665 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
666 u8 *lane_count)
667 {
668 u8 data;
669 int ret;
670
671 /*
672 * For DP rev.1.1, Maximum number of Main Link lanes
673 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
674 */
675 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
676 if (ret < 0)
677 return ret;
678
679 *lane_count = DPCD_MAX_LANE_COUNT(data);
680
681 return 0;
682 }
683
analogix_dp_full_link_train(struct analogix_dp_device * dp,u32 max_lanes,u32 max_rate)684 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
685 u32 max_lanes, u32 max_rate)
686 {
687 struct video_info *video = &dp->video_info;
688 int retval = 0;
689 bool training_finished = false;
690 u8 dpcd;
691
692 /*
693 * MACRO_RST must be applied after the PLL_LOCK to avoid
694 * the DP inter pair skew issue for at least 10 us
695 */
696 analogix_dp_reset_macro(dp);
697
698 /* Initialize by reading RX's DPCD */
699 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
700 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
701
702 /* Setup TX lane count & rate */
703 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lanes);
704 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, max_rate);
705
706 if (!analogix_dp_bandwidth_ok(dp, &video->mode,
707 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate),
708 dp->link_train.lane_count)) {
709 dev_err(dp->dev, "bandwidth overflow\n");
710 return -EINVAL;
711 }
712
713 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd);
714 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);
715
716 /* All DP analog module power up */
717 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
718
719 dp->link_train.lt_state = START;
720
721 /* Process here */
722 while (!retval && !training_finished) {
723 switch (dp->link_train.lt_state) {
724 case START:
725 retval = analogix_dp_link_start(dp);
726 if (retval)
727 dev_err(dp->dev, "LT link start failed!\n");
728 break;
729 case CLOCK_RECOVERY:
730 retval = analogix_dp_process_clock_recovery(dp);
731 if (retval)
732 dev_err(dp->dev, "LT CR failed!\n");
733 break;
734 case EQUALIZER_TRAINING:
735 retval = analogix_dp_process_equalizer_training(dp);
736 if (retval)
737 dev_err(dp->dev, "LT EQ failed!\n");
738 break;
739 case FINISHED:
740 training_finished = 1;
741 break;
742 case FAILED:
743 return -EREMOTEIO;
744 }
745 }
746 if (retval)
747 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
748
749 return retval;
750 }
751
analogix_dp_fast_link_train(struct analogix_dp_device * dp)752 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
753 {
754 int ret;
755 u8 link_align, link_status[2];
756
757 analogix_dp_reset_macro(dp);
758
759 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
760 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
761 analogix_dp_set_lane_link_training(dp);
762 analogix_dp_enable_enhanced_mode(dp, dp->link_train.enhanced_framing);
763
764 /* source Set training pattern 1 */
765 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
766 /* From DP spec, pattern must be on-screen for a minimum 500us */
767 usleep_range(500, 600);
768
769 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
770 /* From DP spec, pattern must be on-screen for a minimum 500us */
771 usleep_range(500, 600);
772
773 analogix_dp_set_training_pattern(dp, DP_NONE);
774
775 /*
776 * Useful for debugging issues with fast link training, disable for more
777 * speed
778 */
779 if (verify_fast_training) {
780 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
781 &link_align);
782 if (ret < 0) {
783 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
784 ret);
785 return ret;
786 }
787
788 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
789 2);
790 if (ret < 0) {
791 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
792 ret);
793 return ret;
794 }
795
796 if (analogix_dp_clock_recovery_ok(link_status,
797 dp->link_train.lane_count)) {
798 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
799 analogix_dp_reduce_link_rate(dp);
800 return -EIO;
801 }
802
803 if (analogix_dp_channel_eq_ok(link_status, link_align,
804 dp->link_train.lane_count)) {
805 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
806 analogix_dp_reduce_link_rate(dp);
807 return -EIO;
808 }
809 }
810
811 return 0;
812 }
813
analogix_dp_train_link(struct analogix_dp_device * dp)814 static int analogix_dp_train_link(struct analogix_dp_device *dp)
815 {
816 if (dp->fast_train_enable)
817 return analogix_dp_fast_link_train(dp);
818
819 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
820 dp->video_info.max_link_rate);
821 }
822
analogix_dp_config_video(struct analogix_dp_device * dp)823 static int analogix_dp_config_video(struct analogix_dp_device *dp)
824 {
825 int timeout_loop = 0;
826 int done_count = 0;
827
828 analogix_dp_config_video_slave_mode(dp);
829
830 analogix_dp_set_video_color_format(dp);
831
832 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
833 dev_err(dp->dev, "PLL is not locked yet.\n");
834 return -EINVAL;
835 }
836
837 for (;;) {
838 timeout_loop++;
839 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
840 break;
841 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
842 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
843 return -ETIMEDOUT;
844 }
845 usleep_range(1000, 1001);
846 }
847
848 /* Set to use the register calculated M/N video */
849 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
850
851 /* For video bist, Video timing must be generated by register */
852 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER);
853
854 /* Disable video mute */
855 analogix_dp_enable_video_mute(dp, 0);
856
857 /* Configure video slave mode */
858 analogix_dp_enable_video_master(dp, 0);
859
860 /* Enable video */
861 analogix_dp_start_video(dp);
862
863 timeout_loop = 0;
864
865 for (;;) {
866 timeout_loop++;
867 if (analogix_dp_is_video_stream_on(dp) == 0) {
868 done_count++;
869 if (done_count > 10)
870 break;
871 } else if (done_count) {
872 done_count = 0;
873 }
874 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
875 dev_warn(dp->dev,
876 "Ignoring timeout of video streamclk ok\n");
877 break;
878 }
879
880 usleep_range(1000, 1001);
881 }
882
883 return 0;
884 }
885
analogix_dp_enable_scramble(struct analogix_dp_device * dp,bool enable)886 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
887 bool enable)
888 {
889 u8 data;
890 int ret;
891
892 if (enable) {
893 analogix_dp_enable_scrambling(dp);
894
895 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
896 &data);
897 if (ret != 1)
898 return ret;
899 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
900 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
901 } else {
902 analogix_dp_disable_scrambling(dp);
903
904 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
905 &data);
906 if (ret != 1)
907 return ret;
908 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
909 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
910 }
911 return ret < 0 ? ret : 0;
912 }
913
analogix_dp_autotest_phy_pattern(struct analogix_dp_device * dp)914 static u8 analogix_dp_autotest_phy_pattern(struct analogix_dp_device *dp)
915 {
916 struct drm_dp_phy_test_params *data = &dp->compliance.phytest;
917
918 if (drm_dp_get_phy_test_pattern(&dp->aux, data)) {
919 dev_err(dp->dev, "DP Phy Test pattern AUX read failure\n");
920 return DP_TEST_NAK;
921 }
922
923 if (data->link_rate > drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) {
924 dev_err(dp->dev, "invalid link rate = 0x%x\n", data->link_rate);
925 return DP_TEST_NAK;
926 }
927
928 /* Set test active flag here so userspace doesn't interrupt things */
929 dp->compliance.test_active = true;
930
931 return DP_TEST_ACK;
932 }
933
analogix_dp_handle_test_request(struct analogix_dp_device * dp)934 static void analogix_dp_handle_test_request(struct analogix_dp_device *dp)
935 {
936 u8 response = DP_TEST_NAK;
937 u8 request = 0;
938 int ret;
939
940 ret = drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &request);
941 if (ret < 0) {
942 dev_err(dp->dev, "Could not read test request from sink\n");
943 goto update_status;
944 }
945
946 switch (request) {
947 case DP_TEST_LINK_PHY_TEST_PATTERN:
948 dev_info(dp->dev, "PHY_PATTERN test requested\n");
949 response = analogix_dp_autotest_phy_pattern(dp);
950 break;
951 default:
952 dev_err(dp->dev, "Invalid test request '%02x'\n", request);
953 break;
954 }
955
956 if (response & DP_TEST_ACK)
957 dp->compliance.test_type = request;
958
959 update_status:
960 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, response);
961 if (ret < 0)
962 dev_err(dp->dev, "Could not write test response to sink\n");
963 }
964
analogix_dp_check_device_service_irq(struct analogix_dp_device * dp)965 void analogix_dp_check_device_service_irq(struct analogix_dp_device *dp)
966 {
967 u8 val;
968 int ret;
969
970 ret = drm_dp_dpcd_readb(&dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, &val);
971 if (ret < 0 || !val)
972 return;
973
974 ret = drm_dp_dpcd_writeb(&dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
975 if (ret < 0)
976 return;
977
978 if (val & DP_AUTOMATED_TEST_REQUEST)
979 analogix_dp_handle_test_request(dp);
980 }
981 EXPORT_SYMBOL_GPL(analogix_dp_check_device_service_irq);
982
analogix_dp_process_phy_request(struct analogix_dp_device * dp)983 static void analogix_dp_process_phy_request(struct analogix_dp_device *dp)
984 {
985 struct drm_dp_phy_test_params *data = &dp->compliance.phytest;
986 u8 spread, adjust_request[2];
987 int ret;
988
989 dp->link_train.link_rate = drm_dp_link_rate_to_bw_code(data->link_rate);
990 dp->link_train.lane_count = data->num_lanes;
991
992 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
993 if (ret < 0) {
994 dev_err(dp->dev, "Could not read ssc from sink\n");
995 return;
996 }
997
998 dp->link_train.ssc = !!(spread & DP_MAX_DOWNSPREAD_0_5);
999
1000 ret = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
1001 adjust_request, 2);
1002 if (ret < 0) {
1003 dev_err(dp->dev, "Could not read swing/pre-emphasis\n");
1004 return;
1005 }
1006
1007 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
1008 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
1009 analogix_dp_get_adjust_training_lane(dp, adjust_request);
1010 analogix_dp_set_lane_link_training(dp);
1011
1012 switch (data->phy_pattern) {
1013 case DP_PHY_TEST_PATTERN_NONE:
1014 dev_info(dp->dev, "Disable Phy Test Pattern\n");
1015 analogix_dp_set_training_pattern(dp, DP_NONE);
1016 break;
1017 case DP_PHY_TEST_PATTERN_D10_2:
1018 dev_info(dp->dev, "Set D10.2 Phy Test Pattern\n");
1019 analogix_dp_set_training_pattern(dp, D10_2);
1020 break;
1021 case DP_PHY_TEST_PATTERN_PRBS7:
1022 dev_info(dp->dev, "Set PRBS7 Phy Test Pattern\n");
1023 analogix_dp_set_training_pattern(dp, PRBS7);
1024 break;
1025 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
1026 dev_info(dp->dev, "Set 80Bit Custom Phy Test Pattern\n");
1027 analogix_dp_set_training_pattern(dp, TEST_PATTERN_80BIT);
1028 break;
1029 case DP_PHY_TEST_PATTERN_CP2520:
1030 dev_info(dp->dev, "Set HBR2 compliance Phy Test Pattern\n");
1031 analogix_dp_set_training_pattern(dp, TEST_PATTERN_HBR2);
1032 break;
1033 default:
1034 dev_err(dp->dev, "Invalid Phy Test Pattern: %d\n", data->phy_pattern);
1035 return;
1036 }
1037
1038 drm_dp_set_phy_test_pattern(&dp->aux, data, 0x11);
1039 }
1040
analogix_dp_phy_test(struct analogix_dp_device * dp)1041 void analogix_dp_phy_test(struct analogix_dp_device *dp)
1042 {
1043 struct drm_device *dev = dp->drm_dev;
1044 struct drm_modeset_acquire_ctx ctx;
1045 int ret;
1046
1047 DRM_DEV_INFO(dp->dev, "PHY test\n");
1048
1049 drm_modeset_acquire_init(&ctx, 0);
1050 for (;;) {
1051 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1052 if (ret != -EDEADLK)
1053 break;
1054
1055 drm_modeset_backoff(&ctx);
1056 }
1057
1058 analogix_dp_process_phy_request(dp);
1059 drm_modeset_drop_locks(&ctx);
1060 drm_modeset_acquire_fini(&ctx);
1061 }
1062 EXPORT_SYMBOL_GPL(analogix_dp_phy_test);
1063
analogix_dp_hpd_irq_handler(int irq,void * arg)1064 static irqreturn_t analogix_dp_hpd_irq_handler(int irq, void *arg)
1065 {
1066 struct analogix_dp_device *dp = arg;
1067
1068 if (dp->drm_dev)
1069 drm_helper_hpd_irq_event(dp->drm_dev);
1070
1071 return IRQ_HANDLED;
1072 }
1073
analogix_dp_irq_thread(int irq,void * arg)1074 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
1075 {
1076 struct analogix_dp_device *dp = arg;
1077
1078 analogix_dp_irq_handler(dp);
1079
1080 return IRQ_HANDLED;
1081 }
1082
analogix_dp_fast_link_train_detection(struct analogix_dp_device * dp)1083 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
1084 {
1085 int ret;
1086 u8 spread;
1087
1088 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
1089 if (ret != 1) {
1090 dev_err(dp->dev, "failed to read downspread %d\n", ret);
1091 return ret;
1092 }
1093 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1094 dev_dbg(dp->dev, "fast link training %s\n",
1095 dp->fast_train_enable ? "supported" : "unsupported");
1096 return 0;
1097 }
1098
analogix_dp_link_power_up(struct analogix_dp_device * dp)1099 static int analogix_dp_link_power_up(struct analogix_dp_device *dp)
1100 {
1101 u8 value;
1102 int ret;
1103
1104 if (dp->dpcd[DP_DPCD_REV] < 0x11)
1105 return 0;
1106
1107 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
1108 if (ret < 0)
1109 return ret;
1110
1111 value &= ~DP_SET_POWER_MASK;
1112 value |= DP_SET_POWER_D0;
1113
1114 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
1115 if (ret < 0)
1116 return ret;
1117
1118 usleep_range(1000, 2000);
1119
1120 return 0;
1121 }
1122
analogix_dp_link_power_down(struct analogix_dp_device * dp)1123 static int analogix_dp_link_power_down(struct analogix_dp_device *dp)
1124 {
1125 u8 value;
1126 int ret;
1127
1128 if (dp->dpcd[DP_DPCD_REV] < 0x11)
1129 return 0;
1130
1131 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
1132 if (ret < 0)
1133 return ret;
1134
1135 value &= ~DP_SET_POWER_MASK;
1136 value |= DP_SET_POWER_D3;
1137
1138 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
1139 if (ret < 0)
1140 return ret;
1141
1142 return 0;
1143 }
1144
analogix_dp_commit(struct analogix_dp_device * dp)1145 static int analogix_dp_commit(struct analogix_dp_device *dp)
1146 {
1147 struct video_info *video = &dp->video_info;
1148 int ret;
1149
1150 ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd);
1151 if (ret < 0) {
1152 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret);
1153 return ret;
1154 }
1155
1156 ret = analogix_dp_link_power_up(dp);
1157 if (ret) {
1158 dev_err(dp->dev, "failed to power up link: %d\n", ret);
1159 return ret;
1160 }
1161
1162 if (device_property_read_bool(dp->dev, "panel-self-test"))
1163 return drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET,
1164 DP_PANEL_SELF_TEST_ENABLE);
1165
1166 ret = analogix_dp_train_link(dp);
1167 if (ret) {
1168 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
1169 return ret;
1170 }
1171
1172 ret = analogix_dp_enable_scramble(dp, 1);
1173 if (ret < 0) {
1174 dev_err(dp->dev, "can not enable scramble\n");
1175 return ret;
1176 }
1177
1178 analogix_dp_init_video(dp);
1179 analogix_dp_set_video_format(dp);
1180
1181 if (video->video_bist_enable)
1182 analogix_dp_video_bist_enable(dp);
1183
1184 ret = analogix_dp_config_video(dp);
1185 if (ret) {
1186 dev_err(dp->dev, "unable to config video\n");
1187 return ret;
1188 }
1189
1190 /* Check whether panel supports fast training */
1191 ret = analogix_dp_fast_link_train_detection(dp);
1192 if (ret)
1193 return ret;
1194
1195 if (analogix_dp_detect_sink_psr(dp)) {
1196 ret = analogix_dp_enable_sink_psr(dp);
1197 if (ret)
1198 return ret;
1199 }
1200
1201 return ret;
1202 }
1203
analogix_dp_enable_psr(struct analogix_dp_device * dp)1204 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
1205 {
1206 struct dp_sdp psr_vsc;
1207 int ret;
1208 u8 sink;
1209
1210 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1211 if (ret != 1)
1212 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1213 else if (sink == DP_PSR_SINK_ACTIVE_RFB)
1214 return 0;
1215
1216 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1217 memset(&psr_vsc, 0, sizeof(psr_vsc));
1218 psr_vsc.sdp_header.HB0 = 0;
1219 psr_vsc.sdp_header.HB1 = 0x7;
1220 psr_vsc.sdp_header.HB2 = 0x2;
1221 psr_vsc.sdp_header.HB3 = 0x8;
1222 psr_vsc.db[0] = 0;
1223 psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1224
1225 ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1226 if (!ret) {
1227 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1228
1229 if (dp->phy) {
1230 union phy_configure_opts phy_cfg = {0};
1231
1232 phy_cfg.dp.lanes = 0;
1233 phy_cfg.dp.set_lanes = true;
1234 ret = phy_configure(dp->phy, &phy_cfg);
1235 if (ret)
1236 return ret;
1237 }
1238 }
1239
1240 return ret;
1241 }
1242
analogix_dp_disable_psr(struct analogix_dp_device * dp)1243 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1244 {
1245 struct dp_sdp psr_vsc;
1246 int ret;
1247 u8 sink;
1248
1249 analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1250
1251 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1252 if (ret != 1) {
1253 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1254 return ret;
1255 }
1256
1257 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1258 if (ret != 1) {
1259 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1260 return ret;
1261 } else if (sink == DP_PSR_SINK_INACTIVE) {
1262 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1263 return 0;
1264 }
1265
1266 ret = analogix_dp_train_link(dp);
1267 if (ret) {
1268 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1269 return ret;
1270 }
1271
1272 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1273 memset(&psr_vsc, 0, sizeof(psr_vsc));
1274 psr_vsc.sdp_header.HB0 = 0;
1275 psr_vsc.sdp_header.HB1 = 0x7;
1276 psr_vsc.sdp_header.HB2 = 0x2;
1277 psr_vsc.sdp_header.HB3 = 0x8;
1278
1279 psr_vsc.db[0] = 0;
1280 psr_vsc.db[1] = 0;
1281
1282 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1283 }
1284
analogix_dp_get_modes(struct drm_connector * connector)1285 static int analogix_dp_get_modes(struct drm_connector *connector)
1286 {
1287 struct analogix_dp_device *dp = to_dp(connector);
1288 struct edid *edid;
1289 int ret, num_modes = 0;
1290
1291 if (dp->plat_data->right && dp->plat_data->right->plat_data->bridge) {
1292 struct drm_bridge *bridge = dp->plat_data->right->plat_data->bridge;
1293
1294 if (bridge->ops & DRM_BRIDGE_OP_MODES) {
1295 if (!drm_bridge_get_modes(bridge, connector))
1296 return 0;
1297 }
1298 }
1299
1300 if (dp->plat_data->panel)
1301 num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1302
1303 if (dp->plat_data->bridge)
1304 num_modes += drm_bridge_get_modes(dp->plat_data->bridge, connector);
1305
1306 if (!num_modes) {
1307 ret = analogix_dp_phy_power_on(dp);
1308 if (ret)
1309 return 0;
1310
1311 if (dp->plat_data->panel)
1312 analogix_dp_panel_prepare(dp);
1313
1314 edid = drm_get_edid(connector, &dp->aux.ddc);
1315 if (edid) {
1316 drm_connector_update_edid_property(&dp->connector,
1317 edid);
1318 num_modes += drm_add_edid_modes(&dp->connector, edid);
1319 kfree(edid);
1320 }
1321
1322 analogix_dp_phy_power_off(dp);
1323 }
1324
1325 if (dp->plat_data->get_modes)
1326 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1327
1328 if (num_modes > 0 && dp->plat_data->split_mode) {
1329 struct drm_display_mode *mode;
1330
1331 list_for_each_entry(mode, &connector->probed_modes, head)
1332 dp->plat_data->convert_to_split_mode(mode);
1333 }
1334
1335 return num_modes;
1336 }
1337
1338 static struct drm_encoder *
analogix_dp_best_encoder(struct drm_connector * connector)1339 analogix_dp_best_encoder(struct drm_connector *connector)
1340 {
1341 struct analogix_dp_device *dp = to_dp(connector);
1342
1343 return dp->encoder;
1344 }
1345
1346
analogix_dp_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1347 static int analogix_dp_atomic_check(struct drm_connector *connector,
1348 struct drm_atomic_state *state)
1349 {
1350 struct analogix_dp_device *dp = to_dp(connector);
1351 struct drm_connector_state *conn_state;
1352 struct drm_crtc_state *crtc_state;
1353
1354 conn_state = drm_atomic_get_new_connector_state(state, connector);
1355 if (WARN_ON(!conn_state))
1356 return -ENODEV;
1357
1358 conn_state->self_refresh_aware = true;
1359
1360 if (!conn_state->crtc)
1361 return 0;
1362
1363 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1364 if (!crtc_state)
1365 return 0;
1366
1367 if (crtc_state->self_refresh_active && !dp->psr_supported)
1368 return -EINVAL;
1369
1370 return 0;
1371 }
1372
1373 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1374 .get_modes = analogix_dp_get_modes,
1375 .best_encoder = analogix_dp_best_encoder,
1376 .atomic_check = analogix_dp_atomic_check,
1377 };
1378
1379 static enum drm_connector_status
analogix_dp_detect(struct analogix_dp_device * dp)1380 analogix_dp_detect(struct analogix_dp_device *dp)
1381 {
1382 enum drm_connector_status status = connector_status_disconnected;
1383 int ret;
1384
1385 ret = analogix_dp_phy_power_on(dp);
1386 if (ret) {
1387 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
1388 return connector_status_disconnected;
1389 }
1390
1391 if (dp->plat_data->panel)
1392 analogix_dp_panel_prepare(dp);
1393
1394 if (!analogix_dp_detect_hpd(dp)) {
1395 ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
1396 if (ret) {
1397 dev_err(dp->dev, "failed to read max link rate\n");
1398 goto out;
1399 }
1400
1401 ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
1402 if (ret) {
1403 dev_err(dp->dev, "failed to read max lane count\n");
1404 goto out;
1405 }
1406
1407 status = connector_status_connected;
1408 }
1409
1410 if (dp->plat_data->bridge) {
1411 struct drm_bridge *next_bridge = dp->plat_data->bridge;
1412
1413 if (next_bridge->ops & DRM_BRIDGE_OP_DETECT)
1414 status = drm_bridge_detect(next_bridge);
1415 }
1416
1417 out:
1418 analogix_dp_phy_power_off(dp);
1419
1420 if (status == connector_status_connected)
1421 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
1422 else
1423 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
1424
1425 return status;
1426 }
1427
1428 static enum drm_connector_status
analogix_dp_connector_detect(struct drm_connector * connector,bool force)1429 analogix_dp_connector_detect(struct drm_connector *connector, bool force)
1430 {
1431 struct analogix_dp_device *dp = to_dp(connector);
1432
1433 if (dp->plat_data->right && analogix_dp_detect(dp->plat_data->right) != connector_status_connected)
1434 return connector_status_disconnected;
1435
1436 return analogix_dp_detect(dp);
1437 }
1438
analogix_dp_connector_force(struct drm_connector * connector)1439 static void analogix_dp_connector_force(struct drm_connector *connector)
1440 {
1441 struct analogix_dp_device *dp = to_dp(connector);
1442
1443 if (connector->status == connector_status_connected)
1444 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
1445 else
1446 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
1447 }
1448
1449 static int
analogix_dp_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1450 analogix_dp_atomic_connector_get_property(struct drm_connector *connector,
1451 const struct drm_connector_state *state,
1452 struct drm_property *property,
1453 uint64_t *val)
1454 {
1455 struct rockchip_drm_private *private = connector->dev->dev_private;
1456 struct analogix_dp_device *dp = to_dp(connector);
1457
1458 if (property == private->split_area_prop) {
1459 switch (dp->split_area) {
1460 case 1:
1461 *val = ROCKCHIP_DRM_SPLIT_LEFT_SIDE;
1462 break;
1463 case 2:
1464 *val = ROCKCHIP_DRM_SPLIT_RIGHT_SIDE;
1465 break;
1466 default:
1467 *val = ROCKCHIP_DRM_SPLIT_UNSET;
1468 break;
1469 }
1470 }
1471
1472 return 0;
1473 }
1474
1475 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1476 .fill_modes = drm_helper_probe_single_connector_modes,
1477 .detect = analogix_dp_connector_detect,
1478 .destroy = drm_connector_cleanup,
1479 .reset = drm_atomic_helper_connector_reset,
1480 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1481 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1482 .force = analogix_dp_connector_force,
1483 .atomic_get_property = analogix_dp_atomic_connector_get_property,
1484 };
1485
analogix_dp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1486 static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1487 enum drm_bridge_attach_flags flags)
1488 {
1489 struct analogix_dp_device *dp = bridge->driver_private;
1490 struct drm_encoder *encoder = dp->encoder;
1491 struct drm_connector *connector = NULL;
1492 int ret = 0;
1493
1494 if (!bridge->encoder) {
1495 DRM_ERROR("Parent encoder object not found");
1496 return -ENODEV;
1497 }
1498
1499 if (dp->plat_data->bridge) {
1500 ret = drm_bridge_attach(bridge->encoder, dp->plat_data->bridge, bridge,
1501 dp->plat_data->skip_connector ?
1502 0 : DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1503 if (ret) {
1504 DRM_ERROR("Failed to attach external bridge: %d\n", ret);
1505 return ret;
1506 }
1507 }
1508
1509 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1510 return 0;
1511
1512 if (!dp->plat_data->skip_connector) {
1513 int connector_type = DRM_MODE_CONNECTOR_eDP;
1514 struct rockchip_drm_private *private;
1515
1516 if (dp->plat_data->bridge &&
1517 dp->plat_data->bridge->type != DRM_MODE_CONNECTOR_Unknown)
1518 connector_type = dp->plat_data->bridge->type;
1519
1520 connector = &dp->connector;
1521 connector->polled = DRM_CONNECTOR_POLL_HPD;
1522 if (dp->plat_data->bridge && dp->plat_data->bridge->ops & DRM_BRIDGE_OP_DETECT)
1523 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1524 DRM_CONNECTOR_POLL_DISCONNECT;
1525
1526 ret = drm_connector_init(dp->drm_dev, connector,
1527 &analogix_dp_connector_funcs,
1528 connector_type);
1529 if (ret) {
1530 DRM_ERROR("Failed to initialize connector with drm\n");
1531 return ret;
1532 }
1533
1534 private = connector->dev->dev_private;
1535
1536 if (dp->split_area)
1537 drm_object_attach_property(&connector->base,
1538 private->split_area_prop,
1539 dp->split_area);
1540
1541 drm_connector_helper_add(connector,
1542 &analogix_dp_connector_helper_funcs);
1543 drm_connector_attach_encoder(connector, encoder);
1544 }
1545
1546 /*
1547 * NOTE: the connector registration is implemented in analogix
1548 * platform driver, that to say connector would be exist after
1549 * plat_data->attch return, that's why we record the connector
1550 * point after plat attached.
1551 */
1552 if (dp->plat_data->attach) {
1553 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1554 if (ret) {
1555 DRM_ERROR("Failed at platform attach func\n");
1556 return ret;
1557 }
1558 }
1559
1560 return 0;
1561 }
1562
analogix_dp_bridge_detach(struct drm_bridge * bridge)1563 static void analogix_dp_bridge_detach(struct drm_bridge *bridge)
1564 {
1565 struct analogix_dp_device *dp = bridge->driver_private;
1566
1567 if (dp->plat_data->detach)
1568 dp->plat_data->detach(dp->plat_data, bridge);
1569 }
1570
1571 static
analogix_dp_get_old_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1572 struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp,
1573 struct drm_atomic_state *state)
1574 {
1575 struct drm_encoder *encoder = dp->encoder;
1576 struct drm_connector *connector;
1577 struct drm_connector_state *conn_state;
1578
1579 connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1580 if (!connector)
1581 return NULL;
1582
1583 conn_state = drm_atomic_get_old_connector_state(state, connector);
1584 if (!conn_state)
1585 return NULL;
1586
1587 return conn_state->crtc;
1588 }
1589
1590 static
analogix_dp_get_new_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1591 struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1592 struct drm_atomic_state *state)
1593 {
1594 struct drm_bridge *bridge = &dp->bridge;
1595 struct drm_encoder *encoder = bridge->encoder;
1596 struct drm_connector *connector;
1597 struct drm_connector_state *conn_state;
1598
1599 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1600 if (!connector)
1601 return NULL;
1602
1603 conn_state = drm_atomic_get_new_connector_state(state, connector);
1604 if (!conn_state)
1605 return NULL;
1606
1607 return conn_state->crtc;
1608 }
1609
1610 static void
analogix_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1611 analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1612 struct drm_bridge_state *old_bridge_state)
1613 {
1614 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1615 struct analogix_dp_device *dp = bridge->driver_private;
1616 struct drm_crtc *crtc;
1617 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1618
1619 crtc = analogix_dp_get_new_crtc(dp, old_state);
1620 if (!crtc)
1621 return;
1622
1623 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1624
1625 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1626 analogix_dp_bridge_mode_set(bridge, &new_crtc_state->adjusted_mode);
1627
1628 /* Don't touch the panel if we're coming back from PSR */
1629 if (old_crtc_state && old_crtc_state->self_refresh_active)
1630 return;
1631
1632 if (dp->plat_data->panel)
1633 analogix_dp_panel_prepare(dp);
1634 }
1635
analogix_dp_set_bridge(struct analogix_dp_device * dp)1636 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1637 {
1638 int ret;
1639
1640 if (dp->plat_data->power_on_start)
1641 dp->plat_data->power_on_start(dp->plat_data);
1642
1643 ret = analogix_dp_phy_power_on(dp);
1644 if (ret)
1645 return ret;
1646
1647 ret = analogix_dp_init_dp(dp);
1648 if (ret)
1649 goto out_dp_init;
1650
1651 /*
1652 * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1653 * We should first make sure the HPD signal is asserted high by device
1654 * when we want to establish a link with it.
1655 */
1656 ret = analogix_dp_detect_hpd(dp);
1657 if (ret) {
1658 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1659 goto out_dp_init;
1660 }
1661
1662 ret = analogix_dp_commit(dp);
1663 if (ret < 0) {
1664 DRM_ERROR("dp commit error, ret = %d\n", ret);
1665 goto out_dp_init;
1666 }
1667
1668 if (dp->plat_data->panel)
1669 drm_panel_enable(dp->plat_data->panel);
1670
1671 if (dp->plat_data->power_on_end)
1672 dp->plat_data->power_on_end(dp->plat_data);
1673
1674 return 0;
1675
1676 out_dp_init:
1677 analogix_dp_phy_power_off(dp);
1678 if (dp->plat_data->power_off)
1679 dp->plat_data->power_off(dp->plat_data);
1680 return ret;
1681 }
1682
analogix_dp_modeset_retry_work_fn(struct work_struct * work)1683 static void analogix_dp_modeset_retry_work_fn(struct work_struct *work)
1684 {
1685 struct analogix_dp_device *dp =
1686 container_of(work, typeof(*dp), modeset_retry_work);
1687
1688 /* Send Hotplug uevent so userspace can reprobe */
1689 drm_kms_helper_hotplug_event(dp->bridge.dev);
1690 }
1691
1692 static void
analogix_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1693 analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1694 struct drm_bridge_state *old_bridge_state)
1695 {
1696 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1697 struct analogix_dp_device *dp = bridge->driver_private;
1698 struct drm_crtc *crtc;
1699 struct drm_crtc_state *old_crtc_state;
1700 int timeout_loop = 0;
1701 int ret;
1702
1703 crtc = analogix_dp_get_new_crtc(dp, old_state);
1704 if (!crtc)
1705 return;
1706
1707 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1708 /* Not a full enable, just disable PSR and continue */
1709 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1710 ret = analogix_dp_disable_psr(dp);
1711 if (ret)
1712 DRM_ERROR("Failed to disable psr %d\n", ret);
1713 return;
1714 }
1715
1716 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1717 return;
1718
1719 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1720 if (analogix_dp_set_bridge(dp) == 0) {
1721 dp->dpms_mode = DRM_MODE_DPMS_ON;
1722 return;
1723 }
1724 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1725 timeout_loop);
1726 timeout_loop++;
1727 usleep_range(10, 11);
1728 }
1729 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1730
1731 /* Schedule a Hotplug Uevent to userspace to start modeset */
1732 schedule_work(&dp->modeset_retry_work);
1733 }
1734
analogix_dp_bridge_disable(struct drm_bridge * bridge)1735 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1736 {
1737 struct analogix_dp_device *dp = bridge->driver_private;
1738
1739 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1740 return;
1741
1742 if (dp->plat_data->panel) {
1743 if (drm_panel_disable(dp->plat_data->panel)) {
1744 DRM_ERROR("failed to disable the panel\n");
1745 return;
1746 }
1747 }
1748
1749 if (!analogix_dp_get_plug_in_status(dp))
1750 analogix_dp_link_power_down(dp);
1751
1752 if (dp->plat_data->power_off)
1753 dp->plat_data->power_off(dp->plat_data);
1754
1755 analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1756 analogix_dp_phy_power_off(dp);
1757
1758 if (dp->plat_data->panel)
1759 analogix_dp_panel_unprepare(dp);
1760
1761 dp->fast_train_enable = false;
1762 dp->psr_supported = false;
1763 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1764 }
1765
analogix_dp_disable(struct analogix_dp_device * dp)1766 void analogix_dp_disable(struct analogix_dp_device *dp)
1767 {
1768 analogix_dp_bridge_disable(&dp->bridge);
1769 }
1770 EXPORT_SYMBOL_GPL(analogix_dp_disable);
1771
1772 static void
analogix_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1773 analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1774 struct drm_bridge_state *old_bridge_state)
1775 {
1776 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1777 struct analogix_dp_device *dp = bridge->driver_private;
1778 struct drm_crtc *old_crtc, *new_crtc;
1779 struct drm_crtc_state *old_crtc_state = NULL;
1780 struct drm_crtc_state *new_crtc_state = NULL;
1781 int ret;
1782
1783 new_crtc = analogix_dp_get_new_crtc(dp, old_state);
1784 if (!new_crtc)
1785 goto out;
1786
1787 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1788 if (!new_crtc_state)
1789 goto out;
1790
1791 /* Don't do a full disable on PSR transitions */
1792 if (new_crtc_state->self_refresh_active)
1793 return;
1794
1795 out:
1796 old_crtc = analogix_dp_get_old_crtc(dp, old_state);
1797 if (old_crtc) {
1798 old_crtc_state = drm_atomic_get_old_crtc_state(old_state,
1799 old_crtc);
1800
1801 /* When moving from PSR to fully disabled, exit PSR first. */
1802 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1803 ret = analogix_dp_disable_psr(dp);
1804 if (ret)
1805 DRM_ERROR("Failed to disable psr (%d)\n", ret);
1806 }
1807 }
1808
1809 analogix_dp_bridge_disable(bridge);
1810 }
1811
1812 static void
analogix_dp_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1813 analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1814 struct drm_bridge_state *old_bridge_state)
1815 {
1816 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1817 struct analogix_dp_device *dp = bridge->driver_private;
1818 struct drm_crtc *crtc;
1819 struct drm_crtc_state *new_crtc_state;
1820 int ret;
1821
1822 crtc = analogix_dp_get_new_crtc(dp, old_state);
1823 if (!crtc)
1824 return;
1825
1826 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1827 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1828 return;
1829
1830 ret = analogix_dp_enable_psr(dp);
1831 if (ret)
1832 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1833 }
1834
analogix_dp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * adj_mode)1835 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1836 const struct drm_display_mode *adj_mode)
1837 {
1838 struct analogix_dp_device *dp = bridge->driver_private;
1839 struct drm_display_info *display_info = &dp->connector.display_info;
1840 struct video_info *video = &dp->video_info;
1841 struct drm_display_mode *mode = &video->mode;
1842 struct device_node *dp_node = dp->dev->of_node;
1843 int vic;
1844
1845 drm_mode_copy(mode, adj_mode);
1846 if (dp->plat_data->split_mode)
1847 dp->plat_data->convert_to_origin_mode(mode);
1848
1849 /* Input video interlaces & hsync pol & vsync pol */
1850 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1851 if (dp->plat_data->dev_type == RK3588_EDP) {
1852 video->v_sync_polarity = true;
1853 video->h_sync_polarity = true;
1854 } else {
1855 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1856 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1857 }
1858
1859 /* Input video dynamic_range & colorimetry */
1860 vic = drm_match_cea_mode(mode);
1861 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1862 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18))
1863 video->dynamic_range = CEA;
1864 else if (vic)
1865 video->dynamic_range = CEA;
1866 else
1867 video->dynamic_range = VESA;
1868
1869 /* Input vide bpc and color_formats */
1870 switch (display_info->bpc) {
1871 case 12:
1872 video->color_depth = COLOR_12;
1873 break;
1874 case 10:
1875 video->color_depth = COLOR_10;
1876 break;
1877 case 8:
1878 video->color_depth = COLOR_8;
1879 break;
1880 case 6:
1881 video->color_depth = COLOR_6;
1882 break;
1883 default:
1884 video->color_depth = COLOR_8;
1885 break;
1886 }
1887 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
1888 video->color_space = COLOR_YCBCR444;
1889 video->ycbcr_coeff = COLOR_YCBCR709;
1890 } else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
1891 video->color_space = COLOR_YCBCR422;
1892 video->ycbcr_coeff = COLOR_YCBCR709;
1893 } else {
1894 video->color_space = COLOR_RGB;
1895 video->ycbcr_coeff = COLOR_YCBCR601;
1896 }
1897
1898 /*
1899 * NOTE: those property parsing code is used for providing backward
1900 * compatibility for samsung platform.
1901 * Due to we used the "of_property_read_u32" interfaces, when this
1902 * property isn't present, the "video_info" can keep the original
1903 * values and wouldn't be modified.
1904 */
1905 of_property_read_u32(dp_node, "samsung,color-space",
1906 &video->color_space);
1907 of_property_read_u32(dp_node, "samsung,dynamic-range",
1908 &video->dynamic_range);
1909 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1910 &video->ycbcr_coeff);
1911 of_property_read_u32(dp_node, "samsung,color-depth",
1912 &video->color_depth);
1913 if (of_property_read_bool(dp_node, "hsync-active-high"))
1914 video->h_sync_polarity = true;
1915 if (of_property_read_bool(dp_node, "vsync-active-high"))
1916 video->v_sync_polarity = true;
1917 if (of_property_read_bool(dp_node, "interlaced"))
1918 video->interlaced = true;
1919 }
1920
analogix_dp_link_config_validate(u8 link_rate,u8 lane_count)1921 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count)
1922 {
1923 switch (link_rate) {
1924 case DP_LINK_BW_1_62:
1925 case DP_LINK_BW_2_7:
1926 case DP_LINK_BW_5_4:
1927 break;
1928 default:
1929 return false;
1930 }
1931
1932 switch (lane_count) {
1933 case 1:
1934 case 2:
1935 case 4:
1936 break;
1937 default:
1938 return false;
1939 }
1940
1941 return true;
1942 }
1943
1944 static enum drm_mode_status
analogix_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1945 analogix_dp_bridge_mode_valid(struct drm_bridge *bridge,
1946 const struct drm_display_info *info,
1947 const struct drm_display_mode *mode)
1948 {
1949 struct analogix_dp_device *dp = bridge->driver_private;
1950 struct drm_display_mode m;
1951 u32 max_link_rate, max_lane_count;
1952
1953 drm_mode_copy(&m, mode);
1954
1955 if (dp->plat_data->split_mode || dp->plat_data->dual_connector_split)
1956 dp->plat_data->convert_to_origin_mode(&m);
1957
1958 max_link_rate = min_t(u32, dp->video_info.max_link_rate,
1959 dp->link_train.link_rate);
1960 max_lane_count = min_t(u32, dp->video_info.max_lane_count,
1961 dp->link_train.lane_count);
1962 if (analogix_dp_link_config_validate(max_link_rate, max_lane_count) &&
1963 !analogix_dp_bandwidth_ok(dp, &m,
1964 drm_dp_bw_code_to_link_rate(max_link_rate),
1965 max_lane_count))
1966 return MODE_BAD;
1967
1968 return MODE_OK;
1969 }
1970
1971 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1972 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1973 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1974 .atomic_reset = drm_atomic_helper_bridge_reset,
1975 .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1976 .atomic_enable = analogix_dp_bridge_atomic_enable,
1977 .atomic_disable = analogix_dp_bridge_atomic_disable,
1978 .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1979 .attach = analogix_dp_bridge_attach,
1980 .detach = analogix_dp_bridge_detach,
1981 .mode_valid = analogix_dp_bridge_mode_valid,
1982 };
1983
analogix_dp_bridge_init(struct analogix_dp_device * dp)1984 static int analogix_dp_bridge_init(struct analogix_dp_device *dp)
1985 {
1986 struct drm_bridge *bridge = &dp->bridge;
1987 int ret;
1988
1989 if (!dp->plat_data->left) {
1990 ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1991 if (ret) {
1992 DRM_ERROR("failed to attach drm bridge\n");
1993 return ret;
1994 }
1995 }
1996
1997 if (dp->plat_data->right) {
1998 struct analogix_dp_device *secondary = dp->plat_data->right;
1999 struct drm_bridge *last_bridge =
2000 list_last_entry(&bridge->encoder->bridge_chain,
2001 struct drm_bridge, chain_node);
2002
2003 ret = drm_bridge_attach(dp->encoder, &secondary->bridge, last_bridge,
2004 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2005 if (ret)
2006 return ret;
2007 }
2008
2009 return 0;
2010 }
2011
analogix_dp_parse_link_frequencies(struct analogix_dp_device * dp)2012 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp)
2013 {
2014 struct device_node *node = dp->dev->of_node;
2015 struct device_node *endpoint;
2016 u64 frequency = 0;
2017 int cnt;
2018
2019 endpoint = of_graph_get_endpoint_by_regs(node, 1, 0);
2020 if (!endpoint)
2021 return 0;
2022
2023 cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
2024 if (cnt > 0)
2025 of_property_read_u64_index(endpoint, "link-frequencies",
2026 cnt - 1, &frequency);
2027 of_node_put(endpoint);
2028
2029 if (!frequency)
2030 return 0;
2031
2032 do_div(frequency, 10 * 1000); /* symbol rate kbytes */
2033
2034 switch (frequency) {
2035 case 162000:
2036 case 270000:
2037 case 540000:
2038 break;
2039 default:
2040 dev_err(dp->dev, "invalid link frequency value: %lld\n", frequency);
2041 return 0;
2042 }
2043
2044 return frequency;
2045 }
2046
analogix_dp_dt_parse_pdata(struct analogix_dp_device * dp)2047 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
2048 {
2049 struct device_node *dp_node = dp->dev->of_node;
2050 struct video_info *video_info = &dp->video_info;
2051 struct property *prop;
2052 int ret, len, num_lanes;
2053 u32 max_link_rate;
2054
2055 switch (dp->plat_data->dev_type) {
2056 case RK3288_DP:
2057 case RK3568_EDP:
2058 /*
2059 * Like Rk3288 DisplayPort TRM indicate that "Main link
2060 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
2061 */
2062 video_info->max_link_rate = 0x0A;
2063 video_info->max_lane_count = 0x04;
2064 break;
2065 case RK3399_EDP:
2066 case RK3588_EDP:
2067 video_info->max_link_rate = 0x14;
2068 video_info->max_lane_count = 0x04;
2069 break;
2070 case EXYNOS_DP:
2071 /*
2072 * NOTE: those property parseing code is used for
2073 * providing backward compatibility for samsung platform.
2074 */
2075 of_property_read_u32(dp_node, "samsung,link-rate",
2076 &video_info->max_link_rate);
2077 of_property_read_u32(dp_node, "samsung,lane-count",
2078 &video_info->max_lane_count);
2079 break;
2080 }
2081
2082 max_link_rate = analogix_dp_parse_link_frequencies(dp);
2083 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(video_info->max_link_rate))
2084 video_info->max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate);
2085
2086 video_info->video_bist_enable =
2087 of_property_read_bool(dp_node, "analogix,video-bist-enable");
2088 video_info->force_stream_valid =
2089 of_property_read_bool(dp_node, "analogix,force-stream-valid");
2090
2091 prop = of_find_property(dp_node, "data-lanes", &len);
2092 if (!prop) {
2093 video_info->lane_map[0] = 0;
2094 video_info->lane_map[1] = 1;
2095 video_info->lane_map[2] = 2;
2096 video_info->lane_map[3] = 3;
2097 DRM_DEV_DEBUG(dp->dev, "failed to find data lane mapping, using default\n");
2098 return 0;
2099 }
2100
2101 num_lanes = len / sizeof(u32);
2102
2103 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) {
2104 DRM_DEV_ERROR(dp->dev, "bad number of data lanes\n");
2105 return -EINVAL;
2106 }
2107
2108 video_info->max_lane_count = num_lanes;
2109
2110 ret = of_property_read_u32_array(dp_node, "data-lanes",
2111 video_info->lane_map, num_lanes);
2112 if (ret) {
2113 DRM_DEV_ERROR(dp->dev, "failed to read lane data\n");
2114 return ret;
2115 }
2116
2117 if (device_property_read_u32(dp->dev, "split-area", &dp->split_area))
2118 dp->split_area = 0;
2119
2120 return 0;
2121 }
2122
analogix_dpaux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)2123 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
2124 struct drm_dp_aux_msg *msg)
2125 {
2126 struct analogix_dp_device *dp = to_dp(aux);
2127 int ret;
2128
2129 pm_runtime_get_sync(dp->dev);
2130
2131 ret = analogix_dp_detect_hpd(dp);
2132 if (ret)
2133 goto out;
2134
2135 ret = analogix_dp_transfer(dp, msg);
2136 out:
2137 pm_runtime_put(dp->dev);
2138
2139 return ret;
2140 }
2141
analogix_dp_audio_hw_params(struct analogix_dp_device * dp,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2142 int analogix_dp_audio_hw_params(struct analogix_dp_device *dp,
2143 struct hdmi_codec_daifmt *daifmt,
2144 struct hdmi_codec_params *params)
2145 {
2146 switch (daifmt->fmt) {
2147 case HDMI_SPDIF:
2148 analogix_dp_audio_config_spdif(dp);
2149 break;
2150 case HDMI_I2S:
2151 analogix_dp_audio_config_i2s(dp);
2152 break;
2153 default:
2154 DRM_DEV_ERROR(dp->dev, "invalid daifmt %d\n", daifmt->fmt);
2155 return -EINVAL;
2156 }
2157
2158 return 0;
2159 }
2160 EXPORT_SYMBOL_GPL(analogix_dp_audio_hw_params);
2161
analogix_dp_audio_shutdown(struct analogix_dp_device * dp)2162 void analogix_dp_audio_shutdown(struct analogix_dp_device *dp)
2163 {
2164 analogix_dp_audio_disable(dp);
2165 }
2166 EXPORT_SYMBOL_GPL(analogix_dp_audio_shutdown);
2167
analogix_dp_audio_startup(struct analogix_dp_device * dp)2168 int analogix_dp_audio_startup(struct analogix_dp_device *dp)
2169 {
2170 analogix_dp_audio_enable(dp);
2171
2172 return 0;
2173 }
2174 EXPORT_SYMBOL_GPL(analogix_dp_audio_startup);
2175
analogix_dp_audio_get_eld(struct analogix_dp_device * dp,u8 * buf,size_t len)2176 int analogix_dp_audio_get_eld(struct analogix_dp_device *dp, u8 *buf, size_t len)
2177 {
2178 memcpy(buf, dp->connector.eld, min(sizeof(dp->connector.eld), len));
2179
2180 return 0;
2181 }
2182 EXPORT_SYMBOL_GPL(analogix_dp_audio_get_eld);
2183
analogix_dp_link_train_restore(struct analogix_dp_device * dp)2184 static void analogix_dp_link_train_restore(struct analogix_dp_device *dp)
2185 {
2186 u32 link_rate, lane_count;
2187 u8 lane, spread;
2188
2189 analogix_dp_get_link_bandwidth(dp, &link_rate);
2190 analogix_dp_get_lane_count(dp, &lane_count);
2191 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
2192
2193 dp->link_train.link_rate = link_rate;
2194 dp->link_train.lane_count = lane_count;
2195 dp->link_train.enhanced_framing = analogix_dp_get_enhanced_mode(dp);
2196 dp->link_train.ssc = !!(spread & DP_MAX_DOWNSPREAD_0_5);
2197
2198 for (lane = 0; lane < 4; lane++)
2199 dp->link_train.training_lane[lane] =
2200 analogix_dp_get_lane_link_training(dp, lane);
2201 }
2202
analogix_dp_loader_protect(struct analogix_dp_device * dp)2203 int analogix_dp_loader_protect(struct analogix_dp_device *dp)
2204 {
2205 u8 link_status[DP_LINK_STATUS_SIZE];
2206 int ret;
2207
2208 ret = analogix_dp_phy_power_on(dp);
2209 if (ret)
2210 return ret;
2211
2212 dp->dpms_mode = DRM_MODE_DPMS_ON;
2213
2214 analogix_dp_link_train_restore(dp);
2215
2216 ret = analogix_dp_fast_link_train_detection(dp);
2217 if (ret)
2218 goto err_disable;
2219
2220 if (analogix_dp_detect_sink_psr(dp)) {
2221 ret = analogix_dp_enable_sink_psr(dp);
2222 if (ret)
2223 goto err_disable;
2224 }
2225
2226 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
2227 if (ret < 0) {
2228 dev_err(dp->dev, "Failed to read link status\n");
2229 goto err_disable;
2230 }
2231
2232 if (!drm_dp_channel_eq_ok(link_status, dp->link_train.lane_count)) {
2233 dev_err(dp->dev, "Channel EQ or CR not ok\n");
2234 ret = -EINVAL;
2235 goto err_disable;
2236 }
2237
2238 return 0;
2239
2240 err_disable:
2241 analogix_dp_disable(dp);
2242 return ret;
2243 }
2244 EXPORT_SYMBOL_GPL(analogix_dp_loader_protect);
2245
2246 struct analogix_dp_device *
analogix_dp_probe(struct device * dev,struct analogix_dp_plat_data * plat_data)2247 analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
2248 {
2249 struct platform_device *pdev = to_platform_device(dev);
2250 struct analogix_dp_device *dp;
2251 struct resource *res;
2252 int ret;
2253
2254 if (!plat_data) {
2255 dev_err(dev, "Invalided input plat_data\n");
2256 return ERR_PTR(-EINVAL);
2257 }
2258
2259 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
2260 if (!dp)
2261 return ERR_PTR(-ENOMEM);
2262
2263 dp->dev = &pdev->dev;
2264 dp->dpms_mode = DRM_MODE_DPMS_OFF;
2265 INIT_WORK(&dp->modeset_retry_work, analogix_dp_modeset_retry_work_fn);
2266
2267 mutex_init(&dp->panel_lock);
2268 dp->panel_is_prepared = false;
2269
2270 /*
2271 * platform dp driver need containor_of the plat_data to get
2272 * the driver private data, so we need to store the point of
2273 * plat_data, not the context of plat_data.
2274 */
2275 dp->plat_data = plat_data;
2276
2277 ret = analogix_dp_dt_parse_pdata(dp);
2278 if (ret)
2279 return ERR_PTR(ret);
2280
2281 dp->phy = devm_phy_get(dp->dev, "dp");
2282 if (IS_ERR(dp->phy)) {
2283 dev_err(dp->dev, "no DP phy configured\n");
2284 ret = PTR_ERR(dp->phy);
2285 if (ret) {
2286 /*
2287 * phy itself is not enabled, so we can move forward
2288 * assigning NULL to phy pointer.
2289 */
2290 if (ret == -ENOSYS || ret == -ENODEV)
2291 dp->phy = NULL;
2292 else
2293 return ERR_PTR(ret);
2294 }
2295 }
2296
2297 ret = devm_clk_bulk_get_all(dev, &dp->clks);
2298 if (ret < 0) {
2299 dev_err(dev, "failed to get clocks %d\n", ret);
2300 return ERR_PTR(ret);
2301 }
2302
2303 dp->nr_clks = ret;
2304
2305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2306
2307 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
2308 if (IS_ERR(dp->reg_base))
2309 return ERR_CAST(dp->reg_base);
2310
2311 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
2312
2313 /* Try two different names */
2314 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2315 if (!dp->hpd_gpiod)
2316 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
2317 GPIOD_IN);
2318 if (IS_ERR(dp->hpd_gpiod)) {
2319 dev_err(dev, "error getting HDP GPIO: %ld\n",
2320 PTR_ERR(dp->hpd_gpiod));
2321 return ERR_CAST(dp->hpd_gpiod);
2322 }
2323
2324 if (dp->hpd_gpiod) {
2325 ret = devm_request_threaded_irq(dev,
2326 gpiod_to_irq(dp->hpd_gpiod),
2327 NULL,
2328 analogix_dp_hpd_irq_handler,
2329 IRQF_TRIGGER_RISING |
2330 IRQF_TRIGGER_FALLING |
2331 IRQF_ONESHOT,
2332 "analogix-hpd", dp);
2333 if (ret) {
2334 dev_err(dev, "failed to request hpd IRQ: %d\n", ret);
2335 return ERR_PTR(ret);
2336 }
2337 }
2338
2339 dp->irq = platform_get_irq(pdev, 0);
2340 if (dp->irq == -ENXIO) {
2341 dev_err(&pdev->dev, "failed to get irq\n");
2342 return ERR_PTR(-ENODEV);
2343 }
2344
2345 irq_set_status_flags(dp->irq, IRQ_NOAUTOEN);
2346 ret = devm_request_threaded_irq(dev, dp->irq, NULL,
2347 analogix_dp_irq_thread,
2348 IRQF_ONESHOT, dev_name(dev), dp);
2349 if (ret) {
2350 dev_err(&pdev->dev, "failed to request irq\n");
2351 return ERR_PTR(ret);
2352 }
2353
2354 dp->extcon = devm_extcon_dev_allocate(dev, analogix_dp_cable);
2355 if (IS_ERR(dp->extcon)) {
2356 dev_err(dev, "failed to allocate extcon device\n");
2357 return ERR_CAST(dp->extcon);
2358 }
2359
2360 ret = devm_extcon_dev_register(dev, dp->extcon);
2361 if (ret) {
2362 dev_err(dev, "failed to register extcon device\n");
2363 return ERR_PTR(ret);
2364 }
2365
2366 dp->bridge.driver_private = dp;
2367 dp->bridge.funcs = &analogix_dp_bridge_funcs;
2368
2369 return dp;
2370 }
2371 EXPORT_SYMBOL_GPL(analogix_dp_probe);
2372
analogix_dp_bind(struct analogix_dp_device * dp,struct drm_device * drm_dev)2373 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
2374 {
2375 int ret;
2376
2377 dp->drm_dev = drm_dev;
2378 dp->encoder = dp->plat_data->encoder;
2379
2380 dp->aux.name = "DP-AUX";
2381 dp->aux.transfer = analogix_dpaux_transfer;
2382 dp->aux.dev = dp->dev;
2383
2384 ret = drm_dp_aux_register(&dp->aux);
2385 if (ret)
2386 return ret;
2387
2388 pm_runtime_enable(dp->dev);
2389 pm_runtime_get_sync(dp->dev);
2390 analogix_dp_init(dp);
2391
2392 ret = analogix_dp_bridge_init(dp);
2393 if (ret) {
2394 DRM_ERROR("failed to init bridge (%d)\n", ret);
2395 goto err_disable_pm_runtime;
2396 }
2397
2398 enable_irq(dp->irq);
2399
2400 return 0;
2401
2402 err_disable_pm_runtime:
2403 pm_runtime_put(dp->dev);
2404 pm_runtime_disable(dp->dev);
2405 drm_dp_aux_unregister(&dp->aux);
2406
2407 return ret;
2408 }
2409 EXPORT_SYMBOL_GPL(analogix_dp_bind);
2410
analogix_dp_unbind(struct analogix_dp_device * dp)2411 void analogix_dp_unbind(struct analogix_dp_device *dp)
2412 {
2413 disable_irq(dp->irq);
2414 if (dp->connector.funcs->destroy)
2415 dp->connector.funcs->destroy(&dp->connector);
2416 drm_dp_aux_unregister(&dp->aux);
2417 pm_runtime_put(dp->dev);
2418 pm_runtime_disable(dp->dev);
2419 }
2420 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
2421
analogix_dp_remove(struct analogix_dp_device * dp)2422 void analogix_dp_remove(struct analogix_dp_device *dp)
2423 {
2424 cancel_work_sync(&dp->modeset_retry_work);
2425 }
2426 EXPORT_SYMBOL_GPL(analogix_dp_remove);
2427
analogix_dp_suspend(struct analogix_dp_device * dp)2428 int analogix_dp_suspend(struct analogix_dp_device *dp)
2429 {
2430 pm_runtime_force_suspend(dp->dev);
2431
2432 return 0;
2433 }
2434 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
2435
analogix_dp_resume(struct analogix_dp_device * dp)2436 int analogix_dp_resume(struct analogix_dp_device *dp)
2437 {
2438 pm_runtime_force_resume(dp->dev);
2439 analogix_dp_init(dp);
2440
2441 return 0;
2442 }
2443 EXPORT_SYMBOL_GPL(analogix_dp_resume);
2444
analogix_dp_runtime_suspend(struct analogix_dp_device * dp)2445 int analogix_dp_runtime_suspend(struct analogix_dp_device *dp)
2446 {
2447 clk_bulk_disable_unprepare(dp->nr_clks, dp->clks);
2448
2449 return 0;
2450 }
2451 EXPORT_SYMBOL_GPL(analogix_dp_runtime_suspend);
2452
analogix_dp_runtime_resume(struct analogix_dp_device * dp)2453 int analogix_dp_runtime_resume(struct analogix_dp_device *dp)
2454 {
2455 return clk_bulk_prepare_enable(dp->nr_clks, dp->clks);
2456 }
2457 EXPORT_SYMBOL_GPL(analogix_dp_runtime_resume);
2458
analogix_dp_start_crc(struct drm_connector * connector)2459 int analogix_dp_start_crc(struct drm_connector *connector)
2460 {
2461 struct analogix_dp_device *dp = to_dp(connector);
2462
2463 if (!connector->state->crtc) {
2464 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
2465 connector->name);
2466 return -EINVAL;
2467 }
2468
2469 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
2470 }
2471 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
2472
analogix_dp_stop_crc(struct drm_connector * connector)2473 int analogix_dp_stop_crc(struct drm_connector *connector)
2474 {
2475 struct analogix_dp_device *dp = to_dp(connector);
2476
2477 return drm_dp_stop_crc(&dp->aux);
2478 }
2479 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
2480
2481 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
2482 MODULE_DESCRIPTION("Analogix DP Core Driver");
2483 MODULE_LICENSE("GPL v2");
2484