1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26
27 #include "amdgv_sriovmsg.h"
28
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36 /* all asic after AI use this offset */
37 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
38 /* tonga/fiji use this offset */
39 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
40
41 enum amdgpu_sriov_vf_mode {
42 SRIOV_VF_MODE_BARE_METAL = 0,
43 SRIOV_VF_MODE_ONE_VF,
44 SRIOV_VF_MODE_MULTI_VF,
45 };
46
47 struct amdgpu_mm_table {
48 struct amdgpu_bo *bo;
49 uint32_t *cpu_addr;
50 uint64_t gpu_addr;
51 };
52
53 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16
54
55 /* struct error_entry - amdgpu VF error information. */
56 struct amdgpu_vf_error_buffer {
57 struct mutex lock;
58 int read_count;
59 int write_count;
60 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
61 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
62 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
63 };
64
65 /**
66 * struct amdgpu_virt_ops - amdgpu device virt operations
67 */
68 struct amdgpu_virt_ops {
69 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
70 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
71 int (*req_init_data)(struct amdgpu_device *adev);
72 int (*reset_gpu)(struct amdgpu_device *adev);
73 int (*wait_reset)(struct amdgpu_device *adev);
74 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
75 };
76
77 /*
78 * Firmware Reserve Frame buffer
79 */
80 struct amdgpu_virt_fw_reserve {
81 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
82 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
83 unsigned int checksum_key;
84 };
85
86 /*
87 * Legacy GIM header
88 *
89 * Defination between PF and VF
90 * Structures forcibly aligned to 4 to keep the same style as PF.
91 */
92 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
93
94 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
95 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
96
97 enum AMDGIM_FEATURE_FLAG {
98 /* GIM supports feature of Error log collecting */
99 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
100 /* GIM supports feature of loading uCodes */
101 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
102 /* VRAM LOST by GIM */
103 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
104 /* MM bandwidth */
105 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
106 /* PP ONE VF MODE in GIM */
107 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
108 };
109
110 struct amdgim_pf2vf_info_v1 {
111 /* header contains size and version */
112 struct amd_sriov_msg_pf2vf_info_header header;
113 /* max_width * max_height */
114 unsigned int uvd_enc_max_pixels_count;
115 /* 16x16 pixels/sec, codec independent */
116 unsigned int uvd_enc_max_bandwidth;
117 /* max_width * max_height */
118 unsigned int vce_enc_max_pixels_count;
119 /* 16x16 pixels/sec, codec independent */
120 unsigned int vce_enc_max_bandwidth;
121 /* MEC FW position in kb from the start of visible frame buffer */
122 unsigned int mecfw_kboffset;
123 /* The features flags of the GIM driver supports. */
124 unsigned int feature_flags;
125 /* use private key from mailbox 2 to create chueksum */
126 unsigned int checksum;
127 } __aligned(4);
128
129 struct amdgim_vf2pf_info_v1 {
130 /* header contains size and version */
131 struct amd_sriov_msg_vf2pf_info_header header;
132 /* driver version */
133 char driver_version[64];
134 /* driver certification, 1=WHQL, 0=None */
135 unsigned int driver_cert;
136 /* guest OS type and version: need a define */
137 unsigned int os_info;
138 /* in the unit of 1M */
139 unsigned int fb_usage;
140 /* guest gfx engine usage percentage */
141 unsigned int gfx_usage;
142 /* guest gfx engine health percentage */
143 unsigned int gfx_health;
144 /* guest compute engine usage percentage */
145 unsigned int compute_usage;
146 /* guest compute engine health percentage */
147 unsigned int compute_health;
148 /* guest vce engine usage percentage. 0xffff means N/A. */
149 unsigned int vce_enc_usage;
150 /* guest vce engine health percentage. 0xffff means N/A. */
151 unsigned int vce_enc_health;
152 /* guest uvd engine usage percentage. 0xffff means N/A. */
153 unsigned int uvd_enc_usage;
154 /* guest uvd engine usage percentage. 0xffff means N/A. */
155 unsigned int uvd_enc_health;
156 unsigned int checksum;
157 } __aligned(4);
158
159 struct amdgim_vf2pf_info_v2 {
160 /* header contains size and version */
161 struct amd_sriov_msg_vf2pf_info_header header;
162 uint32_t checksum;
163 /* driver version */
164 uint8_t driver_version[64];
165 /* driver certification, 1=WHQL, 0=None */
166 uint32_t driver_cert;
167 /* guest OS type and version: need a define */
168 uint32_t os_info;
169 /* in the unit of 1M */
170 uint32_t fb_usage;
171 /* guest gfx engine usage percentage */
172 uint32_t gfx_usage;
173 /* guest gfx engine health percentage */
174 uint32_t gfx_health;
175 /* guest compute engine usage percentage */
176 uint32_t compute_usage;
177 /* guest compute engine health percentage */
178 uint32_t compute_health;
179 /* guest vce engine usage percentage. 0xffff means N/A. */
180 uint32_t vce_enc_usage;
181 /* guest vce engine health percentage. 0xffff means N/A. */
182 uint32_t vce_enc_health;
183 /* guest uvd engine usage percentage. 0xffff means N/A. */
184 uint32_t uvd_enc_usage;
185 /* guest uvd engine usage percentage. 0xffff means N/A. */
186 uint32_t uvd_enc_health;
187 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
188 } __aligned(4);
189
190 struct amdgpu_virt_ras_err_handler_data {
191 /* point to bad page records array */
192 struct eeprom_table_record *bps;
193 /* point to reserved bo array */
194 struct amdgpu_bo **bps_bo;
195 /* the count of entries */
196 int count;
197 /* last reserved entry's index + 1 */
198 int last_reserved;
199 };
200
201 /* GPU virtualization */
202 struct amdgpu_virt {
203 uint32_t caps;
204 struct amdgpu_bo *csa_obj;
205 void *csa_cpu_addr;
206 bool chained_ib_support;
207 uint32_t reg_val_offs;
208 struct amdgpu_irq_src ack_irq;
209 struct amdgpu_irq_src rcv_irq;
210 struct work_struct flr_work;
211 struct amdgpu_mm_table mm_table;
212 const struct amdgpu_virt_ops *ops;
213 struct amdgpu_vf_error_buffer vf_errors;
214 struct amdgpu_virt_fw_reserve fw_reserve;
215 uint32_t gim_feature;
216 uint32_t reg_access_mode;
217 int req_init_data_ver;
218 bool tdr_debug;
219 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
220 bool ras_init_done;
221
222 /* vf2pf message */
223 struct delayed_work vf2pf_work;
224 uint32_t vf2pf_update_interval_ms;
225 };
226
227 #define amdgpu_sriov_enabled(adev) \
228 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
229
230 #define amdgpu_sriov_vf(adev) \
231 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
232
233 #define amdgpu_sriov_bios(adev) \
234 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
235
236 #define amdgpu_sriov_runtime(adev) \
237 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
238
239 #define amdgpu_sriov_fullaccess(adev) \
240 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
241
242 #define amdgpu_passthrough(adev) \
243 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
244
245 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
246 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
247
is_virtual_machine(void)248 static inline bool is_virtual_machine(void)
249 {
250 #ifdef CONFIG_X86
251 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
252 #else
253 return false;
254 #endif
255 }
256
257 #define amdgpu_sriov_is_pp_one_vf(adev) \
258 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
259 #define amdgpu_sriov_is_debug(adev) \
260 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
261 #define amdgpu_sriov_is_normal(adev) \
262 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
263
264 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
265 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
266 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
267 uint32_t reg0, uint32_t rreg1,
268 uint32_t ref, uint32_t mask);
269 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
270 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
271 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
272 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
273 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
274 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
275 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
276 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
277 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
278 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
279 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
280 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
281
282 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
283 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
284 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
285
286 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
287 #endif
288