1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #ifndef _ROCKCHIP_DRM_VOP_H
8 #define _ROCKCHIP_DRM_VOP_H
9
10 #include <drm/drm_plane.h>
11 #include <drm/drm_modes.h>
12
13 #include "rockchip_drm_drv.h"
14
15 /*
16 * major: IP major version, used for IP structure
17 * minor: big feature change under same structure
18 * build: RTL current SVN number
19 */
20 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
21 #define VOP_MAJOR(version) ((version) >> 8)
22 #define VOP_MINOR(version) ((version) & 0xff)
23
24 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
25 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
26 #define VOP2_MINOR(version) (((version) >> 16) & 0xff)
27 #define VOP2_BUILD(version) ((version) & 0xffff)
28
29 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
30 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
31 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
32 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
33
34 /* register one connector */
35 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
36 /* register one connector */
37 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
38 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
39 /* MIPI DSI DataStream(cmd) mode on rk3588 */
40 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
41 /* register two connector */
42 #define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
43
44 #define AFBDC_FMT_RGB565 0x0
45 #define AFBDC_FMT_U8U8U8U8 0x5
46 #define AFBDC_FMT_U8U8U8 0x4
47
48 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
49 #define VOP_FEATURE_INTERNAL_RGB BIT(1)
50 #define VOP_FEATURE_ALPHA_SCALE BIT(2)
51 #define VOP_FEATURE_HDR10 BIT(3)
52 #define VOP_FEATURE_NEXT_HDR BIT(4)
53 /* a feature to splice two windows and two vps to support resolution > 4096 */
54 #define VOP_FEATURE_SPLICE BIT(5)
55 #define VOP_FEATURE_OVERSCAN BIT(6)
56 #define VOP_FEATURE_VIVID_HDR BIT(7)
57 #define VOP_FEATURE_POST_ACM BIT(8)
58 #define VOP_FEATURE_POST_CSC BIT(9)
59
60 #define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
61
62
63 #define WIN_FEATURE_HDR2SDR BIT(0)
64 #define WIN_FEATURE_SDR2HDR BIT(1)
65 #define WIN_FEATURE_PRE_OVERLAY BIT(2)
66 #define WIN_FEATURE_AFBDC BIT(3)
67 #define WIN_FEATURE_CLUSTER_MAIN BIT(4)
68 #define WIN_FEATURE_CLUSTER_SUB BIT(5)
69 /* Left win in splice mode */
70 #define WIN_FEATURE_SPLICE_LEFT BIT(6)
71 /* a mirror win can only get fb address
72 * from source win:
73 * Cluster1---->Cluster0
74 * Esmart1 ---->Esmart0
75 * Smart1 ---->Smart0
76 * This is a feather on rk3566
77 */
78 #define WIN_FEATURE_MIRROR BIT(6)
79 #define WIN_FEATURE_MULTI_AREA BIT(7)
80 #define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
81
82
83 #define VOP2_SOC_VARIANT 4
84
85 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
86
87 enum vop_vp_id {
88 ROCKCHIP_VOP_VP0 = 0,
89 ROCKCHIP_VOP_VP1,
90 ROCKCHIP_VOP_VP2,
91 ROCKCHIP_VOP_VP3,
92 };
93
94 enum vop_win_phy_id {
95 ROCKCHIP_VOP_WIN0 = 0,
96 ROCKCHIP_VOP_WIN1,
97 ROCKCHIP_VOP_WIN2,
98 ROCKCHIP_VOP_WIN3,
99 ROCKCHIP_VOP_PHY_ID_INVALID = -1,
100 };
101
102 enum bcsh_out_mode {
103 BCSH_OUT_MODE_BLACK,
104 BCSH_OUT_MODE_BLUE,
105 BCSH_OUT_MODE_COLOR_BAR,
106 BCSH_OUT_MODE_NORMAL_VIDEO,
107 };
108
109 enum cabc_stage_mode {
110 LAST_FRAME_PWM_VAL = 0x0,
111 CUR_FRAME_PWM_VAL = 0x1,
112 STAGE_BY_STAGE = 0x2
113 };
114
115 enum cabc_stage_up_mode {
116 MUL_MODE,
117 ADD_MODE,
118 };
119
120 /*
121 * the delay number of a window in different mode.
122 */
123 enum vop2_win_dly_mode {
124 VOP2_DLY_MODE_DEFAULT, /**< default mode */
125 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
126 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
127 VOP2_DLY_MODE_MAX,
128 };
129
130 enum vop3_esmart_lb_mode {
131 VOP3_ESMART_8K_MODE,
132 VOP3_ESMART_4K_4K_MODE,
133 VOP3_ESMART_4K_2K_2K_MODE,
134 VOP3_ESMART_2K_2K_2K_2K_MODE,
135 };
136
137 /*
138 * vop2 dsc id
139 */
140 #define ROCKCHIP_VOP2_DSC_8K 0
141 #define ROCKCHIP_VOP2_DSC_4K 1
142
143 /*
144 * vop2 internal power domain id,
145 * should be all none zero, 0 will be
146 * treat as invalid;
147 */
148 #define VOP2_PD_CLUSTER0 BIT(0)
149 #define VOP2_PD_CLUSTER1 BIT(1)
150 #define VOP2_PD_CLUSTER2 BIT(2)
151 #define VOP2_PD_CLUSTER3 BIT(3)
152 #define VOP2_PD_DSC_8K BIT(5)
153 #define VOP2_PD_DSC_4K BIT(6)
154 #define VOP2_PD_ESMART BIT(7)
155
156 /*
157 * vop2 submem power gate,
158 * should be all none zero, 0 will be
159 * treat as invalid;
160 */
161 #define VOP2_MEM_PG_VP0 BIT(0)
162 #define VOP2_MEM_PG_VP1 BIT(1)
163 #define VOP2_MEM_PG_VP2 BIT(2)
164 #define VOP2_MEM_PG_VP3 BIT(3)
165 #define VOP2_MEM_PG_DB0 BIT(4)
166 #define VOP2_MEM_PG_DB1 BIT(5)
167 #define VOP2_MEM_PG_DB2 BIT(6)
168 #define VOP2_MEM_PG_WB BIT(7)
169
170 #define DSP_BG_SWAP 0x1
171 #define DSP_RB_SWAP 0x2
172 #define DSP_RG_SWAP 0x4
173 #define DSP_DELTA_SWAP 0x8
174
175 #define V4L2_COLORSPACE_BT709F 0xfe
176 #define V4L2_COLORSPACE_BT2020F 0xff
177
178 enum vop_csc_format {
179 CSC_BT601L,
180 CSC_BT709L,
181 CSC_BT601F,
182 CSC_BT2020,
183 CSC_BT709L_13BIT,
184 CSC_BT709F_13BIT,
185 CSC_BT2020L_13BIT,
186 CSC_BT2020F_13BIT,
187 };
188
189 enum vop_csc_mode {
190 CSC_RGB,
191 CSC_YUV,
192 };
193
194 enum vop_csc_bit_depth {
195 CSC_10BIT_DEPTH,
196 CSC_13BIT_DEPTH,
197 };
198
199 enum vop_data_format {
200 VOP_FMT_ARGB8888 = 0,
201 VOP_FMT_RGB888,
202 VOP_FMT_RGB565 = 2,
203 VOP_FMT_YUYV = 2,
204 VOP_FMT_YUV420SP = 4,
205 VOP_FMT_YUV422SP,
206 VOP_FMT_YUV444SP,
207 };
208
209 enum vop_dsc_interface_mode {
210 VOP_DSC_IF_DISABLE = 0,
211 VOP_DSC_IF_HDMI = 1,
212 VOP_DSC_IF_MIPI_DS_MODE = 2,
213 VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
214 };
215
216 struct vop_reg_data {
217 uint32_t offset;
218 uint32_t value;
219 };
220
221 struct vop_reg {
222 uint32_t mask;
223 uint32_t offset:17;
224 uint32_t shift:5;
225 uint32_t begin_minor:4;
226 uint32_t end_minor:4;
227 uint32_t reserved:2;
228 uint32_t major:3;
229 uint32_t write_mask:1;
230 };
231
232 struct vop_csc {
233 struct vop_reg y2r_en;
234 struct vop_reg r2r_en;
235 struct vop_reg r2y_en;
236 struct vop_reg csc_mode;
237
238 uint32_t y2r_offset;
239 uint32_t r2r_offset;
240 uint32_t r2y_offset;
241 };
242
243 struct vop_rect {
244 int width;
245 int height;
246 };
247
248 struct vop_ctrl {
249 struct vop_reg version;
250 struct vop_reg standby;
251 struct vop_reg dma_stop;
252 struct vop_reg axi_outstanding_max_num;
253 struct vop_reg axi_max_outstanding_en;
254 struct vop_reg htotal_pw;
255 struct vop_reg hact_st_end;
256 struct vop_reg vtotal_pw;
257 struct vop_reg vact_st_end;
258 struct vop_reg vact_st_end_f1;
259 struct vop_reg vs_st_end_f1;
260 struct vop_reg hpost_st_end;
261 struct vop_reg vpost_st_end;
262 struct vop_reg vpost_st_end_f1;
263 struct vop_reg post_scl_factor;
264 struct vop_reg post_scl_ctrl;
265 struct vop_reg dsp_interlace;
266 struct vop_reg dsp_interlace_pol;
267 struct vop_reg global_regdone_en;
268 struct vop_reg auto_gate_en;
269 struct vop_reg post_lb_mode;
270 struct vop_reg dsp_layer_sel;
271 struct vop_reg overlay_mode;
272 struct vop_reg core_dclk_div;
273 struct vop_reg dclk_ddr;
274 struct vop_reg p2i_en;
275 struct vop_reg hdmi_dclk_out_en;
276 struct vop_reg rgb_en;
277 struct vop_reg lvds_en;
278 struct vop_reg edp_en;
279 struct vop_reg hdmi_en;
280 struct vop_reg mipi_en;
281 struct vop_reg data01_swap;
282 struct vop_reg mipi_dual_channel_en;
283 struct vop_reg dp_en;
284 struct vop_reg dclk_pol;
285 struct vop_reg pin_pol;
286 struct vop_reg rgb_dclk_pol;
287 struct vop_reg rgb_pin_pol;
288 struct vop_reg lvds_dclk_pol;
289 struct vop_reg lvds_pin_pol;
290 struct vop_reg hdmi_dclk_pol;
291 struct vop_reg hdmi_pin_pol;
292 struct vop_reg edp_dclk_pol;
293 struct vop_reg edp_pin_pol;
294 struct vop_reg mipi_dclk_pol;
295 struct vop_reg mipi_pin_pol;
296 struct vop_reg dp_dclk_pol;
297 struct vop_reg dp_pin_pol;
298 struct vop_reg dither_down_sel;
299 struct vop_reg dither_down_mode;
300 struct vop_reg dither_down_en;
301 struct vop_reg pre_dither_down_en;
302 struct vop_reg dither_up_en;
303
304 struct vop_reg sw_dac_sel;
305 struct vop_reg tve_sw_mode;
306 struct vop_reg tve_dclk_pol;
307 struct vop_reg tve_dclk_en;
308 struct vop_reg sw_genlock;
309 struct vop_reg sw_uv_offset_en;
310 struct vop_reg dsp_out_yuv;
311 struct vop_reg dsp_data_swap;
312 struct vop_reg dsp_bg_swap;
313 struct vop_reg dsp_rb_swap;
314 struct vop_reg dsp_rg_swap;
315 struct vop_reg dsp_delta_swap;
316 struct vop_reg dsp_dummy_swap;
317 struct vop_reg yuv_clip;
318 struct vop_reg dsp_ccir656_avg;
319 struct vop_reg dsp_black;
320 struct vop_reg dsp_blank;
321 struct vop_reg dsp_outzero;
322 struct vop_reg update_gamma_lut;
323 struct vop_reg lut_buffer_index;
324 struct vop_reg dsp_lut_en;
325
326 struct vop_reg out_mode;
327
328 struct vop_reg xmirror;
329 struct vop_reg ymirror;
330 struct vop_reg dsp_background;
331
332 /* AFBDC */
333 struct vop_reg afbdc_en;
334 struct vop_reg afbdc_sel;
335 struct vop_reg afbdc_format;
336 struct vop_reg afbdc_hreg_block_split;
337 struct vop_reg afbdc_pic_size;
338 struct vop_reg afbdc_hdr_ptr;
339 struct vop_reg afbdc_rstn;
340 struct vop_reg afbdc_pic_vir_width;
341 struct vop_reg afbdc_pic_offset;
342 struct vop_reg afbdc_axi_ctrl;
343
344 /* BCSH */
345 struct vop_reg bcsh_brightness;
346 struct vop_reg bcsh_contrast;
347 struct vop_reg bcsh_sat_con;
348 struct vop_reg bcsh_sin_hue;
349 struct vop_reg bcsh_cos_hue;
350 struct vop_reg bcsh_r2y_csc_mode;
351 struct vop_reg bcsh_r2y_en;
352 struct vop_reg bcsh_y2r_csc_mode;
353 struct vop_reg bcsh_y2r_en;
354 struct vop_reg bcsh_color_bar;
355 struct vop_reg bcsh_out_mode;
356 struct vop_reg bcsh_en;
357
358 /* HDR */
359 struct vop_reg level2_overlay_en;
360 struct vop_reg alpha_hard_calc;
361 struct vop_reg hdr2sdr_en;
362 struct vop_reg hdr2sdr_en_win0_csc;
363 struct vop_reg hdr2sdr_src_min;
364 struct vop_reg hdr2sdr_src_max;
365 struct vop_reg hdr2sdr_normfaceetf;
366 struct vop_reg hdr2sdr_dst_min;
367 struct vop_reg hdr2sdr_dst_max;
368 struct vop_reg hdr2sdr_normfacgamma;
369
370 struct vop_reg bt1886eotf_pre_conv_en;
371 struct vop_reg rgb2rgb_pre_conv_en;
372 struct vop_reg rgb2rgb_pre_conv_mode;
373 struct vop_reg st2084oetf_pre_conv_en;
374 struct vop_reg bt1886eotf_post_conv_en;
375 struct vop_reg rgb2rgb_post_conv_en;
376 struct vop_reg rgb2rgb_post_conv_mode;
377 struct vop_reg st2084oetf_post_conv_en;
378 struct vop_reg win_csc_mode_sel;
379
380 /* MCU OUTPUT */
381 struct vop_reg mcu_pix_total;
382 struct vop_reg mcu_cs_pst;
383 struct vop_reg mcu_cs_pend;
384 struct vop_reg mcu_rw_pst;
385 struct vop_reg mcu_rw_pend;
386 struct vop_reg mcu_clk_sel;
387 struct vop_reg mcu_hold_mode;
388 struct vop_reg mcu_frame_st;
389 struct vop_reg mcu_rs;
390 struct vop_reg mcu_bypass;
391 struct vop_reg mcu_type;
392 struct vop_reg mcu_rw_bypass_port;
393
394 /* bt1120 */
395 struct vop_reg bt1120_yc_swap;
396 struct vop_reg bt1120_en;
397
398 /* bt656 */
399 struct vop_reg bt656_en;
400
401 struct vop_reg reg_done_frm;
402 struct vop_reg cfg_done;
403 };
404
405 struct vop_intr {
406 const int *intrs;
407 uint32_t nintrs;
408 struct vop_reg line_flag_num[2];
409 struct vop_reg enable;
410 struct vop_reg clear;
411 struct vop_reg status;
412 };
413
414 struct vop_scl_extension {
415 struct vop_reg cbcr_vsd_mode;
416 struct vop_reg cbcr_vsu_mode;
417 struct vop_reg cbcr_hsd_mode;
418 struct vop_reg cbcr_ver_scl_mode;
419 struct vop_reg cbcr_hor_scl_mode;
420 struct vop_reg yrgb_vsd_mode;
421 struct vop_reg yrgb_vsu_mode;
422 struct vop_reg yrgb_hsd_mode;
423 struct vop_reg yrgb_ver_scl_mode;
424 struct vop_reg yrgb_hor_scl_mode;
425 struct vop_reg line_load_mode;
426 struct vop_reg cbcr_axi_gather_num;
427 struct vop_reg yrgb_axi_gather_num;
428 struct vop_reg vsd_cbcr_gt2;
429 struct vop_reg vsd_cbcr_gt4;
430 struct vop_reg vsd_yrgb_gt2;
431 struct vop_reg vsd_yrgb_gt4;
432 struct vop_reg bic_coe_sel;
433 struct vop_reg cbcr_axi_gather_en;
434 struct vop_reg yrgb_axi_gather_en;
435 struct vop_reg lb_mode;
436 };
437
438 struct vop_scl_regs {
439 const struct vop_scl_extension *ext;
440
441 struct vop_reg scale_yrgb_x;
442 struct vop_reg scale_yrgb_y;
443 struct vop_reg scale_cbcr_x;
444 struct vop_reg scale_cbcr_y;
445 };
446
447 struct vop_afbc {
448 struct vop_reg enable;
449 struct vop_reg win_sel;
450 struct vop_reg format;
451 struct vop_reg rb_swap;
452 struct vop_reg uv_swap;
453 struct vop_reg auto_gating_en;
454 struct vop_reg rotate;
455 struct vop_reg block_split_en;
456 struct vop_reg pic_vir_width;
457 struct vop_reg tile_num;
458 struct vop_reg pic_offset;
459 struct vop_reg pic_size;
460 struct vop_reg dsp_offset;
461 struct vop_reg transform_offset;
462 struct vop_reg hdr_ptr;
463 struct vop_reg half_block_en;
464 struct vop_reg xmirror;
465 struct vop_reg ymirror;
466 struct vop_reg rotate_270;
467 struct vop_reg rotate_90;
468 struct vop_reg rstn;
469 };
470
471 struct vop_csc_table {
472 const uint32_t *y2r_bt601;
473 const uint32_t *y2r_bt601_12_235;
474 const uint32_t *y2r_bt601_10bit;
475 const uint32_t *y2r_bt601_10bit_12_235;
476 const uint32_t *r2y_bt601;
477 const uint32_t *r2y_bt601_12_235;
478 const uint32_t *r2y_bt601_10bit;
479 const uint32_t *r2y_bt601_10bit_12_235;
480
481 const uint32_t *y2r_bt709;
482 const uint32_t *y2r_bt709_10bit;
483 const uint32_t *r2y_bt709;
484 const uint32_t *r2y_bt709_10bit;
485
486 const uint32_t *y2r_bt2020;
487 const uint32_t *r2y_bt2020;
488
489 const uint32_t *r2r_bt709_to_bt2020;
490 const uint32_t *r2r_bt2020_to_bt709;
491 };
492
493 struct vop_hdr_table {
494 const uint32_t hdr2sdr_eetf_oetf_y0_offset;
495 const uint32_t hdr2sdr_eetf_oetf_y1_offset;
496 const uint32_t *hdr2sdr_eetf_yn;
497 const uint32_t *hdr2sdr_bt1886oetf_yn;
498 const uint32_t hdr2sdr_sat_y0_offset;
499 const uint32_t hdr2sdr_sat_y1_offset;
500 const uint32_t *hdr2sdr_sat_yn;
501
502 const uint32_t hdr2sdr_src_range_min;
503 const uint32_t hdr2sdr_src_range_max;
504 const uint32_t hdr2sdr_normfaceetf;
505 const uint32_t hdr2sdr_dst_range_min;
506 const uint32_t hdr2sdr_dst_range_max;
507 const uint32_t hdr2sdr_normfacgamma;
508
509 const uint32_t sdr2hdr_eotf_oetf_y0_offset;
510 const uint32_t sdr2hdr_eotf_oetf_y1_offset;
511 const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr;
512 const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020;
513 const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr;
514 const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr;
515 const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020;
516 const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr;
517 const uint32_t sdr2hdr_oetf_dx_dxpow1_offset;
518 const uint32_t *sdr2hdr_st2084oetf_dxn_pow2;
519 const uint32_t *sdr2hdr_st2084oetf_dxn;
520 const uint32_t sdr2hdr_oetf_xn1_offset;
521 const uint32_t *sdr2hdr_st2084oetf_xn;
522 };
523
524 #define RK_HDRVIVID_TONE_SCA_TAB_LENGTH 257
525 #define RK_HDRVIVID_GAMMA_CURVE_LENGTH 81
526 #define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH 9
527 #define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH 69
528 #define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH 6
529 #define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH 6
530 #define RK_SDR2HDR_SMGAIN_LENGTH 64
531 #define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH 264
532
533 struct hdrvivid_regs {
534 uint32_t sdr2hdr_ctrl;
535 uint32_t sdr2hdr_coe0;
536 uint32_t sdr2hdr_coe1;
537 uint32_t sdr2hdr_csc_coe00_01;
538 uint32_t sdr2hdr_csc_coe02_10;
539 uint32_t sdr2hdr_csc_coe11_12;
540 uint32_t sdr2hdr_csc_coe20_21;
541 uint32_t sdr2hdr_csc_coe22;
542 uint32_t hdrvivid_ctrl;
543 uint32_t hdr_pq_gamma;
544 uint32_t hlg_rfix_scalefac;
545 uint32_t hlg_maxluma;
546 uint32_t hlg_r_tm_lin2non;
547 uint32_t hdr_csc_coe00_01;
548 uint32_t hdr_csc_coe02_10;
549 uint32_t hdr_csc_coe11_12;
550 uint32_t hdr_csc_coe20_21;
551 uint32_t hdr_csc_coe22;
552 uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
553 uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
554 uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
555 uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
556 uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
557 uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
558 uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
559 uint32_t hdr_mode;
560 uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
561 };
562
563 struct hdr_extend {
564 uint32_t hdr_type;
565 uint32_t length;
566 union {
567 struct hdrvivid_regs hdrvivid_data;
568 };
569 };
570
571 enum _vop_hdrvivid_mode {
572 PQHDR2HDR_WITH_DYNAMIC = 0,
573 PQHDR2SDR_WITH_DYNAMIC,
574 HLG2PQHDR_WITH_DYNAMIC,
575 HLG2SDR_WITH_DYNAMIC,
576 HLG2PQHDR_WITHOUT_DYNAMIC,
577 HLG2SDR_WITHOUT_DYNAMIC,
578 HDR_BYPASS,
579 HDR102SDR,
580 SDR2HDR10,
581 SDR2HLG,
582 SDR2HDR10_USERSPACE = 100,
583 SDR2HLG_USERSPACE = 101,
584 };
585
586 enum vop_hdr_format {
587 HDR_NONE = 0,
588 HDR_HDR10 = 1,
589 HDR_HLGSTATIC = 2,
590 RESERVED3 = 3, /* reserved for more future static hdr format */
591 RESERVED4 = 4, /* reserved for more future static hdr format */
592 HDR_HDRVIVID = 5,
593 RESERVED6 = 6, /* reserved for hdr vivid */
594 RESERVED7 = 7, /* reserved for hdr vivid */
595 HDR_HDR10PLUS = 8,
596 RESERVED9 = 9, /* reserved for hdr hdr10+ */
597 RESERVED10 = 10, /* reserved for hdr hdr10+ */
598 HDR_NEXT = 11,
599 RESERVED12 = 12, /* reserved for other dynamic hdr format */
600 RESERVED13 = 13, /* reserved for other dynamic hdr format */
601 HDR_FORMAT_MAX,
602 };
603
604 struct post_csc_coef {
605 s32 csc_coef00;
606 s32 csc_coef01;
607 s32 csc_coef02;
608 s32 csc_coef10;
609 s32 csc_coef11;
610 s32 csc_coef12;
611 s32 csc_coef20;
612 s32 csc_coef21;
613 s32 csc_coef22;
614
615 s32 csc_dc0;
616 s32 csc_dc1;
617 s32 csc_dc2;
618
619 u32 range_type;
620 };
621
622 enum {
623 VOP_CSC_Y2R_BT601,
624 VOP_CSC_Y2R_BT709,
625 VOP_CSC_Y2R_BT2020,
626 VOP_CSC_R2Y_BT601,
627 VOP_CSC_R2Y_BT709,
628 VOP_CSC_R2Y_BT2020,
629 VOP_CSC_R2R_BT2020_TO_BT709,
630 VOP_CSC_R2R_BT709_TO_2020,
631 };
632
633 enum _vop_overlay_mode {
634 VOP_RGB_DOMAIN,
635 VOP_YUV_DOMAIN
636 };
637
638 enum _vop_sdr2hdr_func {
639 SDR2HDR_FOR_BT2020,
640 SDR2HDR_FOR_HDR,
641 SDR2HDR_FOR_HLG_HDR,
642 };
643
644 enum _vop_rgb2rgb_conv_mode {
645 BT709_TO_BT2020,
646 BT2020_TO_BT709,
647 };
648
649 enum _MCU_IOCTL {
650 MCU_WRCMD = 0,
651 MCU_WRDATA,
652 MCU_SETBYPASS,
653 };
654
655 struct vop_win_phy {
656 const struct vop_scl_regs *scl;
657 const uint32_t *data_formats;
658 uint32_t nformats;
659
660 struct vop_reg gate;
661 struct vop_reg enable;
662 struct vop_reg format;
663 struct vop_reg interlace_read;
664 struct vop_reg fmt_10;
665 struct vop_reg fmt_yuyv;
666 struct vop_reg csc_mode;
667 struct vop_reg xmirror;
668 struct vop_reg ymirror;
669 struct vop_reg rb_swap;
670 struct vop_reg act_info;
671 struct vop_reg dsp_info;
672 struct vop_reg dsp_st;
673 struct vop_reg yrgb_mst;
674 struct vop_reg uv_mst;
675 struct vop_reg yrgb_vir;
676 struct vop_reg uv_vir;
677
678 struct vop_reg channel;
679 struct vop_reg dst_alpha_ctl;
680 struct vop_reg src_alpha_ctl;
681 struct vop_reg alpha_mode;
682 struct vop_reg alpha_en;
683 struct vop_reg alpha_pre_mul;
684 struct vop_reg global_alpha_val;
685 struct vop_reg color_key;
686 struct vop_reg color_key_en;
687 };
688
689 struct vop_win_data {
690 uint32_t base;
691 enum drm_plane_type type;
692 const struct vop_win_phy *phy;
693 const struct vop_win_phy **area;
694 const uint64_t *format_modifiers;
695 const struct vop_csc *csc;
696 unsigned int area_size;
697 u64 feature;
698 };
699
700 struct vop2_cluster_regs {
701 struct vop_reg enable;
702 struct vop_reg afbc_enable;
703 struct vop_reg lb_mode;
704 struct vop_reg scl_lb_mode;
705 struct vop_reg frm_reset_en;
706
707 struct vop_reg src_color_ctrl;
708 struct vop_reg dst_color_ctrl;
709 struct vop_reg src_alpha_ctrl;
710 struct vop_reg dst_alpha_ctrl;
711 };
712
713 struct vop2_scl_regs {
714 struct vop_reg scale_yrgb_x;
715 struct vop_reg scale_yrgb_y;
716 struct vop_reg scale_cbcr_x;
717 struct vop_reg scale_cbcr_y;
718 struct vop_reg yrgb_hor_scl_mode;
719 struct vop_reg yrgb_hscl_filter_mode;
720 struct vop_reg yrgb_ver_scl_mode;
721 struct vop_reg yrgb_vscl_filter_mode;
722 struct vop_reg cbcr_ver_scl_mode;
723 struct vop_reg cbcr_hscl_filter_mode;
724 struct vop_reg cbcr_hor_scl_mode;
725 struct vop_reg cbcr_vscl_filter_mode;
726 struct vop_reg vsd_cbcr_gt2;
727 struct vop_reg vsd_cbcr_gt4;
728 struct vop_reg vsd_yrgb_gt2;
729 struct vop_reg vsd_yrgb_gt4;
730 struct vop_reg bic_coe_sel;
731 struct vop_reg xavg_en; /* supported from vop3 */
732 struct vop_reg xgt_en;
733 struct vop_reg xgt_mode;
734 struct vop_reg vsd_avg2;
735 struct vop_reg vsd_avg4;
736 };
737
738 struct vop2_win_regs {
739 const struct vop2_scl_regs *scl;
740 const struct vop2_cluster_regs *cluster;
741 const struct vop_afbc *afbc;
742
743 struct vop_reg gate;
744 struct vop_reg enable;
745 struct vop_reg format;
746 struct vop_reg tile_mode;
747 struct vop_reg csc_mode;
748 struct vop_reg csc_13bit_en;
749 struct vop_reg xmirror;
750 struct vop_reg ymirror;
751 struct vop_reg rb_swap;
752 struct vop_reg uv_swap;
753 struct vop_reg act_info;
754 struct vop_reg dsp_info;
755 struct vop_reg dsp_st;
756 struct vop_reg yrgb_mst;
757 struct vop_reg uv_mst;
758 struct vop_reg yrgb_vir;
759 struct vop_reg uv_vir;
760 struct vop_reg yuv_clip;
761 struct vop_reg lb_mode;
762 struct vop_reg y2r_en;
763 struct vop_reg r2y_en;
764 struct vop_reg channel;
765 struct vop_reg dst_alpha_ctl;
766 struct vop_reg src_alpha_ctl;
767 struct vop_reg alpha_mode;
768 struct vop_reg alpha_en;
769 struct vop_reg global_alpha_val;
770 struct vop_reg color_key;
771 struct vop_reg color_key_en;
772 struct vop_reg dither_up;
773 struct vop_reg axi_id;
774 struct vop_reg axi_yrgb_id;
775 struct vop_reg axi_uv_id;
776 struct vop_reg scale_engine_num;
777 };
778
779 struct vop2_video_port_regs {
780 struct vop_reg cfg_done;
781 struct vop_reg overlay_mode;
782 struct vop_reg dsp_background;
783 struct vop_reg port_mux;
784 struct vop_reg out_mode;
785 struct vop_reg standby;
786 struct vop_reg dsp_interlace;
787 struct vop_reg dsp_filed_pol;
788 struct vop_reg dsp_data_swap;
789 struct vop_reg dsp_x_mir_en;
790 struct vop_reg post_dsp_out_r2y;
791 struct vop_reg pre_scan_htiming;
792 struct vop_reg htotal_pw;
793 struct vop_reg hact_st_end;
794 struct vop_reg dsp_vtotal;
795 struct vop_reg sw_dsp_vtotal_imd;
796 struct vop_reg dsp_vs_end;
797 struct vop_reg vact_st_end;
798 struct vop_reg vact_st_end_f1;
799 struct vop_reg vs_st_end_f1;
800 struct vop_reg hpost_st_end;
801 struct vop_reg vpost_st_end;
802 struct vop_reg vpost_st_end_f1;
803 struct vop_reg post_scl_factor;
804 struct vop_reg post_scl_ctrl;
805 struct vop_reg dither_down_sel;
806 struct vop_reg dither_down_mode;
807 struct vop_reg dither_down_en;
808 struct vop_reg pre_dither_down_en;
809 struct vop_reg dither_up_en;
810 struct vop_reg bg_dly;
811
812 struct vop_reg core_dclk_div;
813 struct vop_reg p2i_en;
814 struct vop_reg dual_channel_en;
815 struct vop_reg dual_channel_swap;
816 struct vop_reg dsp_lut_en;
817
818 struct vop_reg dclk_div2;
819 struct vop_reg dclk_div2_phase_lock;
820
821 struct vop_reg hdr10_en;
822 struct vop_reg hdr_lut_update_en;
823 struct vop_reg hdr_lut_mode;
824 struct vop_reg hdr_lut_mst;
825 struct vop_reg hdr_lut_fetch_done;
826 struct vop_reg hdr_vivid_en;
827 struct vop_reg hdr_vivid_bypass_en;
828 struct vop_reg hdr_vivid_path_mode;
829 struct vop_reg hdr_vivid_dstgamut;
830 struct vop_reg sdr2hdr_en;
831 struct vop_reg sdr2hdr_dstmode;
832 struct vop_reg sdr2hdr_eotf_en;
833 struct vop_reg sdr2hdr_r2r_en;
834 struct vop_reg sdr2hdr_r2r_mode;
835 struct vop_reg sdr2hdr_oetf_en;
836 struct vop_reg sdr2hdr_bypass_en;
837 struct vop_reg sdr2hdr_auto_gating_en;
838 struct vop_reg sdr2hdr_path_en;
839 struct vop_reg hdr2sdr_en;
840 struct vop_reg hdr2sdr_bypass_en;
841 struct vop_reg hdr2sdr_auto_gating_en;
842 struct vop_reg hdr2sdr_src_min;
843 struct vop_reg hdr2sdr_src_max;
844 struct vop_reg hdr2sdr_normfaceetf;
845 struct vop_reg hdr2sdr_dst_min;
846 struct vop_reg hdr2sdr_dst_max;
847 struct vop_reg hdr2sdr_normfacgamma;
848 uint32_t hdr2sdr_eetf_oetf_y0_offset;
849 uint32_t hdr2sdr_sat_y0_offset;
850 uint32_t sdr2hdr_eotf_oetf_y0_offset;
851 uint32_t sdr2hdr_oetf_dx_pow1_offset;
852 uint32_t sdr2hdr_oetf_xn1_offset;
853 struct vop_reg hdr_src_color_ctrl;
854 struct vop_reg hdr_dst_color_ctrl;
855 struct vop_reg hdr_src_alpha_ctrl;
856 struct vop_reg hdr_dst_alpha_ctrl;
857 struct vop_reg bg_mix_ctrl;
858 struct vop_reg layer_sel;
859
860 /* BCSH */
861 struct vop_reg bcsh_brightness;
862 struct vop_reg bcsh_contrast;
863 struct vop_reg bcsh_sat_con;
864 struct vop_reg bcsh_sin_hue;
865 struct vop_reg bcsh_cos_hue;
866 struct vop_reg bcsh_r2y_csc_mode;
867 struct vop_reg bcsh_r2y_en;
868 struct vop_reg bcsh_y2r_csc_mode;
869 struct vop_reg bcsh_y2r_en;
870 struct vop_reg bcsh_out_mode;
871 struct vop_reg bcsh_en;
872
873 /* 3d lut */
874 struct vop_reg cubic_lut_en;
875 struct vop_reg cubic_lut_update_en;
876 struct vop_reg cubic_lut_mst;
877
878 /* cru */
879 struct vop_reg dclk_core_div;
880 struct vop_reg dclk_out_div;
881 struct vop_reg dclk_src_sel;
882
883 struct vop_reg splice_en;
884
885 struct vop_reg edpi_wms_hold_en;
886 struct vop_reg edpi_te_en;
887 struct vop_reg edpi_wms_fs;
888 struct vop_reg gamma_update_en;
889 struct vop_reg lut_dma_rid;
890
891 /* MCU output */
892 struct vop_reg mcu_pix_total;
893 struct vop_reg mcu_cs_pst;
894 struct vop_reg mcu_cs_pend;
895 struct vop_reg mcu_rw_pst;
896 struct vop_reg mcu_rw_pend;
897 struct vop_reg mcu_clk_sel;
898 struct vop_reg mcu_hold_mode;
899 struct vop_reg mcu_frame_st;
900 struct vop_reg mcu_rs;
901 struct vop_reg mcu_bypass;
902 struct vop_reg mcu_type;
903 struct vop_reg mcu_rw_bypass_port;
904
905 /* for DCF */
906 struct vop_reg line_flag_or_en;
907 struct vop_reg dsp_hold_or_en;
908 struct vop_reg almost_full_or_en;
909
910 /* CSC */
911 struct vop_reg acm_bypass_en;
912 struct vop_reg csc_en;
913 struct vop_reg acm_r2y_en;
914 struct vop_reg csc_mode;
915 struct vop_reg acm_r2y_mode;
916 struct vop_reg csc_coe00;
917 struct vop_reg csc_coe01;
918 struct vop_reg csc_coe02;
919 struct vop_reg csc_coe10;
920 struct vop_reg csc_coe11;
921 struct vop_reg csc_coe12;
922 struct vop_reg csc_coe20;
923 struct vop_reg csc_coe21;
924 struct vop_reg csc_coe22;
925 struct vop_reg csc_offset0;
926 struct vop_reg csc_offset1;
927 struct vop_reg csc_offset2;
928
929 /* color bar */
930 struct vop_reg color_bar_en;
931 struct vop_reg color_bar_mode;
932 };
933
934 struct vop2_power_domain_regs {
935 struct vop_reg pd;
936 struct vop_reg status;
937 struct vop_reg bisr_en_status;
938 struct vop_reg pmu_status;
939 };
940
941 struct vop2_dsc_regs {
942 /* DSC SYS CTRL */
943 struct vop_reg dsc_port_sel;
944 struct vop_reg dsc_man_mode;
945 struct vop_reg dsc_interface_mode;
946 struct vop_reg dsc_pixel_num;
947 struct vop_reg dsc_pxl_clk_div;
948 struct vop_reg dsc_cds_clk_div;
949 struct vop_reg dsc_txp_clk_div;
950 struct vop_reg dsc_init_dly_mode;
951 struct vop_reg dsc_scan_en;
952 struct vop_reg dsc_halt_en;
953 struct vop_reg rst_deassert;
954 struct vop_reg dsc_flush;
955 struct vop_reg dsc_cfg_done;
956 struct vop_reg dsc_init_dly_num;
957 struct vop_reg scan_timing_para_imd_en;
958 struct vop_reg dsc_htotal_pw;
959 struct vop_reg dsc_hact_st_end;
960 struct vop_reg dsc_vtotal;
961 struct vop_reg dsc_vs_end;
962 struct vop_reg dsc_vact_st_end;
963 struct vop_reg dsc_error_status;
964
965 /* DSC encoder */
966 struct vop_reg dsc_pps0_3;
967 struct vop_reg dsc_en;
968 struct vop_reg dsc_rbit;
969 struct vop_reg dsc_rbyt;
970 struct vop_reg dsc_flal;
971 struct vop_reg dsc_mer;
972 struct vop_reg dsc_epb;
973 struct vop_reg dsc_epl;
974 struct vop_reg dsc_nslc;
975 struct vop_reg dsc_sbo;
976 struct vop_reg dsc_ifep;
977 struct vop_reg dsc_pps_upd;
978 struct vop_reg dsc_status;
979 struct vop_reg dsc_ecw;
980 };
981
982 struct vop2_wb_regs {
983 struct vop_reg enable;
984 struct vop_reg format;
985 struct vop_reg dither_en;
986 struct vop_reg r2y_en;
987 struct vop_reg yrgb_mst;
988 struct vop_reg uv_mst;
989 struct vop_reg vp_id;
990 struct vop_reg fifo_throd;
991 struct vop_reg scale_x_factor;
992 struct vop_reg scale_x_en;
993 struct vop_reg scale_y_en;
994 struct vop_reg axi_yrgb_id;
995 struct vop_reg axi_uv_id;
996 };
997
998 struct vop2_power_domain_data {
999 uint8_t id;
1000 uint8_t parent_id;
1001 /*
1002 * @module_id_mask: module id of which module this power domain is belongs to.
1003 * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
1004 */
1005 uint32_t module_id_mask;
1006
1007 const struct vop2_power_domain_regs *regs;
1008 };
1009
1010 /*
1011 * connector interface(RGB/HDMI/eDP/DP/MIPI) data
1012 */
1013 struct vop2_connector_if_data {
1014 u32 id;
1015 const char *clk_src_name;
1016 const char *clk_parent_name;
1017 const char *pixclk_name;
1018 const char *dclk_name;
1019 u32 post_proc_div_shift;
1020 u32 if_div_shift;
1021 u32 if_div_yuv420_shift;
1022 u32 bus_div_shift;
1023 u32 pixel_clk_div_shift;
1024 };
1025
1026 struct vop2_win_data {
1027 const char *name;
1028 uint8_t phys_id;
1029 uint8_t splice_win_id;
1030 uint8_t pd_id;
1031 uint8_t axi_id;
1032 uint8_t axi_yrgb_id;
1033 uint8_t axi_uv_id;
1034 uint8_t possible_crtcs;
1035
1036 uint32_t base;
1037 enum drm_plane_type type;
1038
1039 uint32_t nformats;
1040 const uint32_t *formats;
1041 const uint64_t *format_modifiers;
1042 const unsigned int supported_rotations;
1043
1044 const struct vop2_win_regs *regs;
1045 const struct vop2_win_regs **area;
1046 unsigned int area_size;
1047
1048 /*
1049 * vertical/horizontal scale up/down filter mode
1050 */
1051 const u8 hsu_filter_mode;
1052 const u8 hsd_filter_mode;
1053 const u8 vsu_filter_mode;
1054 const u8 vsd_filter_mode;
1055 const u8 hsd_pre_filter_mode;
1056 const u8 vsd_pre_filter_mode;
1057 /**
1058 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
1059 */
1060 const uint8_t layer_sel_id[ROCKCHIP_MAX_CRTC];
1061 uint64_t feature;
1062
1063 unsigned int max_upscale_factor;
1064 unsigned int max_downscale_factor;
1065 const uint8_t dly[VOP2_DLY_MODE_MAX];
1066 };
1067
1068 struct dsc_error_info {
1069 u32 dsc_error_val;
1070 char dsc_error_info[50];
1071 };
1072
1073 struct vop2_dsc_data {
1074 uint8_t id;
1075 uint8_t pd_id;
1076 uint8_t max_slice_num;
1077 uint8_t max_linebuf_depth; /* used to generate the bitstream */
1078 uint8_t min_bits_per_pixel; /* bit num after encoder compress */
1079 const char *dsc_txp_clk_src_name;
1080 const char *dsc_txp_clk_name;
1081 const char *dsc_pxl_clk_name;
1082 const char *dsc_cds_clk_name;
1083 const struct vop2_dsc_regs *regs;
1084 };
1085
1086 struct vop2_wb_data {
1087 uint32_t nformats;
1088 const uint32_t *formats;
1089 struct vop_rect max_output;
1090 const struct vop2_wb_regs *regs;
1091 uint32_t fifo_depth;
1092 };
1093
1094 struct vop3_ovl_mix_regs {
1095 struct vop_reg src_color_ctrl;
1096 struct vop_reg dst_color_ctrl;
1097 struct vop_reg src_alpha_ctrl;
1098 struct vop_reg dst_alpha_ctrl;
1099 };
1100
1101 struct vop3_ovl_regs {
1102 const struct vop3_ovl_mix_regs *layer_mix_regs;
1103 const struct vop3_ovl_mix_regs *hdr_mix_regs;
1104 };
1105
1106 struct vop2_video_port_data {
1107 char id;
1108 uint8_t splice_vp_id;
1109 uint16_t lut_dma_rid;
1110 uint32_t feature;
1111 uint64_t soc_id[VOP2_SOC_VARIANT];
1112 uint16_t gamma_lut_len;
1113 uint16_t cubic_lut_len;
1114 unsigned long dclk_max;
1115 struct vop_rect max_output;
1116 const u8 pre_scan_max_dly[4];
1117 const u8 hdrvivid_dly[10];
1118 const u8 sdr2hdr_dly;
1119 const u8 layer_mix_dly;
1120 const u8 hdr_mix_dly;
1121 const u8 win_dly;
1122 const struct vop_intr *intr;
1123 const struct vop_hdr_table *hdr_table;
1124 const struct vop2_video_port_regs *regs;
1125 const struct vop3_ovl_regs *ovl_regs;
1126 };
1127
1128 struct vop2_layer_regs {
1129 struct vop_reg layer_sel;
1130 };
1131
1132 /**
1133 * struct vop2_layer_data - The logic graphic layer in vop2
1134 *
1135 * The zorder:
1136 * LAYERn
1137 * LAYERn-1
1138 * .
1139 * .
1140 * .
1141 * LAYER5
1142 * LAYER4
1143 * LAYER3
1144 * LAYER2
1145 * LAYER1
1146 * LAYER0
1147 *
1148 * Each layer can select a unused window as input than feed to
1149 * mixer for overlay.
1150 *
1151 * The pipeline in vop2:
1152 *
1153 * win-->layer-->mixer-->vp--->connector(RGB/LVDS/HDMI/MIPI)
1154 *
1155 */
1156 struct vop2_layer_data {
1157 char id;
1158 const struct vop2_layer_regs *regs;
1159 };
1160
1161 struct vop_grf_ctrl {
1162 struct vop_reg grf_dclk_inv;
1163 struct vop_reg grf_bt1120_clk_inv;
1164 struct vop_reg grf_bt656_clk_inv;
1165 struct vop_reg grf_edp0_en;
1166 struct vop_reg grf_edp1_en;
1167 struct vop_reg grf_hdmi0_en;
1168 struct vop_reg grf_hdmi1_en;
1169 struct vop_reg grf_hdmi0_dsc_en;
1170 struct vop_reg grf_hdmi1_dsc_en;
1171 struct vop_reg grf_hdmi0_pin_pol;
1172 struct vop_reg grf_hdmi1_pin_pol;
1173 };
1174
1175 struct vop_data {
1176 const struct vop_reg_data *init_table;
1177 unsigned int table_size;
1178 const struct vop_ctrl *ctrl;
1179 const struct vop_intr *intr;
1180 const struct vop_win_data *win;
1181 const struct vop_csc_table *csc_table;
1182 const struct vop_hdr_table *hdr_table;
1183 const struct vop_grf_ctrl *grf_ctrl;
1184 unsigned int win_size;
1185 uint32_t version;
1186 struct vop_rect max_input;
1187 struct vop_rect max_output;
1188 u64 feature;
1189 u64 soc_id;
1190 u8 vop_id;
1191 };
1192
1193 struct vop2_ctrl {
1194 struct vop_reg cfg_done_en;
1195 struct vop_reg wb_cfg_done;
1196 struct vop_reg auto_gating_en;
1197 struct vop_reg aclk_pre_auto_gating_en;
1198 struct vop_reg dma_finish_mode;
1199 struct vop_reg axi_dma_finish_and_en;
1200 struct vop_reg wb_dma_finish_and_en;
1201 struct vop_reg ovl_cfg_done_port;
1202 struct vop_reg ovl_port_mux_cfg_done_imd;
1203 struct vop_reg ovl_port_mux_cfg;
1204 struct vop_reg if_ctrl_cfg_done_imd;
1205 struct vop_reg version;
1206 struct vop_reg standby;
1207 struct vop_reg dma_stop;
1208 struct vop_reg dsp_vs_t_sel;
1209 struct vop_reg lut_dma_en;
1210 struct vop_reg axi_outstanding_max_num;
1211 struct vop_reg axi_max_outstanding_en;
1212 struct vop_reg hdmi_dclk_out_en;
1213 struct vop_reg rgb_en;
1214 struct vop_reg hdmi0_en;
1215 struct vop_reg hdmi1_en;
1216 struct vop_reg dp0_en;
1217 struct vop_reg dp1_en;
1218 struct vop_reg edp0_en;
1219 struct vop_reg edp1_en;
1220 struct vop_reg mipi0_en;
1221 struct vop_reg mipi1_en;
1222 struct vop_reg lvds0_en;
1223 struct vop_reg lvds1_en;
1224 struct vop_reg bt656_en;
1225 struct vop_reg bt1120_en;
1226 struct vop_reg bt656_dclk_pol;
1227 struct vop_reg bt1120_dclk_pol;
1228 struct vop_reg dclk_pol;
1229 struct vop_reg pin_pol;
1230 struct vop_reg rgb_dclk_pol;
1231 struct vop_reg rgb_pin_pol;
1232 struct vop_reg lvds_dclk_pol;
1233 struct vop_reg lvds_pin_pol;
1234 struct vop_reg hdmi_dclk_pol;
1235 struct vop_reg hdmi_pin_pol;
1236 struct vop_reg edp_dclk_pol;
1237 struct vop_reg edp_pin_pol;
1238 struct vop_reg mipi_dclk_pol;
1239 struct vop_reg mipi_pin_pol;
1240 struct vop_reg dp0_dclk_pol;
1241 struct vop_reg dp0_pin_pol;
1242 struct vop_reg dp1_dclk_pol;
1243 struct vop_reg dp1_pin_pol;
1244
1245 /* This will be reference by win_phy_id */
1246 struct vop_reg win_vp_id[16];
1247 struct vop_reg win_dly[16];
1248
1249 /* connector mux */
1250 struct vop_reg rgb_mux;
1251 struct vop_reg hdmi0_mux;
1252 struct vop_reg hdmi1_mux;
1253 struct vop_reg dp0_mux;
1254 struct vop_reg dp1_mux;
1255 struct vop_reg edp0_mux;
1256 struct vop_reg edp1_mux;
1257 struct vop_reg mipi0_mux;
1258 struct vop_reg mipi1_mux;
1259 struct vop_reg lvds0_mux;
1260 struct vop_reg lvds1_mux;
1261
1262 struct vop_reg lvds_dual_en;
1263 struct vop_reg lvds_dual_mode;
1264 struct vop_reg lvds_dual_channel_swap;
1265
1266 struct vop_reg dp_dual_en;
1267 struct vop_reg edp_dual_en;
1268 struct vop_reg hdmi_dual_en;
1269 struct vop_reg mipi_dual_en;
1270
1271 struct vop_reg hdmi0_dclk_div;
1272 struct vop_reg hdmi0_pixclk_div;
1273 struct vop_reg edp0_dclk_div;
1274 struct vop_reg edp0_pixclk_div;
1275
1276 struct vop_reg hdmi1_dclk_div;
1277 struct vop_reg hdmi1_pixclk_div;
1278 struct vop_reg edp1_dclk_div;
1279 struct vop_reg edp1_pixclk_div;
1280
1281 struct vop_reg mipi0_pixclk_div;
1282 struct vop_reg mipi1_pixclk_div;
1283 struct vop_reg mipi0_ds_mode;
1284 struct vop_reg mipi1_ds_mode;
1285
1286 struct vop_reg src_color_ctrl;
1287 struct vop_reg dst_color_ctrl;
1288 struct vop_reg src_alpha_ctrl;
1289 struct vop_reg dst_alpha_ctrl;
1290
1291 struct vop_reg bt1120_yc_swap;
1292 struct vop_reg bt656_yc_swap;
1293 struct vop_reg gamma_port_sel;
1294 struct vop_reg pd_off_imd;
1295
1296 struct vop_reg otp_en;
1297 struct vop_reg esmart_lb_mode;
1298 struct vop_reg reg_done_frm;
1299 struct vop_reg cfg_done;
1300 };
1301
1302 struct vop_dump_regs {
1303 uint32_t offset;
1304 const char *name;
1305 struct vop_reg state;
1306 bool enable_state;
1307 };
1308
1309 struct vop2_vp_plane_mask {
1310 u8 primary_plane_id;
1311 u8 attached_layers_nr;
1312 u8 attached_layers[ROCKCHIP_MAX_LAYER];
1313 };
1314
1315 /**
1316 * VOP2 data structe
1317 *
1318 * @version: VOP IP version
1319 * @win_size: hardware win number
1320 */
1321 struct vop2_data {
1322 uint32_t version;
1323 uint32_t feature;
1324 uint8_t nr_dscs;
1325 uint8_t nr_dsc_ecw;
1326 uint8_t nr_dsc_buffer_flow;
1327 uint8_t nr_vps;
1328 uint8_t nr_mixers;
1329 uint8_t nr_layers;
1330 uint8_t nr_axi_intr;
1331 uint8_t nr_gammas;
1332 uint8_t nr_conns;
1333 uint8_t nr_pds;
1334 uint8_t nr_mem_pgs;
1335 uint8_t esmart_lb_mode;
1336 bool delayed_pd;
1337 const struct vop_intr *axi_intr;
1338 const struct vop2_ctrl *ctrl;
1339 const struct vop2_dsc_data *dsc;
1340 const struct dsc_error_info *dsc_error_ecw;
1341 const struct dsc_error_info *dsc_error_buffer_flow;
1342 const struct vop2_win_data *win;
1343 const struct vop2_video_port_data *vp;
1344 const struct vop2_connector_if_data *conn;
1345 const struct vop2_wb_data *wb;
1346 const struct vop2_layer_data *layer;
1347 const struct vop2_power_domain_data *pd;
1348 const struct vop2_power_domain_data *mem_pg;
1349 const struct vop_csc_table *csc_table;
1350 const struct vop_hdr_table *hdr_table;
1351 const struct vop_grf_ctrl *sys_grf;
1352 const struct vop_grf_ctrl *grf;
1353 const struct vop_grf_ctrl *vo0_grf;
1354 const struct vop_grf_ctrl *vo1_grf;
1355 const struct vop_dump_regs *dump_regs;
1356 uint32_t dump_regs_size;
1357 struct vop_rect max_input;
1358 struct vop_rect max_output;
1359 const struct vop2_vp_plane_mask *plane_mask;
1360 uint32_t plane_mask_base;
1361
1362 unsigned int win_size;
1363 };
1364
1365 #define CVBS_PAL_VDISPLAY 288
1366
1367 /* interrupt define */
1368 #define DSP_HOLD_VALID_INTR BIT(0)
1369 #define FS_INTR BIT(1)
1370 #define LINE_FLAG_INTR BIT(2)
1371 #define BUS_ERROR_INTR BIT(3)
1372 #define FS_NEW_INTR BIT(4)
1373 #define ADDR_SAME_INTR BIT(5)
1374 #define LINE_FLAG1_INTR BIT(6)
1375 #define WIN0_EMPTY_INTR BIT(7)
1376 #define WIN1_EMPTY_INTR BIT(8)
1377 #define WIN2_EMPTY_INTR BIT(9)
1378 #define WIN3_EMPTY_INTR BIT(10)
1379 #define HWC_EMPTY_INTR BIT(11)
1380 #define POST_BUF_EMPTY_INTR BIT(12)
1381 #define PWM_GEN_INTR BIT(13)
1382 #define DMA_FINISH_INTR BIT(14)
1383 #define FS_FIELD_INTR BIT(15)
1384 #define FE_INTR BIT(16)
1385 #define WB_UV_FIFO_FULL_INTR BIT(17)
1386 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
1387 #define WB_COMPLETE_INTR BIT(19)
1388
1389 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
1390 LINE_FLAG_INTR | BUS_ERROR_INTR | \
1391 FS_NEW_INTR | LINE_FLAG1_INTR | \
1392 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
1393 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
1394 HWC_EMPTY_INTR | \
1395 POST_BUF_EMPTY_INTR | \
1396 DMA_FINISH_INTR | FS_FIELD_INTR | \
1397 FE_INTR)
1398 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
1399 #define FS_INTR_EN(x) ((x) << 5)
1400 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
1401 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
1402 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
1403 #define FS_INTR_MASK (1 << 5)
1404 #define LINE_FLAG_INTR_MASK (1 << 6)
1405 #define BUS_ERROR_INTR_MASK (1 << 7)
1406
1407 #define INTR_CLR_SHIFT 8
1408 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
1409 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
1410 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
1411 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
1412
1413 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
1414 #define DSP_LINE_NUM_MASK (0x1fff << 12)
1415
1416 /* src alpha ctrl define */
1417 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
1418 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
1419 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
1420 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
1421 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
1422 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
1423 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
1424 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
1425 /* dst alpha ctrl define */
1426 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
1427
1428 /*
1429 * display output interface supported by rockchip lcdc
1430 */
1431 #define ROCKCHIP_OUT_MODE_P888 0
1432 #define ROCKCHIP_OUT_MODE_BT1120 0
1433 #define ROCKCHIP_OUT_MODE_P666 1
1434 #define ROCKCHIP_OUT_MODE_P565 2
1435 #define ROCKCHIP_OUT_MODE_BT656 5
1436 #define ROCKCHIP_OUT_MODE_S888 8
1437 #define ROCKCHIP_OUT_MODE_S666 9
1438 #define ROCKCHIP_OUT_MODE_YUV422 9
1439 #define ROCKCHIP_OUT_MODE_S565 10
1440 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1441 #define ROCKCHIP_OUT_MODE_YUV420 14
1442 /* for use special outface */
1443 #define ROCKCHIP_OUT_MODE_AAAA 15
1444
1445 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
1446 #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
1447
1448 enum alpha_mode {
1449 ALPHA_STRAIGHT,
1450 ALPHA_INVERSE,
1451 };
1452
1453 enum global_blend_mode {
1454 ALPHA_GLOBAL,
1455 ALPHA_PER_PIX,
1456 ALPHA_PER_PIX_GLOBAL,
1457 };
1458
1459 enum alpha_cal_mode {
1460 ALPHA_SATURATION,
1461 ALPHA_NO_SATURATION,
1462 };
1463
1464 enum color_mode {
1465 ALPHA_SRC_PRE_MUL,
1466 ALPHA_SRC_NO_PRE_MUL,
1467 };
1468
1469 enum factor_mode {
1470 ALPHA_ZERO,
1471 ALPHA_ONE,
1472 ALPHA_SRC,
1473 ALPHA_SRC_INVERSE,
1474 ALPHA_SRC_GLOBAL,
1475 ALPHA_DST_GLOBAL,
1476 };
1477
1478 enum src_factor_mode {
1479 SRC_FAC_ALPHA_ZERO,
1480 SRC_FAC_ALPHA_ONE,
1481 SRC_FAC_ALPHA_DST,
1482 SRC_FAC_ALPHA_DST_INVERSE,
1483 SRC_FAC_ALPHA_SRC,
1484 SRC_FAC_ALPHA_SRC_GLOBAL,
1485 };
1486
1487 enum dst_factor_mode {
1488 DST_FAC_ALPHA_ZERO,
1489 DST_FAC_ALPHA_ONE,
1490 DST_FAC_ALPHA_SRC,
1491 DST_FAC_ALPHA_SRC_INVERSE,
1492 DST_FAC_ALPHA_DST,
1493 DST_FAC_ALPHA_DST_GLOBAL,
1494 };
1495
1496 enum scale_mode {
1497 SCALE_NONE = 0x0,
1498 SCALE_UP = 0x1,
1499 SCALE_DOWN = 0x2
1500 };
1501
1502 enum lb_mode {
1503 LB_YUV_3840X5 = 0x0,
1504 LB_YUV_2560X8 = 0x1,
1505 LB_RGB_3840X2 = 0x2,
1506 LB_RGB_2560X4 = 0x3,
1507 LB_RGB_1920X5 = 0x4,
1508 LB_RGB_1280X8 = 0x5
1509 };
1510
1511 enum sacle_up_mode {
1512 SCALE_UP_BIL = 0x0,
1513 SCALE_UP_BIC = 0x1
1514 };
1515
1516 enum scale_down_mode {
1517 SCALE_DOWN_BIL = 0x0,
1518 SCALE_DOWN_AVG = 0x1
1519 };
1520
1521 enum vop2_scale_up_mode {
1522 VOP2_SCALE_UP_NRST_NBOR,
1523 VOP2_SCALE_UP_BIL,
1524 VOP2_SCALE_UP_BIC,
1525 };
1526
1527 enum vop2_scale_down_mode {
1528 VOP2_SCALE_DOWN_NRST_NBOR,
1529 VOP2_SCALE_DOWN_BIL,
1530 VOP2_SCALE_DOWN_AVG,
1531 };
1532
1533 enum vop3_pre_scale_down_mode {
1534 VOP3_PRE_SCALE_UNSPPORT,
1535 VOP3_PRE_SCALE_DOWN_GT,
1536 VOP3_PRE_SCALE_DOWN_AVG,
1537 };
1538
1539 enum dither_down_mode {
1540 RGB888_TO_RGB565 = 0x0,
1541 RGB888_TO_RGB666 = 0x1
1542 };
1543
1544 enum dither_down_mode_sel {
1545 DITHER_DOWN_ALLEGRO = 0x0,
1546 DITHER_DOWN_FRC = 0x1
1547 };
1548
1549 enum vop_pol {
1550 HSYNC_POSITIVE = 0,
1551 VSYNC_POSITIVE = 1,
1552 DEN_NEGATIVE = 2,
1553 DCLK_INVERT = 3
1554 };
1555
1556
1557 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1558 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1559 #define SCL_MAX_VSKIPLINES 4
1560 #define MIN_SCL_FT_AFTER_VSKIP 1
1561
scl_cal_scale(int src,int dst,int shift)1562 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
1563 {
1564 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
1565 }
1566
scl_cal_scale2(int src,int dst)1567 static inline uint16_t scl_cal_scale2(int src, int dst)
1568 {
1569 return ((src - 1) << 12) / (dst - 1);
1570 }
1571
1572 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
1573 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
1574 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
1575
scl_get_bili_dn_vskip(int src_h,int dst_h,int vskiplines)1576 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
1577 int vskiplines)
1578 {
1579 int act_height;
1580
1581 act_height = (src_h + vskiplines - 1) / vskiplines;
1582
1583 if (act_height == dst_h)
1584 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
1585
1586 return GET_SCL_FT_BILI_DN(act_height, dst_h);
1587 }
1588
scl_get_scl_mode(int src,int dst)1589 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
1590 {
1591 if (src < dst)
1592 return SCALE_UP;
1593 else if (src > dst)
1594 return SCALE_DOWN;
1595
1596 return SCALE_NONE;
1597 }
1598
scl_get_vskiplines(uint32_t srch,uint32_t dsth)1599 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
1600 {
1601 uint32_t vskiplines;
1602
1603 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
1604 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
1605 break;
1606
1607 return vskiplines;
1608 }
1609
scl_vop_cal_lb_mode(int width,bool is_yuv)1610 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
1611 {
1612 int lb_mode;
1613
1614 if (is_yuv) {
1615 if (width > 1280)
1616 lb_mode = LB_YUV_3840X5;
1617 else
1618 lb_mode = LB_YUV_2560X8;
1619 } else {
1620 if (width > 2560)
1621 lb_mode = LB_RGB_3840X2;
1622 else if (width > 1920)
1623 lb_mode = LB_RGB_2560X4;
1624 else
1625 lb_mode = LB_RGB_1920X5;
1626 }
1627
1628 return lb_mode;
1629 }
1630
us_to_vertical_line(struct drm_display_mode * mode,int us)1631 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
1632 {
1633 return us * mode->clock / mode->htotal / 1000;
1634 }
1635
interpolate(int x1,int y1,int x2,int y2,int x)1636 static inline int interpolate(int x1, int y1, int x2, int y2, int x)
1637 {
1638 return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1639 }
1640
1641 extern const struct component_ops vop_component_ops;
1642 extern const struct component_ops vop2_component_ops;
1643 #endif /* _ROCKCHIP_DRM_VOP_H */
1644