1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "phydm_precomp.h"
18
19 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
20 #if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
21 #include "rtl8197f/Hal8197FPhyReg.h"
22 #include "WlanHAL/HalMac88XX/halmac_reg2.h"
23 #else
24 #include "WlanHAL/HalHeader/HalComReg.h"
25 #endif
26 #endif
27
28 #if (PHYDM_LA_MODE_SUPPORT == 1)
29
30 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
31
32 #if WPP_SOFTWARE_TRACE
33 #include "phydm_adc_sampling.tmh"
34 #endif
35
36 #endif
37
38 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
39 boolean
phydm_la_buffer_allocate(void * p_dm_void)40 phydm_la_buffer_allocate(
41 void *p_dm_void
42 )
43 {
44 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
45 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
46 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
47 struct _ADAPTER *adapter = p_dm->adapter;
48 #endif
49 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
50 boolean ret = false;
51
52 dbg_print("[LA mode BufferAllocate]\n");
53
54 if (adc_smp_buf->length == 0) {
55
56 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
57 if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) {
58 #else
59 odm_allocate_memory(p_dm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size);
60 if (!adc_smp_buf->octet) {
61 #endif
62 ret = false;
63 } else
64 adc_smp_buf->length = adc_smp_buf->buffer_size;
65 ret = true;
66 }
67
68 return ret;
69 }
70 #endif
71
72 void
73 phydm_la_get_tx_pkt_buf(
74 void *p_dm_void
75 )
76 {
77 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
78 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
79 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
80 u32 i = 0, value32, data_l = 0, data_h = 0;
81 u32 addr, finish_addr;
82 u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/
83 boolean is_round_up;
84 static u32 page = 0xFF;
85 u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
86 u8 backup_dma = 0;
87
88 odm_memory_set(p_dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
89 odm_write_1byte(p_dm, 0x0106, 0x69);
90
91 dbg_print("GetTxPktBuf\n");
92
93 value32 = odm_read_4byte(p_dm, 0x7c0);
94 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
95 finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
96
97 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
98 #if (RTL8197F_SUPPORT)
99 if (p_dm->support_ic_type & ODM_RTL8197F) {
100 odm_set_bb_reg(p_dm, 0x7c0, BIT(0), 0x0);
101
102 /*Stop DMA*/
103 backup_dma = odm_get_mac_reg(p_dm, 0x300, MASKLWORD);
104 odm_set_mac_reg(p_dm, 0x300, 0x7fff, 0x7fff);
105
106 /*move LA mode content from IMEM to TxPktBuffer
107 Source : OCPBASE_IMEM 0x00000000
108 Destination : OCPBASE_TXBUF 0x18780000
109 Length : 64K*/
110 GET_HAL_INTERFACE(p_dm->priv)->init_ddma_handler(p_dm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
111 }
112 #endif
113 #endif
114
115 if (is_round_up) {
116 addr = (finish_addr + 1) << 3;
117 dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32);
118 smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 8Byte (64bit)*/
119 } else {
120 addr = adc_smp_buf->start_pos;
121 addr_8byte = addr >> 3;
122
123 if (addr_8byte > finish_addr)
124 smp_number = addr_8byte - finish_addr;
125 else
126 smp_number = finish_addr - addr_8byte;
127
128 dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number);
129
130 }
131 /*
132 dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32);
133 dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size);
134 */
135
136 if (p_dm->support_ic_type & ODM_RTL8197F) {
137 for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/
138 if ((addr & 0xfff) == 0)
139 odm_set_bb_reg(p_dm, 0x0140, MASKLWORD, 0x780 + (addr >> 12));
140 data_l = odm_get_bb_reg(p_dm, 0x8000 + (addr & 0xfff), MASKDWORD);
141 data_h = odm_get_bb_reg(p_dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
142
143 dbg_print("%08x%08x\n", data_h, data_l);
144 }
145 } else {
146
147 i = 0;
148 while (addr != (finish_addr << 3)) {
149 if (page != (addr >> 12)) {
150 /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/
151 page = (addr >> 12);
152 }
153 odm_set_bb_reg(p_dm, 0x0140, MASKLWORD, 0x780 + page);
154
155 /*pDataL = 0x8000+(addr&0xfff);*/
156 data_l = odm_get_bb_reg(p_dm, 0x8000 + (addr & 0xfff), MASKDWORD);
157 data_h = odm_get_bb_reg(p_dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
158
159 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
160 adc_smp_buf->octet[i] = data_h;
161 adc_smp_buf->octet[i + 1] = data_l;
162 #endif
163
164 #if DBG /*WIN driver check build*/
165 dbg_print("%08x%08x\n", data_h, data_l);
166 #else /*WIN driver free build*/
167 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
168 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
169 #endif
170 #endif
171
172 i = i + 2;
173
174 if ((addr + 8) >= end_addr)
175 addr = adc_smp_buf->start_pos;
176 else
177 addr = addr + 8;
178
179 smp_cnt++;
180 if (smp_cnt >= (smp_number - 1))
181 break;
182 }
183 dbg_print("smp_cnt = ((%d))\n", smp_cnt);
184
185 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
186 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt));
187 #endif
188 }
189
190 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
191 #if (RTL8197F_SUPPORT)
192 if (p_dm->support_ic_type & ODM_RTL8197F)
193 odm_set_mac_reg(p_dm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/
194 #endif
195 #endif
196 }
197
198 void
199 phydm_la_mode_set_mac_iq_dump(
200 void *p_dm_void
201 )
202 {
203 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
204 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
205 u32 reg_value;
206
207 odm_write_1byte(p_dm, 0x7c0, 0); /*clear all 0x7c0*/
208 odm_set_mac_reg(p_dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
209
210 if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
211
212 adc_smp->is_bb_trigger = 0;
213 odm_set_mac_reg(p_dm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/
214 odm_set_mac_reg(p_dm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/
215
216 dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port);
217 /*[Set MAC Debug Port]*/
218 odm_set_mac_reg(p_dm, 0xF4, BIT(16), 1);
219 odm_set_mac_reg(p_dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
220 odm_set_mac_reg(p_dm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel);
221 odm_set_mac_reg(p_dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
222
223 } else {
224
225 adc_smp->is_bb_trigger = 1;
226 odm_set_mac_reg(p_dm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/
227
228 if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
229
230 odm_set_mac_reg(p_dm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/
231 odm_set_mac_reg(p_dm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel);
232
233 if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
234 odm_set_mac_reg(p_dm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/
235 }
236 }
237
238 reg_value = odm_get_bb_reg(p_dm, 0x7c0, 0xff);
239 dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
240 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
241 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value));
242 #endif
243
244 }
245
246 void
247 phydm_adc_smp_start(
248 void *p_dm_void
249 )
250 {
251 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
252 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
253 u8 tmp_u1b;
254 u8 while_cnt = 0;
255 u8 polling_ok = false, target_polling_bit;
256
257 phydm_la_mode_bb_setting(p_dm);
258 phydm_la_mode_set_trigger_time(p_dm, adc_smp->la_trigger_time);
259
260 if (p_dm->support_ic_type & ODM_RTL8197F)
261 odm_set_bb_reg(p_dm, 0xd00, BIT(26), 0x1);
262 else { /*for 8814A and 8822B?*/
263 odm_write_1byte(p_dm, 0x8b4, 0x80);
264 /* odm_set_bb_reg(p_dm, 0x8b4, BIT(7), 1); */
265 }
266
267 phydm_la_mode_set_mac_iq_dump(p_dm);
268
269 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
270 watchdog_stop(p_dm->priv);
271 #endif
272
273 target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
274 do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/
275 tmp_u1b = odm_read_1byte(p_dm, 0x7c0);
276
277 if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
278 dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
279 break;
280
281 } else if (tmp_u1b & target_polling_bit) {
282 ODM_delay_ms(100);
283 while_cnt = while_cnt + 1;
284 continue;
285 } else {
286 dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit);
287 polling_ok = true;
288 break;
289 }
290 } while (while_cnt < 20);
291
292 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
293
294 if (polling_ok)
295 phydm_la_get_tx_pkt_buf(p_dm);
296 else
297 dbg_print("[Polling timeout]\n");
298 }
299
300 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
301 watchdog_resume(p_dm->priv);
302 #endif
303
304 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
305 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
306 adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
307 #endif
308
309 dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count);
310 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
311 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count));
312 #endif
313
314
315 adc_smp_stop(p_dm);
316
317 if (adc_smp->la_count == 0) {
318 dbg_print("LA Dump finished ---------->\n\n\n");
319 phydm_release_bb_dbg_port(p_dm);
320
321 if ((p_dm->support_ic_type & ODM_RTL8821C) && (p_dm->cut_version >= ODM_CUT_B))
322 odm_set_bb_reg(p_dm, 0x95c, BIT(23), 0);
323
324 } else {
325 adc_smp->la_count--;
326 dbg_print("LA Dump more ---------->\n\n\n");
327 adc_smp_set(p_dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
328 }
329
330 }
331
332 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
333 void
334 adc_smp_work_item_callback(
335 void *p_context
336 )
337 {
338 struct _ADAPTER *adapter = (struct _ADAPTER *)p_context;
339 PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
340 struct PHY_DM_STRUCT *p_dm = &p_hal_data->DM_OutSrc;
341 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
342
343 dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state);
344 phydm_adc_smp_start(p_dm);
345 }
346 #endif
347
348 void
349 adc_smp_set(
350 void *p_dm_void,
351 u8 trig_mode,
352 u32 trig_sig_sel,
353 u8 dma_data_sig_sel,
354 u32 trigger_time,
355 u16 polling_time
356 )
357 {
358 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
359 boolean is_set_success = true;
360 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
361
362 adc_smp->la_trig_mode = trig_mode;
363 adc_smp->la_trig_sig_sel = trig_sig_sel;
364 adc_smp->la_dma_type = dma_data_sig_sel;
365 adc_smp->la_trigger_time = trigger_time;
366
367 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
368 if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
369 is_set_success = false;
370 else if (adc_smp->adc_smp_buf.length == 0)
371 is_set_success = phydm_la_buffer_allocate(p_dm);
372 #endif
373
374 if (is_set_success) {
375 adc_smp->adc_smp_state = ADCSMP_STATE_SET;
376
377 dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state);
378
379 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
380
381 dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index);
382 if (adc_smp->la_work_item_index != 0) {
383 odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1));
384 adc_smp->la_work_item_index = 0;
385 } else {
386 odm_schedule_work_item(&(adc_smp->adc_smp_work_item));
387 adc_smp->la_work_item_index = 1;
388 }
389 #else
390 phydm_adc_smp_start(p_dm);
391 #endif
392 } else
393 dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state);
394
395
396 }
397
398 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
399 enum rt_status
400 adc_smp_query(
401 void *p_dm_void,
402 ULONG information_buffer_length,
403 void *information_buffer,
404 PULONG bytes_written
405 )
406 {
407 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
408 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
409 enum rt_status ret_status = RT_STATUS_SUCCESS;
410 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
411
412 dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state);
413
414 if (information_buffer_length != adc_smp_buf->buffer_size) {
415 *bytes_written = 0;
416 ret_status = RT_STATUS_RESOURCE;
417 } else if (adc_smp_buf->length != adc_smp_buf->buffer_size) {
418 *bytes_written = 0;
419 ret_status = RT_STATUS_RESOURCE;
420 } else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
421 *bytes_written = 0;
422 ret_status = RT_STATUS_PENDING;
423 } else {
424 odm_move_memory(p_dm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size);
425 *bytes_written = adc_smp_buf->buffer_size;
426
427 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
428 }
429
430 dbg_print("Return status %d\n", ret_status);
431
432 return ret_status;
433 }
434 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
435
436 void
437 adc_smp_query(
438 void *p_dm_void,
439 void *output,
440 u32 out_len,
441 u32 *pused
442 )
443 {
444 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
445 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
446 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
447 u32 used = *pused;
448 u32 i;
449 /* struct timespec t; */
450 /* rtw_get_current_timespec(&t); */
451
452 dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state);
453
454 for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
455 PHYDM_SNPRINTF((output + used, out_len - used,
456 "%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
457 }
458
459 PHYDM_SNPRINTF((output + used, out_len - used, "\n"));
460 /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */
461 *pused = used;
462 }
463
464 s32
465 adc_smp_get_sample_counts(
466 void *p_dm_void
467 )
468 {
469 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
470 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
471 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
472
473 return (adc_smp_buf->length >> 2) - 2;
474 }
475
476 s32
477 adc_smp_query_single_data(
478 void *p_dm_void,
479 void *output,
480 u32 out_len,
481 u32 index
482 )
483 {
484 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
485 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
486 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
487 u32 used = 0;
488
489 /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */
490 if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
491 PHYDM_SNPRINTF((output + used, out_len - used,
492 "Error: la data is not ready yet ...\n"));
493 return -1;
494 }
495
496 if (index < ((adc_smp_buf->length >> 2) - 2)) {
497 PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n",
498 adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1]));
499 }
500 return 0;
501 }
502
503 #endif
504
505 void
506 adc_smp_stop(
507 void *p_dm_void
508 )
509 {
510 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
511 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
512
513 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
514 dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state);
515 }
516
517 void
518 adc_smp_init(
519 void *p_dm_void
520 )
521 {
522 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
523 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
524 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
525
526 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
527
528 if (p_dm->support_ic_type & ODM_RTL8814A) {
529 adc_smp_buf->start_pos = 0x30000;
530 adc_smp_buf->buffer_size = 0x10000;
531 } else if (p_dm->support_ic_type & ODM_RTL8822B) {
532 adc_smp_buf->start_pos = 0x20000;
533 adc_smp_buf->buffer_size = 0x20000;
534 } else if (p_dm->support_ic_type & ODM_RTL8197F) {
535 adc_smp_buf->start_pos = 0x00000;
536 adc_smp_buf->buffer_size = 0x10000;
537 } else if (p_dm->support_ic_type & ODM_RTL8821C) {
538 adc_smp_buf->start_pos = 0x8000;
539 adc_smp_buf->buffer_size = 0x8000;
540 }
541
542 }
543
544 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
545 void
546 adc_smp_de_init(
547 void *p_dm_void
548 )
549 {
550 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
551 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
552 struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
553
554 adc_smp_stop(p_dm);
555
556 if (adc_smp_buf->length != 0x0) {
557 odm_free_memory(p_dm, adc_smp_buf->octet, adc_smp_buf->length);
558 adc_smp_buf->length = 0x0;
559 }
560 }
561
562 #endif
563
564
565 void
566 phydm_la_mode_bb_setting(
567 void *p_dm_void
568 )
569 {
570 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
571 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
572
573 u8 trig_mode = adc_smp->la_trig_mode;
574 u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
575 u32 dbg_port = adc_smp->la_dbg_port;
576 u8 is_trigger_edge = adc_smp->la_trigger_edge;
577 u8 sampling_rate = adc_smp->la_smp_rate;
578 u8 la_dma_type = adc_smp->la_dma_type;
579 u32 dbg_port_header_sel = 0;
580
581 dbg_print("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
582 trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type);
583
584 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
585 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
586 trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type));
587 #endif
588
589 if (trig_mode == PHYDM_MAC_TRIG)
590 trig_sig_sel = 0; /*ignore this setting*/
591
592 /*set BB debug port*/
593 if (phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_3, dbg_port)) {
594 dbg_print("Set dbg_port((0x%x)) success\n", dbg_port);
595 }
596
597 if (p_dm->support_ic_type & ODM_IC_11AC_SERIES) {
598
599 if (trig_mode == PHYDM_ADC_RF0_TRIG)
600 dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/
601 else if (trig_mode == PHYDM_ADC_RF1_TRIG)
602 dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/
603 else if ((trig_mode == PHYDM_ADC_BB_TRIG) || (trig_mode == PHYDM_ADC_MAC_TRIG)) {
604
605 if (adc_smp->la_mac_mask_or_hdr_sel <= 0xf) {
606 dbg_port_header_sel = adc_smp->la_mac_mask_or_hdr_sel;
607 } else {
608 dbg_port_header_sel = 0;
609 }
610 }
611
612 phydm_bb_dbg_port_header_sel(p_dm, dbg_port_header_sel);
613
614 odm_set_bb_reg(p_dm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/
615 odm_set_bb_reg(p_dm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/
616 odm_set_bb_reg(p_dm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
617 odm_set_bb_reg(p_dm, 0x95c, 0xe0, sampling_rate);
618 /* (0:) '80MHz'
619 (1:) '40MHz'
620 (2:) '20MHz'
621 (3:) '10MHz'
622 (4:) '5MHz'
623 (5:) '2.5MHz'
624 (6:) '1.25MHz'
625 (7:) '160MHz (for BW160 ic)'
626 */
627 if ((p_dm->support_ic_type & ODM_RTL8821C) && (p_dm->cut_version >= ODM_CUT_B)) {
628 odm_set_bb_reg(p_dm, 0x95c, BIT(23), 1);
629 }
630 } else {
631
632 odm_set_bb_reg(p_dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
633 odm_set_bb_reg(p_dm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/
634 odm_set_bb_reg(p_dm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
635 odm_set_bb_reg(p_dm, 0x9A0, 0xe0, sampling_rate);
636 /* (0:) '80MHz'
637 (1:) '40MHz'
638 (2:) '20MHz'
639 (3:) '10MHz'
640 (4:) '5MHz'
641 (5:) '2.5MHz'
642 (6:) '1.25MHz'
643 (7:) '160MHz (for BW160 ic)'
644 */
645 }
646 }
647
648 void
649 phydm_la_mode_set_trigger_time(
650 void *p_dm_void,
651 u32 trigger_time_mu_sec
652 )
653 {
654 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
655 u8 trigger_time_unit_num;
656 u32 time_unit = 0;
657
658 if (trigger_time_mu_sec < 128) {
659 time_unit = 0; /*unit: 1mu sec*/
660 } else if (trigger_time_mu_sec < 256) {
661 time_unit = 1; /*unit: 2mu sec*/
662 } else if (trigger_time_mu_sec < 512) {
663 time_unit = 2; /*unit: 4mu sec*/
664 } else if (trigger_time_mu_sec < 1024) {
665 time_unit = 3; /*unit: 8mu sec*/
666 } else if (trigger_time_mu_sec < 2048) {
667 time_unit = 4; /*unit: 16mu sec*/
668 } else if (trigger_time_mu_sec < 4096) {
669 time_unit = 5; /*unit: 32mu sec*/
670 } else if (trigger_time_mu_sec < 8192) {
671 time_unit = 6; /*unit: 64mu sec*/
672 }
673
674 trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
675
676 dbg_print("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit);
677 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
678 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit));
679 #endif
680
681 odm_set_mac_reg(p_dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
682 odm_set_mac_reg(p_dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
683
684 }
685
686
687 void
688 phydm_lamode_trigger_setting(
689 void *p_dm_void,
690 char input[][16],
691 u32 *_used,
692 char *output,
693 u32 *_out_len,
694 u32 input_num
695 )
696 {
697 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
698 struct _RT_ADCSMP *adc_smp = &(p_dm->adcsmp);
699 u8 trig_mode, dma_data_sig_sel;
700 u32 trig_sig_sel;
701 boolean is_enable_la_mode;
702 u32 trigger_time_mu_sec;
703 char help[] = "-h";
704 u32 var1[10] = {0};
705 u32 used = *_used;
706 u32 out_len = *_out_len;
707
708 if (p_dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
709
710 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
711 is_enable_la_mode = (boolean)var1[0];
712 /*dbg_print("echo cmd input_num = %d\n", input_num);*/
713
714 if ((strcmp(input[1], help) == 0)) {
715 PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n"));
716 /**/
717 } else if ((is_enable_la_mode == 1)) {
718
719 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
720
721 trig_mode = (u8)var1[1];
722
723 if (trig_mode == PHYDM_MAC_TRIG)
724 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
725 else
726 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
727 trig_sig_sel = var1[2];
728
729 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
730 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
731 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
732 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
733 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
734 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
735 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
736
737 dma_data_sig_sel = (u8)var1[3];
738 trigger_time_mu_sec = var1[4]; /*unit: us*/
739
740 adc_smp->la_mac_mask_or_hdr_sel = var1[5];
741 adc_smp->la_dbg_port = var1[6];
742 adc_smp->la_trigger_edge = (u8) var1[7];
743 adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
744 adc_smp->la_count = var1[9];
745
746
747 dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]);
748 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
749 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]));
750 #endif
751
752 PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel));
753 PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_dbg_port));
754 PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count));
755
756 adc_smp_set(p_dm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0);
757
758 } else {
759 adc_smp_stop(p_dm);
760 PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n"));
761 }
762 }
763 *_used = used;
764 *_out_len = out_len;
765 }
766
767 #endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/
768