1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef __AWINIC_DATA_TYPE_H__ 4 #define __AWINIC_DATA_TYPE_H__ 5 6 #define AW_NAME_BUF_MAX (50) 7 8 9 /****************************************************************** 10 * aw profile 11 *******************************************************************/ 12 #define PROJECT_NAME_MAX (24) 13 #define CUSTOMER_NAME_MAX (16) 14 #define CFG_VERSION_MAX (4) 15 #define DEV_NAME_MAX (16) 16 #define PROFILE_STR_MAX (32) 17 18 #define ACF_FILE_ID (0xa15f908) 19 20 struct aw_msg_hdr { 21 int32_t type; 22 int32_t opcode_id; 23 int32_t version; 24 int32_t reseriver[3]; 25 }; 26 27 enum aw_cfg_hdr_version { 28 AW_CFG_HDR_VER_0_0_0_1 = 0x00000001, 29 AW_CFG_HDR_VER_1_0_0_0 = 0x01000000, 30 }; 31 32 enum aw_cfg_dde_type { 33 AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF, 34 AW_DEV_TYPE_ID = 0x00000000, 35 AW_SKT_TYPE_ID = 0x00000001, 36 AW_DEV_DEFAULT_TYPE_ID = 0x00000002, 37 }; 38 39 enum aw_sec_type { 40 ACF_SEC_TYPE_REG = 0, 41 ACF_SEC_TYPE_DSP, 42 ACF_SEC_TYPE_DSP_CFG, 43 ACF_SEC_TYPE_DSP_FW, 44 ACF_SEC_TYPE_HDR_REG, 45 ACF_SEC_TYPE_HDR_DSP_CFG, 46 ACF_SEC_TYPE_HDR_DSP_FW, 47 ACF_SEC_TYPE_MUTLBIN, 48 ACF_SEC_TYPE_SKT_PROJECT, 49 ACF_SEC_TYPE_DSP_PROJECT, 50 ACF_SEC_TYPE_MONITOR, 51 ACF_SEC_TYPE_MAX, 52 }; 53 54 enum profile_data_type { 55 AW_DATA_TYPE_REG = 0, 56 AW_DATA_TYPE_DSP_CFG, 57 AW_DATA_TYPE_DSP_FW, 58 AW_DATA_TYPE_MAX, 59 }; 60 61 enum aw_prof_type { 62 AW_PROFILE_MUSIC = 0, 63 AW_PROFILE_VOICE, 64 AW_PROFILE_VOIP, 65 AW_PROFILE_RINGTONE, 66 AW_PROFILE_RINGTONE_HS, 67 AW_PROFILE_LOWPOWER, 68 AW_PROFILE_BYPASS, 69 AW_PROFILE_MMI, 70 AW_PROFILE_FM, 71 AW_PROFILE_NOTIFICATION, 72 AW_PROFILE_RECEIVER, 73 AW_PROFILE_MAX, 74 }; 75 76 enum aw_profile_status { 77 AW_PROFILE_WAIT = 0, 78 AW_PROFILE_OK, 79 }; 80 81 struct aw_cfg_hdr { 82 uint32_t a_id; /*acf file ID 0xa15f908*/ 83 char a_project[PROJECT_NAME_MAX]; /*project name*/ 84 char a_custom[CUSTOMER_NAME_MAX]; /*custom name :huawei xiaomi vivo oppo*/ 85 char a_version[CFG_VERSION_MAX]; /*author update version*/ 86 uint32_t a_author_id; /*author id*/ 87 uint32_t a_ddt_size; /*sub section table entry size*/ 88 uint32_t a_ddt_num; /*sub section table entry num*/ 89 uint32_t a_hdr_offset; /*sub section table offset in file*/ 90 uint32_t a_hdr_version; /*sub section table version*/ 91 uint32_t reserve[3]; 92 }; 93 94 struct aw_cfg_dde { 95 uint32_t type; /*DDE type id*/ 96 char dev_name[DEV_NAME_MAX]; 97 uint16_t dev_index; /*dev id*/ 98 uint16_t dev_bus; /*dev bus id*/ 99 uint16_t dev_addr; /*dev addr id*/ 100 uint16_t dev_profile; /*dev profile id*/ 101 uint32_t data_type; /*data type id*/ 102 uint32_t data_size; 103 uint32_t data_offset; 104 uint32_t data_crc; 105 uint32_t reserve[5]; 106 }; 107 108 struct aw_cfg_dde_v_1_0_0_0 { 109 uint32_t type; /*DDE type id*/ 110 char dev_name[DEV_NAME_MAX]; 111 uint16_t dev_index; /*dev id*/ 112 uint16_t dev_bus; /*dev bus id*/ 113 uint16_t dev_addr; /*dev addr id*/ 114 uint16_t dev_profile; /*dev profile id*/ 115 uint32_t data_type; /*data type id*/ 116 uint32_t data_size; 117 uint32_t data_offset; 118 uint32_t data_crc; 119 char dev_profile_str[PROFILE_STR_MAX]; 120 uint32_t chip_id; 121 uint32_t reserve[4]; 122 }; 123 124 struct aw_sec_data_desc { 125 uint32_t len; 126 unsigned char *data; 127 }; 128 129 struct aw_prof_desc { 130 uint32_t id; 131 uint32_t prof_st; 132 char *prf_str; 133 uint32_t fw_ver; 134 struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX]; 135 }; 136 137 struct aw_all_prof_info { 138 struct aw_prof_desc prof_desc[AW_PROFILE_MAX]; 139 }; 140 141 struct aw_prof_info { 142 int count; 143 int prof_type; 144 char **prof_name_list; 145 struct aw_prof_desc *prof_desc; 146 }; 147 148 149 #endif 150 151