1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _SDIO_HALINIT_C_
16
17 #include <rtl8723b_hal.h>
18 #include "hal_com_h2c.h"
19
20 /*
21 * Description:
22 * Call power on sequence to enable card
23 *
24 * Return:
25 * _SUCCESS enable success
26 * _FAIL enable fail
27 */
CardEnable(PADAPTER padapter)28 static u8 CardEnable(PADAPTER padapter)
29 {
30 u8 bMacPwrCtrlOn;
31 u8 ret = _FAIL;
32
33
34 bMacPwrCtrlOn = _FALSE;
35 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
36 if (bMacPwrCtrlOn == _FALSE) {
37 /* RSV_CTRL 0x1C[7:0] = 0x00 */
38 /* unlock ISO/CLK/Power control register */
39 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
40
41 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
42 if (ret == _SUCCESS) {
43 u8 bMacPwrCtrlOn = _TRUE;
44 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
45 }
46 } else
47 ret = _SUCCESS;
48
49 return ret;
50 }
51
52 /* static */
_InitPowerOn_8723BS(PADAPTER padapter)53 u32 _InitPowerOn_8723BS(PADAPTER padapter)
54 {
55 u8 value8;
56 u16 value16;
57 u32 value32;
58 u8 ret;
59 u8 pwron_chk_cnt = 0;
60 /* u8 bMacPwrCtrlOn; */
61
62 _init_power_on:
63
64 #if 1
65 /* all of these MUST be configured before power on */
66 #ifdef CONFIG_XTAL_26M
67 /* Config PLL Reference CLK, */
68 /* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
69 /* APLL_FREF_SEL[0]=1b'1 */
70 value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
71 value8 |= BIT(2);
72 rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
73 /* APLL_FREF_SEL[2:1]=2b'10 */
74 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723B + 1);
75 value8 &= ~(BIT(1) | BIT(0));
76 value8 |= BIT(1);
77 rtw_write16(padapter, REG_AFE_CTRL_4_8723B + 1, value8);
78 /* APLL_FREF_SEL[3]=1b'0 */
79 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723B);
80 value8 &= ~BIT(7);
81 rtw_write16(padapter, REG_AFE_CTRL_4_8723B, value8);
82 #endif /* CONFIG_XTAL_26M */
83
84 #ifdef CONFIG_EXT_CLK
85 /* Use external crystal(XTAL) */
86 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B + 2);
87 value8 |= BIT(7);
88 rtw_write8(padapter, REG_PAD_CTRL1_8723B + 2, value8);
89
90 /* CLK_REQ High active or Low Active */
91 /* Request GPIO polarity: */
92 /* 0: low active */
93 /* 1: high active */
94 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
95 value8 |= BIT(5);
96 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
97 #endif /* CONFIG_EXT_CLK */
98 #endif /* all of these MUST be configured before power on */
99
100 /* only cmd52 can be used before power on(card enable) */
101 ret = CardEnable(padapter);
102 if (ret == _FALSE) {
103 return _FAIL;
104 }
105
106 /* Radio-Off Pin Trigger */
107 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
108 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
109 rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
110 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
111 value8 |= BIT(1);
112 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
113
114 /* Enable power down and GPIO interrupt */
115 value16 = rtw_read16(padapter, REG_APS_FSMCO);
116 value16 |= EnPDN; /* Enable HW power down and RF on */
117 rtw_write16(padapter, REG_APS_FSMCO, value16);
118
119 /* Enable CMD53 R/W Operation
120 * bMacPwrCtrlOn = _TRUE;
121 * rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
122
123 rtw_write8(padapter, REG_CR, 0x00);
124 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
125 value16 = rtw_read16(padapter, REG_CR);
126 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
127 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
128 rtw_write16(padapter, REG_CR, value16);
129
130
131 /* PowerOnCheck() */
132 ret = sdio_power_on_check(padapter);
133 pwron_chk_cnt++;
134 if (_FAIL == ret) {
135 if (pwron_chk_cnt > 1) {
136 RTW_INFO("Failed to init Power On!\n");
137 return _FAIL;
138 }
139 RTW_INFO("Power on Fail! do it again\n");
140 goto _init_power_on;
141 }
142
143 return _SUCCESS;
144 }
145
146 /* Tx Page FIFO threshold */
_init_available_page_threshold(PADAPTER padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)147 static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
148 {
149 u16 HQ_threshold, NQ_threshold, LQ_threshold;
150
151 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
152 HQ_threshold |= (HQ_threshold << 8);
153
154 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
155 NQ_threshold |= (NQ_threshold << 8);
156
157 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
158 LQ_threshold |= (LQ_threshold << 8);
159
160 rtw_write16(padapter, 0x218, HQ_threshold);
161 rtw_write16(padapter, 0x21A, NQ_threshold);
162 rtw_write16(padapter, 0x21C, LQ_threshold);
163 RTW_INFO("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
164 }
165
_InitQueueReservedPage(PADAPTER padapter)166 static void _InitQueueReservedPage(PADAPTER padapter)
167 {
168 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
169 struct registry_priv *pregistrypriv = &padapter->registrypriv;
170 u32 outEPNum = (u32)pHalData->OutEpNumber;
171 u32 numHQ = 0;
172 u32 numLQ = 0;
173 u32 numNQ = 0;
174 u32 numPubQ;
175 u32 value32;
176 u8 value8;
177 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
178
179 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
180 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
181
182 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
183 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
184
185 /* NOTE: This step shall be proceed before writting REG_RQPN. */
186 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
187 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
188
189 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
190
191 value8 = (u8)_NPQ(numNQ);
192 rtw_write8(padapter, REG_RQPN_NPQ, value8);
193
194 /* TX DMA */
195 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
196 rtw_write32(padapter, REG_RQPN, value32);
197
198 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
199
200 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
201 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
202 #endif
203 }
204
_InitTxBufferBoundary(PADAPTER padapter)205 static void _InitTxBufferBoundary(PADAPTER padapter)
206 {
207 struct registry_priv *pregistrypriv = &padapter->registrypriv;
208 #ifdef CONFIG_CONCURRENT_MODE
209 u8 val8;
210 #endif /* CONFIG_CONCURRENT_MODE */
211
212 /* u16 txdmactrl; */
213 u8 txpktbuf_bndy;
214
215 if (!pregistrypriv->wifi_spec)
216 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
217 else {
218 /* for WMM */
219 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
220 }
221
222 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
223 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
224 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
225 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
226 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
227
228 #ifdef CONFIG_CONCURRENT_MODE
229 val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8723B + WOWLAN_PAGE_NUM_8723B;
230 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
231 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B + 1, val8); /* BCN1_HEAD */
232
233 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B + 2);
234 val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
235 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B + 2, val8);
236 #endif /* CONFIG_CONCURRENT_MODE */
237 }
238
239 static VOID
_InitNormalChipRegPriority(IN PADAPTER Adapter,IN u16 beQ,IN u16 bkQ,IN u16 viQ,IN u16 voQ,IN u16 mgtQ,IN u16 hiQ)240 _InitNormalChipRegPriority(
241 IN PADAPTER Adapter,
242 IN u16 beQ,
243 IN u16 bkQ,
244 IN u16 viQ,
245 IN u16 voQ,
246 IN u16 mgtQ,
247 IN u16 hiQ
248 )
249 {
250 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
251
252 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
253 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
254 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
255
256 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
257 }
258
259 static VOID
_InitNormalChipOneOutEpPriority(IN PADAPTER Adapter)260 _InitNormalChipOneOutEpPriority(
261 IN PADAPTER Adapter
262 )
263 {
264 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
265
266 u16 value = 0;
267 switch (pHalData->OutEpQueueSel) {
268 case TX_SELE_HQ:
269 value = QUEUE_HIGH;
270 break;
271 case TX_SELE_LQ:
272 value = QUEUE_LOW;
273 break;
274 case TX_SELE_NQ:
275 value = QUEUE_NORMAL;
276 break;
277 default:
278 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
279 break;
280 }
281
282 _InitNormalChipRegPriority(Adapter,
283 value,
284 value,
285 value,
286 value,
287 value,
288 value
289 );
290
291 }
292
293 static VOID
_InitNormalChipTwoOutEpPriority(IN PADAPTER Adapter)294 _InitNormalChipTwoOutEpPriority(
295 IN PADAPTER Adapter
296 )
297 {
298 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
299 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
300 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
301
302
303 u16 valueHi = 0;
304 u16 valueLow = 0;
305
306 switch (pHalData->OutEpQueueSel) {
307 case (TX_SELE_HQ | TX_SELE_LQ):
308 valueHi = QUEUE_HIGH;
309 valueLow = QUEUE_LOW;
310 break;
311 case (TX_SELE_NQ | TX_SELE_LQ):
312 valueHi = QUEUE_NORMAL;
313 valueLow = QUEUE_LOW;
314 break;
315 case (TX_SELE_HQ | TX_SELE_NQ):
316 valueHi = QUEUE_HIGH;
317 valueLow = QUEUE_NORMAL;
318 break;
319 default:
320 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
321 break;
322 }
323
324 if (!pregistrypriv->wifi_spec) {
325 beQ = valueLow;
326 bkQ = valueLow;
327 viQ = valueHi;
328 voQ = valueHi;
329 mgtQ = valueHi;
330 hiQ = valueHi;
331 } else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
332 beQ = valueLow;
333 bkQ = valueHi;
334 viQ = valueHi;
335 voQ = valueLow;
336 mgtQ = valueHi;
337 hiQ = valueHi;
338 }
339
340 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
341
342 }
343
344 static VOID
_InitNormalChipThreeOutEpPriority(IN PADAPTER padapter)345 _InitNormalChipThreeOutEpPriority(
346 IN PADAPTER padapter
347 )
348 {
349 struct registry_priv *pregistrypriv = &padapter->registrypriv;
350 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
351
352 if (!pregistrypriv->wifi_spec) { /* typical setting */
353 beQ = QUEUE_LOW;
354 bkQ = QUEUE_LOW;
355 viQ = QUEUE_NORMAL;
356 voQ = QUEUE_HIGH;
357 mgtQ = QUEUE_HIGH;
358 hiQ = QUEUE_HIGH;
359 } else { /* for WMM */
360 beQ = QUEUE_LOW;
361 bkQ = QUEUE_NORMAL;
362 viQ = QUEUE_NORMAL;
363 voQ = QUEUE_HIGH;
364 mgtQ = QUEUE_HIGH;
365 hiQ = QUEUE_HIGH;
366 }
367 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
368 }
369
370 static VOID
_InitNormalChipQueuePriority(IN PADAPTER Adapter)371 _InitNormalChipQueuePriority(
372 IN PADAPTER Adapter
373 )
374 {
375 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
376
377 switch (pHalData->OutEpNumber) {
378 case 1:
379 _InitNormalChipOneOutEpPriority(Adapter);
380 break;
381 case 2:
382 _InitNormalChipTwoOutEpPriority(Adapter);
383 break;
384 case 3:
385 _InitNormalChipThreeOutEpPriority(Adapter);
386 break;
387 default:
388 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
389 break;
390 }
391
392
393 }
394
_InitQueuePriority(PADAPTER padapter)395 static void _InitQueuePriority(PADAPTER padapter)
396 {
397 _InitNormalChipQueuePriority(padapter);
398 }
399
_InitPageBoundary(PADAPTER padapter)400 static void _InitPageBoundary(PADAPTER padapter)
401 {
402 /* RX Page Boundary */
403 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
404
405 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
406 }
407
_InitTransferPageSize(PADAPTER padapter)408 static void _InitTransferPageSize(PADAPTER padapter)
409 {
410 /* Tx page size is always 128. */
411
412 u8 value8;
413 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
414 rtw_write8(padapter, REG_PBP, value8);
415 }
416
_InitDriverInfoSize(PADAPTER padapter,u8 drvInfoSize)417 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
418 {
419 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
420 }
421
_InitNetworkType(PADAPTER padapter)422 void _InitNetworkType(PADAPTER padapter)
423 {
424 u32 value32;
425
426 value32 = rtw_read32(padapter, REG_CR);
427
428 /* TODO: use the other function to set network type
429 * value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
430 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
431
432 rtw_write32(padapter, REG_CR, value32);
433 }
434
_InitWMACSetting(PADAPTER padapter)435 void _InitWMACSetting(PADAPTER padapter)
436 {
437 PHAL_DATA_TYPE pHalData;
438 u16 value16;
439 u32 rcr;
440
441 pHalData = GET_HAL_DATA(padapter);
442
443 rcr = 0
444 | RCR_APM | RCR_AM | RCR_AB
445 | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
446 | RCR_HTC_LOC_CTRL
447 | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
448 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
449 | RCR_AAP
450 | RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
451 #endif
452 ;
453 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
454
455 /* Accept all multicast address */
456 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
457 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
458
459 /* Accept all data frames */
460 value16 = 0xFFFF;
461 rtw_write16(padapter, REG_RXFLTMAP2, value16);
462
463 /* 2010.09.08 hpfan */
464 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
465 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
466 value16 = 0x400;
467 rtw_write16(padapter, REG_RXFLTMAP1, value16);
468
469 /* Accept all management frames */
470 value16 = 0xFFFF;
471 rtw_write16(padapter, REG_RXFLTMAP0, value16);
472 }
473
_InitAdaptiveCtrl(PADAPTER padapter)474 void _InitAdaptiveCtrl(PADAPTER padapter)
475 {
476 u16 value16;
477 u32 value32;
478
479 /* Response Rate Set */
480 value32 = rtw_read32(padapter, REG_RRSR);
481 value32 &= ~RATE_BITMAP_ALL;
482 value32 |= RATE_RRSR_CCK_ONLY_1M;
483 rtw_write32(padapter, REG_RRSR, value32);
484
485 /* CF-END Threshold */
486 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
487
488 /* SIFS (used in NAV) */
489 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
490 rtw_write16(padapter, REG_SPEC_SIFS, value16);
491
492 /* Retry Limit */
493 value16 = _LRL(RL_VAL_STA) | _SRL(RL_VAL_STA);
494 rtw_write16(padapter, REG_RL, value16);
495 }
496
_InitEDCA(PADAPTER padapter)497 void _InitEDCA(PADAPTER padapter)
498 {
499 /* Set Spec SIFS (used in NAV) */
500 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
501 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
502
503 /* Set SIFS for CCK */
504 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
505
506 /* Set SIFS for OFDM */
507 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
508
509 /* TXOP */
510 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
511 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
512 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
513 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
514 }
515
_InitRetryFunction(PADAPTER padapter)516 void _InitRetryFunction(PADAPTER padapter)
517 {
518 u8 value8;
519
520 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
521 value8 |= EN_AMPDU_RTY_NEW;
522 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
523
524 /* Set ACK timeout */
525 rtw_write8(padapter, REG_ACKTO, 0x40);
526 }
527
HalRxAggr8723BSdio(PADAPTER padapter)528 static void HalRxAggr8723BSdio(PADAPTER padapter)
529 {
530 struct registry_priv *pregistrypriv;
531 u8 valueDMATimeout;
532 u8 valueDMAPageCount;
533
534
535 pregistrypriv = &padapter->registrypriv;
536
537 if (pregistrypriv->wifi_spec) {
538 /* 2010.04.27 hpfan */
539 /* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
540 /* Timeout value is calculated by 34 / (2^n) */
541 valueDMATimeout = 0x06;
542 valueDMAPageCount = 0x06;
543 } else {
544 /* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
545 #if 1
546 /* TX/RX Balance */
547 valueDMATimeout = 0x06;
548 valueDMAPageCount = 0x06;
549 #endif
550 #if 0
551 /* TX/RX Balance, but TCP ack may be late */
552 valueDMATimeout = 0x16;
553 valueDMAPageCount = 0x06;
554 #endif
555 #if 0
556 /* RX Best */
557 valueDMATimeout = 0x16;
558 valueDMAPageCount = 0x08;
559 #endif
560 }
561
562 #ifdef CONFIG_DONT_CARE_TP
563 valueDMATimeout = 0x0f;
564 valueDMAPageCount = 0x04; /* RxAggUpthreshold = [4]*1K bytes+1.5k. since RxAggUpthreshold+SzAmsdu(3839)<MaxRxBuffSize(8k), MaxvalueDMAPageCount=4. */
565 #endif
566 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
567 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
568 }
569
sdio_AggSettingRxUpdate(PADAPTER padapter)570 void sdio_AggSettingRxUpdate(PADAPTER padapter)
571 {
572 HAL_DATA_TYPE *pHalData;
573 u8 valueDMA;
574 u8 valueRxAggCtrl = 0;
575 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
576 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
577
578 pHalData = GET_HAL_DATA(padapter);
579
580 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
581 valueDMA |= RXDMA_AGG_EN;
582 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
583
584 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
585 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
586 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
587 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
588 }
589
_initSdioAggregationSetting(PADAPTER padapter)590 void _initSdioAggregationSetting(PADAPTER padapter)
591 {
592 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
593
594 /* Tx aggregation setting
595 * sdio_AggSettingTxUpdate(padapter); */
596
597 /* Rx aggregation setting */
598 HalRxAggr8723BSdio(padapter);
599
600 sdio_AggSettingRxUpdate(padapter);
601 }
602
_RXAggrSwitch(PADAPTER padapter,u8 enable)603 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
604 {
605 PHAL_DATA_TYPE pHalData;
606 u8 valueDMA;
607 u8 valueRxAggCtrl;
608
609
610 pHalData = GET_HAL_DATA(padapter);
611
612 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
613 valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8723B);
614
615 if (_TRUE == enable) {
616 valueDMA |= RXDMA_AGG_EN;
617 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
618 } else {
619 valueDMA &= ~RXDMA_AGG_EN;
620 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
621 }
622
623 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
624 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);
625 }
626
_InitInterrupt(PADAPTER padapter)627 void _InitInterrupt(PADAPTER padapter)
628 {
629 /* */
630 /* Initialize and enable SDIO Host Interrupt. */
631 /* */
632 InitInterrupt8723BSdio(padapter);
633
634 /* */
635 /* Initialize system Host Interrupt. */
636 /* */
637 InitSysInterrupt8723BSdio(padapter);
638 }
639
_InitRDGSetting(PADAPTER padapter)640 void _InitRDGSetting(PADAPTER padapter)
641 {
642 rtw_write8(padapter, REG_RD_CTRL, 0xFF);
643 rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
644 rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
645 }
646
_InitRFType(PADAPTER padapter)647 static void _InitRFType(PADAPTER padapter)
648 {
649 struct registry_priv *pregpriv = &padapter->registrypriv;
650 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
651
652 #if DISABLE_BB_RF
653 pHalData->rf_chip = RF_PSEUDO_11N;
654 return;
655 #endif
656 pHalData->rf_chip = RF_6052;
657
658 RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
659 }
660
661 /* Set CCK and OFDM Block "ON" */
_BBTurnOnBlock(PADAPTER padapter)662 static void _BBTurnOnBlock(PADAPTER padapter)
663 {
664 #if (DISABLE_BB_RF)
665 return;
666 #endif
667
668 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
669 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
670 }
671
_RfPowerSave(PADAPTER padapter)672 static void _RfPowerSave(PADAPTER padapter)
673 {
674 /* YJ,TODO */
675 }
676
_InitAntenna_Selection(PADAPTER padapter)677 static void _InitAntenna_Selection(PADAPTER padapter)
678 {
679 rtw_write8(padapter, REG_LEDCFG2, 0x82);
680 }
681
_InitPABias(PADAPTER padapter)682 static void _InitPABias(PADAPTER padapter)
683 {
684 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
685 u8 pa_setting;
686
687 /* FIXED PA current issue */
688 /* efuse_one_byte_read(padapter, 0x1FA, &pa_setting); */
689 efuse_OneByteRead(padapter, 0x1FA, &pa_setting, _FALSE);
690
691
692 if (!(pa_setting & BIT0)) {
693 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
694 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
695 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
696 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
697 }
698
699 if (!(pa_setting & BIT4)) {
700 pa_setting = rtw_read8(padapter, 0x16);
701 pa_setting &= 0x0F;
702 rtw_write8(padapter, 0x16, pa_setting | 0x80);
703 rtw_write8(padapter, 0x16, pa_setting | 0x90);
704 }
705 }
706
707 /*
708 * 2010/08/09 MH Add for power down check.
709 * */
HalDetectPwrDownMode(PADAPTER Adapter)710 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
711 {
712 u8 tmpvalue;
713 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
714 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
715
716
717 EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8723B, (u32 *)&tmpvalue);
718
719 /* 2010/08/25 MH INF priority > PDN Efuse value. */
720 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
721 pHalData->pwrdown = _TRUE;
722 else
723 pHalData->pwrdown = _FALSE;
724
725 RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
726
727 return pHalData->pwrdown;
728 } /* HalDetectPwrDownMode */
729
rtl8723bs_hal_init(PADAPTER padapter)730 static u32 rtl8723bs_hal_init(PADAPTER padapter)
731 {
732 s32 ret;
733 PHAL_DATA_TYPE pHalData;
734 struct pwrctrl_priv *pwrctrlpriv;
735 struct registry_priv *pregistrypriv;
736 struct sreset_priv *psrtpriv;
737 struct dvobj_priv *psdpriv = padapter->dvobj;
738 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
739
740 rt_rf_power_state eRfPowerStateToSet;
741 u32 NavUpper = WiFiNavUpperUs;
742 u8 u1bTmp;
743 u16 value16;
744 u8 typeid;
745 u32 u4Tmp;
746
747 pHalData = GET_HAL_DATA(padapter);
748 psrtpriv = &pHalData->srestpriv;
749 pwrctrlpriv = adapter_to_pwrctl(padapter);
750 pregistrypriv = &padapter->registrypriv;
751
752 /*For AW H64 platform rf interference issue only!*/
753 #ifdef CONFIG_SDIO_PAD_DRIVING_CTRL
754 phy_set_bb_reg(padapter, 0x74, BIT7|BIT6|BIT5|BIT4, 0x2);
755 #endif
756 #ifdef CONFIG_SWLPS_IN_IPS
757 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
758 u8 val8, bMacPwrCtrlOn = _TRUE;
759
760 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
761
762 /* ser rpwm */
763 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
764 val8 &= 0x80;
765 val8 += 0x80;
766 val8 |= BIT(6);
767 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
768
769 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
770
771 rtw_mdelay_os(5); /* wait set rpwm already */
772
773 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_leave_swlps_flow);
774 if (ret == _FALSE) {
775 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
776 return _FAIL;
777 }
778
779 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
780
781 pHalData->LastHMEBoxNum = 0;
782
783 #ifdef CONFIG_BT_COEXIST
784 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
785 #else
786 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
787 #endif /* CONFIG_BT_COEXIST */
788
789 return _SUCCESS;
790 }
791 #elif defined(CONFIG_FWLPS_IN_IPS)
792 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
793 && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
794 systime start_time;
795 u8 cpwm_orig, cpwm_now;
796 u8 val8, bMacPwrCtrlOn = _TRUE;
797
798 RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
799
800 /* for polling cpwm */
801 cpwm_orig = 0;
802 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
803
804 /* ser rpwm */
805 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
806 val8 &= 0x80;
807 val8 += 0x80;
808 val8 |= BIT(6);
809 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
810 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
811 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
812
813 /* do polling cpwm */
814 start_time = rtw_get_current_time();
815 do {
816
817 rtw_mdelay_os(1);
818
819 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
820 if ((cpwm_orig ^ cpwm_now) & 0x80) {
821 #ifdef DBG_CHECK_FW_PS_STATE
822 RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
823 , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
824 #endif /* DBG_CHECK_FW_PS_STATE */
825 break;
826 }
827
828 if (rtw_get_passing_time_ms(start_time) > 100) {
829 RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
830 break;
831 }
832 } while (1);
833
834 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
835
836 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
837
838 #ifdef CONFIG_BT_COEXIST
839 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
840 #else
841 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
842 #endif /* CONFIG_BT_COEXIST */
843
844 #ifdef DBG_CHECK_FW_PS_STATE
845 if (rtw_fw_ps_state(padapter) == _FAIL) {
846 RTW_INFO("after hal init, fw ps state in 32k\n");
847 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
848 }
849 #endif /* DBG_CHECK_FW_PS_STATE */
850 return _SUCCESS;
851 }
852 #endif /* CONFIG_SWLPS_IN_IPS */
853
854 /* Disable Interrupt first.
855 * rtw_hal_disable_interrupt(padapter); */
856
857 if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
858 RTW_INFO("FW exist before power on!!\n");
859 else
860 RTW_INFO("FW does not exist before power on!!\n");
861
862 if (rtw_fw_ps_state(padapter) == _FAIL) {
863 RTW_INFO("check fw_ps_state fail before PowerOn!\n");
864 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
865 }
866
867 ret = rtw_hal_power_on(padapter);
868 if (_FAIL == ret) {
869 return _FAIL;
870 }
871 RTW_INFO("Power on ok!\n");
872
873 if (rtw_fw_ps_state(padapter) == _FAIL) {
874 RTW_INFO("check fw_ps_state fail after PowerOn!\n");
875 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
876 }
877
878
879 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
880
881 /* if (padapter->registrypriv.mp_mode == 0) */
882 {
883 ret = rtl8723b_FirmwareDownload(padapter, _FALSE);
884 if (ret != _SUCCESS) {
885 pHalData->bFWReady = _FALSE;
886 pHalData->fw_ractrl = _FALSE;
887 return ret;
888 } else {
889 pHalData->bFWReady = _TRUE;
890 pHalData->fw_ractrl = _TRUE;
891 }
892 }
893
894 /* SIC_Init(padapter); */
895
896 if (pwrctrlpriv->reg_rfoff == _TRUE)
897 pwrctrlpriv->rf_pwrstate = rf_off;
898
899 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
900 /* HW GPIO pin. Before PHY_RFConfig8192C. */
901 HalDetectPwrDownMode(padapter);
902
903 /* Set RF type for BB/RF configuration */
904 _InitRFType(padapter);
905
906 /* Save target channel */
907 /* <Roger_Notes> Current Channel will be updated again later. */
908 pHalData->current_channel = 6;
909
910 #if (HAL_MAC_ENABLE == 1)
911 ret = PHY_MACConfig8723B(padapter);
912 if (ret != _SUCCESS) {
913 return ret;
914 }
915 #endif
916 /* */
917 /* d. Initialize BB related configurations. */
918 /* */
919 #if (HAL_BB_ENABLE == 1)
920 ret = PHY_BBConfig8723B(padapter);
921 if (ret != _SUCCESS) {
922 return ret;
923 }
924 #endif
925
926 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
927 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
928 /* if(pHalData->eRFPowerState == eRfOn) */
929 {
930 #if (HAL_RF_ENABLE == 1)
931 ret = PHY_RFConfig8723B(padapter);
932 if (ret != _SUCCESS) {
933 return ret;
934 }
935 #endif
936 }
937
938 /* */
939 /* Joseph Note: Keep RfRegChnlVal for later use. */
940 /* */
941 pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
942 pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
943
944
945 /* if (!pHalData->bMACFuncEnable) { */
946 _InitQueueReservedPage(padapter);
947 _InitTxBufferBoundary(padapter);
948
949 /* init LLT after tx buffer boundary is defined */
950 ret = rtl8723b_InitLLTTable(padapter);
951 if (_SUCCESS != ret) {
952 RTW_INFO("%s: Failed to init LLT Table!\n", __FUNCTION__);
953 return _FAIL;
954 }
955 /* } */
956 _InitQueuePriority(padapter);
957 _InitPageBoundary(padapter);
958 _InitTransferPageSize(padapter);
959
960 /* Get Rx PHY status in order to report RSSI and others. */
961 _InitDriverInfoSize(padapter, DRVINFO_SZ);
962 _InitNetworkType(padapter);
963 _InitWMACSetting(padapter);
964 _InitAdaptiveCtrl(padapter);
965 _InitEDCA(padapter);
966 _InitRetryFunction(padapter);
967 _initSdioAggregationSetting(padapter);
968
969 rtl8723b_InitBeaconParameters(padapter);
970 rtl8723b_InitBeaconMaxError(padapter, _TRUE);
971 _InitInterrupt(padapter);
972 _InitBurstPktLen_8723BS(padapter);
973
974 /* YJ,TODO */
975 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */
976 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
977
978 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
979
980 #ifdef CONFIG_CHECK_AC_LIFETIME
981 /* Enable lifetime check for the four ACs */
982 rtw_write8(padapter, REG_LIFETIME_CTRL, rtw_read8(padapter, REG_LIFETIME_CTRL) | 0x0F);
983 #endif /* CONFIG_CHECK_AC_LIFETIME */
984
985 #ifdef CONFIG_TX_MCAST2UNI
986 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
987 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
988 #else /* CONFIG_TX_MCAST2UNI */
989 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); /* unit: 256us. 3s */
990 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); /* unit: 256us. 3s */
991 #endif /* CONFIG_TX_MCAST2UNI */
992 #endif /* CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI */
993
994
995 invalidate_cam_all(padapter);
996
997 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
998 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
999
1000 rtl8723b_InitAntenna_Selection(padapter);
1001
1002 /* */
1003 /* Disable BAR, suggested by Scott */
1004 /* 2010.04.09 add by hpfan */
1005 /* */
1006 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1007
1008 /* HW SEQ CTRL */
1009 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1010 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1011
1012
1013 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1014 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
1015 u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1016 rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
1017
1018 rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1019 rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
1020 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
1021 rtw_write32(padapter, REG_CR, 0x0b0202ff);
1022 #endif
1023
1024 /*
1025 * Configure SDIO TxRx Control to enable Rx DMA timer masking.
1026 * 2010.02.24.
1027 * Only clear necessary bits 0x0[2:0] and 0x2[15:0] and keep 0x0[15:3]
1028 * 2015.03.19.
1029 */
1030 u4Tmp = rtw_read32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL);
1031 u4Tmp &= 0x0000FFF8;
1032 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, u4Tmp);
1033
1034 _RfPowerSave(padapter);
1035
1036 rtl8723b_InitHalDm(padapter);
1037
1038 /* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
1039
1040 /* if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) */ /* The lowest Beacon Type that HW can support */
1041 /* pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; */
1042
1043 /* */
1044 /* Update current Tx FIFO page status. */
1045 /* */
1046 HalQueryTxBufferStatus8723BSdio(padapter);
1047 HalQueryTxOQTBufferStatus8723BSdio(padapter);
1048 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1049
1050 /* Enable MACTXEN/MACRXEN block */
1051 u1bTmp = rtw_read8(padapter, REG_CR);
1052 u1bTmp |= (MACTXEN | MACRXEN);
1053 rtw_write8(padapter, REG_CR, u1bTmp);
1054
1055 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
1056
1057 #ifdef CONFIG_XMIT_ACK
1058 /* ack for xmit mgmt frames. */
1059 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
1060 #endif /* CONFIG_XMIT_ACK */
1061
1062 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
1063
1064 #if (MP_DRIVER == 1)
1065 if (padapter->registrypriv.mp_mode == 1) {
1066 padapter->mppriv.channel = pHalData->current_channel;
1067 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1068 } else
1069 #endif /* #if (MP_DRIVER == 1) */
1070 {
1071 pwrctrlpriv->rf_pwrstate = rf_on;
1072
1073 if (pwrctrlpriv->rf_pwrstate == rf_on) {
1074 struct pwrctrl_priv *pwrpriv;
1075 systime start_time;
1076 u8 restore_iqk_rst;
1077 u8 b2Ant;
1078 u8 h2cCmdBuf;
1079
1080 pwrpriv = adapter_to_pwrctl(padapter);
1081
1082 /*phy_lc_calibrate_8723b(&pHalData->odmpriv);*/
1083 halrf_lck_trigger(&pHalData->odmpriv);
1084
1085 /* Inform WiFi FW that it is the beginning of IQK */
1086 h2cCmdBuf = 1;
1087 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1088
1089 start_time = rtw_get_current_time();
1090 do {
1091 if (rtw_read8(padapter, 0x1e7) & 0x01)
1092 break;
1093
1094 rtw_msleep_os(50);
1095 } while (rtw_get_passing_time_ms(start_time) <= 400);
1096
1097 #ifdef CONFIG_BT_COEXIST
1098 rtw_btcoex_IQKNotify(padapter, _TRUE);
1099 #endif
1100 restore_iqk_rst = (pwrpriv->bips_processing == _TRUE) ? _TRUE : _FALSE;
1101 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE;
1102 /*phy_iq_calibrate_8723b(padapter, _FALSE, restore_iqk_rst, b2Ant, pHalData->ant_path);*/
1103 halrf_iqk_trigger(&pHalData->odmpriv, restore_iqk_rst);
1104 pHalData->bIQKInitialized = _TRUE;
1105 #ifdef CONFIG_BT_COEXIST
1106 rtw_btcoex_IQKNotify(padapter, _FALSE);
1107 #endif
1108
1109 /* Inform WiFi FW that it is the finish of IQK */
1110 h2cCmdBuf = 0;
1111 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1112
1113 odm_txpowertracking_check(&pHalData->odmpriv);
1114 }
1115 }
1116
1117 #ifdef CONFIG_BT_COEXIST
1118 /* Init BT hw config. */
1119 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1120 #else
1121 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1122 #endif
1123
1124
1125 return _SUCCESS;
1126 }
1127
1128 /*
1129 * Description:
1130 * RTL8723e card disable power sequence v003 which suggested by Scott.
1131 *
1132 * First created by tynli. 2011.01.28.
1133 * */
CardDisableRTL8723BSdio(PADAPTER padapter)1134 static void CardDisableRTL8723BSdio(PADAPTER padapter)
1135 {
1136 u8 u1bTmp;
1137 u16 u2bTmp;
1138 u32 u4bTmp;
1139 u8 bMacPwrCtrlOn;
1140 u8 ret = _FAIL;
1141
1142 /* Run LPS WL RFOFF flow */
1143 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1144 if (ret == _FAIL)
1145 RTW_ERR("%s: run RF OFF flow fail!\n", __func__);
1146
1147 /* ==== Reset digital sequence ====== */
1148
1149 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1150 if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
1151 rtl8723b_FirmwareSelfReset(padapter);
1152
1153 /* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
1154 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1155 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1156 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1157
1158 /* MCUFWDL 0x80[1:0]=0 */
1159 /* reset MCU ready status */
1160 rtw_write8(padapter, REG_MCUFWDL, 0);
1161
1162 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1163 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1164 u1bTmp &= ~BIT(0);
1165 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1166 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1167 u1bTmp |= BIT(0);
1168 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1169
1170 /* ==== Reset digital sequence end ====== */
1171
1172 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1173 ret = _FALSE;
1174 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1175 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1176 if (ret == _FALSE)
1177 RTW_ERR("%s: run CARD DISABLE flow fail!\n", __func__);
1178
1179 GET_HAL_DATA(padapter)->bFWReady = _FALSE;
1180 }
1181
rtl8723bs_hal_deinit(PADAPTER padapter)1182 static u32 rtl8723bs_hal_deinit(PADAPTER padapter)
1183 {
1184 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1185 struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1186 struct dvobj_priv *psdpriv = padapter->dvobj;
1187 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1188
1189 #ifdef CONFIG_MP_INCLUDED
1190 if (padapter->registrypriv.mp_mode == 1)
1191 MPT_DeInitAdapter(padapter);
1192 #endif
1193
1194 if (rtw_is_hw_init_completed(padapter)) {
1195 #ifdef CONFIG_SWLPS_IN_IPS
1196 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
1197 u8 bMacPwrCtrlOn;
1198 u8 ret = _TRUE;
1199
1200 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
1201
1202 rtw_write32(padapter, 0x130, 0x0);
1203 rtw_write32(padapter, 0x138, 0x100);
1204 rtw_write8(padapter, 0x13d, 0x1);
1205
1206
1207 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1208 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1209
1210 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_swlps_flow);
1211 if (ret == _FALSE) {
1212 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1213 return _FAIL;
1214 }
1215 } else
1216 #elif defined(CONFIG_FWLPS_IN_IPS)
1217 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
1218 if (padapter->netif_up == _TRUE) {
1219 int cnt = 0;
1220 u8 val8 = 0;
1221
1222 RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1223
1224 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x1);
1225 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
1226 do {
1227 val8 = rtw_read8(padapter, REG_HMETFR);
1228 cnt++;
1229 RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1230 rtw_mdelay_os(10);
1231 } while (cnt < 100 && (val8 != 0));
1232 /* H2C done, enter 32k */
1233 if (val8 == 0) {
1234 /* ser rpwm to enter 32k */
1235 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1236 val8 += 0x80;
1237 val8 |= BIT(0);
1238 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1239 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1240 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1241 cnt = val8 = 0;
1242 do {
1243 val8 = rtw_read8(padapter, REG_CR);
1244 cnt++;
1245 RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1246 rtw_mdelay_os(10);
1247 } while (cnt < 100 && (val8 != 0xEA));
1248 #ifdef DBG_CHECK_FW_PS_STATE
1249 if (val8 != 0xEA)
1250 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1251 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1252 #endif /* DBG_CHECK_FW_PS_STATE */
1253 } else {
1254 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1255 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1256 }
1257
1258 RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1259 , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1260
1261 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1262
1263 } else {
1264 pdbgpriv->dbg_carddisable_cnt++;
1265 #ifdef DBG_CHECK_FW_PS_STATE
1266 if (rtw_fw_ps_state(padapter) == _FAIL) {
1267 RTW_INFO("card disable should leave 32k\n");
1268 pdbgpriv->dbg_carddisable_error_cnt++;
1269 }
1270 #endif /* DBG_CHECK_FW_PS_STATE */
1271 rtw_hal_power_off(padapter);
1272
1273 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1274 }
1275
1276 } else
1277 #endif /* CONFIG_SWLPS_IN_IPS */
1278 {
1279 pdbgpriv->dbg_carddisable_cnt++;
1280 #ifdef DBG_CHECK_FW_PS_STATE
1281 if (rtw_fw_ps_state(padapter) == _FAIL) {
1282 RTW_INFO("card disable should leave 32k\n");
1283 pdbgpriv->dbg_carddisable_error_cnt++;
1284 }
1285 #endif /* DBG_CHECK_FW_PS_STATE */
1286 rtw_hal_power_off(padapter);
1287 }
1288 } else
1289 pdbgpriv->dbg_deinit_fail_cnt++;
1290
1291 return _SUCCESS;
1292 }
rtl8723bs_init_default_value(PADAPTER padapter)1293 static void rtl8723bs_init_default_value(PADAPTER padapter)
1294 {
1295 PHAL_DATA_TYPE pHalData;
1296
1297
1298 pHalData = GET_HAL_DATA(padapter);
1299
1300 rtl8723b_init_default_value(padapter);
1301
1302 /* interface related variable */
1303 pHalData->SdioRxFIFOCnt = 0;
1304 }
1305
rtl8723bs_interface_configure(PADAPTER padapter)1306 static void rtl8723bs_interface_configure(PADAPTER padapter)
1307 {
1308 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1309 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1310 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1311 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
1312
1313
1314 /* F-Cut patch for IC always can response SDIO recognition commands */
1315 if (IS_F_CUT(pHalData->version_id)) {
1316 u32 addr;
1317 u8 val8;
1318
1319 /*
1320 * Always response recognition command
1321 * SDIO Local Register 0x00[4] = 1
1322 */
1323 addr = SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL;
1324 val8 = rtw_read8(padapter, addr);
1325 if (!(val8 & BIT(4))) {
1326 val8 |= BIT(4);
1327 rtw_write8(padapter, addr, val8);
1328 }
1329 }
1330
1331 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1332 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1333 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1334
1335 if (bWiFiConfig)
1336 pHalData->OutEpNumber = 2;
1337 else
1338 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1339
1340 switch (pHalData->OutEpNumber) {
1341 case 3:
1342 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1343 break;
1344 case 2:
1345 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1346 break;
1347 case 1:
1348 pHalData->OutEpQueueSel = TX_SELE_HQ;
1349 break;
1350 default:
1351 break;
1352 }
1353
1354 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1355 }
1356
1357 /*
1358 * Description:
1359 * We should set Efuse cell selection to WiFi cell in default.
1360 *
1361 * Assumption:
1362 * PASSIVE_LEVEL
1363 *
1364 * Added by Roger, 2010.11.23.
1365 * */
1366 static void
_EfuseCellSel(IN PADAPTER padapter)1367 _EfuseCellSel(
1368 IN PADAPTER padapter
1369 )
1370 {
1371 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1372
1373 u32 value32;
1374
1375 /* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
1376 {
1377 value32 = rtw_read32(padapter, EFUSE_TEST);
1378 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1379 rtw_write32(padapter, EFUSE_TEST, value32);
1380 }
1381 }
1382
1383 static VOID
_ReadRFType(IN PADAPTER Adapter)1384 _ReadRFType(
1385 IN PADAPTER Adapter
1386 )
1387 {
1388 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1389
1390 #if DISABLE_BB_RF
1391 pHalData->rf_chip = RF_PSEUDO_11N;
1392 #else
1393 pHalData->rf_chip = RF_6052;
1394 #endif
1395 }
1396
1397 static VOID
_ReadEfuseInfo8723BS(IN PADAPTER padapter)1398 _ReadEfuseInfo8723BS(
1399 IN PADAPTER padapter
1400 )
1401 {
1402 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1403 u8 *hwinfo = NULL;
1404
1405
1406 /* */
1407 /* This part read and parse the eeprom/efuse content */
1408 /* */
1409
1410 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1411 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1412
1413 hwinfo = pHalData->efuse_eeprom_data;
1414
1415 Hal_InitPGData(padapter, hwinfo);
1416
1417 Hal_EfuseParseIDCode(padapter, hwinfo);
1418 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1419 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1420 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1421 Hal_EfuseParseBoardType_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1422
1423 /* */
1424 /* Read Bluetooth co-exist and initialize */
1425 /* */
1426 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1427 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1428 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1429 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1430 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1431 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1432 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1433
1434 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1435
1436 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1437 Hal_DetectWoWMode(padapter);
1438 #endif
1439
1440 #ifdef CONFIG_RF_POWER_TRIM
1441 Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
1442 #endif /*CONFIG_RF_POWER_TRIM*/
1443
1444 }
1445
_ReadPROMContent(IN PADAPTER padapter)1446 static void _ReadPROMContent(
1447 IN PADAPTER padapter
1448 )
1449 {
1450 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1451 u8 eeValue;
1452
1453 eeValue = rtw_read8(padapter, REG_9346CR);
1454 /* To check system boot selection. */
1455 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1456 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1457
1458
1459 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1460
1461 _ReadEfuseInfo8723BS(padapter);
1462 }
1463
1464 static VOID
_InitOtherVariable(IN PADAPTER Adapter)1465 _InitOtherVariable(
1466 IN PADAPTER Adapter
1467 )
1468 {
1469 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1470
1471
1472 /* if(Adapter->bInHctTest){ */
1473 /* pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
1474 /* pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
1475 /* pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
1476 /* pMgntInfo->keepAliveLevel = 0; */
1477 /* } */
1478
1479
1480
1481 }
1482
1483 /*
1484 * Description:
1485 * Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
1486 *
1487 * Assumption:
1488 * PASSIVE_LEVEL (SDIO interface)
1489 *
1490 * */
ReadAdapterInfo8723BS(PADAPTER padapter)1491 static u8 ReadAdapterInfo8723BS(PADAPTER padapter)
1492 {
1493 u8 val8;
1494
1495 val8 = rtw_read8(padapter, 0x4e);
1496 RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
1497 val8 |= BIT(6);
1498 rtw_write8(padapter, 0x4e, val8);
1499
1500 /* Read EEPROM size before call any EEPROM function */
1501 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1502
1503 _EfuseCellSel(padapter);
1504 _ReadRFType(padapter);
1505 _ReadPROMContent(padapter);
1506 _InitOtherVariable(padapter);
1507
1508 #ifdef CONFIG_PLATFORM_INTEL_BYT
1509 { /* for BT, let BT can control ANT when wifi disable */
1510 u32 val32;
1511 RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
1512 val32 = rtw_read32(padapter, 0x64);
1513 RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
1514 val32 |= BIT(13);
1515 rtw_write32(padapter, 0x64, val32);
1516 RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
1517 }
1518 #endif /* CONFIG_PLATFORM_INTEL_BYT */
1519
1520 return _SUCCESS;
1521 }
1522
1523 /*
1524 * If variable not handled here,
1525 * some variables will be processed in SetHwReg8723B()
1526 */
SetHwReg8723BS(PADAPTER padapter,u8 variable,u8 * val)1527 u8 SetHwReg8723BS(PADAPTER padapter, u8 variable, u8 *val)
1528 {
1529 PHAL_DATA_TYPE pHalData;
1530 u8 ret = _SUCCESS;
1531 u8 val8;
1532
1533
1534 pHalData = GET_HAL_DATA(padapter);
1535
1536 switch (variable) {
1537 case HW_VAR_SET_RPWM:
1538 /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
1539 /* BIT0 value - 1: 32k, 0:40MHz. */
1540 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1541 /* BIT7 value - Toggle bit change. */
1542 {
1543 val8 = *val;
1544 val8 &= 0xC1;
1545 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1546 }
1547 break;
1548 case HW_VAR_SET_REQ_FW_PS:
1549 /* 1. driver write 0x8f[4]=1 */ { /* request fw ps state (only can write bit4) */
1550 u8 req_fw_ps = 0;
1551 req_fw_ps = rtw_read8(padapter, 0x8f);
1552 req_fw_ps |= 0x10;
1553 rtw_write8(padapter, 0x8f, req_fw_ps);
1554 }
1555 break;
1556 case HW_VAR_RXDMA_AGG_PG_TH:
1557 val8 = *val;
1558
1559 /* TH=1 => invalidate RX DMA aggregation */
1560 /* TH=0 => validate RX DMA aggregation, use init value. */
1561 if (val8 == 0) {
1562 /* enable RXDMA aggregation */
1563 /* _RXAggrSwitch(padapter, _TRUE); */
1564 } else {
1565 /* disable RXDMA aggregation */
1566 /* _RXAggrSwitch(padapter, _FALSE); */
1567 }
1568 break;
1569 default:
1570 ret = SetHwReg8723B(padapter, variable, val);
1571 break;
1572 }
1573
1574 return ret;
1575 }
1576
1577 /*
1578 * If variable not handled here,
1579 * some variables will be processed in GetHwReg8723B()
1580 */
GetHwReg8723BS(PADAPTER padapter,u8 variable,u8 * val)1581 void GetHwReg8723BS(PADAPTER padapter, u8 variable, u8 *val)
1582 {
1583 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1584
1585
1586 switch (variable) {
1587 case HW_VAR_CPWM:
1588 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
1589 break;
1590
1591 case HW_VAR_FW_PS_STATE: {
1592 /* 3. read dword 0x88 */ /* driver read fw ps state */
1593 *((u16 *)val) = rtw_read16(padapter, 0x88);
1594 }
1595 break;
1596 default:
1597 GetHwReg8723B(padapter, variable, val);
1598 break;
1599 }
1600
1601 }
1602
1603 /*
1604 * Description:
1605 * Query setting of specified variable.
1606 * */
1607 u8
GetHalDefVar8723BSDIO(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)1608 GetHalDefVar8723BSDIO(
1609 IN PADAPTER Adapter,
1610 IN HAL_DEF_VARIABLE eVariable,
1611 IN PVOID pValue
1612 )
1613 {
1614 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1615 u8 bResult = _SUCCESS;
1616
1617 switch (eVariable) {
1618 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1619 #ifdef CONFIG_ANTENNA_DIVERSITY
1620 *((u8 *)pValue) = _FALSE;
1621 #endif
1622 break;
1623
1624 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1625 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1626 /* coding by Lucas@20130730 */
1627 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
1628 break;
1629 default:
1630 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1631 break;
1632 }
1633
1634 return bResult;
1635 }
1636
1637 /*
1638 * Description:
1639 * Change default setting of specified variable.
1640 * */
1641 u8
SetHalDefVar8723BSDIO(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)1642 SetHalDefVar8723BSDIO(
1643 IN PADAPTER Adapter,
1644 IN HAL_DEF_VARIABLE eVariable,
1645 IN PVOID pValue
1646 )
1647 {
1648 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1649 u8 bResult = _SUCCESS;
1650
1651 switch (eVariable) {
1652 default:
1653 bResult = SetHalDefVar8723B(Adapter, eVariable, pValue);
1654 break;
1655 }
1656
1657 return bResult;
1658 }
1659
rtl8723bs_set_hal_ops(PADAPTER padapter)1660 void rtl8723bs_set_hal_ops(PADAPTER padapter)
1661 {
1662 struct hal_ops *pHalFunc = &padapter->hal_func;
1663
1664
1665 rtl8723b_set_hal_ops(pHalFunc);
1666
1667 pHalFunc->hal_power_on = &_InitPowerOn_8723BS;
1668 pHalFunc->hal_power_off = &CardDisableRTL8723BSdio;
1669
1670 pHalFunc->hal_init = &rtl8723bs_hal_init;
1671 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1672
1673 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1674 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1675
1676 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1677 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1678 #ifdef CONFIG_RTW_SW_LED
1679 pHalFunc->InitSwLeds = &rtl8723bs_InitSwLeds;
1680 pHalFunc->DeInitSwLeds = &rtl8723bs_DeInitSwLeds;
1681 #endif
1682 pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1683 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1684 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1685
1686 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1687 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1688 pHalFunc->check_ips_status = &CheckIPSStatus;
1689
1690 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1691 pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
1692 #endif
1693 pHalFunc->set_hw_reg_handler = &SetHwReg8723BS;
1694 pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1695 pHalFunc->get_hal_def_var_handler = &GetHalDefVar8723BSDIO;
1696 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1697
1698 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1699 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1700 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1701
1702 #ifdef CONFIG_HOSTAPD_MLME
1703 pHalFunc->hostap_mgnt_xmit_entry = NULL;
1704 #endif
1705
1706 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
1707 pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
1708 pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
1709 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
1710 pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
1711 #endif
1712
1713 }
1714