1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 //==============================================================================
95 // [mhal_sc.c]
96 // Date: 20081203
97 // Descriptions: Add a new layer for HW setting
98 //==============================================================================
99 #define MHAL_SC_C
100
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <asm/div64.h>
103 #else
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106 #include "UFO.h"
107
108 // Common Definition
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 #include "mhal_xc_chip_config.h"
113 #include "utopia.h"
114 #include "utopia_dapi.h"
115 #include "xc_hwreg_utility2.h"
116 #include "xc_Analog_Reg.h"
117 #include "drvXC_IOPort.h"
118 #include "apiXC.h"
119 #include "drv_sc_display.h"
120 #include "drv_sc_isr.h"
121 #include "apiXC_Adc.h"
122 #include "apiXC_PCMonitor.h"
123 #include "apiXC_ModeParse.h"
124 #include "apiXC_Auto.h"
125 #include "drvXC_HDMI_if.h"
126 #include "mvideo_context.h"
127 #include "drv_sc_ip.h"
128 #include "mhal_dynamicscaling.h"
129 #include "mdrv_sc_dynamicscaling.h"
130 #include "drvXC_HDMI_Internal.h"
131 #include "drvMVOP.h"
132
133 #if (LD_ENABLE==1)
134 #include "mdrv_ld.h"
135 #include "mdrv_ldalgo.h"
136 #endif
137 #include "mdrv_sc_3d.h"
138 #include "drv_sc_menuload.h"
139 #include "drvXC_ADC_Internal.h"
140 #include "mhal_sc.h"
141 #if FRC_INSIDE
142 #include "mdrv_frc.h"
143 #include "mhal_frc.h"
144 #endif
145 #include "XC_private.h"
146 #include "mhal_menuload.h"
147 #include "halCHIP.h"
148 #include "drvSYS.h"
149 #include "drv_sc_scaling.h"
150
151 #ifndef DONT_USE_CMA
152 #if (XC_SUPPORT_CMA ==TRUE)
153 #include "drvCMAPool.h"
154 #include "msos/linux/ion_uapi.h"
155 #include "msos/linux/mdrv_cma_pool_st.h"
156 #include "drvMIU.h"
157 #endif
158 #endif
159
160 #include <assert.h>
161 #ifdef ANDROID
162 #include <cutils/log.h>
163 #ifndef LOGE
164 #define printf(format, args...) ALOGE(format, ##args);
165 #else
166 #define printf(format, args...) LOGE(format, ##args);
167 #endif
168 #endif
169
170 #define DBG_EN 0
171 #if DBG_EN
172 #define SC_DBG(x) x
173 #define FPLL_DBG(x) x
174 #else
175 #define SC_DBG(x)
176 #define FPLL_DBG(x)
177 #endif
178 #define new_chakra
179
180 #define MIU_SEL_USE_XC_INTERNAL TRUE
181
182 //==============================================================================
183 //==============================================================================
184 MS_VIRT _XC_RIU_BASE;
185 MS_VIRT _PM_RIU_BASE;
186
187 MS_VIRT _DVI_ATOP_RIU_BASE;
188 MS_VIRT _DVI_DTOP_RIU_BASE;
189 MS_VIRT _HDCP_RIU_BASE;
190 MS_VIRT _DVI_EQ_RIU_BASE;
191 MS_VIRT _ADC_DTOPB_RIU_BASE;
192
193 MS_VIRT _DDC_RIU_BASE;
194 MS_VIRT _PM_SLEEP_RIU_BASE;
195
196 MS_U32 u32DTVPatchTimer;
197 MS_BOOL bPreFDMaskStatse;
198 MS_U16 u16FDMaskCount;
199
200
201 #define SC0_OP1_DLY 11
202 #define SC0_CTRL_DLY 30
203 #define SC0_COL_BLEND_DLY 17
204 #define SC0_VIP_DLY 150
205 #define SC0_V_DLY 2
206 #define SC1_OP1_DLY 11
207 #define SC1_VIP_DLY 61
208 #define SC1_MISC_DLY 3
209 #define SC1_PRE_RUN_DLY ((SC_R2BYTEMSK(0, REG_SC_BK10_0C_L, 0x3FFF)+1)/4)
210 #define SC_MADI_DIPF 0x9F
211
212 #ifdef UFO_XC_AUTO_DOWNLOAD
213 #define DEBUG_HDR 0
214 #define AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR 512
215 #define AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR 4944
216
217 // HDR client of auto download has these following formats, include format0 and format1.
218 //
219 // Format0:
220 //127 125 116 115 112 60 57 0
221 // | [x[2]] | [addr(10)] | 0 | [sel0(3)] | [data1] | sel1(3) | [data0] |
222 // sel0 = 1 x(52) sel1 = 1 wd0(19),wd1(19),wd2(19)
223 // sel0 = 2 x(4),wd0(16),wd1(16),wd2(16) sel1 = 2 x(9),wd0(16),wd1(16),wd2(16)
224 // sel0 = 3 x(40),wd0(12) sel1 = 3 x(45),wd0(12)
225 // sel0 = 4 idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(5),idx(4),wd0(16),wd1(16),wd2(16)
226 // sel: 0: disable
227 // 1: De-gamma
228 // 2: Gamma
229 // 3: TMO
230 // 4: 3D-lut
231
232 // Format1:
233 //127 125 116 115 112 60 57 0
234 // | [x[2]] | [addr(10)] | 1 | [ctrl0(3)] | [data1] | sel1(3) | [data0] |
235 // x(52) sel1 = 0
236 // idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(10),degam(19),gam(16),tmo(16)
237 // ctrl: bit: 114 113 112
238 // |degam|gam|tmo|
239 // sel: 0: disable
240 // 4: 3D-lut
241 //
242 // HW designer recommand using format1.
243 // These following definitions write datas of tmo/gamma/de-gamma/3d-lut separately by format1,
244 // please refer to definition of WRITE_TMO_DATA_FORMAT_1, WRITE_GAMMA_DATA_FORMAT_1, WRITE_DEGAMMA_DATA_FORMAT_1 and WRITE_3DLUT_DATA_FORMAT_1.
245 #define WRITE_TMO_DATA_FORMAT_1(baseaddr, index, value) \
246 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
247 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x09);\
248 *(baseaddr + 14) = ((*(baseaddr + 14) & 0xF0) | (((value) >> 8) & 0x0F));\
249 *(baseaddr + 15) = ((value) & 0xFF);
250
251 #define WRITE_GAMMA_DATA_FORMAT_1(baseaddr, index, value) \
252 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
253 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0A);\
254 *(baseaddr + 14) = ((*(baseaddr + 14) & 0x0F) | (((value) << 4) & 0xF0));\
255 *(baseaddr + 13) = (((value) >> 4) & 0xFF);\
256 *(baseaddr + 12) = ((*(baseaddr + 12) & 0xF0) | (((value) >> 12) & 0x0F));
257
258 #define WRITE_DEGAMMA_DATA_FORMAT_1(baseaddr, index, value) \
259 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
260 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0C);\
261 *(baseaddr + 12) = ((*(baseaddr + 12) & 0x0F) | (((value) << 4) & 0xF0));\
262 *(baseaddr + 11) = (((value) >> 4) & 0xFF);\
263 *(baseaddr + 10) = ((*(baseaddr + 10) & 0x80) | (((value) >> 12) & 0x7F));
264
265 #define WRITE_3DLUT_DATA_FORMAT_1(baseaddr, index, subindex, rval, gval, bval) \
266 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
267 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x08);\
268 *(baseaddr + 8) = ((*(baseaddr + 8) & 0xF1) | 0x08);\
269 *(baseaddr + 8) = ((*(baseaddr + 8) & 0x0F) | (((bval) << 4) & 0xF0));\
270 *(baseaddr + 7) = (((bval) >> 4) & 0xFF);\
271 *(baseaddr + 6) = ((*(baseaddr + 6) & 0xF0) | (((bval) >> 12) & 0x0F));\
272 *(baseaddr + 6) = ((*(baseaddr + 6) & 0x0F) | (((gval) << 4) & 0xF0));\
273 *(baseaddr + 5) = (((gval) >> 4) & 0xFF);\
274 *(baseaddr + 4) = ((*(baseaddr + 4) & 0xF0) | (((gval) >> 12) & 0x0F));\
275 *(baseaddr + 4) = ((*(baseaddr + 4) & 0x0F) | (((rval) << 4) & 0xF0));\
276 *(baseaddr + 3) = (((rval) >> 4) & 0xFF);\
277 *(baseaddr + 2) = ((*(baseaddr + 2) & 0xF0) | (((rval) >> 12) & 0x0F));\
278 *(baseaddr + 2) = ((*(baseaddr + 2) & 0x0F) | (((subindex) << 4) & 0xF0));
279
280 // The following definition clear bits of format1's ctrl & sel.
281 #define CLEAR_HDR_DATA_FORMAT_1(baseaddr) \
282 *(baseaddr + 1) = ((*(baseaddr + 1)) & 0xF8);\
283 *(baseaddr + 8) = (*(baseaddr + 8) & 0xF1);
284
285 static MS_U32 _au32_3dlut_entry_num[8] = {736, 656, 656, 576, 656, 576, 576, 512};
286 #endif
287
288 // Put this function here because hwreg_utility2 only for hal.
Hal_SC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)289 void Hal_SC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
290 {
291 _XC_RIU_BASE = u32PMriu_base;
292 _PM_RIU_BASE = u32PMriu_base;
293
294
295 _DVI_ATOP_RIU_BASE = u32PMriu_base;
296 _DVI_DTOP_RIU_BASE = u32PMriu_base;
297 _HDCP_RIU_BASE = u32PMriu_base;
298 _DVI_EQ_RIU_BASE = u32PMriu_base;
299 _ADC_DTOPB_RIU_BASE = u32PMriu_base;
300
301 _DDC_RIU_BASE =u32PMriu_base;
302 _PM_SLEEP_RIU_BASE =u32PMriu_base;
303
304 }
305
306 //=========================================================//
307 // Function : Hal_SC_setfield
308 // Description:
309 //=========================================================//
Hal_SC_setfield(void * pInstance,MS_U16 reg_1D,MS_U16 reg_21,MS_U16 reg_23,SCALER_WIN eWindow)310 void Hal_SC_setfield(void *pInstance, MS_U16 reg_1D, MS_U16 reg_21, MS_U16 reg_23, SCALER_WIN eWindow )
311 {
312 //printf("reg_1D=%x, reg_21=%x, reg_23=%x\n", reg_1D, reg_21, reg_23);
313 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
314 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
315
316 if( eWindow == MAIN_WINDOW )
317 {
318 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1D_L, (reg_1D<<8), 0xEF00);
319 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, reg_21, 0x3FFF);
320 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_23_L, (reg_23<<8), HBMASK);
321 }
322 else
323 {
324 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1D_L, (reg_1D<<8), 0xEF00);
325 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, reg_21, 0x3FFF);
326 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_23_L, (reg_23<<8), HBMASK);
327 }
328 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_1D_L, HBMASK));
329 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_21_L, 0x3FFF));
330 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_23_L, HBMASK));
331
332 // printf("%x ",SC_R4BYTE(REG_SC_BK01_21_L));
333 // printf("%x ",SC_R4BYTE(REG_SC_BK01_23_L));
334 }
335
336 //=========================================================//
337 // Function : Hal_SC_de_only_en
338 // Description: DE Only. HSYNC and VSYNC are ignored.
339 //#0: Disable.
340 //#1: Enable.
341 //=========================================================//
Hal_SC_de_only_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)342 void Hal_SC_de_only_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
343 {
344 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
345 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
346 if(eWindow == MAIN_WINDOW)
347 {
348 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(6):0), BIT(6));
349 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
350 }
351 else
352 {
353 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(6):0), BIT(6));
354 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
355 }
356 }
357
358 //=========================================================//
359 // Function : Hal_SC_de_direct_en
360 // Description: Digital Input Horizontal Sample Range
361 //#0: Use DE as sample range, only V position can be adjusted.
362 //#1: Use SPRHST and SPRHDC as sample range, both H and V position can be adjusted.
363 //=========================================================//
Hal_SC_de_direct_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)364 void Hal_SC_de_direct_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
365 {
366 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
367 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
368 if(eWindow == MAIN_WINDOW)
369 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(7):0), BIT(7));
370 else
371 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(7):0), BIT(7));
372
373 }
374
Hal_SC_set_ficlk(void * pInstance,MS_BOOL bPreDown,SCALER_WIN eWindow)375 void Hal_SC_set_ficlk(void *pInstance, MS_BOOL bPreDown, SCALER_WIN eWindow)
376 {
377 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
378 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
379 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
380 {
381 // manhattan is not needed it
382 }
383 else //E_XC_DEVICE1 == psXCInstPri->u32DeviceID
384 {
385 if (bPreDown)
386 {
387 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk
388 }
389 else
390 {
391 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk
392 }
393 }
394 }
395
Hal_SC_set_shiftline(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)396 void Hal_SC_set_shiftline(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow )
397 {
398 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
399 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
400 if( eWindow == MAIN_WINDOW )
401 {
402 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x07)<<8, (BIT(10)|BIT(9)|BIT(8)));
403 }
404 else
405 {
406 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x03)<<13, (BIT(14)|BIT(13)));
407 }
408 }
409
Hal_SC_set_422_cbcr_swap(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)410 void Hal_SC_set_422_cbcr_swap(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
411 {
412 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
413 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
414 if(eWindow == MAIN_WINDOW)
415 {
416 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_0A_L, bEnable ? BIT(6) : 0, BIT(6));
417 }
418 else
419 {
420 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_0A_L, bEnable ? BIT(6) : 0, BIT(6));
421 }
422 }
423
Hal_SC_set_pre_align_pixel(void * pInstance,MS_BOOL bEnable,MS_U16 pixels,SCALER_WIN eWindow)424 void Hal_SC_set_pre_align_pixel(void *pInstance, MS_BOOL bEnable, MS_U16 pixels, SCALER_WIN eWindow)
425 {
426 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
427 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
428 if (bEnable)
429 {
430 if ( eWindow == MAIN_WINDOW )
431 {
432 // Enable pre align pixel for mirror mode.
433 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, BIT(15), BIT(15));
434
435 // Number of pixels need to be inserted. (U3 has 15 pixels)
436 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, pixels << 8 , 0x1F00);
437 }
438 else
439 {
440 // Enable pre align pixel for mirror mode.
441 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, BIT(15), BIT(15));
442
443 // Number of pixels need to be inserted. (U3 has 15 pixels)
444 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, pixels << 8 , 0x1F00);
445 }
446
447 }
448 else
449 {
450 if ( eWindow == MAIN_WINDOW )
451 {
452 // Disable pre align pixel for mirror mode.
453 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, 0x00 , BIT(15));
454 }
455 else
456 {
457 // Disable pre align pixel for mirror mode.
458 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, 0x00 , BIT(15));
459 }
460 }
461 }
462
Hal_SC_get_pre_align_pixel(void * pInstance,SCALER_WIN eWindow)463 MS_BOOL Hal_SC_get_pre_align_pixel(void *pInstance, SCALER_WIN eWindow)
464 {
465 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
466 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
467 if ( eWindow == MAIN_WINDOW )
468 {
469 // Check pre align pixel.
470 return ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, BIT(15))) ? TRUE:FALSE;
471 }
472 else
473 {
474 // Check pre align pixel.
475 return ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, BIT(15))) ? TRUE:FALSE;
476 }
477 }
478
Hal_XC_Set_FreeFRCMD(void * pInstance,MS_BOOL bEnable)479 void Hal_XC_Set_FreeFRCMD(void *pInstance, MS_BOOL bEnable)
480 {
481 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
482 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
483 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, bEnable? BIT(5) : 0, BIT(5));
484 }
485
486 // Obsolete in M10/J2/A5
Hal_SC_set_linearmem_mode(MS_BOOL bEnable,SCALER_WIN eWindow)487 void Hal_SC_set_linearmem_mode(MS_BOOL bEnable, SCALER_WIN eWindow)
488 {
489 }
490
491 // This function will return 8/10/12/14/16 field mode or 8 frame mode.
492 // Otherwise it return IMAGE_STORE_2_FRAMES
Hal_SC_GetFrameStoreMode(void * pInstance,SCALER_WIN eWindow)493 XC_FRAME_STORE_NUMBER Hal_SC_GetFrameStoreMode(void *pInstance, SCALER_WIN eWindow)
494 {
495 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
496 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
497 MS_U16 u16FrameCount = 0x00;
498 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
499 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
500 if (eWindow == MAIN_WINDOW)
501 {
502 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L);
503 }
504 else
505 {
506 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L);
507 }
508
509 switch( u16FrameCount) // Get field type.
510 {
511 default:
512 if (gSrcInfo[MAIN_WINDOW].bInterlace)
513 {
514 return IMAGE_STORE_4_FIELDS;
515 }
516 else
517 {
518 return IMAGE_STORE_2_FRAMES;
519 }
520 case 3:
521 return IMAGE_STORE_3_FRAMES;
522 case 4:
523 if (gSrcInfo[MAIN_WINDOW].bInterlace)
524 {
525 return IMAGE_STORE_4_FIELDS;
526 }
527 else
528 {
529 return IMAGE_STORE_4_FRAMES;
530 }
531 case 6:
532 if (gSrcInfo[MAIN_WINDOW].bInterlace)
533 {
534 return IMAGE_STORE_6_FIELDS;
535 }
536 else
537 {
538 return IMAGE_STORE_6_FRAMES;
539 }
540 case 8:
541 if (gSrcInfo[MAIN_WINDOW].bInterlace)
542 {
543 return IMAGE_STORE_8_FIELDS;
544 }
545 else
546 {
547 return IMAGE_STORE_8_FRAMES;
548 }
549 case 10:
550 return IMAGE_STORE_10_FIELDS;
551 case 12:
552 if (gSrcInfo[MAIN_WINDOW].bInterlace)
553 {
554 return IMAGE_STORE_12_FIELDS;
555 }
556 else
557 {
558 return IMAGE_STORE_12_FRAMES;
559 }
560 case 14:
561 return IMAGE_STORE_14_FIELDS;
562 case 16:
563 return IMAGE_STORE_16_FIELDS;
564
565 }
566
567 return IMAGE_STORE_UNDEFINE;
568 }
569
Hal_SC_set_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)570 void Hal_SC_set_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
571 {
572 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
573 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
574 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
575
576 if( eWindow == MAIN_WINDOW )
577 {
578 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
579 }
580 else
581 {
582 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
583 }
584 }
585
Hal_SC_set_frcm_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)586 void Hal_SC_set_frcm_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
587 {
588 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
589 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
590 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
591
592 if( eWindow == MAIN_WINDOW )
593 {
594 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
595 }
596 else
597 {
598 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
599 }
600 }
601
Hal_SC_set_wr_bank_mapping_num(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)602 void Hal_SC_set_wr_bank_mapping_num(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
603 {
604 Hal_SC_set_wr_bank_mapping(pInstance, u8Val, eWindow);
605 }
606
Hal_SC_Get_WR_Bank_Mapping(void * pInstance,SCALER_WIN eWindow)607 MS_U8 Hal_SC_Get_WR_Bank_Mapping(void *pInstance, SCALER_WIN eWindow)
608 {
609 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
610 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
611 MS_U8 u8val = 0;
612
613 if( eWindow == MAIN_WINDOW )
614 {
615 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
616 }
617 else
618 {
619 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
620 }
621 SC_DBG(printf("Get WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
622 return u8val;
623 }
624
Hal_SC_Get_WR_Bank_Mapping_Num(void * pInstance,SCALER_WIN eWindow)625 MS_U8 Hal_SC_Get_WR_Bank_Mapping_Num(void *pInstance, SCALER_WIN eWindow)
626 {
627 return Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow);
628 }
629
Hal_SC_set_csc(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)630 void Hal_SC_set_csc(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow )
631 {
632 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
633 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
634 if( eWindow == MAIN_WINDOW )
635 {
636 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, (bEnable ? BIT(3):0), BIT(3));
637 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_01_L, (bEnable ? BIT(2):0), BIT(2));
638 }
639 else
640 {
641 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_40_L, (bEnable ? BIT(3):0), BIT(3));
642 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_01_L, (bEnable ? BIT(2):0), BIT(2));
643 }
644 }
645
Hal_SC_get_ip2_csc(void * pInstance,SCALER_WIN eWindow)646 MS_BOOL Hal_SC_get_ip2_csc(void *pInstance, SCALER_WIN eWindow)
647 {
648 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
649 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
650 MS_BOOL bYUVInput;
651 if(eWindow == MAIN_WINDOW)
652 {
653 // If it has CSC, it shows it must be RGB input.
654 // Because in scaler, it must be YUV. So if input is RGB, then we need to do CSC
655 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
656 }
657 else
658 {
659 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
660 }
661 return bYUVInput;
662 }
663
Hal_SC_set_delayline(void * pInstance,MS_U8 u8DelayLines,SCALER_WIN eWindow)664 void Hal_SC_set_delayline(void *pInstance, MS_U8 u8DelayLines, SCALER_WIN eWindow )
665 {
666 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
667 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
668 //skip bit7, which is other usage
669 MS_U16 u16DelayLines = ((MS_U16)u8DelayLines) & 0xFF;
670 if( eWindow == MAIN_WINDOW )
671 {
672 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
673 }
674 else
675 {
676 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
677 }
678 }
679
Hal_SC_set_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)680 void Hal_SC_set_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
681 {
682 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
683 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
684 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
685 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
686
687 MS_PHY u32MinLimitAddress = 0;
688 MS_PHY u32MaxLimitAddress = 0;
689
690 #ifndef DONT_USE_CMA
691 #if (XC_SUPPORT_CMA ==TRUE)
692 #if ((HW_DESIGN_4K2K_VER == 4)||(HW_DESIGN_4K2K_VER == 6))
693 #if (defined (ANDROID))
694 UNUSED(u32WritelimitAddrBase);
695 UNUSED(eWindow);
696 return;
697 #endif
698 #endif
699 #endif
700 #endif
701
702 #if (HW_DESIGN_4K2K_VER == 4)
703 // in Monaco, the 4K data path need to setup the IPM write on the FRCM base, and the max/min limit region also need to change
704 if(gSrcInfo[eWindow].stCapWin.width > 3800)
705 {
706 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
707 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
708 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
709 else
710 u32MaxLimitAddress = u32MinLimitAddress;
711 }
712 //monaco mm DS VB size always be 4k2k , mvop timing is 4k2k , 2p mode
713 else if ((pXCResourcePrivate->sthal_SC.bDynamicScalingEnable || pXCResourcePrivate->stdrvXC_Dynamicscaling._bDSForceIndexEnable[eWindow] ) &&
714 (gSrcInfo[eWindow].Status2.u16VirtualBox_Width >= 0xF00) && (gSrcInfo[eWindow].Status2.u16VirtualBox_Height>= 0x870))
715 {
716 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
717 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
718 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
719 else
720 u32MaxLimitAddress = u32MinLimitAddress;
721 }
722 else
723 #endif
724 {
725 u32MinLimitAddress = MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
726 if((MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))!=0)
727 u32MaxLimitAddress = (MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
728 else
729 u32MaxLimitAddress = u32MinLimitAddress;
730 }
731 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%tx, MHal_XC_GetDNRBufSize=%tx\n", eWindow, (ptrdiff_t)(MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ),(ptrdiff_t) (MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD);
732 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%tx, u32MaxLimitAddress=%tx\n", eWindow, (ptrdiff_t)u32MinLimitAddress, (ptrdiff_t)u32MaxLimitAddress);
733
734 if(eWindow == MAIN_WINDOW)
735 {
736 /// need to disable the r/w request, when change the write limit base
737 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
738 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(0):0),BIT(0)); //F2 memory address limit enable
739 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_40_L, u32MinLimitAddress); //F2 memory min address
740 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_42_L, u32MaxLimitAddress); //F2 memory max address
741 /// need to enable the r/w request
742 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
743 }
744 else
745 {
746 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
747 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(1):0),BIT(1)); //F1 memory address limit enable
748 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_44_L, u32MinLimitAddress); //F1 memory min address
749 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_46_L, u32MaxLimitAddress); //F1 memory max address
750 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0x00, BIT(0)|BIT(1));
751 }
752 }
753
Hal_SC_set_frcm_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)754 void Hal_SC_set_frcm_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
755 {
756 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
757 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
758 MS_PHY u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
759 MS_PHY u32MaxLimitAddress = 0;
760
761 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
762 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
763 else
764 u32MaxLimitAddress = u32MinLimitAddress;
765
766 if(eWindow == MAIN_WINDOW)
767 {
768 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
769 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_64_L, u32MinLimitAddress); //F2 memory min address
770 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_66_L, u32MaxLimitAddress); //F2 memory max address
771 }
772 else
773 {
774 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(5):0),BIT(5)); //F1 memory address limit enable
775 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_68_L, u32MinLimitAddress); //F1 memory min address
776 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_6A_L, u32MaxLimitAddress); //F1 memory max address
777 }
778
779 }
780
Hal_SC_set_dual_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)781 void Hal_SC_set_dual_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
782 {
783 #ifdef SUPPORT_DUAL_MIU
784 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
785 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
786 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
787 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
788
789 MS_PHY u32MinLimitAddress = 0;
790 MS_PHY u32MaxLimitAddress = 0;
791
792 u32MinLimitAddress = MHal_XC_GetDualDNRBufSize(pInstance, eWindow)/BYTE_PER_WORD ;
793 if((MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))!=0)
794 u32MaxLimitAddress = (MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
795 else
796 u32MaxLimitAddress = u32MinLimitAddress;
797
798 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%llx, MHal_XC_GetDNRBufSize=%llx\n", eWindow, (MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ), (MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD);
799 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%llx, u32MaxLimitAddress=%llx\n", eWindow, u32MinLimitAddress, u32MaxLimitAddress);
800
801 if(eWindow == MAIN_WINDOW)
802 {
803 /// need to disable the r/w request, when change the write limit base
804 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
805 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
806 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, u32MinLimitAddress); //F2 memory min address
807 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, u32MaxLimitAddress); //F2 memory max address
808 /// need to enable the r/w request
809 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
810 }
811 #endif
812 }
813
Hal_SC_set_opm_write_limit(void * pInstance,MS_BOOL bEnable,MS_BOOL bFlag,MS_U32 u32OPWlimitAddr,SCALER_WIN eWindow)814 void Hal_SC_set_opm_write_limit(void *pInstance, MS_BOOL bEnable, MS_BOOL bFlag, MS_U32 u32OPWlimitAddr, SCALER_WIN eWindow)
815 {
816 #if 0
817
818 MS_U16 u16temp = 0x00;
819 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
820 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
821
822 // Only support address of Main_Window
823 if (eWindow != MAIN_WINDOW )
824 return;
825
826 // Bit 0 ~ 24
827 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5E_L, u32OPWlimitAddr & 0xFFFF);
828 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L, (u32OPWlimitAddr >> 16) & 0x1FF);
829
830 // OPW limit enable
831 if (bEnable)
832 u16temp = BIT(9);
833
834 // OPW limit flag 0: maximum 1:minimum
835 if (bFlag)
836 u16temp |= BIT(10);
837
838 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L,u16temp ,BIT(9) | BIT(10) );
839 #endif
840 }
841
Hal_SC_is_extra_req_en(void * pInstance,MS_U16 * pu16MainHStart,MS_U16 * pu16MainHEnd,MS_U16 * pu16SubHStart,MS_U16 * pu16SubHEnd)842 MS_BOOL Hal_SC_is_extra_req_en(void *pInstance,
843 MS_U16 *pu16MainHStart, MS_U16 *pu16MainHEnd,
844 MS_U16 *pu16SubHStart, MS_U16 *pu16SubHEnd)
845 {
846 MS_BOOL bEn = FALSE;
847 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
848 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
849
850 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
851 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
852
853 MS_U16 u16MainHStart, u16SubHStart;
854 MS_U16 u16MainHEnd, u16SubHEnd;
855 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
856 u16MainHStart = pu16MainHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L) : *pu16MainHStart;
857 u16MainHEnd = pu16MainHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) : *pu16MainHEnd;
858 u16SubHStart = pu16SubHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L) : *pu16SubHStart;
859 u16SubHEnd = pu16SubHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) : *pu16SubHEnd;
860
861 if( SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1))
862 &&(((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
863 ||(psXCInstPri->u32DeviceID == 1))
864 ) // Only Legacy mode use old rule for extra enable
865 {
866 if(u16MainHStart > u16SubHStart || u16MainHEnd < u16SubHEnd)
867 {
868 bEn = FALSE;
869 }
870 else
871 {
872 bEn = TRUE;
873 }
874 }
875 else
876 {
877 bEn = FALSE;
878 }
879 #if DBG_EN
880 SC_DBG(printf("Sub=%d, MainHs=%d, SubHs=%d, MainHe=%d, SubHe=%d :: Extra=%d\n",
881 SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1)),
882 u16MainHStart, u16SubHStart, u16MainHEnd, u16SubHEnd, bEn));
883 #endif
884 return bEn;
885
886 }
887
888 #ifdef SUPPORT_DUAL_MIU
889 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
890 // Miu opm1 opm2 need to be switched just under Dual Mirror case, so it should be Called in runtime.
891 // This API just for swap OPM when miu select control by miu arb.
_Hal_SC_adjust_dual_miu_setting(void * pInstance,MS_PHY u32FBAddress,MS_PHY u32DualFBAddress,MS_BOOL bMirrorWithDual,MS_U16 * pu16OPMLeftMiuSel,MS_U16 * pu16OPMRightMiuSel)892 static void _Hal_SC_adjust_dual_miu_setting(void *pInstance, MS_PHY u32FBAddress, MS_PHY u32DualFBAddress, MS_BOOL bMirrorWithDual, MS_U16 *pu16OPMLeftMiuSel, MS_U16 *pu16OPMRightMiuSel)
893 {
894 MS_U8 u8MIUSel = 0;
895 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
896 if (u8MIUSel == 0)
897 {
898 //IPM0 OPM0 access miu0
899 *pu16OPMLeftMiuSel = 0x0;
900 }
901 else if(u8MIUSel == 1)
902 {
903 // OPM0 access miu 1
904 *pu16OPMLeftMiuSel = 0x1;
905 }
906 else if(u8MIUSel == 2)
907 {
908 // OPM0 access miu 1
909 *pu16OPMLeftMiuSel = 0x2;
910 }
911
912 _phy_to_miu_offset(u8MIUSel, u32DualFBAddress, u32DualFBAddress);
913 if (u8MIUSel == 0)
914 {
915 //IPM0 OPM0 access miu0
916 *pu16OPMRightMiuSel = 0x0;
917 }
918 else if(u8MIUSel == 1)
919 {
920 // OPM0 access miu 1
921 *pu16OPMRightMiuSel = 0x1;
922 }
923 else if(u8MIUSel == 2)
924 {
925 // OPM0 access miu 1
926 *pu16OPMRightMiuSel = 0x2;
927 }
928
929 if (bMirrorWithDual)
930 {
931 MS_U16 u16Tmp = *pu16OPMLeftMiuSel;
932 *pu16OPMLeftMiuSel = *pu16OPMRightMiuSel;
933 *pu16OPMRightMiuSel = u16Tmp;
934 }
935
936 }
937
938 #else
939 //the patch to reset the miu selection ,becuase HW always swaps the miu selection on dual or without dual.
_Hal_SC_adjust_swap_miu_setting(void * pInstance,MS_PHY u32FBAddress)940 static void _Hal_SC_adjust_swap_miu_setting(void *pInstance,MS_PHY u32FBAddress)
941 {
942 MS_U8 u8MIUSel = 0;
943 MS_U8 u8MIUSel_temp= 0;
944 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
945 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
946 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
947 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
948 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
949 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
950 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
951 if(u8MIUSel_temp != u8MIUSel)
952 {
953 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 , 0x0010);
954 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 , 0x0010);
955 }
956 else
957 {
958 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
959 }
960 }
_Hal_SC_adjust_swap_miu_setting_burst(void * pInstance,MS_PHY u32FBAddress)961 static void _Hal_SC_adjust_swap_miu_setting_burst(void *pInstance,MS_PHY u32FBAddress)
962 {
963 MS_U8 u8MIUSel = 0;
964 MS_U8 u8MIUSel_temp= 0;
965 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
966 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
967 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
968 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
969 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
970 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
971 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
972 if(u8MIUSel_temp != u8MIUSel)
973 {
974 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 ,BIT(4));
975 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 ,BIT(4));
976 }
977 else
978 {
979 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
980 }
981 Mhal_XC_MLoad_Fire(pInstance, TRUE);
982 }
983 #endif
984 #endif
_Hal_SC_fill_main_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)985 static void _Hal_SC_fill_main_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
986 {
987 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
988 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
989 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
990 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
991
992 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
993 {
994 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
995 }
996 else
997 {
998 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
999 }
1000
1001 //H pre-scaling
1002 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1003 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1004 //V pre-scaling
1005 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1006 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1007 //H post-scaling
1008 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1009 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1010 //V post-scaling
1011 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1012 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1013
1014 //SCMI: vertical limitation
1015 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_18_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1016 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1017 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1018
1019 //SCMI: IPM address 0
1020 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_08_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1021 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_09_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1022 //SCMI: DNR address 1
1023 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1024 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1025 //SCMI: DNR address 2
1026 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1027 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1028
1029 //SCMI: DNR offset
1030 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1031 //SCMI: DNR fetch
1032 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1033
1034 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1035
1036 //SCMI: OPM address 0
1037 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1038 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_11_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1039 //SCMI: OPM address 1
1040 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_12_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1041 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_13_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1042 //SCMI: OPM address 2
1043 // Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_14_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1044 // Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_15_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1045 //SCMI: OPM offset
1046 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_16_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1047 //SCMI: OPM fetch
1048 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_17_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1049
1050 #ifdef SUPPORT_DUAL_MIU
1051 if(gSrcInfo[MAIN_WINDOW].Status2.stMiuDualModCfg.bEnableMiuDualMod)
1052 {
1053 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1054 MS_U16 u16OPMLeftMiuSel = 0;
1055 MS_U16 u16OPMRightMiuSel = 0;
1056 if(IsHMirrorMode(MAIN_WINDOW))
1057 {
1058 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1059 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1060 }
1061 else
1062 {
1063 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1064 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1065 }
1066
1067 // miu request0 IPM/OPM LSB
1068 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1069 // miu request0 IPM/OPM MSB
1070 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1071 // miu request1 IPM/OPM
1072 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1073 #else
1074 _Hal_SC_adjust_swap_miu_setting_burst(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1075 #endif
1076 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_08_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 0), 0xFFFF); //F2_1 IPM base addr
1077 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_09_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 16), 0xFFFF);
1078 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0E_L, (MS_U16)(pDBreg->u16DualDNROffset), 0x1FFF); //F2_1 IPM offset
1079 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0F_L, (MS_U16)(pDBreg->u16DualDNRFetch), 0x1FFF); //F2_1 IPM fetch number
1080 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_10_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 0), 0xFFFF); //F2_1 OPM base addr
1081 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_11_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 16), 0xFFFF);
1082 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_16_L, (MS_U16)(pDBreg->u16DualOPMOffset), 0x1FFF); //F2_1 OPM offset
1083 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_17_L, (MS_U16)(pDBreg->u16DualOPMFetch), 0x1FFF); //F2_1 OPM fetch number
1084 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_28_L, (MS_U16)(pDBreg->u16DualDNRFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16DNRFetch), 0x1FFF); //F2 IPM total fetch
1085 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, (MS_U16)(BIT(15)|(pDBreg->u16DualOPMFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16OPMFetch)), 0x1FFF | BIT(15)); //F2 OPM total fetch
1086 }
1087 else
1088 {
1089 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, 0, BIT(15));
1090 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1091 MS_U16 u16OPMLeftMiuSel = 0;
1092 MS_U16 u16OPMRightMiuSel = 0;
1093 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1094 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1095 // miu request0 IPM/OPM LSB
1096 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1097 // miu request0 IPM/OPM MSB
1098 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1099 // miu request1 IPM/OPM
1100 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1101 #endif
1102 }
1103 #endif
1104
1105 //PIP
1106 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1107 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)(pDBreg->u16LBOffset&0xFF), 0x00FF);
1108 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)(pDBreg->u16DispOffset&0xFF), 0x00FF);
1109 // if LB Offset > externded pixels of bottom A session,
1110 // there would be garbage on the left side of sub video
1111 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0x00FF))
1112 {
1113 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0x00FF);
1114 }
1115
1116 //HDR input DE Window info
1117 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_08_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0x1FFF);
1118 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_09_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0x0FFF);
1119 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1120 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1121 pDBreg->u16H_CapSize |= 0x8000;
1122 else
1123 pDBreg->u16H_CapSize |= 0x0000;
1124
1125 //capture window
1126 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1127 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1128 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1129 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1130 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1131 if (psXCInstPri->u32DeviceID == 1)
1132 {
1133 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
1134 //Display window
1135 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, u16HDEStart/2, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
1136 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart), VOP_DISPLAY_HEND_MASK);
1137 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_04_L, u16HDEStart/2, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
1138 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart), VOP_DISPLAY_HEND_MASK);
1139
1140 // E_FRC_PIPE_DELAY_MODE ePipeDlyMode = E_FRC_PIPE_DELAY_MODE_AUTO;
1141 MS_U32 u32Sc1OneLineDly = (SC_R2BYTE(0, REG_SC_BK10_0C_L) + 1)/2;
1142 MS_U32 u32Sc1TGEN_Dly = 0;
1143 {
1144 MS_U32 u32Sc0TGEN_Dly = SC0_V_DLY*u32Sc1OneLineDly + SC0_OP1_DLY + SC0_CTRL_DLY + SC0_COL_BLEND_DLY + SC0_VIP_DLY;
1145 MS_U32 u32Sc1VIP_Dly = SC1_OP1_DLY + SC1_VIP_DLY + SC1_MISC_DLY;
1146 MS_U32 u32HComp = (pDBreg->u16H_DisStart - u16HDEStart)/2;
1147 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY + u32HComp;
1148 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK68_61_L, (MS_U16)(u32Sc1TGEN_Dly%u32Sc1OneLineDly)*2, 0xFFFF);
1149 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK68_62_L, (MS_U16)(u32Sc1TGEN_Dly/u32Sc1OneLineDly), 0xFFFF);
1150 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1151 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1152 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_06_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart, 0x1FFF); // DE V start
1153 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1, 0x1FFF); // DE V end
1154 }
1155 //Display window
1156 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_07_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1157 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_08_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1158 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1159 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1160
1161 }
1162 else
1163 {
1164 //Display window
1165 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1166 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1167 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1168 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1169 }
1170 #else
1171 //Display window
1172 #if FRC_INSIDE
1173 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)&&(psXCInstPri->u32DeviceID != 1))
1174 {
1175 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart), VOP_DISPLAY_HSTART_MASK);
1176 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart +pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width-1), VOP_DISPLAY_HEND_MASK);
1177 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart), VOP_DISPLAY_VSTART_MASK);
1178 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1), VOP_DISPLAY_VEND_MASK);
1179 }
1180 else
1181 #endif
1182 {
1183 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1184 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1185 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart>>00), VOP_DISPLAY_VSTART_MASK);
1186 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), VOP_DISPLAY_VEND_MASK);
1187 }
1188 #endif
1189 // Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1190
1191 #if SUPPORT_2_FRAME_MIRROR
1192
1193 if( (gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[MAIN_WINDOW].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1194 {
1195 // 2_frmae_mirror cannot work when UC on
1196
1197 //SCMI: DNR address 1
1198 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1199 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1200
1201 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x4000,0xFFFF);// enable two frame mirror
1202
1203 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1204 {
1205 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, 0x20,0x00F0); // opm_ce_lcnt_inv
1206 }
1207 }
1208 else
1209 {
1210 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1211 {
1212 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1213 }
1214
1215 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x0000,0xFFFF);// disable two frame mirror
1216 }
1217 #endif
1218
1219 MS_U16 u16reg = 0;
1220 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1221 ||(psXCInstPri->u32DeviceID == 1))
1222 {
1223 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1224 }
1225 else
1226 {
1227 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1228 }
1229
1230
1231 if(pDBreg->bOpmLcntInv_En)
1232 {
1233 u16reg |= BIT(5);
1234 }
1235 else
1236 {
1237 u16reg &= ~ BIT(5);
1238 }
1239
1240
1241 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1242 #if (HW_DESIGN_4K2K_VER == 4)
1243 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1244 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1245 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1246 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1247 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1248 {
1249 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1250 if(pDBreg->bOpmLcntInv_En)
1251 {
1252 u16reg |= BIT(4);
1253 }
1254 else
1255 {
1256 u16reg &= ~ BIT(4);
1257 }
1258 }
1259 #endif
1260
1261 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1262 ||(psXCInstPri->u32DeviceID == 1))
1263 {
1264 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1265 }
1266 else
1267 {
1268 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1269 }
1270 #ifdef XC_SUPPORT_2STEP_SCALING
1271 if(MDrv_XC_IsSupport2StepScaling())
1272 {
1273 //VIP is FHD resolution
1274
1275 //mantis 1173333: Fix by HW RD David.shih's advice (/4). (mantis 1173333 is mantis 1152986's side effect)
1276 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_17_L, (pDBreg->u16H_DisEnd - pDBreg->u16H_DisStart+1)/4, 0x1FFF);//set user mode Hsize
1277 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_17_L, BIT(15), BIT(15));//2stepscaling need check Hsize,otherwise nosignal main window will disappear
1278 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, BIT(0), BIT(0));
1279 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK18_75_L, 0, BIT(2));
1280 }
1281 else
1282 {
1283 //VIP is 4K resolution
1284 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_17_L, 0, 0x1FFF);
1285 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_17_L, 0, BIT(15));
1286 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, 0, BIT(0));
1287 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK18_75_L, BIT(2), BIT(2));
1288 }
1289 #endif
1290 }
1291
_Hal_SC_fill_sub_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)1292 static void _Hal_SC_fill_sub_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
1293 {
1294 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1295 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1296 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1297 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1298
1299 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1300 {
1301 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
1302 }
1303 else
1304 {
1305 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
1306 }
1307
1308 //H pre-scaling
1309 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1310 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1311 //V pre-scaling
1312 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1313 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1314
1315 //H post-scaling
1316 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_27_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1317 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_28_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1318 //V post-scaling
1319 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_29_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1320 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_2A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1321
1322 //SCMI: vertical limitation
1323 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_58_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1324 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5A_L, (MS_U16)(pDBreg->u32WritelimitBase>>00), 0xFFFF);
1325 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5B_L, (MS_U16)(pDBreg->u32WritelimitBase>>16), 0xFFFF);
1326 //SCMI: IPM address 0
1327 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_48_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1328 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_49_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1329 //SCMI: DNR address 1
1330 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1331 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1332 //SCMI: DNR address 2
1333 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1334 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1335 //SCMI: DNR offset
1336 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1337 //SCMI: DNR fetch
1338 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1339 //SCMI: OPM address 0
1340 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_50_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1341 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_51_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1342 //SCMI: OPM address 1
1343 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_52_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1344 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_53_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1345 //SCMI: OPM address 2
1346 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_54_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1347 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_55_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1348 //SCMI: OPM offset
1349 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_56_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1350 //SCMI: OPM fetch
1351 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_57_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1352 //PIP
1353 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_16_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1354 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)((pDBreg->u16LBOffset&0xFF)<<8), 0xFF00);
1355 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)((pDBreg->u16DispOffset&0xFF)<<8), 0xFF00);
1356
1357 /// before enable ML bit mask feature, the capture size for 2P setting BK03_07[15] need to be considered
1358 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, BIT(15)))
1359 pDBreg->u16H_CapSize |= 0x8000;
1360 else
1361 pDBreg->u16H_CapSize |= 0x0000;
1362
1363 // capture window
1364 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1365 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1366 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1367 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1368
1369 //Display window
1370 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, (MS_U16)(pDBreg->u16H_DisStart>>00), 0xFFFF);
1371 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), 0xFFFF);
1372 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, (MS_U16)(pDBreg->u16V_DisStart>>00), 0xFFFF);
1373 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), 0xFFFF);
1374
1375 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1376
1377 MS_U16 u16reg = 0;
1378 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1379 ||(psXCInstPri->u32DeviceID == 1))
1380 {
1381 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1382 }
1383 else
1384 {
1385 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1386 }
1387
1388 if(pDBreg->bOpmLcntInv_En)
1389 {
1390 u16reg |= BIT(4);
1391 }
1392 else
1393 {
1394 u16reg &= ~ BIT(4);
1395 }
1396
1397 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1398 ||(psXCInstPri->u32DeviceID == 1))
1399 {
1400 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1401 }
1402 else
1403 {
1404 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1405 }
1406 }
1407
Hal_SC_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1408 void Hal_SC_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1409 {
1410 _MLOAD_ENTRY(pInstance);
1411
1412 if( eWindow == MAIN_WINDOW )
1413 {
1414 _Hal_SC_fill_main_sw_db_burst(pInstance, pDBreg);
1415 Mhal_XC_MLoad_Fire(pInstance, TRUE);
1416 }
1417 else
1418 {
1419 _Hal_SC_fill_sub_sw_db_burst(pInstance, pDBreg);
1420 Mhal_XC_MLoad_Fire(pInstance, TRUE);
1421 }
1422
1423 _MLOAD_RETURN(pInstance);
1424 }
1425
Hal_SC_dual_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pMainDBreg,P_SC_SWDB_INFO pSubDBreg)1426 void Hal_SC_dual_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pMainDBreg, P_SC_SWDB_INFO pSubDBreg)
1427 {
1428 _MLOAD_ENTRY(pInstance);
1429
1430 _Hal_SC_fill_main_sw_db_burst(pInstance, pMainDBreg);
1431 _Hal_SC_fill_sub_sw_db_burst(pInstance, pSubDBreg);
1432 Mhal_XC_MLoad_Fire(pInstance, TRUE);
1433
1434 _MLOAD_RETURN(pInstance);
1435 }
1436
Hal_SC_sw_db(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1437 void Hal_SC_sw_db(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1438 {
1439 MS_U32 u32LcentInvReg = 0;
1440 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1441 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1442 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1443 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1444
1445 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] bDynamicScalingEnable%d \n",__func__,__LINE__,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1446
1447 if( eWindow == MAIN_WINDOW )
1448 {
1449 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
1450 {
1451 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1452 }
1453 else
1454 {
1455 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1456 }
1457
1458 // H pre-scaling
1459 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, pDBreg->u32H_PreScalingRatio);
1460 // V pre-scaling
1461 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, pDBreg->u32V_PreScalingRatio);
1462 // H post-scaling
1463 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, pDBreg->u32H_PostScalingRatio);
1464 // V post-scaling
1465 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, pDBreg->u32V_PostScalingRatio);
1466
1467 //SCMI
1468 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, pDBreg->u16VWritelimit); // Set vertical limitation
1469 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1);
1470
1471 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, pDBreg->u32DNRBase0); // input address0
1472 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, pDBreg->u32DNRBase1); // input address1
1473 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, pDBreg->u32DNRBase2); // input address2
1474
1475 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pDBreg->u16DNROffset);// input Offset
1476 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pDBreg->u16DNRFetch); // input fetch
1477 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1478
1479
1480 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, pDBreg->u32OPMBase0); // output address0
1481 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, pDBreg->u32OPMBase1); // output address1
1482 // SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_14_L, pDBreg->u32OPMBase2); // output address2
1483 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, pDBreg->u16OPMOffset); // output offset
1484 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, pDBreg->u16OPMFetch); // output fetch
1485
1486 #ifdef SUPPORT_DUAL_MIU
1487 if(gSrcInfo[eWindow].Status2.stMiuDualModCfg.bEnableMiuDualMod)
1488 {
1489 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1490 MS_U16 u16OPMLeftMiuSel = 0;
1491 MS_U16 u16OPMRightMiuSel = 0;
1492 if(IsHMirrorMode(eWindow))
1493 {
1494 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1495 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1496 }
1497 else
1498 {
1499 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1500 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1501 }
1502 // miu request0 IPM/OPM LSB
1503 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1504 // miu request0 IPM/OPM MSB
1505 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1506 // miu request1 IPM/OPM
1507 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1508 #else
1509 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1510 #endif
1511 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, pDBreg->u32DualDNRBase0 >> 0, 0xFFFF); //F2_1 IPM base addr
1512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_09_L, pDBreg->u32DualDNRBase0 >> 16, 0x03FF);
1513 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0E_L, pDBreg->u16DualDNROffset, 0x1FFF); //F2_1 IPM offset
1514 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0F_L, pDBreg->u16DualDNRFetch, 0x1FFF); //F2_1 IPM fetch number
1515 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, pDBreg->u32DualOPMBase0 >> 0, 0xFFFF); //F2_1 OPM base addr
1516 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_11_L, pDBreg->u32DualOPMBase0 >> 16, 0x03FF);
1517 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_16_L, pDBreg->u16DualOPMOffset, 0x1FFF); //F2_1 OPM offset
1518 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_17_L, pDBreg->u16DualOPMFetch, 0x1FFF); //F2_1 OPM fetch number
1519 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_28_L, pDBreg->u16DualDNRFetch + pDBreg->u16DNRFetch, 0x1FFF); //F2 IPM total fetch
1520 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, pDBreg->u16DualOPMFetch + pDBreg->u16OPMFetch, 0x1FFF); //F2 OPM total fetch
1521 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, BIT(15), BIT(15)); //Enable SCMI MIU Dual mode
1522 }
1523 else
1524 {
1525 SC_W2BYTEMSK(0, REG_SC_BK11_29_L, 0, BIT(15));
1526 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1527 MS_U16 u16OPMLeftMiuSel = 0;
1528 MS_U16 u16OPMRightMiuSel = 0;
1529 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1530 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1531 // miu request0 IPM/OPM LSB
1532 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1533 // miu request0 IPM/OPM MSB
1534 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1535 // miu request1 IPM/OPM
1536 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1537 #else
1538 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW]);
1539 #endif
1540 }
1541 #endif
1542
1543 //PIP
1544 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, pDBreg->u16VLen); // Write V length
1545 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1546 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF), 0xFF);
1547 // if LB Offset > externded pixels of bottom A session,
1548 // there would be garbage on the left side of sub video
1549 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0xFF))
1550 {
1551 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1552 }
1553
1554 //HDR input DE Window info
1555 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_08_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0x1FFF);
1556 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_09_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0x0FFF);
1557 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1558 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1559 pDBreg->u16H_CapSize |= 0x8000;
1560 else
1561 pDBreg->u16H_CapSize |= 0x0000;
1562
1563 // capture window
1564 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, pDBreg->u16V_CapStart); // Capture V start
1565 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, pDBreg->u16H_CapStart); // Capture H start
1566 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, pDBreg->u16V_CapSize); // Capture V size
1567 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, pDBreg->u16H_CapSize); // Capture H size
1568
1569 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1570 //Display window
1571 if (psXCInstPri->u32DeviceID == 1)
1572 {
1573 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
1574 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, u16HDEStart/2);//temp solution(+90)
1575 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart));
1576 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, u16HDEStart/2);//temp solution(+90)
1577 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart));
1578
1579 // E_FRC_PIPE_DELAY_MODE ePipeDlyMode = E_FRC_PIPE_DELAY_MODE_AUTO;
1580 MS_U32 u32Sc1OneLineDly = (SC_R2BYTE(0, REG_SC_BK10_0C_L) + 1)/2;
1581 MS_U32 u32Sc1TGEN_Dly = 0;
1582 {
1583 MS_U32 u32Sc0TGEN_Dly = SC0_V_DLY*u32Sc1OneLineDly + SC0_OP1_DLY + SC0_CTRL_DLY + SC0_COL_BLEND_DLY + SC0_VIP_DLY;
1584 MS_U32 u32Sc1VIP_Dly = SC1_OP1_DLY + SC1_VIP_DLY + SC1_MISC_DLY;
1585 MS_U32 u32HComp = (pDBreg->u16H_DisStart - u16HDEStart)/2;
1586 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY + u32HComp;
1587
1588 SC_W2BYTEMSK(0, REG_SC_BK68_61_L, (u32Sc1TGEN_Dly%u32Sc1OneLineDly)*2, 0xFFFF);
1589 SC_W2BYTEMSK(0, REG_SC_BK68_62_L, u32Sc1TGEN_Dly/u32Sc1OneLineDly, 0xFFFF);
1590 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart);
1591 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd);
1592 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart, 0x1FFF); // DE V start
1593 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1, 0x1FFF); // DE V end
1594 }
1595 }
1596 else
1597 {
1598 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pDBreg->u16H_DisStart);
1599 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pDBreg->u16H_DisEnd);
1600 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart);
1601 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd);
1602 }
1603
1604 if (psXCInstPri->u32DeviceID == 1)//follow HW_DESIGN_4K2K_VER = 6 rule
1605 {
1606 //Display window
1607 SC_W2BYTE(0, REG_SC_BK0F_07_L, pDBreg->u16H_DisStart); // Display H start
1608 SC_W2BYTE(0, REG_SC_BK0F_08_L, pDBreg->u16H_DisEnd); // Display H end
1609 SC_W2BYTE(0, REG_SC_BK0F_09_L, pDBreg->u16V_DisStart); // Display V start
1610 SC_W2BYTE(0, REG_SC_BK0F_0A_L, pDBreg->u16V_DisEnd); // Display V end
1611 }
1612 #else
1613 //Display window
1614 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pDBreg->u16H_DisStart); // Display H start
1615 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pDBreg->u16H_DisEnd); // Display H end
1616 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart); // Display V start
1617 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd); // Display V end
1618 #endif
1619
1620 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1621
1622 // 2_frame_mirror setting
1623 #if SUPPORT_2_FRAME_MIRROR
1624 // 2_frmae_mirror cannot work when UC on
1625 if( (gSrcInfo[eWindow].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[eWindow].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1626 {
1627 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1); // IPM base1
1628 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x4000, BIT(14)); // enable two frame mirror
1629
1630 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1631 {
1632 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, 0X20 ,0x00F0 ); // opm_ce_lcnt_inv
1633 }
1634 }
1635 else
1636 {
1637 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1638 {
1639 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1640 }
1641
1642 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x00 , BIT(14)); // disable two frame mirror
1643 }
1644 #endif
1645 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1646 ||(psXCInstPri->u32DeviceID == 1))
1647 {
1648 u32LcentInvReg = REG_SC_BK08_32_L;
1649 }
1650 else
1651 {
1652 u32LcentInvReg = REG_SC_BK33_32_L;
1653 }
1654
1655 if(pDBreg->bOpmLcntInv_En)
1656 {
1657 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(5), BIT(5));
1658 }
1659 else
1660 {
1661 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(5));
1662 }
1663
1664 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1665 #if (HW_DESIGN_4K2K_VER == 4)
1666 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1667 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1668 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1669 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1670 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1671 {
1672 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1673 if(pDBreg->bOpmLcntInv_En)
1674 {
1675 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1676 }
1677 else
1678 {
1679 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1680 }
1681 }
1682 #endif
1683 #ifdef XC_SUPPORT_2STEP_SCALING
1684 if(MDrv_XC_IsSupport2StepScaling())
1685 {
1686 //VIP is FHD resolution
1687
1688 //mantis 1173333: Fix by HW RD David.shih's advice (/4). (mantis 1173333 is mantis 1152986's side effect)
1689 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_17_L, (pDBreg->u16H_DisEnd - pDBreg->u16H_DisStart+1)/4, 0x1FFF);//set user mode Hsize
1690 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_17_L, BIT(15), BIT(15));//2stepscaling will check Hsize,otherwise nosignal main window will disappear
1691 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_10_L, BIT(0), BIT(0));
1692 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_75_L, 0, BIT(2));
1693 }
1694 else
1695 {
1696 //VIP is 4K resolution
1697 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_17_L, 0, 0x1FFF);
1698 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_17_L, 0, BIT(15));
1699 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK4F_10_L, 0, BIT(0));
1700 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_75_L, BIT(2), BIT(2));
1701 }
1702 #endif
1703 }
1704 else
1705 {
1706 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1707 {
1708 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1709 }
1710 else
1711 {
1712 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1713 }
1714
1715 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_04_L, pDBreg->u32H_PreScalingRatio); // H pre-scaling
1716 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_08_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
1717
1718 //HVSP
1719 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_27_L, pDBreg->u32H_PostScalingRatio); // H post-scaling
1720 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_29_L, pDBreg->u32V_PostScalingRatio); // V post-scaling
1721
1722 //SCMI
1723 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_58_L, pDBreg->u16VWritelimit); // Set vertical limitation
1724 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5A_L, pDBreg->u32WritelimitBase);
1725 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, pDBreg->u32DNRBase0); // input address0
1726 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L, pDBreg->u32DNRBase1); // input address1
1727 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4C_L, pDBreg->u32DNRBase2); // input address2
1728 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, pDBreg->u16DNROffset);// input Offset
1729 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, pDBreg->u16DNRFetch); // input fetch
1730 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, pDBreg->u32OPMBase0); // output address0
1731 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, pDBreg->u32OPMBase1); // output address1
1732 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_54_L, pDBreg->u32OPMBase2); // output address2
1733 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, pDBreg->u16OPMOffset); // output offset
1734 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, pDBreg->u16OPMFetch); // output fetch
1735 //PIP
1736 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, pDBreg->u16VLen); // Write V length
1737 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF)<<8, 0xFF00);
1738 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF)<<8, 0xFF00);
1739
1740 // capture window
1741 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, pDBreg->u16V_CapStart); // Capture V start
1742 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, pDBreg->u16H_CapStart); // Capture H start
1743 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, pDBreg->u16V_CapSize); // Capture V size
1744 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, pDBreg->u16H_CapSize); // Capture H size
1745
1746 //Display window
1747 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pDBreg->u16H_DisStart); // Display H start
1748 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pDBreg->u16H_DisEnd); // Display H end
1749 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pDBreg->u16V_DisStart); // Display V start
1750 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pDBreg->u16V_DisEnd); // Display V end
1751
1752 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1753
1754 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1755 ||(psXCInstPri->u32DeviceID == 1))
1756 {
1757 u32LcentInvReg = REG_SC_BK08_32_L;
1758 }
1759 else
1760 {
1761 u32LcentInvReg = REG_SC_BK33_32_L;
1762 }
1763
1764 if(pDBreg->bOpmLcntInv_En)
1765 {
1766 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1767 }
1768 else
1769 {
1770 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1771 }
1772 }
1773 }
1774
Hal_SC_SWDS_AddCmd(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1775 void Hal_SC_SWDS_AddCmd(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow)
1776 {
1777 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1778 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1779 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1780 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1781
1782 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] eWindow:%d bDynamicScalingEnable%d \n",__func__,__LINE__,eWindow,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1783
1784 XC_DS_CMDCNT PSTXC_DS_CMDCNT;
1785
1786 PSTXC_DS_CMDCNT.u16CMDCNT_IPM =0;
1787 PSTXC_DS_CMDCNT.u16CMDCNT_IPS =0;
1788 PSTXC_DS_CMDCNT.u16CMDCNT_OPM =0;
1789 PSTXC_DS_CMDCNT.u16CMDCNT_OPS =0;
1790
1791 if(eWindow == MAIN_WINDOW)
1792 {
1793 if(pXCResourcePrivate->sthal_SC.bDynamicScalingEnable)
1794 {
1795 pXCResourcePrivate->sthal_SC.u8DynamicScalingNextIndex[MAIN_WINDOW] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[MAIN_WINDOW];
1796
1797 //Command Priority:
1798 //1.GOP
1799 //2.MVOP
1800 //3.XC
1801 //---------------------------------------------------------------------IP Command Start---------------------------------------------------------------------------------------//
1802
1803 MS_U32 ActiveSWClearEn = 0;
1804 MS_U32 u32SW_Reset_Enable = 0;
1805 //ActiveSWClearEn enable in first DS IP command ;
1806 u32SW_Reset_Enable = 0x4000; // bit14: reg_ds_ipm_active_clr
1807 ActiveSWClearEn = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK1F_17_L, 0xFFFF);
1808 ActiveSWClearEn |= u32SW_Reset_Enable;
1809
1810 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1811
1812 //XC_PRINTF("[%s,%5d] bR_FBL:%d bFBL:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].bR_FBL,gSrcInfo[MAIN_WINDOW].bFBL);
1813 //XC_PRINTF("[%s,%5d] Crop(x,y,w,h)=(%d,%d,%d,%d) \n",__func__,__LINE__,gSrcInfo[eWindow].stCropWin.x,gSrcInfo[eWindow].stCropWin.y,gSrcInfo[eWindow].stCropWin.width,gSrcInfo[eWindow].stCropWin.height);
1814
1815 if(IsSrcTypeStorage(gSrcInfo[MAIN_WINDOW].enInputSourceType))
1816 {
1817 if((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL))//set MVOP crop info
1818 {
1819 // GET MVOP crop info first
1820 MVOP_Handle stHdl = { E_MVOP_MODULE_MAIN };
1821 MVOP_XCGetCrop stCropInfo;
1822 stCropInfo.u16XStart = gSrcInfo[eWindow].stCropWin.x;
1823 stCropInfo.u16YStart = gSrcInfo[eWindow].stCropWin.y;
1824 stCropInfo.u16XSize = gSrcInfo[eWindow].stCropWin.width;
1825 stCropInfo.u16YSize = gSrcInfo[eWindow].stCropWin.height;
1826
1827 MDrv_MVOP_GetCommand(&stHdl, E_MVOP_CMD_GET_CROP_FOR_XC, &stCropInfo, sizeof(MVOP_XCGetCrop));
1828
1829 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,stCropInfo.u16XStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
1830 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000|stCropInfo.u16YStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
1831 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,stCropInfo.u16XSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
1832 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,stCropInfo.u16YSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
1833 pDBreg->u16LBOffset = 0; // mvop do crop, align in 2pixel, so xc don't need crop
1834 }
1835 else
1836 {
1837 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
1838 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
1839 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
1840 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
1841 }
1842 }
1843
1844 //H pre-scaling
1845 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_04_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8104XXXX
1846 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_05_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8105XXXX
1847 //V pre-scaling
1848 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_08_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8108XXXX
1849 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_09_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8109XXXX
1850
1851 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_18_L,(MS_U16)(pDBreg->u16VWritelimit>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8918XXXX
1852
1853 if(IsVMirrorMode(MAIN_WINDOW))
1854 {
1855 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_08_L,(MS_U16)(pDBreg->u32DNRBase0>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1856 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_09_L,(MS_U16)(pDBreg->u32DNRBase0>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1857 }
1858 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_0F_L,(MS_U16)(pDBreg->u16DNRFetch>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 890FXXXX
1859
1860 //H_mirror_offset
1861 if(IsHMirrorMode(MAIN_WINDOW)||IsVMirrorMode(MAIN_WINDOW))
1862 {
1863 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] VB_width:%d framNum:%d u8BitPerPixel:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].Status2.u16VirtualBox_Width,Hal_XC_TransFrameNumToFactor(pInstance,gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber, gSrcInfo[MAIN_WINDOW].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED),gSrcInfo[MAIN_WINDOW].u8BitPerPixel);
1864
1865 MS_U32 H_mirror_offset;
1866 H_mirror_offset = (gSrcInfo[eWindow].Status2.u16VirtualBox_Width * gSrcInfo[eWindow].u8BitPerPixel * 2 / 8 * Hal_XC_TransFrameNumToFactor(pInstance,gSrcInfo[eWindow].Status2.eFrameStoreNumber, gSrcInfo[eWindow].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED)) / BYTE_PER_WORD;
1867
1868 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,H_mirror_offset,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
1869 }
1870 else
1871 {
1872 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,0x0000,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
1873 }
1874
1875 //HDR input DE Window info
1876 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_08_L,(MS_U16)(pDBreg->u16H_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1877 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_09_L,(MS_U16)(pDBreg->u16V_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1878 //Cap info
1879 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1880 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1881 pDBreg->u16H_CapSize |= 0x8000;
1882 else
1883 pDBreg->u16H_CapSize |= 0x0000;
1884
1885 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_06_L,(MS_U16)(pDBreg->u16V_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8086XXXX
1886 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_07_L,(MS_U16)(pDBreg->u16H_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8087XXXX
1887
1888 #if (SUPPORT_KERNEL_DS == 0)//if SUPPORT_KERNEL_DS is true,this cmd will be set in kernel ds
1889 //toggle reg_ds_ipm_active_set in last DS IP command
1890 MS_U32 u32SW_Reset_IPM = 0;
1891 u32SW_Reset_IPM = 0x0010 ;//bit4 : reg_ds_ipm_active_clr
1892 ActiveSWClearEn |= u32SW_Reset_IPM;
1893 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1894 #endif
1895 //---------------------------------------------------------------------IP Command End---------------------------------------------------------------------------------------//
1896
1897 //---------------------------------------------------------------------OP Command Start---------------------------------------------------------------------------------------//
1898 if(!((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL))) //FB case
1899 {
1900 //H post-scaling
1901 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_07_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9187XXXX
1902 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_08_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9188XXXX
1903 //V post-scaling
1904 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_09_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9189XXXX
1905 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_0A_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 918AXXXX
1906
1907 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8910XXXX
1908 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_11_L,(MS_U16)(pDBreg->u32OPMBase0>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8911XXXX
1909 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_17_L,(MS_U16)(pDBreg->u16OPMFetch>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM fetch //0xFFFF0009 8917XXXX
1910 //Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len
1911 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1912 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1913 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len //0xFFFF0009 9015XXXX
1914 #if FRC_INSIDE
1915 //STGEN setting
1916 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_23_L,(MS_U16)(0x0001),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1917
1918 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled)&&(psXCInstPri->u32DeviceID != 1))
1919 {
1920 if(MHal_FRC_IsFHDToFSC(pInstance,MAIN_WINDOW))
1921 {
1922 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_05_L,(MS_U16)((pDBreg->u16H_DisStart/2 +1) & ~1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1923 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_06_L,(MS_U16)( ((pDBreg->u16H_DisStart/2 +1) & ~1) + gSrcInfo[eWindow].stDispWin.width/2 - 1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1924 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0D_L,(MS_U16)( (pDBreg->u16V_DisStart/2)+ VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1925 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0E_L,(MS_U16)((pDBreg->u16V_DisEnd/2) + VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1926 }
1927 else
1928 {
1929 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_05_L,(MS_U16)(pDBreg->u16H_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1930 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_06_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1931 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0D_L,(MS_U16)(pDBreg->u16V_DisStart + VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1932 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0E_L,(MS_U16)(pDBreg->u16V_DisEnd + VSTART_OFFSET ),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1933 }
1934 }
1935
1936 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_23_L,(MS_U16)(0x0000),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1937 #endif
1938
1939 #if FRC_INSIDE
1940 //Disp info
1941 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled && pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)&&(psXCInstPri->u32DeviceID != 1))
1942 {
1943 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
1944 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart +pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width-1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
1945 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
1946 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
1947 }
1948 else
1949 #endif
1950 {
1951 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pDBreg->u16H_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
1952 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
1953 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pDBreg->u16V_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
1954 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pDBreg->u16V_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
1955 }
1956 }
1957 else //RFBL or FBL case
1958 {
1959 //H post-scaling
1960 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_07_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9187XXXX
1961 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_08_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9188XXXX
1962 //V post-scaling
1963 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_09_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9189XXXX
1964 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_0A_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 918AXXXX
1965
1966 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8910XXXX
1967 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_11_L,(MS_U16)(pDBreg->u32OPMBase0>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8911XXXX
1968 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_17_L,(MS_U16)(pDBreg->u16OPMFetch>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM fetch //0xFFFF0009 8917XXXX
1969 //Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len
1970 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1971 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1972 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // V Len //0xFFFF0009 9015XXXX
1973 //Disp info
1974 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pDBreg->u16H_DisStart),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
1975 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
1976 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pDBreg->u16V_DisStart),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
1977 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pDBreg->u16V_DisEnd),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
1978 }
1979 //---------------------------------------------------------------------OP Command End---------------------------------------------------------------------------------------//
1980
1981 MS_U8 u8MaxCmdCnt = pXCResourcePrivate->sthal_SC.u8DynamicScalingIndexDepth * (Hal_XC_MLoad_Get_64Bits_MIU_Bus_Sel(pInstance) + 1);
1982
1983 //XC_PRINTF("[%s,%5d] u16CMDCNT_IPM:%d u8MaxCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_IPM,u8MaxCmdCnt);
1984 //XC_PRINTF("[%s,%5d] u16CMDCNT_OPM:%d u8MaxCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_OPM,u8MaxCmdCnt);
1985 if(PSTXC_DS_CMDCNT.u16CMDCNT_IPM < u8MaxCmdCnt)
1986 {
1987 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_IP,&PSTXC_DS_CMDCNT);
1988 }
1989 if(!((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL)))
1990 {
1991 if(PSTXC_DS_CMDCNT.u16CMDCNT_OPM < u8MaxCmdCnt)
1992 {
1993 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_OP,&PSTXC_DS_CMDCNT);
1994 }
1995 }
1996 }
1997 }
1998 }
1999
Hal_SC_SWDS_Fire(void * pInstance,SCALER_WIN eWindow)2000 void Hal_SC_SWDS_Fire(void *pInstance, SCALER_WIN eWindow)
2001 {
2002 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2003 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2004 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2005 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2006
2007 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]++;
2008 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]);
2009
2010 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow] % DS_BUFFER_NUM_EX;
2011 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx_Ring:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow])
2012 }
2013
Hal_SC_VIP_Peaking_Setting(void * pInstance,SCALER_WIN eWindow)2014 E_APIXC_ReturnValue Hal_SC_VIP_Peaking_Setting(void *pInstance, SCALER_WIN eWindow)
2015 {
2016 UNUSED(eWindow);
2017 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
2018 }
2019
Hal_SC_support_source_to_ve(void * pInstance,MS_U16 * pOutputCapability)2020 E_APIXC_ReturnValue Hal_SC_support_source_to_ve(void *pInstance, MS_U16* pOutputCapability)
2021 {
2022 *pOutputCapability = E_XC_IP | E_XC_OP2 | E_XC_OVERLAP;
2023 return E_APIXC_RET_OK;
2024 }
2025
Hal_SC_set_output_capture_enable(void * pInstance,MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)2026 E_APIXC_ReturnValue Hal_SC_set_output_capture_enable(void *pInstance, MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)
2027 {
2028 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2029 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2030 MS_BOOL bCaptureEna;
2031 MS_U16 u16CaptureSrc;
2032 // Current only support IP and OP2
2033 bCaptureEna = bEnable;
2034 switch(eSourceToVE)
2035 {
2036 case E_XC_VOP2:
2037 case E_XC_OVERLAP: // compatible to previous IC, overlap is before osd blending
2038 u16CaptureSrc = 0;
2039 break;
2040 case E_XC_OP2:
2041 u16CaptureSrc = 1;
2042 break;
2043 case E_XC_BRI:
2044 u16CaptureSrc = 3;
2045 break;
2046 default:
2047 u16CaptureSrc = 0;
2048 bCaptureEna = FALSE;
2049 break;
2050 }
2051
2052 if(bCaptureEna)
2053 {
2054 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(11), BIT(11)); // Disable
2055 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, u16CaptureSrc<<4, BMASK(7:4)); // Disable
2056 }
2057 else
2058 {
2059 //DIP and VE Opcapture both need enable this bit, so dont disable it.
2060 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0, BIT(11)); // Disable
2061 }
2062 return E_APIXC_RET_OK; // Support Scaler OP -> VE
2063 }
2064
2065 /******************************************************************************/
2066 ///Set output DE window size
2067 ///@param pstWindow \b IN
2068 ///- pointer to window information
2069 /******************************************************************************/
Hal_SC_set_de_window(void * pInstance,XC_PANEL_INFO * pPanel_Info)2070 void Hal_SC_set_de_window(void *pInstance, XC_PANEL_INFO *pPanel_Info)
2071 {
2072 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2073 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2074 #ifdef new_chakra
2075 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2076 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2077 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pPanel_Info->u16VStart); // DE V start
2078 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pPanel_Info->u16VStart + pPanel_Info->u16Height - 1); // DE V end
2079 #else
2080 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2081 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2082 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pSrcInfo->u8DE_V_Start); // DE V start
2083 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pSrcInfo->u16DE_V_End); // DE V end
2084 #endif
2085 }
2086
Hal_SC_get_disp_de_window(void * pInstance,MS_WINDOW_TYPE * pWin)2087 void Hal_SC_get_disp_de_window(void *pInstance, MS_WINDOW_TYPE *pWin)
2088 {
2089 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2090 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2091 pWin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L);
2092 pWin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L);
2093 pWin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L) - pWin->x + 1;
2094 pWin->height= SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L) - pWin->y + 1;
2095 }
2096
Hal_SC_Get_DNRBase0(void * pInstance,SCALER_WIN eWindow)2097 MS_PHY Hal_SC_Get_DNRBase0(void *pInstance, SCALER_WIN eWindow)
2098 {
2099 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2100 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2101 if(eWindow == MAIN_WINDOW)
2102 {
2103 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L); // input address0
2104 }
2105 else
2106 {
2107 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L); // input address0
2108 }
2109 }
2110
Hal_SC_Get_DNRBase1(void * pInstance,SCALER_WIN eWindow)2111 MS_PHY Hal_SC_Get_DNRBase1(void *pInstance, SCALER_WIN eWindow)
2112 {
2113 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2114 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2115 if(eWindow == MAIN_WINDOW)
2116 {
2117 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L); // input address1
2118 }
2119 else
2120 {
2121 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L); // input address1
2122 }
2123 }
2124
Hal_SC_Get_OPMBase0(void * pInstance,SCALER_WIN eWindow)2125 MS_PHY Hal_SC_Get_OPMBase0(void *pInstance, SCALER_WIN eWindow)
2126 {
2127 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2128 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2129 if(eWindow == MAIN_WINDOW)
2130 {
2131 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L); // output address0
2132 }
2133 else
2134 {
2135 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L); // output address0
2136 }
2137 }
2138
Hal_SC_Get_OPMBase1(void * pInstance,SCALER_WIN eWindow)2139 MS_PHY Hal_SC_Get_OPMBase1(void *pInstance, SCALER_WIN eWindow)
2140 {
2141 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2142 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2143 if(eWindow == MAIN_WINDOW)
2144 {
2145 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L); // output address1
2146 }
2147 else
2148 {
2149 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L); // output address1
2150 }
2151 }
2152
Hal_SC_Get_FRCMBaseAddr(void * pInstance,MS_U8 u8id,SCALER_WIN eWindow)2153 MS_PHY Hal_SC_Get_FRCMBaseAddr(void *pInstance, MS_U8 u8id,SCALER_WIN eWindow)
2154 {
2155 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2156 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2157 if(eWindow == MAIN_WINDOW)
2158 {
2159 if(u8id == 0)
2160 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L); // frcm_w base address0
2161 else if(u8id == 1)
2162 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L); // frcm_w base address1
2163 else //if(u8id == 2)
2164 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_0C_L); // frcm_w base address2
2165 }
2166 else
2167 {
2168 if(u8id == 0)
2169 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L); // frcm_w base address0
2170 else if(u8id == 1)
2171 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4A_L); // frcm_w base address1
2172 else //if(u8id == 2)
2173 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4C_L); // frcm_w base address2
2174 }
2175 }
2176
Hal_SC_Get_LBOffset(void * pInstance,SCALER_WIN eWindow)2177 MS_U8 Hal_SC_Get_LBOffset(void *pInstance, SCALER_WIN eWindow)
2178 {
2179 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2180 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2181 if(eWindow == MAIN_WINDOW)
2182 {
2183 return SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0x00FF);
2184 }
2185 else
2186 {
2187 return (SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0xFF00) >> 8);
2188 }
2189 }
2190
Hal_SC_Set_LBOffset(void * pInstance,MS_U8 u8LBOffset,SCALER_WIN eWindow)2191 void Hal_SC_Set_LBOffset(void *pInstance, MS_U8 u8LBOffset, SCALER_WIN eWindow)
2192 {
2193 if(eWindow == MAIN_WINDOW)
2194 {
2195 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset, 0x00FF);
2196 }
2197 else
2198 {
2199 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset << 8, 0xFF00);
2200 }
2201 }
2202
Hal_SC_set_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2203 void Hal_SC_set_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2204 {
2205 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2206 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2207 if(eWindow == MAIN_WINDOW)
2208 {
2209 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2210 }
2211 else
2212 {
2213 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2214 }
2215 }
2216
Hal_SC_set_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2217 void Hal_SC_set_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2218 {
2219 UNUSED(u32DNRBase1);
2220 UNUSED(eWindow);
2221 }
2222
Hal_SC_set_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2223 void Hal_SC_set_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2224 {
2225 UNUSED(u32DNRBase2);
2226 UNUSED(eWindow);
2227 }
2228
Hal_SC_set_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2229 void Hal_SC_set_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2230 {
2231 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2232 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2233 if(eWindow == MAIN_WINDOW)
2234 {
2235 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2236 }
2237 else
2238 {
2239 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2240 }
2241 }
2242
Hal_SC_set_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2243 void Hal_SC_set_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2244 {
2245 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2246 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2247 if(eWindow == MAIN_WINDOW)
2248 {
2249 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2250 }
2251 else
2252 {
2253 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2254 }
2255 }
2256
Hal_SC_set_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2257 void Hal_SC_set_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2258 {
2259 UNUSED(u32OPMBase2);
2260 UNUSED(eWindow);
2261 }
2262
Hal_SC_set_FRCM_WBase0(void * pInstance,MS_PHY u32FRCM_WBase0,SCALER_WIN eWindow)2263 void Hal_SC_set_FRCM_WBase0(void *pInstance, MS_PHY u32FRCM_WBase0, SCALER_WIN eWindow)
2264 {
2265 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2266 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2267 if(eWindow == MAIN_WINDOW)
2268 {
2269 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2270 }
2271 else
2272 {
2273 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2274 }
2275 }
2276
Hal_SC_set_FRCM_WBase1(void * pInstance,MS_PHY u32FRCM_WBase1,SCALER_WIN eWindow)2277 void Hal_SC_set_FRCM_WBase1(void *pInstance, MS_PHY u32FRCM_WBase1, SCALER_WIN eWindow)
2278 {
2279 UNUSED(u32FRCM_WBase1);
2280 UNUSED(eWindow);
2281 }
2282
Hal_SC_set_FRCM_WBase2(void * pInstance,MS_PHY u32FRCM_WBase2,SCALER_WIN eWindow)2283 void Hal_SC_set_FRCM_WBase2(void *pInstance, MS_PHY u32FRCM_WBase2, SCALER_WIN eWindow)
2284 {
2285 UNUSED(u32FRCM_WBase2);
2286 UNUSED(eWindow);
2287 }
2288
Hal_SC_set_FRCM_RBase0(void * pInstance,MS_PHY u32FRCM_RBase0,SCALER_WIN eWindow)2289 void Hal_SC_set_FRCM_RBase0(void *pInstance, MS_PHY u32FRCM_RBase0, SCALER_WIN eWindow)
2290 {
2291 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2292 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2293 if(eWindow == MAIN_WINDOW)
2294 {
2295 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_10_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2296 }
2297 else
2298 {
2299 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_50_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2300 }
2301 }
2302
Hal_SC_set_FRCM_RBase1(void * pInstance,MS_PHY u32FRCM_RBase1,SCALER_WIN eWindow)2303 void Hal_SC_set_FRCM_RBase1(void *pInstance, MS_PHY u32FRCM_RBase1, SCALER_WIN eWindow)
2304 {
2305 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2306 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2307 if(eWindow == MAIN_WINDOW)
2308 {
2309 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_12_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2310 }
2311 else
2312 {
2313 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_52_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2314 }
2315 }
2316
Hal_SC_set_FRCM_RBase2(void * pInstance,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2317 void Hal_SC_set_FRCM_RBase2(void *pInstance, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2318 {
2319 UNUSED(u32FRCM_RBase2);
2320 UNUSED(eWindow);
2321 }
2322
Hal_SC_set_Dual_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2323 void Hal_SC_set_Dual_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2324 {
2325 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2326 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2327 // Dual just support scaler0, main only
2328 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2329 {
2330 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2331 return;
2332 }
2333 if(eWindow == MAIN_WINDOW)
2334 {
2335 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2336 }
2337 else
2338 {
2339 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2340 }
2341 }
2342
Hal_SC_set_Dual_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2343 void Hal_SC_set_Dual_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2344 {
2345 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2346 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2347 // Dual just support scaler0, main only
2348 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2349 {
2350 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2351 return;
2352 }
2353 if(eWindow == MAIN_WINDOW)
2354 {
2355 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_1A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2356 }
2357 else
2358 {
2359 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_5A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2360 }
2361
2362 }
2363
Hal_SC_set_Dual_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2364 void Hal_SC_set_Dual_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2365 {
2366 UNUSED(u32DNRBase2);
2367 UNUSED(eWindow);
2368 }
2369
Hal_SC_set_Dual_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2370 void Hal_SC_set_Dual_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2371 {
2372 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2373 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2374 // Dual just support scaler0, main only
2375 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2376 {
2377 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2378 return;
2379 }
2380 if(eWindow == MAIN_WINDOW)
2381 {
2382 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2383 }
2384 else
2385 {
2386 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2387 }
2388 }
2389
Hal_SC_set_Dual_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2390 void Hal_SC_set_Dual_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2391 {
2392 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2393 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2394 // Dual just support scaler0, main only
2395 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2396 {
2397 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2398 return;
2399 }
2400 if(eWindow == MAIN_WINDOW)
2401 {
2402 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2403 }
2404 else
2405 {
2406 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2407 }
2408 }
2409
Hal_SC_set_Dual_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2410 void Hal_SC_set_Dual_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2411 {
2412 UNUSED(u32OPMBase2);
2413 UNUSED(eWindow);
2414 }
2415
Hal_SC_set_WriteVLength(void * pInstance,SCALER_WIN eWindow)2416 void Hal_SC_set_WriteVLength(void *pInstance, SCALER_WIN eWindow)
2417 {
2418 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2419 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2420 if(eWindow == MAIN_WINDOW)
2421 {
2422 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, 0x0); // Write V length
2423 }
2424 else
2425 {
2426 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, 0x0); // Write V length
2427 }
2428 }
2429
Hal_SC_set_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2430 void Hal_SC_set_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2431 {
2432 Hal_SC_set_DNRBase0(pInstance, u32DNRBase0, eWindow);
2433 Hal_SC_set_DNRBase1(pInstance, u32DNRBase1, eWindow);
2434 Hal_SC_set_DNRBase2(pInstance, u32DNRBase2, eWindow);
2435 Hal_SC_set_OPMBase0(pInstance, u32OPMBase0, eWindow);
2436 Hal_SC_set_OPMBase1(pInstance, u32OPMBase1, eWindow);
2437 Hal_SC_set_OPMBase2(pInstance, u32OPMBase2, eWindow);
2438 }
2439
Hal_SC_set_frcm_memoryaddress(void * pInstance,MS_PHY u32FRCM_WBase0,MS_PHY u32FRCM_WBase1,MS_PHY u32FRCM_WBase2,MS_PHY u32FRCM_RBase0,MS_PHY u32FRCM_RBase1,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2440 void Hal_SC_set_frcm_memoryaddress(void *pInstance, MS_PHY u32FRCM_WBase0, MS_PHY u32FRCM_WBase1, MS_PHY u32FRCM_WBase2, MS_PHY u32FRCM_RBase0, MS_PHY u32FRCM_RBase1, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2441 {
2442 Hal_SC_set_FRCM_WBase0(pInstance, u32FRCM_WBase0, eWindow);
2443 Hal_SC_set_FRCM_WBase1(pInstance, u32FRCM_WBase1, eWindow);
2444 Hal_SC_set_FRCM_WBase2(pInstance, u32FRCM_WBase2, eWindow);
2445 Hal_SC_set_FRCM_RBase0(pInstance, u32FRCM_RBase0, eWindow);
2446 Hal_SC_set_FRCM_RBase1(pInstance, u32FRCM_RBase1, eWindow);
2447 Hal_SC_set_FRCM_RBase2(pInstance, u32FRCM_RBase2, eWindow);
2448 }
2449
Hal_SC_set_dual_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2450 void Hal_SC_set_dual_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2451 {
2452 Hal_SC_set_Dual_DNRBase0(pInstance, u32DNRBase0, eWindow);
2453 Hal_SC_set_Dual_DNRBase1(pInstance, u32DNRBase1, eWindow);
2454 Hal_SC_set_Dual_DNRBase2(pInstance, u32DNRBase2, eWindow);
2455 Hal_SC_set_Dual_OPMBase0(pInstance, u32OPMBase0, eWindow);
2456 Hal_SC_set_Dual_OPMBase1(pInstance, u32OPMBase1, eWindow);
2457 Hal_SC_set_Dual_OPMBase2(pInstance, u32OPMBase2, eWindow);
2458 }
2459
Hal_SC_get_miu0mask(void)2460 static SC_MIUMASK_t Hal_SC_get_miu0mask(void)
2461 {
2462 SC_MIUMASK_t mask;
2463
2464 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU0_G0_REQUEST_MASK);
2465 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU0_G1_REQUEST_MASK);
2466 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU0_G2_REQUEST_MASK);
2467 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU0_G3_REQUEST_MASK);
2468 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU0_G4_REQUEST_MASK);
2469 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU0_G5_REQUEST_MASK);
2470 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU0_G6_REQUEST_MASK);
2471
2472 return mask;
2473 }
2474
Hal_SC_get_miu1mask(void)2475 static SC_MIUMASK_t Hal_SC_get_miu1mask(void)
2476 {
2477 SC_MIUMASK_t mask;
2478
2479 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU1_G0_REQUEST_MASK);
2480 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU1_G1_REQUEST_MASK);
2481 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU1_G2_REQUEST_MASK);
2482 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU1_G3_REQUEST_MASK);
2483 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU1_G4_REQUEST_MASK);
2484 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU1_G5_REQUEST_MASK);
2485 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU1_G6_REQUEST_MASK);
2486
2487 return mask;
2488 }
2489
Hal_SC_get_miu2mask(void)2490 static SC_MIUMASK_t Hal_SC_get_miu2mask(void)
2491 {
2492 SC_MIUMASK_t mask;
2493
2494 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU2_G0_REQUEST_MASK);
2495 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU2_G1_REQUEST_MASK);
2496 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU2_G2_REQUEST_MASK);
2497 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU2_G3_REQUEST_MASK);
2498 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU2_G4_REQUEST_MASK);
2499 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU2_G5_REQUEST_MASK);
2500 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU2_G6_REQUEST_MASK);
2501
2502 return mask;
2503 }
2504
Hal_SC_set_miu0mask(SC_MIUMASK_t mask)2505 static void Hal_SC_set_miu0mask(SC_MIUMASK_t mask)
2506 {
2507 MDrv_Write2Byte(MIU0_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2508 MDrv_Write2Byte(MIU0_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2509 MDrv_Write2Byte(MIU0_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2510 MDrv_Write2Byte(MIU0_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2511 MDrv_Write2Byte(MIU0_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2512 MDrv_Write2Byte(MIU0_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2513 MDrv_Write2Byte(MIU0_G6_REQUEST_MASK, mask.u16MiuG6Mask);
2514
2515 }
2516
Hal_SC_set_miu1mask(SC_MIUMASK_t mask)2517 static void Hal_SC_set_miu1mask(SC_MIUMASK_t mask)
2518 {
2519 MDrv_Write2Byte(MIU1_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2520 MDrv_Write2Byte(MIU1_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2521 MDrv_Write2Byte(MIU1_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2522 MDrv_Write2Byte(MIU1_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2523 MDrv_Write2Byte(MIU1_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2524 MDrv_Write2Byte(MIU1_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2525 MDrv_Write2Byte(MIU1_G5_REQUEST_MASK, mask.u16MiuG6Mask);
2526 }
2527
Hal_SC_set_miu2mask(SC_MIUMASK_t mask)2528 static void Hal_SC_set_miu2mask(SC_MIUMASK_t mask)
2529 {
2530 MDrv_Write2Byte(MIU2_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2531 MDrv_Write2Byte(MIU2_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2532 MDrv_Write2Byte(MIU2_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2533 MDrv_Write2Byte(MIU2_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2534 MDrv_Write2Byte(MIU2_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2535 MDrv_Write2Byte(MIU2_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2536 MDrv_Write2Byte(MIU2_G6_REQUEST_MASK, mask.u16MiuG6Mask);
2537 }
2538
Hal_SC_Enable_MiuMask(void * pInstance)2539 void Hal_SC_Enable_MiuMask(void *pInstance)
2540 {
2541 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2542 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2543 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2544 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2545 pXCResourcePrivate->sthal_SC.Miu0MaskOld = Hal_SC_get_miu0mask();
2546 pXCResourcePrivate->sthal_SC.Miu1MaskOld = Hal_SC_get_miu1mask();
2547 pXCResourcePrivate->sthal_SC.Miu2MaskOld = Hal_SC_get_miu2mask();
2548
2549 pXCResourcePrivate->sthal_SC.Miu0Mask = pXCResourcePrivate->sthal_SC.Miu0MaskOld;
2550 pXCResourcePrivate->sthal_SC.Miu1Mask = pXCResourcePrivate->sthal_SC.Miu1MaskOld;
2551 pXCResourcePrivate->sthal_SC.Miu2Mask = pXCResourcePrivate->sthal_SC.Miu2MaskOld;
2552
2553 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2554 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2555 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2556 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2557 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2558 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2559 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2560
2561
2562 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2563 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2564 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2565 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2566 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2567 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2568 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2569
2570 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2571 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2572 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2573 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2574 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2575 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2576 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2577
2578 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0Mask);
2579 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1Mask);
2580 Hal_SC_set_miu2mask(pXCResourcePrivate->sthal_SC.Miu2Mask);
2581 }
2582
Hal_SC_Disable_MiuMask(void * pInstance)2583 void Hal_SC_Disable_MiuMask(void *pInstance)
2584 {
2585 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2586 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2587 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2588 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2589 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0MaskOld);
2590 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1MaskOld);
2591 Hal_SC_set_miu2mask(pXCResourcePrivate->sthal_SC.Miu2MaskOld);
2592 }
2593
Hal_SC_set_miusel(void * pInstance,MS_U8 u8MIUSel)2594 void Hal_SC_set_miusel(void *pInstance, MS_U8 u8MIUSel)
2595 {
2596 // Scaler control MIU by itself
2597 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2598 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2599 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2600 #if 0 // remove and decided by miu_setting.txt
2601 // MIU 1, GROUP0~5: 0x78~0x7D
2602 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
2603 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
2604 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
2605 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
2606 #endif
2607
2608 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
2609 if (psXCInstPri->u32DeviceID == 0)
2610 {
2611 //IPM_R2 miu select need follow IPM miu select.
2612 //Mload use MIU0 but DS use MIU1. IP select replace MIU select BIT(9) enable
2613 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, BIT(0) | BIT(1) | BIT(9) | BIT(10) | BIT(14) | BIT(15), BIT(0) | BIT(1) | BIT(9) | BIT(10) | BIT(14) | BIT(15));
2614 }
2615 else
2616 {
2617 SC_W2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(12) | BIT(14), BIT(12) | BIT(14));
2618 }
2619 if (u8MIUSel==0)
2620 {
2621 ///SCM
2622 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2623 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2624 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2625 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2626 }
2627 else if(u8MIUSel==1)
2628 {
2629 ///SCM
2630 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2631 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2632 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2633 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2634 }
2635 else if(u8MIUSel==2)
2636 {
2637 ///SCM
2638 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2639 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2640 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2641 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2642 }
2643 #else
2644 // When MIU select controlled by miu, miu IPM0 use: BK7F_18[0] BK7F_10[0] Selecet miu chip select
2645 // When MIU select controlled by miu, miu OPM0 use: BK7F_18[1] BK7F_10[1] Selecet miu chip select
2646 // 00'b: MIU0, 01'b: MIU1, 10'b: MIU2
2647 if (psXCInstPri->u32DeviceID == 0)
2648 {
2649 // miu request0 IPM/OPM LSB
2650 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u8MIUSel & BIT(0)) << 15)|((u8MIUSel & BIT(0)) << 1)|(u8MIUSel & BIT(0)), BIT(15)|BIT(1)| BIT(0));
2651 // miu request0 IPM/OPM MSB
2652 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, ((u8MIUSel & BIT(1)) << 14)|(u8MIUSel & BIT(1))|((u8MIUSel & BIT(1)) >> 1), BIT(15)|BIT(1)| BIT(0));
2653 }
2654 else if (psXCInstPri->u32DeviceID == 1)
2655 {
2656 // miu request0 IPM/OPM LSB
2657 SC_W2BYTEMSK(0, REG_SC_BK7F_10_L, ((u8MIUSel & BIT(0)) << 14)|((u8MIUSel & BIT(0)) << 12), BIT(14)| BIT(12));
2658 // miu request0 IPM/OPM MSB
2659 u8MIUSel = (u8MIUSel & BIT(1)) >> 1;
2660 SC_W2BYTEMSK(0, REG_SC_BK7F_18_L, (u8MIUSel << 14) | (u8MIUSel << 12), BIT(14)| BIT(12));
2661 }
2662 #endif
2663 }
2664
Hal_SC_get_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)2665 void Hal_SC_get_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
2666 {
2667 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
2668 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2669 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2670
2671 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, BIT(4)))
2672 {
2673 stMIUSel-> u8MainFBSel = 1;
2674 }
2675 else
2676 {
2677 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, BIT(4)))
2678 {
2679 stMIUSel-> u8MainFBSel = 2;
2680 }
2681 else
2682 {
2683 stMIUSel-> u8MainFBSel = 0;
2684 }
2685 }
2686
2687 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_05_L, BIT(4)))
2688 {
2689 stMIUSel-> u8SubFBSel = 1;
2690 }
2691 else
2692 {
2693 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK31_05_L, BIT(4)))
2694 {
2695 stMIUSel-> u8SubFBSel = 2;
2696 }
2697 else
2698 {
2699 stMIUSel-> u8SubFBSel = 0;
2700 }
2701 }
2702 #else
2703 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2704 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2705 MS_U16 u16MiuSel = 0;
2706 //return OPM MIU select
2707 if (psXCInstPri->u32DeviceID == 0)
2708 {
2709 u16MiuSel = SC_R2BYTEMSK(0, REG_SC_BK7F_10_L, BIT(1)) >> 1;
2710 u16MiuSel |= SC_R2BYTEMSK(0, REG_SC_BK7F_18_L, BIT(1));
2711
2712 stMIUSel-> u8MainFBSel = (MS_U8)(u16MiuSel & 0xff);
2713 }
2714 else if (psXCInstPri->u32DeviceID == 1)
2715 {
2716 u16MiuSel = SC_R2BYTEMSK(0, REG_SC_BK7F_10_L, BIT(12)) >> 1;
2717 u16MiuSel |= SC_R2BYTEMSK(0, REG_SC_BK7F_18_L, BIT(12));
2718
2719 stMIUSel-> u8MainFBSel = (MS_U8)(u16MiuSel & 0xff);
2720 }
2721 #endif
2722 }
2723
Hal_SC_set_dual_miusel(void * pInstance,MS_U8 u8MIUSel)2724 void Hal_SC_set_dual_miusel(void *pInstance, MS_U8 u8MIUSel)
2725 {
2726 // Scaler control MIU by itself
2727 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2728 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2729 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2730 // Dual just support scaler0, main only
2731 if (psXCInstPri->u32DeviceID > 0)
2732 {
2733 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2734 return;
2735 }
2736 #if 0 // remove and decided by miu_setting.txt
2737 // MIU 1, GROUP0~5: 0x78~0x7D
2738 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
2739 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
2740 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
2741 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
2742 #endif
2743
2744 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU select ctorled by xc internal
2745 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, BIT(0) | BIT(1), BIT(0) | BIT(1));
2746 if (u8MIUSel==0)
2747 {
2748 ///SCM
2749 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2750 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2752 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2753 }
2754 else if(u8MIUSel==1)
2755 {
2756 ///SCM
2757 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2758 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2759 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2760 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2761 }
2762 else if(u8MIUSel==2)
2763 {
2764 ///SCM
2765 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2766 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2767 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2768 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2769 }
2770
2771 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0x0, BIT(0) | BIT(1));
2772 #else
2773 // When MIU select controlled by miu, IPM1 use: BK7F_19[0..1] Selecet miu chip select
2774 // When MIU select controlled by miu, OPM1 use: BK7F_19[2..3] Selecet miu chip select
2775 // 00'b: MIU0, 01'b: MIU1, 10'b: MIU2
2776
2777 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u8MIUSel << 2) | u8MIUSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
2778 #endif
2779 }
2780
Hal_SC_set_dual_disable(void * pInstance)2781 void Hal_SC_set_dual_disable(void *pInstance)
2782 {
2783 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2784 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2785 // Dual just support scaler0, main only
2786 if (psXCInstPri->u32DeviceID > 0)
2787 {
2788 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2789 return;
2790 }
2791
2792 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0, BIT(15)); // reg_miu_select_f1 to MIU1
2793 }
2794
Hal_SC_get_dual_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)2795 void Hal_SC_get_dual_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
2796 {
2797 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2798 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2799 // Dual just support scaler0, main only
2800 if (psXCInstPri->u32DeviceID > 0)
2801 {
2802 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2803 return;
2804 }
2805 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
2806 if(SC_R2BYTEMSK(0, REG_SC_BK52_05_L, BIT(4)))
2807 {
2808 stMIUSel->u8MainFBSel = 1;
2809 }
2810 else
2811 {
2812 if(SC_R2BYTEMSK(0, REG_SC_BK51_05_L, BIT(4)))
2813 {
2814 stMIUSel->u8MainFBSel = 2;
2815 }
2816 else
2817 {
2818 stMIUSel->u8MainFBSel = 0;
2819 }
2820 }
2821
2822 if(SC_R2BYTEMSK(0, REG_SC_BK52_44_L, BIT(4)))
2823 {
2824 stMIUSel->u8SubFBSel = 1;
2825 }
2826 else
2827 {
2828 if(SC_R2BYTEMSK(0, REG_SC_BK51_44_L, BIT(4)))
2829 {
2830 stMIUSel->u8SubFBSel = 2;
2831 }
2832 else
2833 {
2834 stMIUSel->u8SubFBSel = 0;
2835 }
2836 }
2837 #else // MIU Select control by miu
2838 MS_U16 u16Tmp = SC_R2BYTEMSK(0, REG_SC_BK7F_19_L, BIT(0)|BIT(1));
2839 stMIUSel->u8MainFBSel = (MS_U8)(u16Tmp & 0xff);
2840 #endif
2841 }
2842
Hal_SC_set_blsk(void * pInstance,MS_BOOL bEn)2843 void Hal_SC_set_blsk(void *pInstance, MS_BOOL bEn)
2844 {
2845 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2846 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2847 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
2848 }
2849
Hal_SC_set_blsk_burst(void * pInstance,MS_BOOL bEn)2850 void Hal_SC_set_blsk_burst(void *pInstance, MS_BOOL bEn)
2851 {
2852 _MLOAD_ENTRY(pInstance);
2853 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
2854 Mhal_XC_MLoad_Fire(pInstance, TRUE);
2855 _MLOAD_RETURN(pInstance);
2856 }
2857
Hal_SC_set_main_black_screen_burst(void * pInstance,MS_BOOL bEn)2858 void Hal_SC_set_main_black_screen_burst(void *pInstance, MS_BOOL bEn)
2859 {
2860 _MLOAD_ENTRY(pInstance);
2861
2862 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
2863 Mhal_XC_MLoad_Fire(pInstance, TRUE);
2864
2865 _MLOAD_RETURN(pInstance);
2866 }
2867
Hal_SC_set_main_sub_black_screen_burst(void * pInstance,MS_BOOL bEn)2868 void Hal_SC_set_main_sub_black_screen_burst(void *pInstance, MS_BOOL bEn)
2869 {
2870 _MLOAD_ENTRY(pInstance);
2871
2872 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
2873 Mhal_XC_MLoad_Fire(pInstance, TRUE);
2874
2875 _MLOAD_RETURN(pInstance);
2876 }
2877
Hal_SC_set_main_black_screen(void * pInstance,MS_BOOL bEn)2878 void Hal_SC_set_main_black_screen(void *pInstance, MS_BOOL bEn)
2879 {
2880 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2881 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2882 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
2883 }
2884
Hal_SC_set_main_sub_black_screen(void * pInstance,MS_BOOL bEn)2885 void Hal_SC_set_main_sub_black_screen(void *pInstance, MS_BOOL bEn)
2886 {
2887 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2888 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2889 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
2890 }
2891
Hal_SC_set_sub_blue_screen_burst(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)2892 void Hal_SC_set_sub_blue_screen_burst(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
2893 {
2894 _MLOAD_ENTRY(pInstance);
2895
2896 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
2897 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
2898 Mhal_XC_MLoad_Fire(pInstance, TRUE);
2899
2900 _MLOAD_RETURN(pInstance);
2901 }
2902
Hal_SC_set_sub_blue_screen(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)2903 void Hal_SC_set_sub_blue_screen(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
2904 {
2905 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2906 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2907 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
2908 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
2909 }
2910
2911 #ifdef UFO_XC_FORCEWRITE_V2
Hal_SC_CheckMuteStatusByRegister(void * pInstance,SCALER_WIN eWindow)2912 MS_BOOL Hal_SC_CheckMuteStatusByRegister(void *pInstance, SCALER_WIN eWindow)
2913 {
2914 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2915 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2916 MS_BOOL bRet = FALSE;
2917
2918 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB)
2919 if(((MAIN_WINDOW == eWindow) && (psXCInstPri->u32DeviceID == 1))
2920 || (SUB_WINDOW == eWindow)
2921 )
2922 {
2923 bRet = (SC_R2BYTEMSK(0, REG_SC_BK10_19_L, BIT(5)) ? TRUE: FALSE);
2924 }
2925 #else
2926 if(SUB_WINDOW == eWindow)
2927 {
2928 bRet = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, BIT(5)) ? TRUE: FALSE);
2929 }
2930 #endif
2931 else if(MAIN_WINDOW == eWindow)
2932 {
2933 bRet = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, BIT(1)) ? TRUE: FALSE);
2934 }
2935 return bRet;
2936 }
2937
2938 #endif
2939
Hal_SC_IP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2940 E_APIXC_ReturnValue Hal_SC_IP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2941 {
2942 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2943 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2944 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2945 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2946 if(MAIN_WINDOW == eWindow)
2947 {
2948 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, bEnable? 0 : BIT(0) , BIT(0));
2949 }
2950 else
2951 {
2952 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, bEnable? 0 : BIT(0) , BIT(0));
2953 }
2954
2955 return E_APIXC_RET_OK;
2956 }
2957
Hal_SC_IP_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2958 E_APIXC_ReturnValue Hal_SC_IP_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2959 {
2960 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2961 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2962 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2963 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2964 if(MAIN_WINDOW == eWindow)
2965 {
2966 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, bEnable? 0 : BIT(14) , BIT(14));
2967 }
2968 else
2969 {
2970 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_42_L, bEnable? 0 : BIT(14) , BIT(14));
2971 }
2972 return E_APIXC_RET_OK;
2973 }
2974
Hal_SC_OP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2975 E_APIXC_ReturnValue Hal_SC_OP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2976 {
2977 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2978 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2979 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will stop OPW and OP memory write request
2980 return E_APIXC_RET_OK;
2981 }
2982
Hal_SC_frcmw_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2983 E_APIXC_ReturnValue Hal_SC_frcmw_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2984 {
2985 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2986 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2987 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2988 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2989 if(MAIN_WINDOW == eWindow)
2990 {
2991 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, bEnable? 0 : BIT(0) , BIT(0));
2992 }
2993 else
2994 {
2995 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, bEnable? 0 : BIT(0) , BIT(0));
2996 }
2997 return E_APIXC_RET_OK;
2998 }
2999
Hal_SC_frcmr_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3000 E_APIXC_ReturnValue Hal_SC_frcmr_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3001 {
3002 return E_APIXC_RET_OK;
3003 }
3004
Hal_SC_disable_inputsource_burst(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)3005 void Hal_SC_disable_inputsource_burst(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
3006 {
3007 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3008 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3009 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3010 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3011
3012 _MLOAD_ENTRY(pInstance);
3013
3014 // HW PIP architeucture
3015 // Becasue BK3_02[8] and BK20_11[15] can not be enabled toghter,
3016 // otherwise garbage will be showed,we need to use BK12_47[0] to instead.
3017 if( eWindow == MAIN_WINDOW )
3018 {
3019 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
3020 }
3021 else
3022 {
3023 //Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
3024 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_47_L, (bDisable ? BIT(0) : 0), BIT(0));
3025 #if (HW_DESIGN_4K2K_VER == 4)
3026 if ((psXCInstPri->u32DeviceID==0)
3027 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3028 {
3029 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_47_L, (bDisable ? BIT(0) : 0), BIT(0));
3030 }
3031 #endif
3032 }
3033 Mhal_XC_MLoad_Fire(pInstance, TRUE);
3034 _MLOAD_RETURN(pInstance);
3035 }
3036
Hal_SC_disable_inputsource(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)3037 void Hal_SC_disable_inputsource(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
3038 {
3039 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3040 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3041 if( eWindow == MAIN_WINDOW )
3042 {
3043 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
3044 }
3045 else
3046 {
3047 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
3048 }
3049 }
3050
3051
Hal_SC_Is_InputSource_Disable(void * pInstance,SCALER_WIN eWindow)3052 MS_U16 Hal_SC_Is_InputSource_Disable(void *pInstance, SCALER_WIN eWindow)
3053 {
3054 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3055 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3056 if(eWindow == MAIN_WINDOW)
3057 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L)&0x80);
3058 else
3059 {
3060 if((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L)&0x01) == 0)
3061 {
3062 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L)&0x80);
3063 }
3064 else
3065 {
3066 return TRUE;
3067 }
3068 }
3069 }
3070
3071
Hal_SC_set_nosignal_color(void * pInstance,MS_U8 u8Color,SCALER_WIN eWindow)3072 void Hal_SC_set_nosignal_color(void *pInstance, MS_U8 u8Color,SCALER_WIN eWindow)
3073 {
3074 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3075 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3076 if (Mhal_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
3077 {
3078 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3079 _MLOAD_ENTRY(pInstance);
3080 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3081 if(psXCInstPri->u32DeviceID == 0)
3082 #else
3083 if ( eWindow == MAIN_WINDOW )
3084 #endif
3085 {
3086 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_24_L, u8Color, LBMASK);
3087 }
3088 else
3089 {
3090 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3091 _MLOAD_RETURN(pInstance);
3092 _MLOAD_ENTRY(g_pDevice0Instance);
3093 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3094 _MLOAD_RETURN(g_pDevice0Instance);
3095 _MLOAD_ENTRY(pInstance);
3096 #else
3097 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3098 #endif
3099 }
3100 Mhal_XC_MLoad_Fire(pInstance, TRUE);
3101 _MLOAD_RETURN(pInstance);
3102 }
3103 else
3104 {
3105 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3106 if(psXCInstPri->u32DeviceID == 0)
3107 #else
3108 if ( eWindow == MAIN_WINDOW )
3109 #endif
3110 {
3111 #ifdef new_chakra
3112 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
3113 #else
3114 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
3115 #endif
3116 }
3117 else
3118 {
3119 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3120 SC_W2BYTEMSK(0, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3121 #else
3122 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3123 #endif
3124 }
3125 }
3126 }
3127
Hal_SC_set_fbl(void * pInstance,MS_BOOL bEn)3128 void Hal_SC_set_fbl(void *pInstance, MS_BOOL bEn)
3129 {
3130 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3131 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3132 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn ? BIT(7): 0), BIT(7)); //Enable/Disable FBL
3133 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, (bEn ? BIT(14):0), BIT(14)); //F2 force IP read request disable
3134
3135 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (bEn ? 0x3:0), 0x3); //F2 IP read/write request disable
3136 }
3137
Hal_SC_get_fbl(void * pInstance)3138 MS_BOOL Hal_SC_get_fbl(void *pInstance)
3139 {
3140 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3141 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3142 return SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(7)); //Enable/Disable FBL
3143 }
3144
Hal_SC_set_freezeimg_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3145 void Hal_SC_set_freezeimg_burst(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3146 {
3147 _MLOAD_ENTRY(pInstance);
3148 #if (HW_DESIGN_4K2K_VER == 4)
3149 if( eWindow == MAIN_WINDOW )
3150 {
3151 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3152 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3153 }
3154 else
3155 {
3156 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3157 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3158 }
3159 #else
3160 if( eWindow == MAIN_WINDOW )
3161 {
3162 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3163 }
3164 else
3165 {
3166 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3167 }
3168 #endif
3169 Mhal_XC_MLoad_Fire(pInstance, TRUE);
3170 _MLOAD_RETURN(pInstance);
3171 }
3172
3173
Hal_SC_set_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3174 void Hal_SC_set_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3175 {
3176 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3177 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3178 #if (HW_DESIGN_4K2K_VER == 4)
3179 if( eWindow == MAIN_WINDOW )
3180 {
3181 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3182 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3183 }
3184 else
3185 {
3186 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3187 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3188 }
3189 #else
3190 if( eWindow == MAIN_WINDOW )
3191 {
3192 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3193 }
3194 else
3195 {
3196 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3197 }
3198 #endif
3199 }
3200
Hal_SC_set_frcm_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3201 void Hal_SC_set_frcm_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3202 {
3203 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3204 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3205 if( eWindow == MAIN_WINDOW )
3206 {
3207 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3208 }
3209 else
3210 {
3211 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3212 }
3213 }
3214
Hal_SC_get_freezeimg(void * pInstance,SCALER_WIN eWindow)3215 MS_BOOL Hal_SC_get_freezeimg(void *pInstance, SCALER_WIN eWindow)
3216 {
3217 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3218 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3219 #if (HW_DESIGN_4K2K_VER == 4)
3220 if( eWindow == MAIN_WINDOW )
3221 {
3222 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, BIT(11)) ? TRUE: FALSE);
3223 }
3224 else
3225 {
3226 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, BIT(11)) ? TRUE: FALSE);
3227 }
3228 #else
3229 if( eWindow == MAIN_WINDOW )
3230 {
3231 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(11)) ? TRUE: FALSE);
3232 }
3233 else
3234 {
3235 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, BIT(11)) ? TRUE: FALSE);
3236 }
3237 #endif
3238 }
3239
Hal_SC_exwith_miuprotect_swreset(void * pInstance,MS_U8 x)3240 void Hal_SC_exwith_miuprotect_swreset(void *pInstance, MS_U8 x)
3241 {
3242 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3243 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3244 //reset IP1F2
3245 //select pattern generator source
3246 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, x, x);
3247 //MsOS_DelayTask(2);
3248
3249 //select pattern generator source
3250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, 0, x);
3251 //MsOS_DelayTask(2);
3252 }
3253
Hal_SC_ip_Init_for_internal_timing(void * pInstance,XC_Internal_TimingType timingtype,SCALER_WIN eWindow)3254 void Hal_SC_ip_Init_for_internal_timing(void *pInstance, XC_Internal_TimingType timingtype, SCALER_WIN eWindow)
3255 {
3256 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3257 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3258 if(eWindow == SUB_WINDOW)
3259 {
3260 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3261
3262 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, 0x104) ; //Video source
3263 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F1); //when source is changed, we must reset it to make it work
3264 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, 0x890);
3265
3266 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, 0x01, 0x03); //force progressive mode
3267 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3268
3269 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, 0x020); //capture V start
3270 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, 0x50) ; //capture H start
3271
3272 switch (timingtype)
3273 {
3274 case E_XC_480P:
3275 default:
3276
3277 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x1c0) ; // V size
3278 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x280) ; // h size
3279
3280 break;
3281 case E_XC_720P:
3282 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3283 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3284
3285 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3286 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x0460); //DNR Fetch
3287 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3288 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x0460); //OPM Fetch
3289
3290 break;
3291 case E_XC_1080P:
3292 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3293 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3294
3295 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3296 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x06E0); //DNR Fetch
3297 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3298 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x06E0); //OPM Fetch
3299 break;
3300 }
3301 }
3302 else
3303 {
3304 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3305
3306 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, 0x104) ; //Video source
3307 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F2); //when source is changed, we must reset it to make it work
3308 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0x890);
3309
3310 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, 0x01, 0x03); //force progressive mode
3311 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3312
3313 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, 0x020); //capture V start
3314 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, 0x50) ; //capture H start
3315
3316 switch (timingtype)
3317 {
3318 case E_XC_480P:
3319 default:
3320
3321 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x1c0) ; // V size
3322 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x280) ; // h size
3323
3324 break;
3325 case E_XC_720P:
3326 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3327 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3328
3329 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3330 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x0460); //DNR Fetch
3331 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3332 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x0460); //OPM Fetch
3333
3334 break;
3335 case E_XC_1080P:
3336 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3337 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3338
3339 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3340 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x06E0); //DNR Fetch
3341 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3342 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x06E0); //OPM Fetch
3343 break;
3344 }
3345
3346 }
3347 }
3348
Hal_SC_rgb_average_info(void * pInstance,MS_U16 u16mask,SCALER_WIN eWindow)3349 MS_U16 Hal_SC_rgb_average_info(void *pInstance, MS_U16 u16mask, SCALER_WIN eWindow)
3350 {
3351 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3352 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3353 MS_U16 u16value;
3354
3355 if(eWindow == MAIN_WINDOW)
3356 {
3357 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16mask, 0x0F);
3358 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_11_L);
3359 }
3360 else
3361 {
3362 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0F_L, u16mask, 0x0F);
3363 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_11_L);
3364 }
3365
3366 return u16value;
3367 }
3368
3369
Hal_SC_autogain_enable(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3370 void Hal_SC_autogain_enable(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3371 {
3372 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3373 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3374 //auto gain enable
3375 if(eWindow == MAIN_WINDOW)
3376 {
3377 if(bEnable)
3378 W2BYTEMSK(REG_SC_BK01_0E_L, 0x11, 0x11);
3379 else
3380 W2BYTEMSK(REG_SC_BK01_0E_L, 0x00, 0x11);
3381 }
3382 else
3383 {
3384 if(bEnable)
3385 W2BYTEMSK(REG_SC_BK03_0E_L, 0x11, 0x11);
3386 else
3387 W2BYTEMSK(REG_SC_BK03_0E_L, 0x00, 0x11);
3388 }
3389 }
3390
Hal_SC_autogain_status(void * pInstance,SCALER_WIN eWindow)3391 MS_BOOL Hal_SC_autogain_status(void *pInstance, SCALER_WIN eWindow)
3392 {
3393 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3394 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3395 MS_BOOL bvalue;
3396 if(eWindow == MAIN_WINDOW)
3397 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(1));
3398 else
3399 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(1));
3400
3401 return bvalue;
3402
3403 }
3404
Hal_SC_set_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3405 void Hal_SC_set_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3406 {
3407 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3408 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3409 MS_U32 u32NoSigReg, u32MirrorReg;
3410
3411 if(eWindow == MAIN_WINDOW)
3412 {
3413 u32NoSigReg = REG_SC_BK01_02_L;
3414 u32MirrorReg = REG_SC_BK12_03_L;
3415 }
3416 else
3417 {
3418 u32NoSigReg = REG_SC_BK03_02_L;
3419 u32MirrorReg = REG_SC_BK12_43_L;
3420
3421 }
3422
3423 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3424
3425 if( bEnable )
3426 {
3427 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3428 }
3429 else
3430 {
3431 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3432 }
3433 }
3434
Hal_SC_set_frcm_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3435 void Hal_SC_set_frcm_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3436 {
3437 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3438 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3439 MS_U32 u32NoSigReg = 0, u32MirrorReg = 0;
3440
3441 if(eWindow == MAIN_WINDOW)
3442 {
3443 u32NoSigReg = REG_SC_BK01_02_L;
3444 u32MirrorReg = REG_SC_BK32_03_L;
3445 }
3446 else
3447 {
3448 u32NoSigReg = REG_SC_BK03_02_L;
3449 u32MirrorReg = REG_SC_BK32_43_L;
3450 }
3451
3452 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3453
3454 if( bEnable )
3455 {
3456 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3457 }
3458 else
3459 {
3460 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3461 }
3462 }
3463
Hal_SC_GetAVDStatus(void)3464 MS_U16 Hal_SC_GetAVDStatus(void)
3465 {
3466 return MDrv_Read2Byte(L_BK_AFEC(0x66));
3467 }
3468
Hal_SC_set_rep_window(void * pInstance,MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)3469 void Hal_SC_set_rep_window(void *pInstance, MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)
3470 {
3471 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3472 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3473 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, bEnable?BIT(9):0x0, BIT(9));
3474 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L,x);
3475 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L,x + w);
3476 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L,y);
3477 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L,y + h);
3478 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, (~u8Color)<<8, 0xFF00);
3479 }
3480
3481 //--------------------------------------------------
3482 //update display window registers with input window
3483 //IN:
3484 // pdspwin: input window info
3485 //--------------------------------------------------
Hal_SC_set_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3486 void Hal_SC_set_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3487 {
3488 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3489 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3490 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3491 if (Mhal_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
3492 {
3493 _MLOAD_ENTRY(pInstance);
3494
3495 if(eWindow == MAIN_WINDOW)
3496 {
3497 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3498 if (psXCInstPri->u32DeviceID == 1)
3499 {
3500 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
3501 //Display window
3502 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, u16HDEStart+90, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
3503 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (u16HDEStart+pdspwin->x+pdspwin->width-1 - pdspwin->x+90), VOP_DISPLAY_HEND_MASK);
3504 }
3505 else
3506 {
3507 //Display window
3508 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pdspwin->x>>00), VOP_DISPLAY_HSTART_MASK);
3509 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)((pdspwin->x+pdspwin->width-1)>>00), VOP_DISPLAY_HEND_MASK);
3510 }
3511 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pdspwin->y), VOP_DISPLAY_VSTART_MASK);
3512 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pdspwin->y+pdspwin->height-1), VOP_DISPLAY_VEND_MASK);
3513
3514 if (psXCInstPri->u32DeviceID == 1)//follow HW_DESIGN_4K2K_VER = 6 rule
3515 {
3516 //Display window
3517 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_07_L, (MS_U16)(pdspwin->x>>00), VOP_DISPLAY_HSTART_MASK);
3518 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_08_L, (MS_U16)((pdspwin->x+pdspwin->width-1)>>00), VOP_DISPLAY_HEND_MASK);
3519 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pdspwin->y), 0xFFFF);
3520 Mhal_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pdspwin->y+pdspwin->height-1), 0xFFFF);
3521 }
3522 #else
3523 //Display window
3524 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, pdspwin->x,VOP_DISPLAY_HSTART_MASK); // Display H start
3525 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1,VOP_DISPLAY_HEND_MASK); // Display H end
3526 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, pdspwin->y,VOP_DISPLAY_VSTART_MASK); // Display V start
3527 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1,VOP_DISPLAY_VEND_MASK); // Display V end
3528 #endif
3529 }
3530 else
3531 {
3532 //Display window
3533 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, pdspwin->x,0x3FFF); // Display H start
3534 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1,0x3FFF); // Display H end
3535 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, pdspwin->y,0x1FFF); // Display V start
3536 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1,0x1FFF); // Display V end
3537 }
3538
3539 Mhal_XC_MLoad_Fire(pInstance, TRUE);
3540 _MLOAD_RETURN(pInstance);
3541 }
3542 else
3543 {
3544 if(eWindow == MAIN_WINDOW)
3545 {
3546 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3547 //FIX ME:following HW_DESIGN_4K2K_VER = 6 rule
3548 //Display window
3549 if (psXCInstPri->u32DeviceID == 1)
3550 {
3551 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
3552 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, u16HDEStart+90);//temp solution(+90)
3553 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, (u16HDEStart+ pdspwin->width+90-1));
3554 }
3555 else
3556 {
3557 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pdspwin->x);
3558 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1);
3559 }
3560 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pdspwin->y);
3561 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1);
3562 if (psXCInstPri->u32DeviceID == 1)//follow HW_DESIGN_4K2K_VER = 6 rule
3563 {
3564 //Display window
3565 SC_W2BYTE(0, REG_SC_BK0F_07_L, pdspwin->x); // Display H start
3566 SC_W2BYTE(0, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1); // Display H end
3567 SC_W2BYTE(0, REG_SC_BK0F_09_L, pdspwin->y); // Display V start
3568 SC_W2BYTE(0, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1); // Display V end
3569 }
3570 #else
3571 //Display window
3572 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pdspwin->x); // Display H start
3573 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1); // Display H end
3574 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pdspwin->y); // Display V start
3575 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1); // Display V end
3576 #endif
3577 }
3578 else
3579 {
3580 //Display window
3581 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pdspwin->x); // Display H start
3582 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1); // Display H end
3583 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pdspwin->y); // Display V start
3584 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1); // Display V end
3585 }
3586 }
3587 }
3588
3589 //--------------------------------------------------
3590 //get display window registers setting
3591 //OUT:
3592 // pdspwin: Pointer for ouput disp window register
3593 //--------------------------------------------------
Hal_SC_get_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3594 void Hal_SC_get_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3595 {
3596 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3597 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3598 if(eWindow == MAIN_WINDOW)
3599 {
3600 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3601 //Display window
3602 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L); // Display H start
3603 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) - pdspwin->x + 1; // Display H end
3604 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L); // Display V start
3605 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L) - pdspwin->y + 1; // Display V end
3606 }
3607 else
3608 {
3609 //Display window
3610 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L); // Display H start
3611 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) - pdspwin->x + 1; // Display H end
3612 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L); // Display V start
3613 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L) - pdspwin->y + 1; // Display V end
3614 }
3615 }
3616
Hal_SC_set_Fclk(void * pInstance,EN_SET_FCLK_CASE enCase)3617 void Hal_SC_set_Fclk(void *pInstance, EN_SET_FCLK_CASE enCase)
3618 {
3619 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3620 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3621 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3622 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3623
3624 if (enCase == EN_FCLK_FBL)
3625 {
3626 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3627 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK);
3628 else
3629 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK);
3630 }
3631 else
3632 {
3633 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3634 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_DEFAULT, CKG_FCLK_MASK);
3635 else
3636 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK);
3637 }
3638 }
3639
Hal_SC_GetScmiV1Speical4frame(void * pInstance,XC_FRAME_STORE_NUMBER enStoreNum)3640 MS_BOOL Hal_SC_GetScmiV1Speical4frame(void *pInstance, XC_FRAME_STORE_NUMBER enStoreNum)
3641 {
3642 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3643 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3644 return (enStoreNum == IMAGE_STORE_4_FRAMES) && ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_04_L) & BIT(6)) != 0);
3645 }
3646
Hal_XC_TransFrameNumToFactor(void * pInstance,XC_FRAME_STORE_NUMBER eFrameStoreNumber,MS_BOOL bLinearMode,MS_BOOL bFieldPackingMode)3647 MS_U8 Hal_XC_TransFrameNumToFactor(void *pInstance, XC_FRAME_STORE_NUMBER eFrameStoreNumber, MS_BOOL bLinearMode, MS_BOOL bFieldPackingMode)
3648 {
3649 MS_U8 u8Factor = 0;
3650
3651 switch(eFrameStoreNumber)
3652 {
3653 #if ENABLE_16_FIELD_SUPPORTED
3654 case IMAGE_STORE_6_FIELDS:
3655
3656 if(bFieldPackingMode)
3657 {
3658 u8Factor = 6;
3659 }
3660 else
3661 {
3662 u8Factor = 3;
3663 }
3664 break;
3665
3666 case IMAGE_STORE_8_FIELDS:
3667
3668 if(bFieldPackingMode)
3669 {
3670 u8Factor = 8;
3671 }
3672 else
3673 {
3674 u8Factor = 4;
3675 }
3676
3677 break;
3678
3679 case IMAGE_STORE_10_FIELDS:
3680
3681 if(bFieldPackingMode)
3682 {
3683 u8Factor = 10;
3684 }
3685 else
3686 {
3687 u8Factor = 5;
3688 }
3689
3690 break;
3691
3692 case IMAGE_STORE_12_FIELDS:
3693
3694 if(bFieldPackingMode)
3695 {
3696 u8Factor = 12;
3697 }
3698 else
3699 {
3700 u8Factor = 6;
3701 }
3702
3703 break;
3704 case IMAGE_STORE_14_FIELDS:
3705
3706 if(bFieldPackingMode)
3707 {
3708 u8Factor = 14;
3709 }
3710 else
3711 {
3712 u8Factor = 7;
3713 }
3714
3715 break;
3716 case IMAGE_STORE_16_FIELDS:
3717
3718 if(bFieldPackingMode)
3719 {
3720 u8Factor = 16;
3721 }
3722 else
3723 {
3724 u8Factor = 8;
3725 }
3726
3727 break;
3728 #endif
3729
3730 case IMAGE_STORE_3_FRAMES:
3731
3732 if (bLinearMode)
3733 {
3734 u8Factor = 1;
3735 }
3736 else
3737 {
3738 // Put all field together.
3739 if(bFieldPackingMode)
3740 {
3741 u8Factor = 3;
3742 }
3743 else
3744 {
3745 u8Factor = 2;
3746 }
3747 }
3748
3749 break;
3750
3751 case IMAGE_STORE_4_FRAMES:
3752
3753 if (bLinearMode)
3754 {
3755 u8Factor = 1;
3756 }
3757 else
3758 {
3759 // Put all field together.
3760 if(bFieldPackingMode)
3761 {
3762 u8Factor = 4;
3763 }
3764 else
3765 {
3766 if(Hal_SC_GetScmiV1Speical4frame(pInstance, IMAGE_STORE_4_FRAMES))
3767 {
3768 u8Factor = 4;
3769 }
3770 else
3771 {
3772 u8Factor = 2;
3773 }
3774 }
3775 }
3776
3777 break;
3778 case IMAGE_STORE_5_FRAMES:
3779
3780 if (bLinearMode)
3781 {
3782 u8Factor = 1;
3783 }
3784 else
3785 {
3786 // Put all field together.
3787 if(bFieldPackingMode)
3788 {
3789 u8Factor = 5;
3790 }
3791 else
3792 {
3793 u8Factor = 2;
3794 }
3795 }
3796
3797 break;
3798 case IMAGE_STORE_6_FRAMES:
3799
3800 if (bLinearMode)
3801 {
3802 u8Factor = 1;
3803 }
3804 else
3805 {
3806 // Put all field together.
3807 if(bFieldPackingMode)
3808 {
3809 u8Factor = 6;
3810 }
3811 else
3812 {
3813 u8Factor = 2;
3814 }
3815 }
3816
3817 break;
3818 case IMAGE_STORE_7_FRAMES:
3819
3820 if (bLinearMode)
3821 {
3822 u8Factor = 1;
3823 }
3824 else
3825 {
3826 // Put all field together.
3827 if(bFieldPackingMode)
3828 {
3829 u8Factor = 7;
3830 }
3831 else
3832 {
3833 u8Factor = 2;
3834 }
3835 }
3836
3837 break;
3838
3839 case IMAGE_STORE_8_FRAMES:
3840
3841 if (bLinearMode)
3842 {
3843 u8Factor = 1;
3844 }
3845 else
3846 {
3847 if(bFieldPackingMode)
3848 {
3849 u8Factor = 8;
3850 }
3851 else
3852 {
3853 u8Factor = 4;
3854 }
3855 }
3856 break;
3857
3858 case IMAGE_STORE_10_FRAMES:
3859
3860 if (bLinearMode)
3861 {
3862 u8Factor = 1;
3863 }
3864 else
3865 {
3866 // Put all field together.
3867 if(bFieldPackingMode)
3868 {
3869 u8Factor = 10;
3870 }
3871 else
3872 {
3873 u8Factor = 2;
3874 }
3875 }
3876
3877 break;
3878
3879 case IMAGE_STORE_12_FRAMES:
3880
3881 if (bLinearMode)
3882 {
3883 u8Factor = 1;
3884 }
3885 else
3886 {
3887 // Put all field together.
3888 if(bFieldPackingMode)
3889 {
3890 u8Factor = 12;
3891 }
3892 else
3893 {
3894 u8Factor = 2;
3895 }
3896 }
3897
3898 break;
3899
3900 case IMAGE_STORE_4_FIELDS:
3901 if (bLinearMode)
3902 {
3903 u8Factor = 1;
3904 }
3905 else
3906 {
3907 // Put all field together.
3908 if(bFieldPackingMode)
3909 {
3910 u8Factor = 4;
3911 }
3912 else
3913 {
3914 u8Factor = 2;
3915 }
3916 }
3917 break;
3918
3919 case IMAGE_STORE_2_FIELDS:
3920 if (bLinearMode)
3921 {
3922 u8Factor = 1;
3923 }
3924 else
3925 {
3926 // Put all field together.
3927 if(bFieldPackingMode)
3928 {
3929 u8Factor = 2;
3930 }
3931 else
3932 {
3933 u8Factor = 1;
3934 }
3935 }
3936 break;
3937
3938 case IMAGE_STORE_2_FRAMES:
3939 default:
3940 if (bLinearMode)
3941 {
3942 u8Factor = 1;
3943 }
3944 else
3945 {
3946 // 2 frame mode is same for packet or non packet mode
3947 u8Factor = 2;
3948 }
3949 break;
3950 }
3951
3952 return u8Factor;
3953 }
3954
Hal_SC_get_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t * pFrameBufInfo,SCALER_WIN eWindow)3955 void Hal_SC_get_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t *pFrameBufInfo, SCALER_WIN eWindow)
3956 {
3957 MS_U8 u8Reg;
3958
3959 if (!pFrameBufInfo) return;
3960
3961 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3962 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3963 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3964 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3965
3966 pFrameBufInfo->u32IPMBase0 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_09_L:REG_SC_BK12_49_L, 0x00FF)<<16) |
3967 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_08_L:REG_SC_BK12_48_L))) * BYTE_PER_WORD;
3968 pFrameBufInfo->u32IPMBase1 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0B_L:REG_SC_BK12_4B_L, 0x00FF)<<16) |
3969 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0A_L:REG_SC_BK12_4A_L))) * BYTE_PER_WORD;
3970 pFrameBufInfo->u32IPMBase2 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0D_L:REG_SC_BK12_4D_L, 0x00FF)<<16) |
3971 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0C_L:REG_SC_BK12_4C_L))) * BYTE_PER_WORD;
3972 pFrameBufInfo->u16IPMOffset = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0E_L:REG_SC_BK12_4E_L);
3973 pFrameBufInfo->u16IPMFetch = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0F_L:REG_SC_BK12_4F_L);
3974 pFrameBufInfo->u16VLength = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_18_L:REG_SC_BK12_58_L, 0x0FFF);
3975 pFrameBufInfo->bLinearAddrMode = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_03_L:REG_SC_BK12_43_L, BIT(4));
3976 pFrameBufInfo->bYCSeparate = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(10)) )?TRUE:FALSE;
3977 pFrameBufInfo->u32WriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK0D_42_L:REG_SC_BK0D_44_L);
3978 // frcm write base address limit
3979 #if 0
3980 #if (HW_DESIGN_4K2K_VER == 4)
3981 if ((psXCInstPri->u32DeviceID==0)
3982 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3983 {
3984 pFrameBufInfo->u32FRCMWriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L);
3985 }
3986 #endif
3987 #endif
3988 pFrameBufInfo->u8BitPerPixel = 24;//default
3989
3990 u8Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0x00FF);
3991 if (u8Reg & 0x30)
3992 {//444
3993 pFrameBufInfo->bMemFormat422 = FALSE;
3994 if (u8Reg & 0x10)
3995 { // 444 8BIT
3996 pFrameBufInfo->u8BitPerPixel = 24;
3997 }
3998 else
3999 { // 444 10BIT
4000 pFrameBufInfo->u8BitPerPixel = 32;
4001 }
4002 pFrameBufInfo->bInterlace = FALSE;
4003 }
4004 else
4005 {//422
4006 pFrameBufInfo->bMemFormat422 = TRUE;
4007
4008 if((BIT(8)|BIT(9)) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(8)|BIT(9))) //user mode
4009 {
4010 MS_U8 u8MemFmt = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L) & 0x0F;
4011 if((4 == u8MemFmt) || (5 == u8MemFmt) || (6 == u8MemFmt))
4012 {
4013 pFrameBufInfo->u8BitPerPixel = 20;
4014 }
4015 else if((8 == u8MemFmt) || (9 == u8MemFmt) || (10 == u8MemFmt) || (11 == u8MemFmt))
4016 {
4017 pFrameBufInfo->u8BitPerPixel = 24;
4018 }
4019 }
4020 else
4021 {
4022 u8Reg = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0xFF00)) >> 8;
4023
4024 switch(u8Reg & 0x77)
4025 {
4026 case 0x25:
4027 pFrameBufInfo->u8BitPerPixel = 24;
4028 pFrameBufInfo->bInterlace = TRUE;
4029 break;
4030 case 0x24:
4031 pFrameBufInfo->u8BitPerPixel = 20;
4032 pFrameBufInfo->bInterlace = TRUE;
4033 break;
4034 case 0x27:
4035 pFrameBufInfo->u8BitPerPixel = 16;
4036 pFrameBufInfo->bInterlace = TRUE;
4037 break;
4038 case 0x21:
4039 if(BIT(1) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_04_L:REG_SC_BK12_44_L, BIT(0)|BIT(1)))
4040 {
4041 pFrameBufInfo->u8BitPerPixel = 24;
4042 }
4043 else
4044 {
4045 pFrameBufInfo->u8BitPerPixel = 20;
4046 }
4047 pFrameBufInfo->bInterlace = FALSE;
4048 break;
4049 case 0x20:
4050 pFrameBufInfo->u8BitPerPixel = 16;
4051 pFrameBufInfo->bInterlace = FALSE;
4052 break;
4053 case 0x00:
4054 default:
4055 pFrameBufInfo->u8BitPerPixel = 16;
4056 pFrameBufInfo->bInterlace = FALSE;
4057 break;
4058 }
4059 }
4060 }
4061
4062 //In M10/J2/A5/A6/A3, New SCMI
4063 pFrameBufInfo->u8FBNum = (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_19_L:REG_SC_BK12_59_L, 0x1F));
4064
4065 #if 0
4066 printf("base0=0x%x, base1=0x%x, base2=0x%x, offset=%u, 422=%u, i=%u, bpp=%u, fbnum=%u\n",
4067 (unsigned int)pFrameBufInfo->u32IPMBase0,
4068 (unsigned int)pFrameBufInfo->u32IPMBase1,
4069 (unsigned int)pFrameBufInfo->u32IPMBase2,
4070 pFrameBufInfo->u16IPMOffset,
4071 pFrameBufInfo->bMemFormat422,
4072 pFrameBufInfo->bInterlace,
4073 pFrameBufInfo->u8BitPerPixel,
4074 pFrameBufInfo->u8FBNum);
4075 #endif
4076 }
Hal_SC_set_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t pFrameBufInfo)4077 void Hal_SC_set_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t pFrameBufInfo)
4078 {
4079 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4080 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4081 MS_PHY u32IPMBase0, u32IPMBase1, u32IPMBase2;
4082 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4083 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4084
4085 u32IPMBase0=pFrameBufInfo.u32IPMBase0/BYTE_PER_WORD;
4086 u32IPMBase1=pFrameBufInfo.u32IPMBase1/BYTE_PER_WORD;
4087 u32IPMBase2=pFrameBufInfo.u32IPMBase2/BYTE_PER_WORD;
4088
4089 //Step 5.4, Memory Limit V : BK12_18[15] = 1, BK12_18[12:0] to the real V line number
4090 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x8000),0x8FFF);
4091
4092 // u32WritelimitBase = ((u32IPMBase0 + u32MemSize) / BYTE_PER_WORD - 1) | 0x2000000;
4093 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pFrameBufInfo.u32IPMBase1);
4094 // frcm write base address limit
4095 #if 0
4096 #if (HW_DESIGN_4K2K_VER == 4)
4097 if ((psXCInstPri->u32DeviceID==0)
4098 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
4099 {
4100 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L, pFrameBufInfo.u32FRCMWriteLimitBase);
4101 }
4102 #endif
4103 #endif
4104 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_09_L, (MS_U16)(u32IPMBase0 & 0xFF0000)>>16,0x00FF);
4105 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, (MS_U16)(u32IPMBase0 & 0xFFFF));
4106
4107 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0B_L, (MS_U16)(u32IPMBase1 & 0xFF0000)>>16,0x00FF);
4108 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, (MS_U16)(u32IPMBase1 & 0xFFFF));
4109
4110 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0D_L, (MS_U16)(u32IPMBase2 & 0xFF0000)>>16,0x00FF);
4111 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, (MS_U16)(u32IPMBase2 & 0xFFFF));
4112
4113
4114 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pFrameBufInfo.u16IPMOffset);
4115 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pFrameBufInfo.u16IPMFetch);
4116 // SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x1000),0x1FFF);
4117 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_03_L, ((pFrameBufInfo.bLinearAddrMode)?BIT(4):0),BIT(4));
4118
4119 }
4120
Hal_SC_get_cs_det_cnt(void * pInstance,SCALER_WIN eWindow)4121 MS_U8 Hal_SC_get_cs_det_cnt(void *pInstance, SCALER_WIN eWindow)
4122 {
4123 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4124 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4125 MS_U8 u8val;
4126
4127 if(eWindow == MAIN_WINDOW)
4128 {
4129 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L) & 0xFF00) >> 8);
4130 }
4131 else
4132 {
4133 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L) & 0xFF00) >> 8);
4134 }
4135 return u8val;
4136 }
4137
Hal_SC_set_cs_det_cnt(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)4138 void Hal_SC_set_cs_det_cnt(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
4139 {
4140 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4141 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4142 if(eWindow == MAIN_WINDOW)
4143 {
4144 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
4145 }
4146 else
4147 {
4148 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
4149 }
4150 }
4151
Hal_SC_get_plus_width(void * pInstance,SCALER_WIN eWindow)4152 MS_U8 Hal_SC_get_plus_width(void *pInstance, SCALER_WIN eWindow)
4153 {
4154 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4155 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4156 MS_U8 u8val;
4157
4158 if(eWindow == MAIN_WINDOW)
4159 {
4160 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0x00FF);
4161 }
4162 else
4163 {
4164 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_22_L) & 0x00FF);
4165 }
4166 return u8val;
4167 }
4168
Hal_SC_set_opm_fetch(void * pInstance,SCALER_WIN eWindow,MS_U16 u16OPMFetch)4169 void Hal_SC_set_opm_fetch(void *pInstance, SCALER_WIN eWindow, MS_U16 u16OPMFetch)
4170 {
4171 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4172 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4173 if(eWindow == MAIN_WINDOW)
4174 {
4175 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, u16OPMFetch, 0x1FFF);
4176 }
4177 else
4178 {
4179 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, u16OPMFetch, 0x1FFF);
4180 }
4181 }
4182
Hal_SC_get_opm_fetch(void * pInstance,SCALER_WIN eWindow)4183 MS_U16 Hal_SC_get_opm_fetch(void *pInstance, SCALER_WIN eWindow)
4184 {
4185 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4186 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4187 MS_U16 u16Val = 0;
4188 if(eWindow == MAIN_WINDOW)
4189 {
4190 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L) & 0x0FFF;
4191 }
4192 else
4193 {
4194 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L) & 0x0FFF;
4195 }
4196 return u16Val;
4197 }
4198
HAL_SC_get_dnr_setting(void * pInstance,SCALER_WIN eWindow)4199 MS_U8 HAL_SC_get_dnr_setting(void *pInstance, SCALER_WIN eWindow)
4200 {
4201 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4202 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4203 if(eWindow == MAIN_WINDOW)
4204 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, BIT(1)|BIT(0));
4205 else
4206 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, BIT(1)|BIT(0));
4207 }
4208
HAL_SC_enable_field_avg_y(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4209 void HAL_SC_enable_field_avg_y(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4210 {
4211 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4212 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4213 if(eWindow == MAIN_WINDOW)
4214 {
4215 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(6) : 0, BIT(6));
4216 }
4217 else
4218 {
4219 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(6) : 0, BIT(6));
4220 }
4221
4222 }
4223
HAL_SC_enable_field_avg_c(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4224 void HAL_SC_enable_field_avg_c(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4225 {
4226 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4227 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4228 if(eWindow == MAIN_WINDOW)
4229 {
4230 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(7) : 0, BIT(7));
4231 }
4232 else
4233 {
4234 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(7) : 0, BIT(7));
4235 }
4236 }
4237
HAL_SC_enable_dnr(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)4238 void HAL_SC_enable_dnr(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
4239 {
4240 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4241 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4242 if(eWindow == MAIN_WINDOW)
4243 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, u8Val, BIT(1)|BIT(0));
4244 else
4245 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, u8Val, BIT(1)|BIT(0));
4246 }
4247
HAL_SC_VOP_Set_Contrast_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)4248 void HAL_SC_VOP_Set_Contrast_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
4249 {
4250 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4251 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4252 if(eWindow == MAIN_WINDOW)
4253 {
4254 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(0):0), BIT(0));
4255 }
4256 else
4257 {
4258 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(8):0), BIT(8));
4259 }
4260 }
HAL_SC_VOP_Set_Contrast_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)4261 void HAL_SC_VOP_Set_Contrast_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
4262 {
4263 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4264 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4265 if(eWindow == MAIN_WINDOW)
4266 {
4267 switch(eVop_Channel)
4268 {
4269 default:
4270 case XC_VOP_CHR:
4271 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
4272 break;
4273 case XC_VOP_CHG:
4274 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
4275 break;
4276 case XC_VOP_CHB:
4277 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
4278 break;
4279 case XC_VOP_ALL:
4280 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
4281 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
4282 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
4283 break;
4284 }
4285 }
4286 else
4287 {
4288 switch(eVop_Channel)
4289 {
4290 default:
4291 case XC_VOP_CHR:
4292 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
4293 break;
4294 case XC_VOP_CHG:
4295 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
4296 break;
4297 case XC_VOP_CHB:
4298 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
4299 break;
4300 case XC_VOP_ALL:
4301 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
4302 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
4303 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
4304 break;
4305 }
4306 }
4307 }
4308
HAL_SC_VOP_Set_Brightness_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)4309 void HAL_SC_VOP_Set_Brightness_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
4310 {
4311 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4312 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4313 if(eWindow == MAIN_WINDOW)
4314 {
4315 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(1):0), BIT(1));
4316 }
4317 else
4318 {
4319 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(9):0), BIT(9));
4320 }
4321 }
HAL_SC_VOP_Set_Brightness_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)4322 void HAL_SC_VOP_Set_Brightness_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
4323 {
4324 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4325 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4326 if(eWindow == MAIN_WINDOW)
4327 {
4328 switch(eVop_Channel)
4329 {
4330 default:
4331 case XC_VOP_CHR:
4332 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
4333 break;
4334 case XC_VOP_CHG:
4335 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
4336 break;
4337 case XC_VOP_CHB:
4338 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
4339 break;
4340 case XC_VOP_ALL:
4341 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
4342 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
4343 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
4344 break;
4345 }
4346 }
4347 else
4348 {
4349 switch(eVop_Channel)
4350 {
4351 default:
4352 case XC_VOP_CHR:
4353 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
4354 break;
4355 case XC_VOP_CHG:
4356 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
4357 break;
4358 case XC_VOP_CHB:
4359 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
4360 break;
4361 case XC_VOP_ALL:
4362 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
4363 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
4364 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
4365 break;
4366 }
4367 }
4368 }
4369
HAL_SC_Set_FB_Num(void * pInstance,SCALER_WIN eWindow,XC_FRAME_STORE_NUMBER enFBType,MS_BOOL bInterlace)4370 void HAL_SC_Set_FB_Num(void *pInstance, SCALER_WIN eWindow, XC_FRAME_STORE_NUMBER enFBType, MS_BOOL bInterlace)
4371 {
4372 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4373 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4374 MS_U8 u8FrameCount = 2;
4375
4376 switch( enFBType )
4377 {
4378 case IMAGE_STORE_2_FRAMES:
4379 u8FrameCount = 2;
4380 break;
4381 case IMAGE_STORE_3_FRAMES:
4382 u8FrameCount = 3;
4383 break;
4384 case IMAGE_STORE_4_FRAMES:
4385 u8FrameCount = 4;
4386 break;
4387 case IMAGE_STORE_6_FRAMES:
4388 u8FrameCount = 6;
4389 break;
4390 case IMAGE_STORE_8_FRAMES:
4391 u8FrameCount = 8;
4392 break;
4393 case IMAGE_STORE_12_FRAMES:
4394 u8FrameCount = 12;
4395 break;
4396 default:
4397 break;
4398 }
4399
4400 if (!bInterlace)
4401 {
4402 if (eWindow == MAIN_WINDOW)
4403 {
4404 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, u8FrameCount , BITMASK(4:0) );
4405 }
4406 else
4407 {
4408 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, u8FrameCount , BITMASK(4:0) );
4409 }
4410 }
4411 }
4412
HAL_SC_Enable_VInitFactor(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4413 void HAL_SC_Enable_VInitFactor(void *pInstance, MS_BOOL bEnable,SCALER_WIN eWindow)
4414 {
4415 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4416 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4417 if (eWindow == MAIN_WINDOW)
4418 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_13_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
4419 else
4420 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_33_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
4421 }
4422
HAL_SC_Set_VInitFactorOne(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)4423 void HAL_SC_Set_VInitFactorOne(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
4424 {
4425 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4426 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4427 if (eWindow == MAIN_WINDOW)
4428 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_03_L, u32Value);
4429 else
4430 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_23_L, u32Value);
4431 }
4432
HAL_SC_Set_VInitFactorTwo(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)4433 void HAL_SC_Set_VInitFactorTwo(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
4434 {
4435 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4436 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4437 if (eWindow == MAIN_WINDOW)
4438 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_05_L, u32Value);
4439 else
4440 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_25_L, u32Value);
4441 }
4442
HAL_SC_Set_vsd_output_line_count(void * pInstance,MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)4443 void HAL_SC_Set_vsd_output_line_count(void *pInstance, MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)
4444 {
4445 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4446 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4447 MS_U16 u16OutputLineCount = 0x00;
4448
4449 if (bEnable)
4450 {
4451 u16OutputLineCount = BIT(15);
4452 u16OutputLineCount |= (MS_U16)(u32LineCount & 0x1FFF);
4453 }
4454
4455 if (eWindow == MAIN_WINDOW)
4456 {
4457 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_37_L, u16OutputLineCount);
4458 }
4459 else
4460 {
4461 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_37_L, u16OutputLineCount);
4462 }
4463
4464 }
4465
4466 /*
4467 bEnable : Enable input line count.
4468 bUserMode : 1 -> the input line count will ref u32UserLineCount
4469 0 -> the input line count will ref V capture win
4470 */
HAL_SC_Set_vsd_input_line_count(void * pInstance,MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)4471 void HAL_SC_Set_vsd_input_line_count(void *pInstance, MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)
4472 {
4473 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4474 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4475 MS_U16 u16InputLineCount = 0x00;
4476
4477 if (bEnable)
4478 {
4479 u16InputLineCount = BIT(15);
4480
4481 if (bUserMode)
4482 {
4483 u16InputLineCount |= BIT(14);
4484 u16InputLineCount |= (MS_U16)(u32UserLineCount & 0x1FFF);
4485 }
4486 }
4487
4488 if (eWindow == MAIN_WINDOW)
4489 {
4490 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_36_L, u16InputLineCount);
4491 }
4492 else
4493 {
4494 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_36_L, u16InputLineCount);
4495 }
4496
4497 }
4498
Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)4499 MS_U32 Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)
4500 {
4501 UNUSED(u16ScaleDst);
4502 UNUSED(bInterlace);
4503 //New chip sub window unnecessary to the same with the main window's pre scaling setting.
4504 return 0;
4505 }
4506
HAL_SC_FilmMode_Patch1(void * pInstance)4507 void HAL_SC_FilmMode_Patch1(void *pInstance)
4508 {
4509 #if 1
4510 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4511 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4512 MS_U16 u16Value;
4513 MS_U16 u16RegValue;
4514 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4515 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4516
4517 u16RegValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK22_7D_L, 0xFF);
4518 if(pXCResourcePrivate->sthal_SC.g_bCntFlg)
4519 pXCResourcePrivate->sthal_SC.g_u16TmpValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0xFF);
4520
4521 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, BIT(6)))
4522 {
4523 //Counter
4524 if(pXCResourcePrivate->sthal_SC.u8Time_count != 0xFF)
4525 pXCResourcePrivate->sthal_SC.u8Time_count ++;
4526
4527 if(pXCResourcePrivate->sthal_SC.u8Time_count < u16RegValue) // fake out duration
4528 u16Value = 0x06; // madi fake out enable
4529 else
4530 u16Value = 0x00; // madi fake out disable
4531
4532 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x10<<8), 0xFF00);
4533 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0x22, 0xFF);
4534 pXCResourcePrivate->sthal_SC.g_bCntFlg = 0;
4535 }
4536 else
4537 {
4538 pXCResourcePrivate->sthal_SC.u8Time_count = 0;
4539 u16Value = 0x00; // madi fake out disable
4540 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x08<<8), 0xFF00);
4541 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, pXCResourcePrivate->sthal_SC.g_u16TmpValue, 0xFF);
4542 pXCResourcePrivate->sthal_SC.g_bCntFlg = 1;
4543 }
4544 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, u16Value, BIT(2)|BIT(1));
4545
4546 #else
4547 MS_U8 u8Bank, u8Value;
4548 MS_U8 u8RegValue;
4549
4550 static MS_U8 u8Time_count = 0;
4551
4552 MDrv_WriteByte(BK_SELECT_00, REG_BANK_MADI); //bk22
4553 u8RegValue = MDrv_ReadByte(L_BK_MADI(0x7D));
4554
4555 MDrv_WriteByte(BK_SELECT_00, REG_BANK_FILM);
4556
4557
4558 if(MDrv_ReadRegBit(L_BK_FILM(0x21), BIT(6)))
4559 {
4560 //Counter
4561 if(u8Time_count != 0xFF)
4562 u8Time_count ++;
4563
4564 if(u8Time_count < u8RegValue) // fake out duration
4565 u8Value = 0x06; // madi fake out enable
4566 else
4567 u8Value = 0x00; // madi fake out disable
4568
4569 MDrv_WriteByte(H_BK_FILM(0x25), 0x10);
4570
4571 }
4572 else
4573 {
4574 u8Time_count = 0;
4575 u8Value = 0x00; // madi fake out disable
4576 MDrv_WriteByte(H_BK_FILM(0x25), 0x08);
4577 }
4578
4579 MDrv_WriteByteMask(L_BK_FILM(0x21), u8Value, BIT(2)|BIT(1));
4580 MDrv_WriteByte(BK_SELECT_00, u8Bank);
4581 #endif
4582 }
4583
HAL_SC_EnableFPLL(void)4584 void HAL_SC_EnableFPLL(void)
4585 {
4586 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3));
4587 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6));
4588 }
4589
4590
_HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum,void * pParam)4591 static void _HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum, void *pParam)
4592 {
4593 volatile MS_XC_GET_FPLL_PHASEDIFF * pFpllPhaseDiff = (volatile MS_XC_GET_FPLL_PHASEDIFF *) pParam;
4594
4595 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11));
4596 pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP : E_XC_FPLL_DIR_DOWN;
4597 pFpllPhaseDiff->u8Debounce++;
4598
4599 if(pFpllPhaseDiff->u8Debounce > 3)
4600 {
4601 if(pFpllPhaseDiff->u16PhaseDiff < 0x200)
4602 {
4603 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_FINISHED;
4604 }
4605 else
4606 {
4607 if(pFpllPhaseDiff->u8Debounce > 90)
4608 {
4609 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_TIMEOUT;
4610 }
4611 }
4612 }
4613 }
4614
HAL_SC_WaitFPLLDone(void * pInstance)4615 MS_BOOL HAL_SC_WaitFPLLDone(void *pInstance)
4616 {
4617 MS_XC_GET_FPLL_PHASEDIFF stGetFpllPhaseDiff = {0, 0, E_XC_FPLL_DIR_UNKNOWN, E_XC_FPLL_RES_WAITING};
4618
4619 Mhal_XC_InterruptAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4620 while(*(volatile MS_BOOL*)(&(stGetFpllPhaseDiff.eFpllResult)) == E_XC_FPLL_RES_WAITING);
4621 Mhal_XC_InterruptDeAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4622
4623 if(stGetFpllPhaseDiff.eFpllResult == E_XC_FPLL_RES_FINISHED)
4624 {
4625 return TRUE;
4626 }
4627 else
4628 {
4629 return FALSE;
4630 }
4631 }
4632
HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)4633 MS_U16 HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)
4634 {
4635 return ((MS_U16) ((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23))));
4636 }
4637
4638 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4639 //Main Win Line buffer offset , start from max size of main's
HAL_SC_SetMainLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4640 void HAL_SC_SetMainLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4641 {
4642 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4643 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4644 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_12_L, u16Linebuffer);
4645 }
4646
4647 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4648 //Sub Win Line buffer offset , start from max size of main's
HAL_SC_SetSubLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4649 void HAL_SC_SetSubLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4650 {
4651 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4652 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4653 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_13_L, u16Linebuffer);
4654 }
4655
4656 //Select the trig mode
4657 //0: Line base(Line Buffer Mode)
4658 //1: Fill line buffer(Ring Buffer Mode)
HAL_SC_SetDisplay_LineBuffer_Mode(void * pInstance,MS_BOOL bEnable)4659 void HAL_SC_SetDisplay_LineBuffer_Mode(void *pInstance, MS_BOOL bEnable)
4660 {
4661 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4662 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4663 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(4) : 0), BIT(4));
4664 }
4665
4666 //Select the start mode
4667 //0: start at advance 1 display line
4668 //1: start at faling edge of Vsync_init
HAL_SC_SetDisplay_Start_Mode(void * pInstance,MS_BOOL bEnable)4669 void HAL_SC_SetDisplay_Start_Mode(void *pInstance, MS_BOOL bEnable)
4670 {
4671 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4672 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4673 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(5) : 0), BIT(5));
4674 }
4675
4676 //bk20_10[10]: Fill the main window's line buffer in vertical blanking for pip left and up corner
4677 //bk20_10[11]: Fill the sub window's line buffer in vertical blanking for pip left and down corner
HAL_SC_FillLineBuffer(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4678 void HAL_SC_FillLineBuffer(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4679 {
4680 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4681 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4682 if(bEnable)
4683 {
4684 if(eWindow == MAIN_WINDOW)
4685 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(10), BIT(10));
4686 else
4687 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11), BIT(11));
4688 }
4689 else
4690 {
4691 if(eWindow == MAIN_WINDOW)
4692 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(10));
4693 else
4694 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
4695 }
4696 }
4697
Hal_SC_enable_window(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4698 void Hal_SC_enable_window(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4699 {
4700 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4701 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4702 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4703 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4704
4705 if (eWindow == MAIN_WINDOW)
4706 {
4707 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4708 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4709 if (psXCInstPri->u32DeviceID == 1)
4710 {
4711 // set SC1 auto no signal by SC1 control
4712 SC_W2BYTEMSK(0, REG_SC_BK11_07_L, bEn ? BIT(5) : 0, BIT(5));
4713 SC_W2BYTEMSK(0, REG_SC_BK20_10_L, bEn ? BIT(2)|BIT(1) : 0, BIT(2)|BIT(1));
4714 //#if FRC_INSIDE
4715 SC_W2BYTEMSK(0, REG_SC_BK68_40_L, bEn ? BIT(4) : 0, BIT(4));
4716 //#endif
4717 SC_W2BYTEMSK(0, REG_SC_BK46_3F_L, bEn ? 0 : BIT(0), BIT(0));
4718 }
4719 #endif
4720 }
4721 else
4722 {
4723 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4724 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11) , BIT(11));
4725 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(1) : 0, BIT(1));
4726 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, bEn ? BIT(0) : 0, BIT(0));
4727
4728 #ifdef XC_SUPPORT_2STEP_SCALING
4729 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4730 {
4731 if (bEn == TRUE)
4732 {
4733 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == BIT(0)) // enable 2-step scaling.
4734 {
4735 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4736 // Disable 2 Step Scaling
4737 SC_W2BYTEMSK(0, REG_SC_BK4F_10_L, 0, BIT(0));
4738 // Adjust XC postScaling
4739 MS_U32 u32TmpScaling = 0;
4740 //H post-scaling
4741 u32TmpScaling = pDBreg->u32H_PostScalingRatio & (~0x1000000L);
4742 u32TmpScaling = u32TmpScaling/2;
4743 u32TmpScaling |= 0x1000000L;
4744
4745 SC_W2BYTEMSK(0, REG_SC_BK23_07_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4746 SC_W2BYTEMSK(0, REG_SC_BK23_08_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4747
4748 //V post-scaling
4749 u32TmpScaling = pDBreg->u32V_PostScalingRatio & (~0x1000000L);
4750 u32TmpScaling = u32TmpScaling/2;
4751 u32TmpScaling |= 0x1000000L;
4752 SC_W2BYTEMSK(0, REG_SC_BK23_09_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4753 SC_W2BYTEMSK(0, REG_SC_BK23_0A_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4754 }
4755 }
4756 else
4757 {
4758 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == 0) // Disable 2-step scaling.
4759 {
4760 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4761 // Restore 2 Step Scaling
4762 SC_W2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0), BIT(0));
4763 // Restore XC postScaling
4764 //H post-scaling
4765
4766 SC_W2BYTEMSK(0, REG_SC_BK23_07_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>00), 0xFFFF);
4767 SC_W2BYTEMSK(0, REG_SC_BK23_08_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>16), 0xFFFF);
4768 //V post-scaling
4769 SC_W2BYTEMSK(0, REG_SC_BK23_09_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>00), 0xFFFF);
4770 SC_W2BYTEMSK(0, REG_SC_BK23_0A_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>16), 0xFFFF);
4771 }
4772 }
4773 }
4774
4775 #endif
4776
4777
4778 }
4779 }
4780
_Hal_SC_GetInputVPeriod(void * pInstance,SCALER_WIN eWindow)4781 static MS_U16 _Hal_SC_GetInputVPeriod(void *pInstance, SCALER_WIN eWindow)
4782 {
4783 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4784 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4785 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4786 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4787 MS_U16 u16VFreq = gSrcInfo[eWindow].u16InputVFreq * 10;
4788 SC_DBG(printf("(100000+u16VFreq/2)/u16VFreq)=%u, u16VFreq=%u\n",((100000+u16VFreq/2)/u16VFreq), u16VFreq));
4789 if(u16VFreq == 0)
4790 {
4791 return 0;
4792 }
4793 else
4794 {
4795 return ((100000+u16VFreq/2)/u16VFreq); //Period = 1000/(vfreq/100)
4796 }
4797 }
4798
Hal_SC_enable_window_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4799 void Hal_SC_enable_window_burst(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4800 {
4801 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4802 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4803 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4804 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4805 _MLOAD_ENTRY(pInstance);
4806 if (eWindow == MAIN_WINDOW)
4807 {
4808 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4809 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4810 void *pInstanceTmp = NULL;
4811 if (psXCInstPri->u32DeviceID == 1)
4812 {
4813 pInstanceTmp = pInstance; // store instance 0
4814 pInstance = g_pDevice0Instance; //switch to instance 1
4815 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4816 // set SC1 auto no signal by SC1 control
4817 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_07_L, bEn ? BIT(5) : 0, BIT(5));
4818 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(2)|BIT(1) : 0, BIT(2)|BIT(1));
4819 //#if FRC_INSIDE
4820 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_40_L, bEn ? BIT(4) : 0, BIT(4));
4821 //#endif
4822 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3F_L, bEn ? 0 : BIT(0), BIT(0));
4823
4824 pInstance = pInstanceTmp; // restore instance 0
4825 }
4826
4827 #endif
4828
4829 Mhal_XC_MLoad_Fire(pInstance, TRUE);
4830 }
4831 else
4832 {
4833 if(bEn == TRUE)
4834 {
4835 MS_U16 u16extra_req = 0;
4836 MS_U16 u16Delaytime = 0;
4837
4838 // When Main is foreground, sub is background, extra must enable.
4839 u16extra_req = 0x01;
4840
4841 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL , NULL , NULL))
4842 {
4843 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
4844 u16extra_req = u16extra_req | 0x8000;
4845 }
4846
4847 // HW PIP architeucture
4848 // Becasue BK3_02[8] and BK20_11[15] should enable together, otherwise garbage will be showed,
4849 // we need to use BK12_47[0] to instead. And the default value of BK3_02[8] is 1. So, we need
4850 // to set it to 0 in this function.
4851 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, u16extra_req , 0x800F);
4852 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0, 0x0080);
4853
4854 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4855 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(11), BIT(11) );
4856 Mhal_XC_MLoad_Fire(pInstance, TRUE);
4857 //if we let REG_SC_BK20_10_L[1] to enable with other register settings in the same menuload fire
4858 //it will produce a rectangular horizontal noise. so we move outside to let those register settings
4859 //to be set first then let REG_SC_BK20_10_L[1] on.
4860
4861 //betwen REG_SC_BK03_02_L[7] and REG_SC_BK20_10_L[1], we need to delay time of wr mapping mode,
4862 // to let the data fill in xc sub buffer
4863 u16Delaytime = _Hal_SC_GetInputVPeriod(pInstance, eWindow) * (Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow) + 1);
4864 MsOS_DelayTask(u16Delaytime);
4865
4866 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(1), BIT(1));
4867 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, BIT(0), BIT(0));
4868 #ifdef XC_SUPPORT_2STEP_SCALING
4869 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4870 {
4871 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == BIT(0)) // enable 2-step scaling.
4872 {
4873 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4874 // Disable 2 Step Scaling
4875 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, 0, BIT(0));
4876 // Adjust XC postScaling
4877 MS_U32 u32TmpScaling = 0;
4878
4879 //H post-scaling
4880 u32TmpScaling = pDBreg->u32H_PostScalingRatio & (~0x1000000L);
4881 u32TmpScaling = u32TmpScaling/2;
4882 u32TmpScaling |= 0x1000000L;
4883 //H post-scaling
4884 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4885 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4886 //V post-scaling
4887 u32TmpScaling = pDBreg->u32V_PostScalingRatio & (~0x1000000L);
4888 u32TmpScaling = u32TmpScaling/2;
4889 u32TmpScaling |= 0x1000000L;
4890 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4891 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4892 }
4893 }
4894 #endif
4895 Mhal_XC_MLoad_Fire(pInstance, TRUE);
4896 }
4897 else
4898 {
4899 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, 0, BIT(0));
4900 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(1));
4901 Mhal_XC_MLoad_Fire(pInstance, TRUE);
4902 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0x0080, 0x0080);
4903
4904 #ifdef XC_SUPPORT_2STEP_SCALING
4905 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4906 {
4907 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == 0) // Disable 2-step scaling.
4908 {
4909 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4910 // Restore 2 Step Scaling
4911 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, BIT(0), BIT(0));
4912 // Restore XC postScaling
4913 //H post-scaling
4914 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>00), 0xFFFF);
4915 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>16), 0xFFFF);
4916 //V post-scaling
4917 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>00), 0xFFFF);
4918 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>16), 0xFFFF);
4919 }
4920 }
4921 #endif
4922
4923 Mhal_XC_MLoad_Fire(pInstance, TRUE);
4924 }
4925 }
4926
4927 _MLOAD_RETURN(pInstance);
4928 }
4929
Hal_SC_set_trigger_signal(void)4930 void Hal_SC_set_trigger_signal(void)
4931 {
4932 // only used in U4
4933 }
4934
Hal_SC_Set_OSD2VE(void * pInstance,EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)4935 void Hal_SC_Set_OSD2VE(void *pInstance, EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)
4936 {
4937 UNUSED(eVOPSelOSD_MUX);
4938 }
4939
Hal_SC_IsOPMFetchPatch_Enable(void)4940 MS_BOOL Hal_SC_IsOPMFetchPatch_Enable(void)
4941 {
4942 //Patch for Janus u01 and T4 U01/02: OPMFetch need +2
4943 return FALSE;
4944 }
Hal_SC_Check_HNonLinearScaling(void * pInstance)4945 MS_BOOL Hal_SC_Check_HNonLinearScaling(void *pInstance)
4946 {
4947 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4948 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4949 MS_U16 u16Offset = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_15_L)>>8);
4950 MS_U16 u16MaxOffset = ((SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L) & 0xFFFFFF)>>12);
4951 //Non-Linear scaling Postive offset, the maximum offset is HPstRatio[23:12]
4952 if(((u16Offset & BIT(7)) == 0) && (u16Offset > u16MaxOffset))
4953 {
4954 return FALSE;
4955 }
4956 return TRUE;
4957 }
4958
4959 //IP2 Pre-Filter enable
Hal_SC_IP2_PreFilter_Enable(void * pInstance,MS_BOOL bEnable)4960 void Hal_SC_IP2_PreFilter_Enable(void* pInstance, MS_BOOL bEnable)
4961 {
4962 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4963 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4964 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_48_L, (bEnable?BIT(15):0), BIT(15));
4965 }
4966
Hal_SC_Set_extra_fetch_line(void * pInstance,MS_U8 u8val)4967 void Hal_SC_Set_extra_fetch_line(void *pInstance, MS_U8 u8val)
4968 {
4969 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4970 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4971 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<8, 0x0F00);
4972 }
4973
Hal_SC_Set_extra_adv_line(void * pInstance,MS_U8 u8val)4974 void Hal_SC_Set_extra_adv_line(void *pInstance, MS_U8 u8val)
4975 {
4976 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4977 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4978 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<12, 0xF000);
4979 }
4980
HAL_SC_Set_FPLL_Limit(void * pInstance,MS_U32 * u32PllSet,MS_U32 u32LowBound,MS_U32 u32UpBound,MS_BOOL _bInFPLLDbgMode,MS_U32 _U32LimitD5D6D7)4981 void HAL_SC_Set_FPLL_Limit(void *pInstance, MS_U32 *u32PllSet, MS_U32 u32LowBound, MS_U32 u32UpBound, MS_BOOL _bInFPLLDbgMode, MS_U32 _U32LimitD5D6D7)
4982 {
4983 MS_U32 u32LpllLimitLow, u32LpllLimitHigh;
4984 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4985 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4986 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4987 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4988 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
4989
4990 if(_bInFPLLDbgMode)
4991 {
4992 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit
4993 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
4994 {
4995 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7);
4996 }
4997 }
4998 else
4999 {
5000 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
5001
5002 // check if u32PllSet out of range and also the FPLL limit
5003 if (*u32PllSet <= u32LowBound)
5004 {
5005 *u32PllSet = u32LowBound;
5006 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
5007 }
5008 else if (*u32PllSet >= u32UpBound)
5009 {
5010 *u32PllSet = u32UpBound;
5011 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
5012 }
5013
5014 u32LpllLimitHigh = u32UpBound - *u32PllSet;
5015 u32LpllLimitLow = *u32PllSet - u32LowBound - 1;
5016
5017 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
5018
5019 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
5020 {
5021 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
5022 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
5023 }
5024
5025 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
5026 }
5027 }
5028
Hal_XC_Get_3D_Output_Mode(void * pInstance)5029 E_XC_3D_OUTPUT_MODE Hal_XC_Get_3D_Output_Mode(void *pInstance)
5030 {
5031 #ifndef DISABLE_3D_FUNCTION
5032 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5033 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5034 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5035 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5036 return pXCResourcePrivate->stdrvXC_3D._eOutput3DMode;
5037 #else
5038 return E_XC_3D_OUTPUT_MODE_NONE;
5039 #endif
5040 }
5041
Hal_XC_H3D_Enable(void * pInstance,MS_BOOL bEn)5042 void Hal_XC_H3D_Enable(void *pInstance, MS_BOOL bEn)
5043 {
5044 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5045 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5046 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_70_L, (bEn<<15), (BIT(15)));
5047 }
5048
Hal_XC_H3D_Input3DType(void * pInstance,E_XC_3D_INPUT_MODE e3DType)5049 void Hal_XC_H3D_Input3DType(void *pInstance, E_XC_3D_INPUT_MODE e3DType)
5050 {
5051 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5052 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5053 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (e3DType), (BIT(1) | BIT(0)));
5054 }
5055
Hal_XC_H3D_Breakline_Enable(void * pInstance,MS_BOOL bEn)5056 void Hal_XC_H3D_Breakline_Enable(void *pInstance, MS_BOOL bEn)
5057 {
5058 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5059 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5060 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (bEn<<7), (BIT(7)));
5061 if(bEn)
5062 {
5063 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (8<<8), HBMASK);
5064 }
5065 else
5066 {
5067 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (0<<8), HBMASK);
5068 }
5069 }
5070
Hal_XC_H3D_HDE(void * pInstance,MS_U16 u16Hde)5071 void Hal_XC_H3D_HDE(void *pInstance, MS_U16 u16Hde)
5072 {
5073 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5074 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5075 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_71_L, (u16Hde), 0x0FFF);
5076 }
5077
Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)5078 void Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)
5079 {
5080 SC_W2BYTEMSK(0, REG_SC_BK01_73_L, (u16Vde), 0x0FFF);
5081 }
5082
Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)5083 void Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)
5084 {
5085 SC_W2BYTEMSK(0, REG_SC_BK01_77_L, (u16Vde), 0x0FFF);
5086 }
5087
Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)5088 void Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)
5089 {
5090 SC_W2BYTEMSK(0, REG_SC_BK01_70_L, (u16Hblank), 0x03FF);
5091 }
5092
Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)5093 void Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)
5094 {
5095 SC_W2BYTEMSK(0, REG_SC_BK01_72_L, (u8Vblank), LBMASK);
5096 }
5097
Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)5098 void Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)
5099 {
5100 SC_W2BYTEMSK(0, REG_SC_BK01_74_L, (u8Vblank), LBMASK);
5101 }
5102
Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)5103 void Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)
5104 {
5105 SC_W2BYTEMSK(0, REG_SC_BK01_76_L, (u8Vblank), LBMASK);
5106 }
5107
Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)5108 void Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)
5109 {
5110 SC_W2BYTEMSK(0, REG_SC_BK01_78_L, (u8Vblank), LBMASK);
5111 }
5112
Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)5113 void Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)
5114 {
5115 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u8Width), 0x001F);
5116 }
5117
Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)5118 void Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)
5119 {
5120 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u16Position), HBMASK);
5121 }
5122
Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)5123 void Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)
5124 {
5125 SC_W2BYTEMSK(0, REG_SC_BK01_7B_L, (bEn<<4), (BIT(4)));
5126 }
5127
Hal_XC_H3D_LR_Toggle_Enable(void * pInstance,MS_BOOL bEn,MS_BOOL b2DTo3D,MS_BOOL bSkipDefaultLRFlag)5128 void Hal_XC_H3D_LR_Toggle_Enable(void *pInstance, MS_BOOL bEn, MS_BOOL b2DTo3D, MS_BOOL bSkipDefaultLRFlag)
5129 {
5130 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5131 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5132 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5133 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5134
5135 if(!bSkipDefaultLRFlag)
5136 {
5137 if(bEn)
5138 {
5139 //Enanble I2S_IN_SD to send out lr flag
5140 MDrv_WriteByteMask(0x101E24, 0x00, BIT(4)|BIT(5)|BIT(6));
5141 MDrv_WriteByteMask(0x101EC9, 0x00, BIT(0)|BIT(1));
5142 MDrv_WriteByteMask(0x101EDC, 0x00, BIT(2));
5143 MDrv_WriteByteMask(0x101EB3, 0xC0, 0xC0);
5144 // after timing change , hw must do L/R alignment,BK12, 33[2]=1 to enable it.
5145 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, BIT(2), BIT(2));
5146 }
5147 else
5148 {
5149 MDrv_WriteByteMask(0x101EB3, 0x00, 0xC0);
5150 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, BIT(2));
5151 }
5152 }
5153
5154 ///3D lr flag selection: RD's advice
5155 ///{BK20_24[13], BK20_24[11], BK20_24[1:0]}
5156 ///4'b0100: source 3D + FB
5157 ///4'b0101: source 3D + RFBL
5158 ///4'b0111: 2D to 3D
5159 ///4'b1000: FRC on
5160 if(bEn)
5161 {
5162 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(11), BIT(11)); //Output 3D L/R selection
5163 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, (bEn<<8), (BIT(8))); //enable Enable free run 3D LR flag: if disable, when image freezed,the output is always L or always R.
5164 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, (bEn<<1), (BIT(1)));//L first,
5165
5166 if(b2DTo3D)
5167 {
5168 if(pXCResourcePrivate->stdrvXC_3D._bFALLRRToFA)//output FA_LLRR for 4k0.5k@240Hz
5169 {
5170 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x00, BIT(0)|BIT(1));
5171 }
5172 else
5173 {
5174 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
5175 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, BIT(11), (BIT(11)));
5176 }
5177 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, BIT(15), BIT(15));///2Dto3D LR flag enable
5178 }
5179 else
5180 {
5181 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x00, BIT(0)|BIT(1));
5182 }
5183 }
5184 else
5185 {
5186 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x0000, BIT(0)|BIT(1)|BIT(11)|BIT(13)); //Output 3D L/R selection
5187 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0, (BIT(8))); //enable Enable free run 3D LR flag
5188 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, (BIT(1)));
5189 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, BIT(15));
5190 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0, (BIT(11)));
5191 }
5192 }
5193
HAL_XC_H3D_OPM_SBYS_PIP_Enable(void * pInstance,MS_BOOL bEn)5194 void HAL_XC_H3D_OPM_SBYS_PIP_Enable(void *pInstance, MS_BOOL bEn)
5195 {
5196 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5197 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5198 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_34_L, (bEn<<7), (BIT(7)));
5199 }
5200
Hal_SC_enable_cursor_report(void * pInstance,MS_BOOL bEn)5201 void Hal_SC_enable_cursor_report(void *pInstance, MS_BOOL bEn)
5202 {
5203 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5204 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5205 if(bEn)
5206 {
5207 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
5208 }
5209 else
5210 {
5211 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00 , BIT(8) | BIT(10));
5212 }
5213 }
5214
Hal_SC_get_pixel_rgb(void * pInstance,XC_Get_Pixel_RGB * pData)5215 MS_BOOL Hal_SC_get_pixel_rgb(void *pInstance, XC_Get_Pixel_RGB *pData)
5216 {
5217 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5218 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5219 MS_BOOL bret = TRUE;
5220
5221 switch(pData->enStage)
5222 {
5223 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
5224 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
5225 bret = FALSE;//Not support, Must set to stage C for HW issue
5226 break;
5227 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
5228 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
5229 bret = FALSE;//Not support, Must set to stage C for HW issue
5230 break;
5231 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
5232 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0x0D, 0xFF);
5233 break;
5234 default:
5235 bret = FALSE;
5236 break;
5237 }
5238 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5239 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5240 if(bret)
5241 {
5242 // Enable
5243 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
5244 {
5245 Hal_SC_enable_cursor_report(pInstance, TRUE);
5246 }
5247
5248 // Initial position (x,y) Set point you want to read.
5249 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_19_L, pData->u16x);
5250 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_1A_L, pData->u16y);
5251
5252 //SW trigger for reading
5253 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, BIT(8), BIT(8));
5254 MsOS_DelayTask(5);
5255 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0, BIT(8));
5256 MsOS_DelayTask(32); // Must wait .
5257
5258 pData->u32r = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2D_L);
5259 pData->u32g = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2E_L);
5260 pData->u32b = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2F_L);
5261
5262 // Disable
5263 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
5264 {
5265 Hal_SC_enable_cursor_report(pInstance, FALSE);
5266 }
5267 }
5268 return bret;
5269 }
5270
Hal_SC_SetOPWriteOff(void * pInstance,MS_BOOL bEna)5271 void Hal_SC_SetOPWriteOff(void *pInstance, MS_BOOL bEna)
5272 {
5273 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5274 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5275 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5276 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5277
5278 MS_BOOL u16OldReg = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0)));
5279
5280 #if (HW_DESIGN_4K2K_VER == 4)
5281 // For monaco new chip design, only Legacy mode need to control OPW
5282 // If Monaco mode, always keep OPW is on
5283 if ((psXCInstPri->u32DeviceID==0)
5284 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
5285 {
5286 bEna = FALSE;
5287 }
5288 #endif
5289
5290 if(u16OldReg != bEna)
5291 {
5292 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, bEna, BIT(0));//This will stop OPW only, OP memory write request still on
5293 }
5294 }
5295
5296
Hal_SC_GetOPWriteOff(void * pInstance)5297 MS_BOOL Hal_SC_GetOPWriteOff(void *pInstance)
5298 {
5299 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5300 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5301 return (MS_BOOL)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0));
5302 }
5303
Hal_SC_Detect_RequestFBL_Mode(void * pInstance)5304 MS_BOOL Hal_SC_Detect_RequestFBL_Mode(void *pInstance)
5305 {
5306 UNUSED(pInstance);
5307 return ENABLE_REQUEST_FBL;
5308 }
5309
Hal_SC_Set_RequestFBL_Mode(void * pInstance,MS_BOOL bEn)5310 MS_BOOL Hal_SC_Set_RequestFBL_Mode(void *pInstance, MS_BOOL bEn)
5311 {
5312 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5313 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5314 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5315 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5316
5317 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType) || (IsSrcTypeStorage(gSrcInfo[MAIN_WINDOW].enInputSourceType)))//MVOP source
5318 {
5319 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = bEn;
5320
5321 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, bEn?BIT(14):0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
5322 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, bEn?(BIT(0)|BIT(2)):0 , BIT(0)|BIT(2)); // Bit0: Enable HSK mode Bit2:reg_ip2_vs_sel 0:ip1 1:mvop
5323
5324 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5D_L, 0x0828 , 0xFFFF);
5325 Hal_XC_MLoad_set_trig_p(pInstance, 0x14, 0x18);
5326
5327 //this feature conflicts with HSK mode
5328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_45_L, 0x0000, 0x9FFF); // edclk pd control start and edclk pd control enable
5329 }
5330 else
5331 {
5332 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = FALSE;
5333
5334 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, 0x0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
5335 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, 0x0 , BIT(0)|BIT(2)); // Disable HSK mode Bit2:reg_ip2_vs_sel 0:ip1 1:mvop
5336 }
5337
5338 #ifdef UFO_XC_HDR
5339 #if (UFO_XC_HDR_VERSION >= 2)
5340 if (IsSrcTypeHDMI(gSrcInfo[MAIN_WINDOW].enInputSourceType))
5341 {
5342 // enable hdr dma seamless with rfbl mode on maserati
5343 MApi_XC_W2BYTEMSK(REG_SC_BK79_03_L, 1, BIT(15));
5344 }
5345 #endif
5346 #endif
5347
5348 return ENABLE_REQUEST_FBL;
5349 }
5350
Hal_XC_SetFrameColor(void * pInstance,MS_U32 u32aRGB)5351 void Hal_XC_SetFrameColor(void *pInstance, MS_U32 u32aRGB)
5352 {
5353 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5354 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5355 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, (u32aRGB >> 8),0xFF00); ///< R
5356 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB >> 8),0x00FF); ///< G
5357 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB << 8),0xFF00); ///< B
5358 }
Hal_SC_getVSyncWidth(void * pInstance,SCALER_WIN eWindow)5359 MS_U8 Hal_SC_getVSyncWidth(void *pInstance, SCALER_WIN eWindow)
5360 {
5361 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5362 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5363 MS_U8 u8val = 0;
5364
5365 if(eWindow == MAIN_WINDOW)
5366 {
5367 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0xFF00) >> 8);
5368 }
5369 else
5370 {
5371 }
5372 return u8val;
5373 }
5374
Hal_SC_Set_OSDLayer(void * pInstance,E_VOP_OSD_LAYER_SEL eVOPOSDLayer,SCALER_WIN eWindow)5375 E_APIXC_ReturnValue Hal_SC_Set_OSDLayer(void *pInstance, E_VOP_OSD_LAYER_SEL eVOPOSDLayer, SCALER_WIN eWindow)
5376 {
5377 return E_APIXC_RET_FAIL;
5378 }
5379
Hal_SC_Get_OSDLayer(void * pInstance,SCALER_WIN eWindow)5380 E_VOP_OSD_LAYER_SEL Hal_SC_Get_OSDLayer(void *pInstance, SCALER_WIN eWindow)
5381 {
5382 //do nothing
5383 return E_VOP_LAYER_RESERVED;
5384 }
5385
Hal_SC_Set_VideoAlpha(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)5386 E_APIXC_ReturnValue Hal_SC_Set_VideoAlpha(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
5387 {
5388 //do nothing
5389 return E_APIXC_RET_FAIL;
5390 }
5391
Hal_SC_Get_VideoAlpha(void * pInstance,MS_U8 * pu8Val,SCALER_WIN eWindow)5392 E_APIXC_ReturnValue Hal_SC_Get_VideoAlpha(void *pInstance, MS_U8 *pu8Val, SCALER_WIN eWindow)
5393 {
5394 *pu8Val += 0;
5395
5396 //do nothing
5397 return E_APIXC_RET_FAIL;
5398 }
5399
Hal_XC_ClearScalingFactorForInternalCalib(void * pInstance)5400 void Hal_XC_ClearScalingFactorForInternalCalib(void *pInstance)
5401 {
5402 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5403 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5404 //MDrv_WriteRegBit(H_BK_SCMI(0x09), FALSE, BIT(7));
5405 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, 0x0000); // H pre-scaling
5406 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_05_L, 0xC010); // H pre-scaling
5407 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, 0x0000); // V pre-scaling
5408 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_09_L, 0x0000); // V pre-scaling
5409
5410 //HVSP
5411 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, 0x0000); // H post-scaling
5412 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_08_L, 0x0100); // H post-scaling
5413 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, 0x0000); // V post-scaling
5414 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_0A_L, 0x0100); // V post-scaling
5415 }
5416
MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)5417 MS_U8 MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)
5418 {
5419 MS_U8 u8Value = 0;
5420
5421 if (u16UsedGain_x32 >=65536) u8Value = 16;
5422 else if (u16UsedGain_x32 >=32768) u8Value = 15;
5423 else if (u16UsedGain_x32 >=16384) u8Value = 14;
5424 else if (u16UsedGain_x32 >= 8192) u8Value = 13;
5425 else if (u16UsedGain_x32 >= 4096) u8Value = 12;
5426 else if (u16UsedGain_x32 >= 2048) u8Value = 11;
5427 else if (u16UsedGain_x32 >= 1024) u8Value = 10;
5428 else if (u16UsedGain_x32 >= 512) u8Value = 9;
5429 else if (u16UsedGain_x32 >= 256) u8Value = 8;
5430 else if (u16UsedGain_x32 >= 128) u8Value = 7;
5431 else if (u16UsedGain_x32 >= 64) u8Value = 6;
5432 else if (u16UsedGain_x32 >= 32) u8Value = 5;
5433 else if (u16UsedGain_x32 >= 16) u8Value = 4;
5434 else if (u16UsedGain_x32 >= 8) u8Value = 3;
5435 else if (u16UsedGain_x32 >= 4) u8Value = 2;
5436 else if (u16UsedGain_x32 >= 2) u8Value = 1;
5437 else if (u16UsedGain_x32 >= 1) u8Value = 0;
5438 else {
5439 u8Value = 0;
5440 }
5441
5442 u8Value += IPGAIN_REFACTOR;
5443
5444 return u8Value;
5445 }
5446
Hal_SC_OP2VOPDESel(void * pInstance,E_OP2VOP_DE_SEL eVopDESel)5447 E_APIXC_ReturnValue Hal_SC_OP2VOPDESel(void *pInstance, E_OP2VOP_DE_SEL eVopDESel)
5448 {
5449 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5450 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5451 //Select op2vop de, for DWIN capture etc
5452 if(eVopDESel == E_OP2VOPDE_WHOLEFRAME_WITHOSD)
5453 {
5454 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, ((MS_U16)(E_OP2VOPDE_WHOLEFRAME) << 12), (BIT(12)+BIT(13)));
5455 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(15), BIT(15));
5456 }
5457 else
5458 {
5459 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, 0, BIT(15));
5460 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, (eVopDESel << 12), (BIT(12)+BIT(13)));
5461 }
5462 return E_APIXC_RET_OK;
5463 }
5464
Hal_XC_SVOutput_GetCaps(void * pInstance)5465 MS_BOOL Hal_XC_SVOutput_GetCaps(void *pInstance)
5466 {
5467 return FALSE;
5468 }
5469
5470 /////Add for FRC
_MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)5471 void _MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)
5472 {
5473 #if 0 // Manhattan only 1 LPLL
5474 MS_U64 ldPllSet = 0xff;
5475
5476 ldPllSet = ((MS_U64)320 * 524288 * 10000000 + (u32Dclk>>1)); // LPLL BK01 LPLL Set
5477 do_div(ldPllSet, u32Dclk);
5478
5479 LPLL_BK_STORE;
5480 LPLL_BK_SWITCH(0x01);
5481 W4BYTE(L_BK_LPLL(0x0F), (MS_U32)ldPllSet);
5482 LPLL_BK_RESTORE;
5483 #endif
5484 }
5485
_MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh,MS_U32 u32LpllLimitLow,MS_U8 u8Lpll_bank)5486 void _MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh, MS_U32 u32LpllLimitLow, MS_U8 u8Lpll_bank)
5487 {
5488 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
5489 LPLL_BK_STORE;
5490 LPLL_BK_SWITCH(u8Lpll_bank);
5491
5492
5493 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
5494
5495 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
5496 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
5497 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
5498
5499 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
5500
5501 LPLL_BK_RESTORE;
5502 }
5503 #define LVDS_FRC_CLOCK_MHZ 320
_MHal_SC_Flock_Set_IGainPGain(void * pInstance,MS_U8 u8FRC_Out,MS_U16 u16OutputVfreqAfterFRC,MS_U16 u16Htt,MS_U16 u16Vtt)5504 void _MHal_SC_Flock_Set_IGainPGain(void *pInstance, MS_U8 u8FRC_Out, MS_U16 u16OutputVfreqAfterFRC, MS_U16 u16Htt, MS_U16 u16Vtt)
5505 {
5506 #if 0 // Manhattan only 1 LPLL
5507 MS_U32 u32dclk=0;
5508 MS_U8 u8GainI, u8GainP;
5509 MS_U64 u64Div_Factor;
5510 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5511 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5512 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5513 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5514
5515 //check parameter valid, avoiding the diving zero failure
5516 if(0 == u8FRC_Out)
5517 {
5518 u8FRC_Out = 1;
5519 }
5520
5521 u32dclk = (MS_U32)(u16Vtt * u16Htt * u8FRC_Out);
5522 //u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock;
5523 u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000;
5524 do_div(u64Div_Factor, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock);
5525 do_div(u64Div_Factor, (MS_U32)u32dclk * 8);
5526
5527 u8GainI = MHal_SC_cal_usedgain_to_reggain(u64Div_Factor);
5528
5529 if((u8FRC_Out == 5)&&(u64Div_Factor==0))
5530 {
5531 //24 to 60Hz, because the SW can't get the real value by log table
5532 u8GainI = 1;
5533
5534 u8GainI += 2;
5535 }
5536
5537 u8GainP = u8GainI+1;
5538 if((u8FRC_Out >= 2) && (u8GainP == u8GainI))
5539 {
5540 u8GainP++;
5541 }
5542
5543 LPLL_BK_STORE;
5544 LPLL_BK_SWITCH(0x01);
5545 MDrv_WriteByte(H_BK_LPLL(0x0B), (u8GainP<<4)|u8GainI); //Gain
5546 LPLL_BK_RESTORE;
5547 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "i_Gain= 0x%tx (%tu)\n", (ptrdiff_t)u64Div_Factor, (ptrdiff_t)u64Div_Factor)
5548 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_IGain= 0x%x (%u)\n", u8GainI, u8GainI)
5549 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_PGain= 0x%x (%u)\n", u8GainP, u8GainP)
5550 #endif
5551 }
5552
5553
_MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)5554 void _MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)
5555 {
5556 #if 0 // Manhattan only 1 LPLL
5557 MS_BOOL bDiv_en = DISABLE;
5558
5559 switch(eFlock_type)
5560 {
5561 case E_XC_FLOCK_DIV_ON:
5562 bDiv_en = ENABLE;
5563 break;
5564
5565 case E_XC_FLOCK_FPLL_ON:
5566 case E_XC_FLOCK_DIV_OFF:
5567 default:
5568 break;
5569 }
5570
5571 LPLL_BK_STORE;
5572 LPLL_BK_SWITCH(0x01);
5573 MDrv_Write2ByteMask(L_BK_LPLL(0x7F), bDiv_en?BIT(8):0, BIT(8));
5574 LPLL_BK_RESTORE;
5575 #endif
5576
5577 }
5578
MHal_CLKGEN_FRC_Init(MS_U8 u8LPLL_Mode)5579 void MHal_CLKGEN_FRC_Init(MS_U8 u8LPLL_Mode)
5580 {
5581 //Patch for MSTV_TOOL to R/W FRC base address
5582 MDrv_WriteByte(0x103C0E, 0x02);
5583
5584 // Enable FSC CLK: reg_ckg_fclk_frc_fsc
5585 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz
5586 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert
5587 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock
5588
5589 // Enable FRC CLK: reg_ckg_fdclk_frc
5590 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz
5591 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert
5592 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock
5593
5594 #if FRC_INSIDE
5595 // Enable CLK_IDCLK_FRC, Reg_ckg_idclk_frc: bk119_02[8]
5596 // Enable CLK_FICLK_FRC, Reg_ckg_ficlk_frc: bk119_02[14]
5597 // Enable CLK_FDCLK_FRC, Reg_ckg_fdclk_frc: bk119_03[8]
5598 // Enable CLK_FOCLK_FRC, Reg_ckg_foclk_frc: bk119_02[6]
5599 // Enable CLK_ODCLK_FRC, Reg_ckg_odclk_frc: bk119_02[0]
5600
5601 W2BYTEMSK(REG_FRC_BK119_02_L, 0x3434, 0x7777);
5602 W2BYTEMSK(REG_FRC_BK119_03_L, 0x0000, 0x0100);
5603 #endif
5604
5605 #if 0 // Move into Panel driver
5606 // Enable CLK_DOT_MINI
5607 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK
5608 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert
5609 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock
5610
5611 // Enable CLK_DOT_MINI_PRE
5612 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK
5613 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert
5614 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock
5615 #endif
5616
5617 #if 0 // Move into panel driver
5618 // Enable CLK_R2_FRC
5619 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz
5620 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert
5621 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock
5622
5623 // Enable CLK_MCU_FRC
5624 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz
5625 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0200); // Not Invert
5626 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0100); // Enable clock
5627
5628 // Enable CLK_ODCLK_FRC
5629 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0C00); // CLK_LPLL
5630 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0200); // Not Invert
5631 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0100); // Enable clock
5632
5633
5634 // Enable CLK_TX_MOD_FRC
5635 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x000C); // clk_odclk_frc
5636 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0002); // Not Invert
5637 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0001); // Enable clock
5638
5639
5640 // Enable CLK_MINIFIFO_FRC
5641 if (u8LPLL_Mode== E_XC_MOD_OUTPUT_SINGLE ) //0: single, 1: dual
5642 {
5643 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0C00); // CLK_LPLL
5644 }
5645 else
5646 {
5647 W2BYTEMSK(L_CLKGEN1(0x32), 0x0800, 0x0C00); // CLK_LPLL_div2
5648 }
5649 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0200); // Not Invert
5650 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0100); // Enable clock
5651
5652
5653 // Enable CLK_MISC_FRC
5654 if (u8LPLL_Mode == E_XC_MOD_OUTPUT_SINGLE)
5655 {
5656 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0C00); // CLK_LPLL
5657 }
5658 else
5659 {
5660 W2BYTEMSK(L_CLKGEN1(0x33), 0x0400, 0x0C00); // CLK_LPLL_div2
5661 }
5662
5663 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0200); // Not Invert
5664 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0100); // Enable clock
5665
5666
5667
5668 // Enable CLK_MFT_FRC
5669 W2BYTEMSK(L_CLKGEN1(0x34), 0x0008, 0x000C); // CLK_LPLL_div2
5670 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0002); // Not Invert
5671 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0001); // Enable clock
5672
5673 // Enable CLK_FDCLK_FRC
5674 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x1C00); // 172 MHz
5675 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert
5676 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock
5677
5678 // Enable CLK_ICLK_FRC
5679 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0004); // clk_fdclk_frc
5680 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0002); // Not Invert
5681 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0001); // Enable clock
5682
5683 // Enable CLK_OP2_SRAM_FRC
5684 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0004); // clk_odclk_frc_p
5685 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0002); // Not Invert
5686 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0001); // Enable clock
5687
5688 // Enable CLK_LD_SRAM_FRC
5689 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0400); // clk_odclk_frc_p
5690 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0200); // Not Invert
5691 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0100); // Enable clock
5692
5693 // Enable CLK_OD_SRAM_FRC
5694 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0004); // clk_odclk_frc_p
5695 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0002); // Not Invert
5696 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0001); // Enable clock
5697
5698 // Enable CLK_LPLL_FRC
5699 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x000C); // CLK_LPLL
5700 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0002); // Not Invert
5701 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0001); // Enable clock
5702
5703 // Enable CLK_OCC_FRC
5704 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0C00); // flock_clk_synth_out
5705 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0200); // Not Invert
5706 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0100); // Enable clock
5707 #endif
5708 // Enable LVDS_MPLL
5709 //[10]reg_lvds_mpll_clk_adc432m_pd, [8]reg_lvds_mpll_pd
5710 //W2BYTEMSK(L_BK_AFEC(0x41), 0x0000, 0x0500); // MPLL_CLK_DP432M
5711 }
5712
MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)5713 void MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)
5714 {
5715
5716 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert
5717 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock
5718
5719 if (bEnable)
5720 {
5721 // Enable CLK_ODCLK
5722 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock
5723 // Disable CLK_R2_FRC
5724 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0xFFFF); // turn-on clk_mcu_frc
5725 // Enable CLK_SPI_M_FRC
5726 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Disable clock
5727 }
5728 else
5729 {
5730 // Enable CLK_ODCLK
5731 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out
5732 // Enable CLK_R2_FRC
5733 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x0C); // 216 MHz
5734 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x02); // Not Invert
5735 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x01); // Enable clock
5736 // Enable CLK_SPI_M_FRC
5737 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x1C); // 27 MHz
5738 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x02); // Not Invert
5739 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Enable clock
5740 }
5741 }
5742
5743
Hal_XC_IsForcePrescaling(void * pInstance,const XC_InternalStatus * pSrcInfo,MS_BOOL * pbForceV,MS_BOOL * pbForceH,SCALER_WIN eWindow)5744 E_APIXC_ReturnValue Hal_XC_IsForcePrescaling(void *pInstance, const XC_InternalStatus *pSrcInfo, MS_BOOL *pbForceV, MS_BOOL *pbForceH, SCALER_WIN eWindow)
5745 {
5746 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5747 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5748 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5749 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5750 *pbForceV = FALSE;
5751 *pbForceH = FALSE;
5752
5753 //-----------------------------------------
5754 // Vertical
5755 //-----------------------------------------
5756
5757 //FHD case. FHD has tight bandwidth in FCLK (post scaling), so force pre-scaling if disp.v size > 80% of crop.v size.
5758 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000) &&
5759 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5760 {
5761 // 80%
5762 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 8 ) )
5763 {
5764 *pbForceV = TRUE;
5765 }
5766 }
5767 else // SD, HD panel.
5768 {
5769 // 60%
5770 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 6 ) )
5771 {
5772 *pbForceV = TRUE;
5773 }
5774 }
5775
5776 //-----------------------------------------
5777 // Horizontal
5778 //-----------------------------------------
5779
5780 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000)
5781 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5782 {
5783 // 80% ( SEC using 80% for HD panel ). Increase % if meet FCLK bandwidth issue in the future.
5784 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 8 ) )
5785 {
5786 *pbForceH = TRUE;
5787 }
5788 }
5789 else // SD panel.
5790 {
5791 // 60%
5792 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 6 ) )
5793 {
5794 *pbForceH = TRUE;
5795 }
5796 }
5797
5798 return E_APIXC_RET_OK;
5799 }
5800
Hal_SC_IsHW2Dto3DPatch_Enable(void)5801 MS_BOOL Hal_SC_IsHW2Dto3DPatch_Enable(void)
5802 {
5803 MS_BOOL bRet = FALSE;
5804 if(PM_R1BYTE(REG_CHIP_REVISION, 7:0) < 1)//a1 u01 2d to 3d hw bug
5805 {
5806 bRet = TRUE;
5807 }
5808 return bRet;
5809 }
5810
MHal_SC_Get_LpllSet_Factor(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5811 MS_U32 MHal_SC_Get_LpllSet_Factor(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5812 {
5813 MS_U32 u32Factor = 0;
5814 UNUSED(u8LPLL_Type);
5815 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5816 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5817 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5818 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5819
5820 u32Factor = LPLL_LOOPGAIN/8/2;
5821
5822 if (((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
5823 || (u8LPLL_Type == E_XC_PNL_LPLL_ISP_8BIT_12P))
5824 {
5825 //printf("\033[0;31m [%s][%d] enter For 4K2K used!!! \033[0m\n", __FUNCTION__, __LINE__);
5826 u32Factor = 1;
5827 }
5828
5829 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5830 {
5831 u32Factor = 3;
5832 }
5833
5834 // for the WUXGA 1920x1200 case
5835 if((u8LPLL_Mode==E_XC_MOD_OUTPUT_DUAL)&&(u32DefaultDClk > 1500000000)
5836 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1100)
5837 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width < 2000))
5838 {
5839 u32Factor = LPLL_LOOPGAIN/8;
5840 }
5841
5842 if((u8LPLL_Type >= E_XC_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type <= E_XC_PNL_LPLL_VBY1_8BIT_8LANE))
5843 {
5844 u32Factor = 8;
5845 }
5846
5847 return u32Factor;
5848 }
5849
MHal_SC_Get_LpllSet_Div(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5850 MS_U32 MHal_SC_Get_LpllSet_Div(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5851 {
5852 MS_U32 u32Div = 5;
5853
5854 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5855 {
5856 u32Div = 2;
5857 }
5858 else if((E_XC_PNL_LPLL_VBY1_10BIT_2LANE == u8LPLL_Type)||(E_XC_PNL_LPLL_VBY1_8BIT_2LANE== u8LPLL_Type))
5859 {
5860 // 2 lane: 2/1
5861 u32Div = 4;
5862 }
5863 else if(u8LPLL_Type == E_XC_PNL_LPLL_ISP_8BIT_12P)
5864 {
5865 u32Div = 1;
5866 }
5867 return u32Div;
5868 }
5869
Hal_SC_Enable_AVMute(void * pInstance,SCALER_WIN eWindow)5870 E_APIXC_ReturnValue Hal_SC_Enable_AVMute(void *pInstance, SCALER_WIN eWindow)
5871 {
5872 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5873 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5874 if (eWindow == MAIN_WINDOW)
5875 {
5876 //HDMI V-mute detect enable
5877 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_34_L, BIT(9), BIT(9));
5878 //force IPM enable at av-mute case
5879 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, BIT(5), BIT(5));
5880 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_19_L, BIT(5), BIT(5));
5881
5882 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(13) | BIT(15), BIT(13) | BIT(15));
5883 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5884 // SC1 as subwindow case, use bank25_2E to back main window,HW bug fix after manhattan U02
5885 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, BIT(2), BIT(2));
5886 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(9) | BIT(11), BIT(9) | BIT(11));
5887 #else
5888 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(9) | BIT(11), BIT(9) | BIT(11));
5889 #endif
5890 }
5891 else
5892 {
5893 //HDMI V-mute detect enable
5894 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_34_L, BIT(9), BIT(9));
5895 //force IPM enable at av-mute case
5896 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, BIT(5), BIT(5));
5897 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_59_L, BIT(5), BIT(5));
5898
5899 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(12) | BIT(14), BIT(12) | BIT(14));
5900 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
5901 }
5902
5903 return E_APIXC_RET_OK;
5904 }
5905
Hal_XC_ReportPixelInfo(void * pInstance,MS_XC_REPORT_PIXELINFO * pstRepPixInfo)5906 MS_BOOL Hal_XC_ReportPixelInfo(void *pInstance, MS_XC_REPORT_PIXELINFO *pstRepPixInfo)
5907 {
5908 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5909 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5910 MS_BOOL bret = TRUE;
5911
5912 switch(pstRepPixInfo->enStage)
5913 {
5914 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
5915 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
5916 break;
5917 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
5918 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
5919 break;
5920 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
5921 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x0C, BMASK(3:0));
5922 break;
5923 default:
5924 bret = FALSE;
5925 break;
5926 }
5927
5928 if(bret)
5929 {
5930 // Enable
5931 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8), BIT(8));
5932
5933 if(pstRepPixInfo->bShowRepWin)
5934 {
5935 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(9), BIT(9));
5936 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, pstRepPixInfo->u16RepWinColor<<8, 0xFF00);
5937 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, BIT(0), BIT(0));
5938 }
5939
5940 // Set Report Window
5941 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L, pstRepPixInfo->u16XStart);
5942 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L, pstRepPixInfo->u16XEnd);
5943 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L, pstRepPixInfo->u16YStart);
5944 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L, pstRepPixInfo->u16YEnd);
5945
5946 MsOS_DelayTask(50); // Must wait .
5947
5948 pstRepPixInfo->u16RCrMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_64_L);
5949 pstRepPixInfo->u16RCrMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_65_L);
5950 pstRepPixInfo->u16GYMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_66_L);
5951 pstRepPixInfo->u16GYMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_67_L);
5952 pstRepPixInfo->u16BCbMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_68_L);
5953 pstRepPixInfo->u16BCbMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_69_L);
5954 pstRepPixInfo->u32RCrSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_01_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_02_L)<<16);
5955 pstRepPixInfo->u32GYSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_03_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_04_L)<<16);
5956 pstRepPixInfo->u32BCbSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_05_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_06_L)<<16);
5957
5958 if(pstRepPixInfo->bShowRepWin)
5959 {
5960 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, 0x00, BIT(0));
5961 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(9));
5962 }
5963 // Disable
5964 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(8));
5965 }
5966
5967 return bret;
5968 }
5969
Hal_SC_set_mrq_miusel(void * pInstance,MS_U8 u8MIUSel)5970 void Hal_SC_set_mrq_miusel(void *pInstance, MS_U8 u8MIUSel)
5971 {
5972 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5973 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5974
5975 // Scaler control MRQ MIU by itself
5976 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
5977 if (u8MIUSel==0)
5978 {
5979 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, 0, BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU0
5980 }
5981 else if (u8MIUSel==1)
5982 {
5983 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(8), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU1
5984 }
5985 else if (u8MIUSel==2)
5986 {
5987 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(9), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU2
5988 }
5989
5990 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x80); // MIU select (Group1 BIT15)
5991 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select
5992 }
5993
Hal_SC_set_mcdi_memoryaddress(void * pInstance,MS_PHY u32FBAddress,E_XC_MCDI_TYPE eType)5994 void Hal_SC_set_mcdi_memoryaddress(void *pInstance, MS_PHY u32FBAddress, E_XC_MCDI_TYPE eType)
5995 {
5996 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5997 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5998
5999 if (eType == E_XC_MCDI_BOTH) // MAIN
6000 {
6001 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
6002 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
6003 }
6004 else if(eType == E_XC_MCDI_SUB_BOTH) // SUB
6005 {
6006 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
6007 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
6008 }
6009 else if(eType == E_XC_MCDI_ME1)
6010 {
6011 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
6012 }
6013 else if (eType == E_XC_MCDI_ME2)
6014 {
6015 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
6016 }
6017 else if (eType == E_XC_MCDI_SUB_ME1)
6018 {
6019 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
6020 }
6021 else if (eType == E_XC_MCDI_SUB_ME2)
6022 {
6023 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
6024 }
6025 }
6026
Hal_SC_set_mcdi_write_limit(void * pInstance,MS_BOOL bEn,MS_PHY u32LimitAddress,E_XC_MCDI_TYPE eType)6027 void Hal_SC_set_mcdi_write_limit(void *pInstance, MS_BOOL bEn, MS_PHY u32LimitAddress, E_XC_MCDI_TYPE eType)
6028 {
6029 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6030 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6031
6032 u32LimitAddress = u32LimitAddress / MCDI_BYTE_PER_WORD -1;
6033
6034 if(eType == E_XC_MCDI_BOTH)
6035 {
6036 // Main/Sub shares the same enable bit of ME1
6037 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6038 // Bit 0 ~ 26
6039 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
6040 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
6041
6042 // Main/Sub shares the same enable bit of ME2
6043 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6044 // Bit 0 ~ 26
6045 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
6046 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
6047 }
6048 else if(eType==E_XC_MCDI_SUB_BOTH)
6049 {
6050 // Main/Sub shares the same enable bit of ME1
6051 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6052 // Bit 0 ~ 26
6053 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
6054 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
6055
6056 // Main/Sub shares the same enable bit of ME2
6057 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6058 // Bit 0 ~ 26
6059 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
6060 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
6061 }
6062 else if(eType == E_XC_MCDI_ME1)
6063 {
6064 // Main/Sub shares the same enable bit
6065 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6066 // Bit 0 ~ 26
6067 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
6068 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
6069 }
6070 else if (eType == E_XC_MCDI_ME2)
6071 {
6072 // Main/Sub shares the same enable bit
6073 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6074 // Bit 0 ~ 26
6075 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
6076 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
6077 }
6078 else if (eType == E_XC_MCDI_SUB_ME1)
6079 {
6080 // Main/Sub shares the same enable bit
6081 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6082 // Bit 0 ~ 26
6083 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
6084 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
6085 }
6086 else if (eType == E_XC_MCDI_SUB_ME2)
6087 {
6088 // Main/Sub shares the same enable bit
6089 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6090 // Bit 0 ~ 26
6091 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
6092 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
6093 }
6094 }
Hal_SC_enable_mcdi(void * pInstance,MS_BOOL bEn,E_XC_MCDI_TYPE eType)6095 void Hal_SC_enable_mcdi(void *pInstance, MS_BOOL bEn, E_XC_MCDI_TYPE eType)
6096 {
6097 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6098 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6099
6100 #define ME1_CTRL_BIT ( BIT(1) )
6101 #define ME2_CTRL_BIT ( BIT(2) )
6102 MS_U16 u16Value = 0;
6103 MS_U16 u16Mask = 0;
6104 switch (eType)
6105 {
6106 case E_XC_MCDI_ME1:
6107 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
6108 u16Mask = ME1_CTRL_BIT;
6109 break;
6110 case E_XC_MCDI_ME2:
6111 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
6112 u16Mask = ME2_CTRL_BIT;
6113 break;
6114 case E_XC_MCDI_BOTH:
6115 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
6116 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
6117 u16Mask = ME1_CTRL_BIT | ME2_CTRL_BIT;
6118 break;
6119 case E_XC_MCDI_SUB_ME1:
6120 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
6121 u16Mask = ME1_CTRL_BIT << 3;
6122 break;
6123 case E_XC_MCDI_SUB_ME2:
6124 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
6125 u16Mask = ME2_CTRL_BIT << 3;
6126 break;
6127 case E_XC_MCDI_SUB_BOTH:
6128 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
6129 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
6130 u16Mask = (ME1_CTRL_BIT | ME2_CTRL_BIT)<<3;
6131 break;
6132 default:
6133 u16Value = 0;
6134 break;
6135 }
6136 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L, u16Value, u16Mask);
6137 if (bEn)
6138 {
6139 // Turn on MIU access arbitor
6140 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, 0x00 , BIT(6) );
6141 }
6142 else
6143 {
6144 MS_U16 u16MCDiCtrl_Main = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & ( ME1_CTRL_BIT | ME2_CTRL_BIT ) ;
6145 MS_U16 u16MCDiCtrl_Sub = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & (( ME1_CTRL_BIT | ME2_CTRL_BIT )<<3) ;
6146 MS_U16 u16MCDiCtrl = u16MCDiCtrl_Main | u16MCDiCtrl_Sub;
6147 // Current ME1/2 is turned off
6148 if ( u16MCDiCtrl == ( ( ME1_CTRL_BIT | ME2_CTRL_BIT) // Main_Window
6149 | ((ME1_CTRL_BIT | ME2_CTRL_BIT)<<3))) // Sub_Window
6150 {
6151 // Turn off arbitor only when all MCDi function is off.
6152 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, BIT(6) , BIT(6) );
6153 }
6154 }
6155 }
6156
6157 /// bandwidth saving Mode
Hal_SC_set_bws_mode(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6158 void Hal_SC_set_bws_mode(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6159 {
6160 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6161 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6162
6163 if(eWindow == MAIN_WINDOW)
6164 {
6165 //ipm Main
6166 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(0)), BIT(0));
6167 }
6168 else
6169 {
6170 //ipm Sub
6171 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(1)), BIT(1));
6172 }
6173 }
6174
Hal_SC_get_bws_mode(void * pInstance,SCALER_WIN eWindow)6175 MS_BOOL Hal_SC_get_bws_mode(void *pInstance, SCALER_WIN eWindow)
6176 {
6177 MS_BOOL bEnable = FALSE;
6178 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6179 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6180
6181 if(eWindow == MAIN_WINDOW)
6182 {
6183 //ipm Main
6184 bEnable = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, BIT(0)) != 0);
6185 }
6186 else
6187 {
6188 //ipm Sub
6189 bEnable = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, BIT(1)) != 0);
6190 }
6191 return bEnable;
6192 }
6193
Hal_SC_sw_lcnt_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6194 void Hal_SC_sw_lcnt_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6195 {
6196 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6197 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6198
6199 if(eWindow == MAIN_WINDOW)
6200 {
6201 //ipm Main
6202 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(0):0x00), BIT(0));
6203 }
6204 else
6205 {
6206 //ipm Sub
6207 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(0):0x00), BIT(0));
6208 }
6209 }
6210
Hal_SC_set_sw_lcnt(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6211 void Hal_SC_set_sw_lcnt(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6212 {
6213 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6214 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6215
6216 if(eWindow == MAIN_WINDOW)
6217 {
6218 //ipm Main
6219 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(1):0x00), BIT(1));
6220 }
6221 else
6222 {
6223 //ipm Sub
6224 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(1):0x00), BIT(1));
6225 }
6226 }
6227
Hal_SC_set_ipmw_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6228 void Hal_SC_set_ipmw_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6229 {
6230 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6231 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6232
6233 if(eWindow == MAIN_WINDOW)
6234 {
6235 //ipm Main
6236 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(4):0x00), BIT(4));
6237 }
6238 else
6239 {
6240 //ipm Sub
6241 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(4):0x00), BIT(4));
6242 }
6243 }
6244
Hal_SC_set_ipmr_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6245 void Hal_SC_set_ipmr_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6246 {
6247 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6248 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6249
6250 if(eWindow == MAIN_WINDOW)
6251 {
6252 //ipm Main
6253 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(12):0x00), BIT(12));
6254 }
6255 else
6256 {
6257 //ipm Sub
6258 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(12):0x00), BIT(12));
6259 }
6260 }
6261
Hal_SC_set_opm_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6262 void Hal_SC_set_opm_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6263 {
6264 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6265 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6266 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6267 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6268
6269 if(eWindow == MAIN_WINDOW)
6270 {
6271 //opm Main
6272 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(5):0x00), BIT(5));
6273 }
6274 else
6275 {
6276 //opm Sub
6277 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(4):0x00), BIT(4));
6278 }
6279
6280 }
6281
MHal_XC_Calc_IGainPGain(void * pInstance,MS_U8 * u8GainI,MS_U8 * u8GainP,MS_U32 u32XTAL_Clock,MS_U8 u8LGain,MS_U8 u8Vco,MS_U16 u16HTotal,MS_U16 u16VTotal,MS_U8 u8FRC_Out)6282 void MHal_XC_Calc_IGainPGain(void *pInstance, MS_U8 *u8GainI, MS_U8 *u8GainP, MS_U32 u32XTAL_Clock, MS_U8 u8LGain, MS_U8 u8Vco, MS_U16 u16HTotal, MS_U16 u16VTotal, MS_U8 u8FRC_Out)
6283 {
6284 MS_U32 u32Factor, u32Temp;
6285 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6286 UtopiaResourceGetPrivate(g_pXCResource[E_XC_POOL_ID_INTERNAL_VARIABLE],(void**)(&pXCResourcePrivate));
6287 u32Temp = (MS_U32)(u16VTotal*u16HTotal*u8FRC_Out);
6288 u32XTAL_Clock*=2;
6289 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain)/((MS_U32)(u32Temp*u8Vco/2*8));
6290
6291 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MM=%ld,u8LGain1=%d,Htt=%d,Vtt=%d,Ovs=%d,Vco=%d,i_gain=%td,REGIg=%d,u32XTAL_Clock=%tu\n",
6292 (LVDS_MPLL_CLOCK_MHZ*1000000UL/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock),u8LGain,
6293 u16HTotal,u16VTotal,u8FRC_Out,u8Vco/2,(ptrdiff_t)u32Factor,MHal_SC_cal_usedgain_to_reggain(u32Factor),(ptrdiff_t)u32XTAL_Clock);
6294
6295 *u8GainI = MHal_SC_cal_usedgain_to_reggain(u32Factor);
6296 /// for high accurate log value
6297 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain*10)/((MS_U32)(u32Temp*u8Vco/2*8));
6298
6299 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "new i_gain=%td\n", (ptrdiff_t)u32Factor);
6300
6301 if(u32Factor <= 1)
6302 *u8GainI=2;
6303 else if(u32Factor <= 3)
6304 *u8GainI=3;
6305 else if(u32Factor <= 7)
6306 *u8GainI=4;
6307
6308 *u8GainP = *u8GainI+1;
6309
6310 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "==>LG1=%d,iGain=%td,I=%d,P=%d\n",u8LGain,(ptrdiff_t)u32Factor,*u8GainI,*u8GainP);
6311 }
6312
MHAL_SC_set_osdc_tgen_hsync_start(void * pInstance,MS_U16 u16Value)6313 void MHAL_SC_set_osdc_tgen_hsync_start(void *pInstance, MS_U16 u16Value)
6314 {
6315 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6316 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6317
6318 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, u16Value, 0x1FFF);
6319 }
6320
MHAL_SC_set_osdc_tgen_hsync_end(void * pInstance,MS_U16 u16Value)6321 void MHAL_SC_set_osdc_tgen_hsync_end(void *pInstance, MS_U16 u16Value)
6322 {
6323 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6324 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6325
6326 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, u16Value, 0x1FFF);
6327 }
6328
MHAL_SC_set_osdc_tgen_hframe_de_start(void * pInstance,MS_U16 u16Value)6329 void MHAL_SC_set_osdc_tgen_hframe_de_start(void *pInstance, MS_U16 u16Value)
6330 {
6331 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6332 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6333
6334 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, u16Value, 0x1FFF);
6335 }
6336
MHAL_SC_set_osdc_tgen_hframe_de_end(void * pInstance,MS_U16 u16Value)6337 void MHAL_SC_set_osdc_tgen_hframe_de_end(void *pInstance, MS_U16 u16Value)
6338 {
6339 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6340 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6341
6342 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, u16Value, 0x1FFF);
6343 }
6344
MHAL_SC_set_osdc_tgen_htotal(void * pInstance,MS_U16 u16Value)6345 void MHAL_SC_set_osdc_tgen_htotal(void *pInstance, MS_U16 u16Value)
6346 {
6347 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6348 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6349
6350 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, u16Value, 0x1FFF);
6351 }
6352
MHAL_SC_set_osdc_tgen_vtotal(void * pInstance,MS_U16 u16Value)6353 void MHAL_SC_set_osdc_tgen_vtotal(void *pInstance, MS_U16 u16Value)
6354 {
6355 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6356 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6357
6358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, u16Value, 0x1FFF);
6359 }
6360
MHAL_SC_set_osdc_tgen_vframe_de_start(void * pInstance,MS_U16 u16Value)6361 void MHAL_SC_set_osdc_tgen_vframe_de_start(void *pInstance, MS_U16 u16Value)
6362 {
6363 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6364 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6365
6366 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, u16Value, 0x1FFF);
6367 }
6368
MHAL_SC_set_osdc_tgen_vframe_de_end(void * pInstance,MS_U16 u16Value)6369 void MHAL_SC_set_osdc_tgen_vframe_de_end(void *pInstance, MS_U16 u16Value)
6370 {
6371 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6372 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6373
6374 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, u16Value, 0x1FFF);
6375 }
6376
MHAL_SC_set_osdc_tgen_vsync_start(void * pInstance,MS_U16 u16Value)6377 void MHAL_SC_set_osdc_tgen_vsync_start(void *pInstance, MS_U16 u16Value)
6378 {
6379 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6380 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6381
6382 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, u16Value, 0x1FFF);
6383 }
6384
MHAL_SC_set_osdc_tgen_vsync_end(void * pInstance,MS_U16 u16Value)6385 void MHAL_SC_set_osdc_tgen_vsync_end(void *pInstance, MS_U16 u16Value)
6386 {
6387 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6388 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6389
6390 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, u16Value, 0x1FFF);
6391 }
6392
MHAL_SC_set_osdc_tgen_reset_enable(void * pInstance,MS_BOOL bEnable)6393 void MHAL_SC_set_osdc_tgen_reset_enable(void *pInstance, MS_BOOL bEnable)
6394 {
6395 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6396 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6397
6398 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_20_L, bEnable?BIT(0):0x00, BIT(0));
6399 }
6400
MHAL_SC_set_osdc_swreset_enable(void * pInstance,MS_BOOL bEnable)6401 void MHAL_SC_set_osdc_swreset_enable(void *pInstance, MS_BOOL bEnable)
6402 {
6403 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6404 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6405
6406 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_21_L, bEnable?BIT(0):0x00, BIT(0));
6407 }
6408
MHAL_SC_set_osdc_mixer_bypass_enable(void * pInstance,MS_BOOL bEnable)6409 void MHAL_SC_set_osdc_mixer_bypass_enable(void *pInstance, MS_BOOL bEnable)
6410 {
6411 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6412 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6413
6414 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(0):0x00, BIT(0));
6415 }
6416
MHAL_SC_set_osdc_mixer_inv_alpha_enable(void * pInstance,MS_BOOL bEnable)6417 void MHAL_SC_set_osdc_mixer_inv_alpha_enable(void *pInstance, MS_BOOL bEnable)
6418 {
6419 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6420 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6421
6422 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(1):0x00, BIT(1));
6423 }
6424 //1:hs_out = hs&vfde
MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void * pInstance,MS_BOOL bEnable)6425 void MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
6426 {
6427 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6428 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6429
6430 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(2):0x00, BIT(2));
6431 }
6432 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void * pInstance,MS_BOOL bEnable)6433 void MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
6434 {
6435 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6436 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6437
6438 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(3):0x00, BIT(3));
6439 }
6440
MHAL_SC_set_osdc_clk_mux(void * pInstance,MS_U8 u8Clk_Mux)6441 void MHAL_SC_set_osdc_clk_mux(void *pInstance, MS_U8 u8Clk_Mux)
6442 {
6443 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK);
6444 }
6445
MHAL_SC_enable_osdc(void * pInstance,MS_BOOL bEnable)6446 void MHAL_SC_enable_osdc(void *pInstance, MS_BOOL bEnable)
6447 {
6448 // Enable OSDC LPLL
6449 if(bEnable)
6450 {
6451 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert
6452 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock
6453 }
6454 else
6455 {
6456 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert
6457 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock
6458 }
6459 }
6460
MHAL_SC_get_osdc_tgen_hsync_start(void * pInstance)6461 MS_U16 MHAL_SC_get_osdc_tgen_hsync_start(void *pInstance)
6462 {
6463 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6464 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6465
6466 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, 0x1FFF);
6467 }
6468
MHAL_SC_get_osdc_tgen_hsync_end(void * pInstance)6469 MS_U16 MHAL_SC_get_osdc_tgen_hsync_end(void *pInstance)
6470 {
6471 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6472 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6473
6474 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, 0x1FFF);
6475 }
6476
MHAL_SC_get_osdc_tgen_hframe_de_start(void * pInstance)6477 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_start(void *pInstance)
6478 {
6479 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6480 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6481
6482 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, 0x1FFF);
6483 }
6484
MHAL_SC_get_osdc_tgen_hframe_de_end(void * pInstance)6485 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_end(void *pInstance)
6486 {
6487 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6488 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6489
6490 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, 0x1FFF);
6491 }
6492
MHAL_SC_get_osdc_tgen_htotal(void * pInstance)6493 MS_U16 MHAL_SC_get_osdc_tgen_htotal(void *pInstance)
6494 {
6495 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6496 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6497
6498 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, 0x1FFF);
6499 }
6500
MHAL_SC_get_osdc_tgen_vtotal(void * pInstance)6501 MS_U16 MHAL_SC_get_osdc_tgen_vtotal(void *pInstance)
6502 {
6503 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6504 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6505
6506 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, 0x1FFF);
6507 }
6508
MHAL_SC_get_osdc_tgen_vframe_de_start(void * pInstance)6509 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_start(void *pInstance)
6510 {
6511 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6512 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6513
6514 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, 0x1FFF);
6515 }
6516
MHAL_SC_get_osdc_tgen_vframe_de_end(void * pInstance)6517 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_end(void *pInstance)
6518 {
6519 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6520 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6521
6522 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, 0x1FFF);
6523 }
6524
MHAL_SC_get_osdc_tgen_vsync_start(void * pInstance)6525 MS_U16 MHAL_SC_get_osdc_tgen_vsync_start(void *pInstance)
6526 {
6527 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6528 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6529
6530 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, 0x1FFF);
6531 }
6532
MHAL_SC_get_osdc_tgen_vsync_end(void * pInstance)6533 MS_U16 MHAL_SC_get_osdc_tgen_vsync_end(void *pInstance)
6534 {
6535 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6536 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6537
6538 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, 0x1FFF);
6539 }
6540
MHAL_SC_get_osdc_mixer_bypass_status(void * pInstance)6541 MS_BOOL MHAL_SC_get_osdc_mixer_bypass_status(void *pInstance)
6542 {
6543 MS_BOOL bEnable = DISABLE;
6544 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6545 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6546
6547 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(0)));
6548 return bEnable;
6549 }
6550
MHAL_SC_get_osdc_mixer_inv_alpha_status(void * pInstance)6551 MS_BOOL MHAL_SC_get_osdc_mixer_inv_alpha_status(void *pInstance)
6552 {
6553 MS_BOOL bEnable = DISABLE;
6554 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6555 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6556
6557 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(1))>>1);
6558 return bEnable;
6559 }
6560 //1:hs_out = hs&vfde
MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void * pInstance)6561 MS_BOOL MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void *pInstance)
6562 {
6563 MS_BOOL bEnable = DISABLE;
6564 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6565 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6566
6567 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(2))>>2);
6568 return bEnable;
6569 }
6570 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void * pInstance)6571 MS_BOOL MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void *pInstance)
6572 {
6573 MS_BOOL bEnable = DISABLE;
6574 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6575 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6576
6577 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(3))>>3);
6578 return bEnable;
6579 }
6580
MHAL_SC_get_osdc_onoff_status(void * pInstance)6581 MS_BOOL MHAL_SC_get_osdc_onoff_status(void *pInstance)
6582 {
6583 // Enable OSDC LPLL
6584 MS_BOOL bEnable = DISABLE;
6585 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED));
6586 return bEnable;
6587 }
6588
MHal_XC_SetForceCurrentReadBank(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6589 void MHal_XC_SetForceCurrentReadBank(void *pInstance,MS_BOOL bEnable, SCALER_WIN eWindow)
6590 {
6591 MS_U16 u16Bank = 0;
6592 MS_U8 u8Bank = 0;
6593 MS_U16 u16temp = 0;
6594 static MS_U16 u16RegForceMryValue = 0;
6595
6596 u16temp = SC_R2BYTEMSK(0, REG_SC_BK22_20_L, SC_MADI_DIPF);
6597 if(u16temp != SC_MADI_DIPF)
6598 {
6599 u16RegForceMryValue = u16temp;
6600 }
6601 //color team suggest setting
6602 //film mode setting
6603 if(bEnable)
6604 {
6605 SC_W2BYTEMSK(0,REG_SC_BK22_20_L, SC_MADI_DIPF, SC_MADI_DIPF);
6606 }
6607 else
6608 {
6609 SC_W2BYTEMSK(0,REG_SC_BK22_20_L, u16RegForceMryValue, SC_MADI_DIPF);
6610 }
6611
6612 if(bEnable)
6613 {
6614 if (eWindow == MAIN_WINDOW)
6615 {
6616 u16Bank = SC_R2BYTEMSK(0, REG_SC_BK12_3A_L, BIT(7)|BIT(6)|BIT(5)|BIT(4));
6617 }
6618 #if 0 // need to check with sub window
6619 else
6620 {
6621 u16Bank = SC_R2BYTEMSK(0, REG_SC_BK12_7A_L, BIT(7)|BIT(6)|BIT(5)|BIT(4));
6622 }
6623 #endif
6624 }
6625
6626 u8Bank = (MS_U8)u16Bank >> 4;
6627
6628 MHal_XC_SetForceReadBank(pInstance, bEnable, u8Bank, eWindow);
6629 }
6630
MHal_XC_SetForceReadBank(void * pInstance,MS_BOOL bEnable,MS_U8 u8Bank,SCALER_WIN eWindow)6631 void MHal_XC_SetForceReadBank(void *pInstance, MS_BOOL bEnable, MS_U8 u8Bank, SCALER_WIN eWindow)
6632 {
6633 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6634 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6635 if (eWindow == MAIN_WINDOW)
6636 {
6637 if (bEnable)
6638 {
6639 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(11), BIT(11));
6640 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
6641 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
6642 }
6643 else
6644 {
6645 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(11));
6646 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(10)|BIT(9)|BIT(8));
6647 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, 0, BIT(14));
6648 }
6649 }
6650 else
6651 {
6652 if (bEnable)
6653 {
6654 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(11), BIT(11));
6655 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
6656 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
6657 }
6658 else
6659 {
6660 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(11));
6661 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(10)|BIT(9)|BIT(8));
6662 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, 0, BIT(14));
6663 }
6664 }
6665 }
6666
MHal_XC_SetDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)6667 MS_BOOL MHal_XC_SetDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
6668 {
6669 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6670 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6671 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6672 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6673 pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] = u32DNRBaseAddr;
6674 return TRUE;
6675 }
6676
MHal_XC_GetDNRBufAddress(void * pInstance,SCALER_WIN eWindow)6677 MS_PHY MHal_XC_GetDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
6678 {
6679 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6680 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6681 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6682 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6683 return pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] ;
6684 }
6685
MHal_XC_SetDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6686 MS_BOOL MHal_XC_SetDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6687 {
6688 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6689 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6690 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6691 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6692 pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] = u32DNRBufSize;
6693 return TRUE;
6694 }
6695
MHal_XC_GetDNRBufSize(void * pInstance,SCALER_WIN eWindow)6696 MS_PHY MHal_XC_GetDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6697 {
6698 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6699 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6700 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6701 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6702 return pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] ;
6703 }
6704
MHal_XC_SetFRCMBufAddress(void * pInstance,MS_PHY u32BaseAddr,SCALER_WIN eWindow)6705 MS_BOOL MHal_XC_SetFRCMBufAddress(void *pInstance, MS_PHY u32BaseAddr, SCALER_WIN eWindow)
6706 {
6707 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6708 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6709 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6710 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6711 pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] = u32BaseAddr;
6712 return TRUE;
6713 }
6714
MHal_XC_GetFRCMBufAddress(void * pInstance,SCALER_WIN eWindow)6715 MS_PHY MHal_XC_GetFRCMBufAddress(void *pInstance, SCALER_WIN eWindow)
6716 {
6717 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6718 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6719 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6720 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6721 return pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] ;
6722 }
6723
MHal_XC_SetFRCMBufSize(void * pInstance,MS_PHY u32BufSize,SCALER_WIN eWindow)6724 MS_BOOL MHal_XC_SetFRCMBufSize(void *pInstance, MS_PHY u32BufSize, SCALER_WIN eWindow)
6725 {
6726 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6727 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6728 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6729 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6730 pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] = u32BufSize;
6731 return TRUE;
6732 }
6733
MHal_XC_GetFRCMBufSize(void * pInstance,SCALER_WIN eWindow)6734 MS_PHY MHal_XC_GetFRCMBufSize(void *pInstance, SCALER_WIN eWindow)
6735 {
6736 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6737 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6738 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6739 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6740 return pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] ;
6741 }
6742
MHal_XC_SetDualDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)6743 MS_BOOL MHal_XC_SetDualDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
6744 {
6745 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6746 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6747 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6748 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6749 pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow] = u32DNRBaseAddr;
6750 return TRUE;
6751 }
6752
MHal_XC_GetDualDNRBufAddress(void * pInstance,SCALER_WIN eWindow)6753 MS_PHY MHal_XC_GetDualDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
6754 {
6755 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6756 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6757 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6758 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6759 return pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow];
6760 }
6761
MHal_XC_SetDualDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6762 MS_BOOL MHal_XC_SetDualDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6763 {
6764 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6765 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6766 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6767 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6768 pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] = u32DNRBufSize;
6769 return TRUE;
6770 }
6771
MHal_XC_GetDualDNRBufSize(void * pInstance,SCALER_WIN eWindow)6772 MS_PHY MHal_XC_GetDualDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6773 {
6774 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6775 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6776 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6777 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6778 return pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] ;
6779 }
6780
MHal_XC_Init_Patch(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6781 MS_BOOL MHal_XC_Init_Patch(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6782 {
6783 if (eWindow >= MAX_WINDOW)
6784 {
6785 printf("[%s,%5d] maximum window exceeded",__FUNCTION__,__LINE__);
6786 return FALSE;
6787 }
6788
6789 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6790 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6791 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6792 //FIX ME:review manhattan need it?
6793 if (psXCInstPri->u32DeviceID >= 1)
6794 {
6795 // by HW RD's request, for sub video BW issue, adjust R/W line buffer length
6796 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_20_L, 0x1E1E);
6797 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_21_L, 0x1E1E);
6798 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_22_L, 0x1E1E);
6799 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_23_L, 0x1010);
6800 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_24_L, 0x20, 0xFF);
6801 return FALSE;
6802 }
6803 #endif
6804
6805 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_6F_L, 0x20, 0x3F); // by HW RD's request, for BB section offset issue
6806
6807 // by HW RD's request, for main video BW issue, adjust R/W line buffer length
6808 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_20_L, 0x1818);
6809 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_21_L, 0x1818);
6810 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_22_L, 0x1818);
6811
6812 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6813 #ifdef SUPPORT_DUAL_MIU
6814 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6815 #endif
6816
6817 // SW patch for Monaco
6818 // by HW RD's request, to fix HDMI 1080i repeat garbage at left side
6819 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_37_L, 0x20); // bypass main line buffer length setting
6820 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK11_37_L, 0x20); // bypass sub line buffer length setting
6821
6822 // ECO item for Monaco: hvsp PIP B section last flag error
6823 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_5F_L, BIT(14), BIT(14));
6824
6825 // ECO item for Monaco: ip2ve 4K path Vsync need inverse
6826 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, BIT(14), BIT(14));
6827 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_7F_L, BIT(14), BIT(14));
6828
6829 // SW patch for muji : 4k2k 3D LA out show garbage on the top, issue with BW
6830 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, 0x0000, BIT(0));//disable SCM sub OP
6831
6832 // BK00_03[13] conflict with compression mode (patch for HW issue)
6833 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_03_L, 0x0000, 0x2000);
6834
6835 if(MDrv_ReadByte(REG_CHIP_REVISION) < 1)//Monaco U02 fix .
6836 {
6837 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_53_L, 0x00, BIT(10));
6838 }
6839
6840 //U03 compatible setting
6841 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_66_L, BIT(13), BIT(13));
6842
6843 ///Patch here ////
6844 #if (FRC_INSIDE)
6845 MHal_FRC_interrupt_mask(pInstance, 0xFF);
6846
6847 //enable fsc clk
6848 MDrv_WriteByteMask( REG_FSC_BK20_05, 0x10, 0x10); // reg_ckg_ficlk
6849 #endif
6850
6851 // SW patch for Eisntein
6852 // With HW Auto no signal case, sub video source change would causes OP1 broken, looks like main video broken
6853 Hal_SC_ip_enable_turnoff_OP1_for_AutoNoSignal(pInstance, DISABLE);
6854
6855 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_61_L, 0x01, 0x03); // for HDMI 2.0, always receive 444 format
6856 SC_W2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK01_63_L, 0x01, 0x01); // for HDMI odd Htt support
6857
6858 //enable 6 tap mode for macan
6859 SC_W2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK20_23_L, BIT(10), BIT(10)); //
6860 //HW default value is wrong, need reset to 0x0404 under 6 tap mode
6861 SC_W2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK20_29_L, 0x0404, 0x1F1F); //
6862 return TRUE;
6863 }
MHal_XC_IsPNLYUVOutput(void * pInstance)6864 MS_BOOL MHal_XC_IsPNLYUVOutput(void *pInstance)
6865 {
6866 MS_BOOL bIsPNLYUVOutput = TRUE;
6867 #if 0//below is logic from TV, need box RD's confirm, disable it temporary
6868 MS_BOOL bIsY2REnable = FALSE, bIsR2YEnable = FALSE;
6869 SCALER_WIN eWindow = MAIN_WINDOW;
6870 MS_U16 u16Temp = 0;
6871 //Get CSC state before OP2
6872 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled || gSrcInfo[MAIN_WINDOW].bBluescreenEnabled)
6873 {
6874 //Main is mute, so check sub
6875 if(Hal_SC_Is_subwindow_enable())
6876 {
6877 if(!(gSrcInfo[SUB_WINDOW].bBlackscreenEnabled || gSrcInfo[SUB_WINDOW].bBluescreenEnabled))
6878 {
6879 eWindow = SUB_WINDOW;
6880 }
6881 }
6882 }
6883
6884 if(eWindow == MAIN_WINDOW)
6885 {
6886 u16Temp = SC_R2BYTE(REG_SC_BK10_2F_L);
6887 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6888 {
6889 bIsY2REnable = TRUE;
6890 }
6891 }
6892 else
6893 {
6894 u16Temp = SC_R2BYTE(REG_SC_BK0F_26_L);
6895 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6896 {
6897 bIsY2REnable = TRUE;
6898 }
6899 }
6900
6901 if(bIsY2REnable)
6902 {
6903 bIsPNLYUVOutput = FALSE;
6904 }
6905 else
6906 {
6907 //OP Y2R disable, so check op input
6908 if(eWindow == MAIN_WINDOW)
6909 {
6910 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK02_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_06_L, BIT(0)));
6911
6912 }
6913 else
6914 {
6915 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK04_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_76_L, BIT(0)));
6916 }
6917
6918 if(bIsR2YEnable)
6919 {
6920 //Y2R enable
6921 bIsPNLYUVOutput = TRUE;
6922 }
6923 else
6924 {
6925 //All Csc is off, so check input
6926 //VGA/DVI/rgb HDMI is rgb input
6927 if( IsSrcTypeVga(gSrcInfo[eWindow].enInputSourceType) //VGA
6928 ||IsSrcTypeDVI(gSrcInfo[eWindow].enInputSourceType) //DVI
6929 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6930 &&(g_HdmiPollingStatus.bIsHDMIMode == TRUE)
6931 &&(g_HdmiPollingStatus.u8ColorFormat == MS_HDMI_COLOR_RGB))//HDMI RGB
6932 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6933 &&(g_HdmiPollingStatus.bIsHDMIMode == FALSE)) //HDMI_DVI
6934 )
6935 {
6936 bIsPNLYUVOutput = FALSE;
6937 }
6938 else
6939 {
6940 bIsPNLYUVOutput = TRUE;
6941 }
6942 }
6943 }
6944 #endif
6945 return bIsPNLYUVOutput;
6946 }
6947
Hal_SC_Init(void * pInstance)6948 MS_BOOL Hal_SC_Init(void *pInstance)
6949 {
6950 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6951 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6952 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6953 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6954
6955 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
6956 MHal_FRC_Composer_User_Mode_Enable(pInstance, ENABLE);
6957 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_VIP, FALSE);
6958 MHal_FRC_Set_Pipe_Delay_Mode(pInstance, E_FRC_PIPE_DELAY_MODE_USER);
6959 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FRC, FRC_PIPE_DELAY_VCNT_FRC);
6960 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_FDE); // make FSC use FDE range from VIP to do SR
6961
6962 // For FSC/FRC clk init
6963 MHal_CLKGEN_FRC_Init(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode);
6964
6965 // For STGEN init
6966 MHal_FRC_TGEN_Init(pInstance);
6967
6968 // For STGEN init setting
6969 MST_PANEL_INFO_t stFRCPanelInfo;
6970 if (FALSE == pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
6971 {
6972 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth;
6973 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch;
6974 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth;
6975 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch;
6976 }
6977
6978 MHal_FRC_PNLInfo_Transform(pInstance, &pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo,&pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc, &stFRCPanelInfo);
6979 MDrv_FRC_Tx_SetTgen(pInstance, &stFRCPanelInfo);
6980
6981 MHal_FRC_ByPass_Enable(pInstance, TRUE); // default disable FRC
6982 #endif
6983
6984 #if 0
6985 MHal_XC_FRCR2_IP_Patch(pInstance, MAIN_WINDOW);
6986 MHal_XC_FRCR2_OP_Patch(pInstance, MAIN_WINDOW);
6987 #endif
6988
6989 //For mantis issue 1184035,Repeat last point instead of black point at IPM
6990 //to avoid wrong scaling result at the border
6991 SC_W2BYTEMSK(0, REG_SC_BK02_68_L, BIT(11) , BIT(11));
6992
6993 return TRUE;
6994 }
6995
Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)6996 MS_U32 Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)
6997 {
6998 MS_U32 ret_U32 = 0 ;
6999 if(deviceIdx == 0 )
7000 {
7001 ret_U32 = MAX_XC_DEVICE0_OFFSET;
7002 }
7003 else if(deviceIdx == 1)
7004 {
7005 ret_U32 = MAX_XC_DEVICE1_OFFSET;
7006 }
7007 return ret_U32;
7008 }
7009
HAL_SC_Set_LB_MergeAddress(void * pInstance)7010 void HAL_SC_Set_LB_MergeAddress(void *pInstance)
7011 {
7012 return;
7013 }
7014
Hal_SC_set_edclk(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)7015 void Hal_SC_set_edclk(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
7016 {
7017 if(eWindow==MAIN_WINDOW)
7018 {
7019 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED);
7020 if(bEnable)
7021 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK);
7022 }
7023 else if(eWindow==SUB_WINDOW)
7024 {
7025 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, (bEnable? 0x00 : CKG_EDCLK_F1_GATED), CKG_EDCLK_F1_GATED);
7026 if(bEnable)
7027 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, u8Clk_Mux, CKG_EDCLK_F1_MASK);
7028 }
7029 }
7030
Hal_SC_set_ficlk2(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)7031 void Hal_SC_set_ficlk2(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
7032 {
7033 if(eWindow==MAIN_WINDOW)
7034 {
7035 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED);
7036 if(bEnable)
7037 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK);
7038 }
7039 else if(eWindow==SUB_WINDOW)
7040 {
7041 printf("[%s,%5d] ficlk2_f2 not support sub!",__FUNCTION__,__LINE__);// no ficlk2_f1 for sub window
7042 }
7043 }
7044
Hal_SC_set_fmclk(void * pInstance,MS_BOOL bEnable)7045 void Hal_SC_set_fmclk(void *pInstance, MS_BOOL bEnable)
7046 {
7047 if(bEnable == TRUE)
7048 {
7049 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK);
7050 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED);
7051 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT);
7052 }
7053 else
7054 {
7055 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock
7056 }
7057 }
7058
HAL_SC_EnableLegacyMode(void * pInstance,MS_BOOL bEnable)7059 void HAL_SC_EnableLegacyMode(void *pInstance, MS_BOOL bEnable)
7060 {
7061 #if (HW_DESIGN_4K2K_VER == 4)
7062 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7063 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7064
7065 if (psXCInstPri->u32DeviceID == 0)
7066 {
7067 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_01_L, (bEnable<<0), BIT(0));
7068 }
7069 else
7070 {
7071 // do nothing, because there is only legacy mode in SC2, we don't have to do any switch
7072 }
7073 #endif
7074 }
7075
MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum,void * pParam)7076 static void MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum, void * pParam)
7077 {
7078 void *pInstance = pu32XCInst_private;
7079 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7080 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7081 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7082 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7083
7084 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled==FALSE)
7085 {
7086 //Check timing 2s
7087 if(((MsOS_GetSystemTime()- u32DTVPatchTimer)>2000))
7088 {
7089 u32DTVPatchTimer = MsOS_GetSystemTime();
7090 u16FDMaskCount=0;
7091 }
7092
7093 //Check FD mask
7094 if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0))
7095 {
7096 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0);
7097 u16FDMaskCount++;
7098 }
7099
7100 if(u16FDMaskCount>6)
7101 {
7102 if (Mhal_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
7103 {
7104 //UC_CTL off
7105 _MLOAD_ENTRY(pInstance);
7106 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK17_01_L, 0 ,BIT(0));
7107 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK57_23_L, 0 ,0x40);
7108 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0);
7109 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_07_L, 0 ,BIT(0));
7110 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_20_L, 0 ,BIT(7));
7111 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_21_L, 0 ,BIT(15));
7112 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_78_L, 0 ,0xC000);
7113 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
7114 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_20_L, 0 ,BIT(0));
7115 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_12_L, 0 ,BIT(0));
7116 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_07_L, 0 ,BIT(0));
7117 Mhal_XC_MLoad_Fire(pInstance, TRUE);
7118 _MLOAD_RETURN(pInstance);
7119 }
7120 else
7121 {
7122 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_01_L, 0 ,BIT(0));
7123 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, 0 ,0x40);
7124 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0);
7125 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0 ,BIT(0));
7126 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_20_L, 0 ,BIT(7));
7127 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_21_L, 0 ,BIT(15));
7128 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_78_L, 0 ,0xC000);
7129 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
7130 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_20_L, 0 ,BIT(0));
7131 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_12_L, 0 ,BIT(0));
7132 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_07_L, 0 ,BIT(0));
7133 }
7134
7135 u16FDMaskCount=0;
7136
7137 if(TRUE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
7138 {
7139 //Disable ISR
7140 Mhal_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
7141 }
7142 }
7143 }
7144 }
7145
MHal_XC_DTVPatch(void * pInstance,SCALER_WIN eWindow)7146 void MHal_XC_DTVPatch(void *pInstance, SCALER_WIN eWindow)
7147 {
7148 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7149 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7150 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7151 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7152
7153 if(eWindow ==MAIN_WINDOW)
7154 {
7155 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType)
7156 &&(gSrcInfo[MAIN_WINDOW].stCapWin.width==1920)
7157 &&(gSrcInfo[MAIN_WINDOW].stCapWin.height==1080)
7158 &&(gSrcInfo[MAIN_WINDOW].bInterlace==TRUE))
7159 {
7160 //DTV 1080i patch
7161 if(FALSE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL))
7162 {
7163 //Start DTV 1080i patch, enable ISR
7164 Mhal_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL);
7165 }
7166 }
7167 else
7168 {
7169 if(TRUE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
7170 {
7171 //Disable ISR
7172 Mhal_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
7173 }
7174 }
7175 }
7176 }
7177
7178
7179 #ifndef DONT_USE_CMA
7180 #if (XC_SUPPORT_CMA ==TRUE)
MHal_XC_Get_CMA_Addr(void * pInstance,XC_CMA_CLIENT enCmaClient,MS_U32 u32GetCMASize,SCALER_WIN eWindow)7181 MS_U64 MHal_XC_Get_CMA_Addr(void *pInstance, XC_CMA_CLIENT enCmaClient, MS_U32 u32GetCMASize, SCALER_WIN eWindow)
7182 {
7183 MS_U64 u64CMAAddr = 0;
7184 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7185 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7186 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7187 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7188
7189 if (u32GetCMASize == 0)
7190 {
7191 return u64CMAAddr;
7192 }
7193
7194 struct CMA_Pool_Alloc_Param CMA_Pool_GetMem;
7195 CMA_Pool_GetMem.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].pool_handle_id;
7196 CMA_Pool_GetMem.offset_in_pool = stXC_CMA_Config[enCmaClient].u64AddrHeapOffset;
7197 CMA_Pool_GetMem.flags = CMA_FLAG_VIRT_ADDR;
7198 if(CMA_Pool_Init_PARAM[enCmaClient].heap_length >= u32GetCMASize)
7199 {
7200 CMA_Pool_GetMem.length = u32GetCMASize;
7201 }
7202 else
7203 {
7204 printf("\033[35m Function = %s, Line = %d, CMA_POOL_INIT GetMem ERROR!!\033[m\n", __PRETTY_FUNCTION__, __LINE__);
7205 assert(0);
7206 }
7207
7208 MApi_CMA_Pool_GetMem(&CMA_Pool_GetMem);
7209 u64CMAAddr = CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset;
7210 if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_1)
7211 {
7212 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU1_BASE;
7213 }
7214 else if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_2)
7215 {
7216 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU2_BASE;
7217 }
7218
7219 return u64CMAAddr;
7220 }
7221
MHal_SC_Limit_WriteMem(void * pInstance,SCALER_WIN eWindow)7222 MS_PHY MHal_SC_Limit_WriteMem(void *pInstance, SCALER_WIN eWindow)
7223 {
7224 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7225 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7226 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7227 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7228 MS_PHY u32WriteLimitAddr = pXCResourcePrivate->stdrvXC_3D._u32HW2DTO3D_DD_Buf;
7229
7230 return u32WriteLimitAddr;
7231
7232 }
7233
MHal_SC_Limit_Dual_WriteMem(void * pInstance,SCALER_WIN eWindow)7234 void MHal_SC_Limit_Dual_WriteMem(void *pInstance, SCALER_WIN eWindow)
7235 {
7236 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7237 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7238 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7239 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7240
7241 if(eWindow == MAIN_WINDOW)
7242 {
7243 /// need to disable the r/w request, when change the write limit base
7244 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
7245 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, BIT(4),BIT(4)); //F2 memory address limit enable
7246 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0, BIT(15)); // disable dual to defect xc dual write miu
7247 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, 0x00); //F2 memory min address
7248 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, 0x00); //F2 memory max address
7249 }
7250 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[eWindow] = 0;
7251 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBSize[eWindow] = 0;
7252
7253 }
MHal_XC_Get_CMA_UsingCondition(void * pInstance,MS_BOOL bIsGetCMABuff[],MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[],MS_U32 * pu32DualMiuMemSize,MS_U32 u32DataSize,SCALER_WIN eWindow)7254 MS_BOOL MHal_XC_Get_CMA_UsingCondition(void *pInstance, MS_BOOL bIsGetCMABuff[], MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[], MS_U32* pu32DualMiuMemSize, MS_U32 u32DataSize, SCALER_WIN eWindow)
7255 {
7256 MS_U32 u32CMAMemSCMSize = 0;
7257 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7258 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7259 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7260 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7261
7262 if (u32DataSize < CMA_XC_MEM_NUM)
7263 {
7264 return FALSE;
7265 }
7266
7267 if ((MHal_XC_Is_DSForceIndexEnabled(pInstance, MAIN_WINDOW)||MHAL_SC_Get_DynamicScaling_Status(pInstance))
7268 && IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType))
7269 {
7270 // MM source and DS on 4K2K case, interlace also using 4k2k virtualbox because some streams is i/p change
7271 u32CMAMemSCMSize = XC_CMA_96MB;
7272 }
7273 else if (IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType))
7274 {
7275 u32CMAMemSCMSize = XC_CMA_96MB;
7276 }
7277 else if ( (IsSrcTypeAV(gSrcInfo[eWindow].enInputSourceType))
7278 ||(IsSrcTypeSV(gSrcInfo[eWindow].enInputSourceType))
7279 ||(IsSrcTypeATV(gSrcInfo[eWindow].enInputSourceType))
7280 ||(IsSrcTypeScart(gSrcInfo[eWindow].enInputSourceType)))
7281 {
7282 u32CMAMemSCMSize = XC_CMA_19MB;
7283 }
7284 else
7285 {
7286 if ((gSrcInfo[(eWindow)].stCapWin.width>= 3840) && (gSrcInfo[(eWindow)].stCapWin.height>= 2160))
7287 {
7288 if (stXC_CMA_Config[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID && ((gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI2)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI3)))
7289 {
7290 // HDMI dual miu
7291 u32CMAMemSCMSize = XC_CMA_48MB;
7292 }
7293 else
7294 {
7295 // 4K2K DTV
7296 u32CMAMemSCMSize = XC_CMA_96MB;
7297 }
7298 }
7299 else
7300 {
7301 u32CMAMemSCMSize = XC_CMA_48MB;
7302 }
7303 }
7304
7305 if ( (stXC_CMA_Config[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID)
7306 &&((gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI2)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI3))
7307 &&((gSrcInfo[(eWindow)].stCapWin.width>= 3840) && (gSrcInfo[(eWindow)].stCapWin.height>= 2160)))
7308 {
7309 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
7310 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
7311 *pu32DualMiuMemSize = XC_CMA_48MB;
7312 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
7313 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
7314 }
7315 else
7316 {
7317 if (stXC_CMA_Config[CMA_XC_COBUFF_MEM].u32HeapID == XC_INVALID_HEAP_ID || IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType) || IsSrcTypeDTV(gSrcInfo[eWindow].enInputSourceType))
7318 {
7319 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
7320 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = FALSE;
7321 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
7322 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
7323 }
7324 else
7325 {
7326 bIsGetCMABuff[CMA_XC_SELF_MEM] = FALSE;
7327 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
7328 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = 0;
7329 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = u32CMAMemSCMSize;
7330 }
7331 *pu32DualMiuMemSize = 0;
7332 }
7333
7334 au32CMAMemFRCMSize[CMA_XC_SELF_MEM] = 0;
7335 au32CMAMemFRCMSize[CMA_XC_COBUFF_MEM] = 0;
7336
7337 return TRUE;
7338 }
7339 #endif
7340 #endif
7341
MHAL_SC_set_r2y_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7342 void MHAL_SC_set_r2y_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7343 {
7344 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7345 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7346 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7347 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7348
7349 if(eWindow == MAIN_WINDOW)
7350 {
7351 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, bEnable?BIT(0):0x00, BIT(0));
7352 }
7353 else if(eWindow == SUB_WINDOW)
7354 {
7355 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, bEnable?BIT(0):0x00, BIT(0));
7356 }
7357 }
7358
MHAL_SC_get_r2y_en_status(void * pInstance,SCALER_WIN eWindow)7359 MS_BOOL MHAL_SC_get_r2y_en_status(void *pInstance, SCALER_WIN eWindow)
7360 {
7361 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7362 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7363 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7364 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7365
7366 MS_BOOL bstatus = FALSE;
7367
7368 if(eWindow == MAIN_WINDOW)
7369 {
7370 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, BIT(0));
7371 }
7372 else if(eWindow == SUB_WINDOW)
7373 {
7374 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, BIT(0));
7375 }
7376
7377 return bstatus;
7378 }
7379
Hal_SC_set_T3D_setting(void * pInstance,MS_BOOL bEnable)7380 void Hal_SC_set_T3D_setting(void *pInstance, MS_BOOL bEnable)
7381 {
7382 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7383 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7384
7385 if (Mhal_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
7386 {
7387 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
7388 }
7389 else
7390 {
7391 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
7392 }
7393
7394 }
7395
Hal_SC_set_T3D_H_size(void * pInstance,MS_U16 u16Hsize)7396 void Hal_SC_set_T3D_H_size(void *pInstance, MS_U16 u16Hsize)
7397 {
7398 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7399 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7400
7401 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_55_L, u16Hsize, 0x1FFF); //horizontal pixel number
7402 }
7403
Hal_SC_3D_Is_LR_Sbs2Line(void * pInstance)7404 MS_BOOL Hal_SC_3D_Is_LR_Sbs2Line(void *pInstance)
7405 {
7406 if(SC_R2BYTEMSK(0, REG_SC_BK23_53_L, BIT(15)))
7407 {
7408 return TRUE;
7409 }
7410 else
7411 {
7412 return FALSE;
7413 }
7414 }
7415
Hal_SC_3D_SetLRChgMode(void * pInstance,HAL_SC_3D_LRCHGMODE eLRChgMode)7416 void Hal_SC_3D_SetLRChgMode(void *pInstance, HAL_SC_3D_LRCHGMODE eLRChgMode)
7417 {
7418 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7419 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7420 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, eLRChgMode, BIT(1)|BIT(0));
7421 }
7422
7423 // 0: L is the first frame, 1: R is the first frame
Hal_SC_3D_SetInitialLRIndex(void * pInstance,MS_BOOL bRFirst)7424 void Hal_SC_3D_SetInitialLRIndex(void *pInstance, MS_BOOL bRFirst)
7425 {
7426 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7427 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7428 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bRFirst==TRUE)?BIT(4):0, BIT(4));
7429 }
7430
7431 // Split 1 frame into 2 frames
Hal_SC_3D_SetSplitHalf(void * pInstance,MS_BOOL bEnable)7432 void Hal_SC_3D_SetSplitHalf(void *pInstance, MS_BOOL bEnable)
7433 {
7434 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7435 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7436 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
7437 }
7438
Hal_SC_set_frcm_to_FD_mask(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7439 void Hal_SC_set_frcm_to_FD_mask(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7440 {
7441 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7442 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7443 if (eWindow == MAIN_WINDOW)
7444 {
7445 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(2):0, BIT(2));
7446 }
7447 else
7448 {
7449 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(10):0, BIT(10));
7450 }
7451 }
7452
Hal_SC_3D_set_top_win_6Tap(void * pInstance,MS_BOOL bEnable)7453 void Hal_SC_3D_set_top_win_6Tap(void *pInstance, MS_BOOL bEnable)
7454 {
7455 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7456 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7457 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, (bEnable==TRUE)?BIT(10):0, BIT(10)); //force top window using 6line
7458 }
7459
Hal_SC_3D_SetActiveVideoHeight(void * pInstance,MS_U16 u16VideoSize)7460 void Hal_SC_3D_SetActiveVideoHeight(void *pInstance, MS_U16 u16VideoSize)
7461 {
7462 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7463 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7464
7465 #if _ENABLE_SW_DS
7466 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7467 {
7468 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_65_L,u16VideoSize,DS_IP);
7469 }
7470 else
7471 #endif
7472 {
7473 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_65_L, u16VideoSize, 0x1FFF);//v_active region
7474 }
7475 }
7476
7477 // 0 for blank area 0
7478 //v blanking between field1&field2 or field3&field4
Hal_SC_3D_SetActiveBlankSize0(void * pInstance,MS_U16 u16BlankSize)7479 void Hal_SC_3D_SetActiveBlankSize0(void *pInstance, MS_U16 u16BlankSize)
7480 {
7481 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7482 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7483 #if _ENABLE_SW_DS
7484 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7485 {
7486 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_66_L,u16BlankSize,DS_IP);
7487 }
7488 else
7489 #endif
7490 {
7491 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_66_L, u16BlankSize, 0x1FFF);
7492 }
7493 }
7494
7495 // 1 for blank area 1
7496 //v blanking between field2&field3
Hal_SC_3D_SetActiveBlankSize1(void * pInstance,MS_U16 u16BlankSize)7497 void Hal_SC_3D_SetActiveBlankSize1(void *pInstance, MS_U16 u16BlankSize)
7498 {
7499 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7500 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7501 #if _ENABLE_SW_DS
7502 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7503 {
7504 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_67_L,u16BlankSize,DS_IP);
7505 }
7506 else
7507 #endif
7508 {
7509 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_67_L, u16BlankSize, 0x1FFF);//v blanking between field1&field2 or field3&field4
7510 }
7511 }
7512
Hal_SC_3D_SetActiveVideoWidth(void * pInstance,MS_U16 u16VideoSize)7513 void Hal_SC_3D_SetActiveVideoWidth(void *pInstance, MS_U16 u16VideoSize)
7514 {
7515 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7516 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7517
7518 MS_U16 u16ActiveWidthUsrEnable = 0;
7519 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
7520 {
7521 u16ActiveWidthUsrEnable = BIT(15);
7522 }
7523
7524 #if _ENABLE_SW_DS
7525 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7526 {
7527 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_7F_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
7528 }
7529 else
7530 #endif
7531 {
7532 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x9FFF);//v_active region
7533 }
7534 }
7535
7536
Hal_SC_3D_SetActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)7537 void Hal_SC_3D_SetActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
7538 {
7539 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7540 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7541
7542 MS_U16 u16Enable = BIT(15);
7543
7544 #if _ENABLE_SW_DS
7545 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7546 {
7547 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_38_L,u16VideoSize | u16Enable,DS_IP);
7548 }
7549 else
7550 #endif
7551 {
7552 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_38_L, u16VideoSize | u16Enable, 0x9FFF);
7553 }
7554 }
7555
Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)7556 void Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
7557 {
7558 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7559 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7560
7561 MS_U16 u16Enable = BIT(15);
7562
7563 #if _ENABLE_SW_DS
7564 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7565 {
7566 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK48_38_L,u16VideoSize | u16Enable,DS_IP);
7567 }
7568 else
7569 #endif
7570 {
7571 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK48_38_L, u16VideoSize | u16Enable, 0x9FFF);
7572 }
7573 }
7574
Hal_SC_3D_SetPixelSeparationWidth(void * pInstance,MS_U16 u16VideoSize)7575 void Hal_SC_3D_SetPixelSeparationWidth(void *pInstance, MS_U16 u16VideoSize)
7576 {
7577 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7578 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7579
7580 MS_U16 u16ActiveWidthUsrEnable = 0;
7581 #if (HW_DESIGN_3D_VER >= 3)
7582 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
7583 {
7584 u16ActiveWidthUsrEnable = BIT(15);
7585 }
7586 #endif
7587
7588 #if _ENABLE_SW_DS
7589 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7590 {
7591 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_6C_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
7592 }
7593 else
7594 #endif
7595 {
7596 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_6C_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x87FF);
7597 }
7598 }
7599
Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)7600 void Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
7601 {
7602 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7603 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7604
7605 #if _ENABLE_SW_DS
7606 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7607 {
7608 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4F_L,u16VideoSize,DS_IP);
7609 }
7610 else
7611 #endif
7612 {
7613 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4F_L, u16VideoSize, 0x0FFF);
7614 }
7615 }
7616
Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)7617 void Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
7618 {
7619 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7620 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7621
7622 #if _ENABLE_SW_DS
7623 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7624 {
7625 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4D_L,u16VideoSize,DS_IP);
7626 }
7627 else
7628 #endif
7629 {
7630 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4D_L, u16VideoSize, 0x0FFF);
7631 }
7632 }
7633
Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void * pInstance,MS_U16 u16VideoSize)7634 void Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void *pInstance, MS_U16 u16VideoSize)
7635 {
7636 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7637 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7638
7639 #if _ENABLE_SW_DS
7640 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7641 {
7642 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4E_L,u16VideoSize,DS_IP);
7643 }
7644 else
7645 #endif
7646 {
7647 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4E_L, u16VideoSize, 0x0FFF);
7648 }
7649 }
7650
Hal_SC_set_frcm_to_freeze(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7651 void Hal_SC_set_frcm_to_freeze(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7652 {
7653 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7654 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7655 if (eWindow == MAIN_WINDOW)
7656 {
7657 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(0):0, BIT(0));
7658 }
7659 else
7660 {
7661 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
7662 }
7663 }
7664
Hal_SC_SetOSDDetect(void * pInstance,MS_BOOL bEnable,MS_U32 Threhold)7665 E_APIXC_ReturnValue Hal_SC_SetOSDDetect(void *pInstance, MS_BOOL bEnable, MS_U32 Threhold)
7666 {
7667 MS_U16 u16Reg = 0;
7668 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7669 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7670 if(Threhold == 0)
7671 {
7672 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, 0x0, (BIT(15)+BMASK(11:0)));
7673 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, BIT(1), BIT(1));
7674
7675 }
7676 else
7677 {
7678 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, 0x0, BIT(1));
7679 u16Reg = ((MS_U16)Threhold*2)|(bEnable << 15);
7680 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, u16Reg, (BIT(15)+BMASK(11:0)));
7681 }
7682 return E_APIXC_RET_OK;
7683 }
7684
Hal_SC_GetOSDDetect(void * pInstance,MS_BOOL * pbOSD)7685 E_APIXC_ReturnValue Hal_SC_GetOSDDetect(void *pInstance, MS_BOOL *pbOSD)
7686 {
7687 MS_U16 u16Reg = 0;
7688 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7689 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7690
7691 u16Reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L);
7692 *pbOSD = ((u16Reg&BIT(14))>>14);
7693 return E_APIXC_RET_OK;
7694 }
7695
Hal_SC_SetHDMI_Spliter(void * pInstance,XC_IP_SYNC_STATUS * sXC_Sync_Status,E_MUX_INPUTPORT enInputPort,SCALER_WIN eWindow)7696 void Hal_SC_SetHDMI_Spliter(void *pInstance,XC_IP_SYNC_STATUS *sXC_Sync_Status,E_MUX_INPUTPORT enInputPort ,SCALER_WIN eWindow)
7697 {
7698
7699 #if 0//SUPPORT_HDMI20
7700 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7701 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7702
7703 MS_U16 u16HDE_temp_size,u16HDE_size =0;
7704
7705 if((sXC_Sync_Status->u8SyncStatus & XC_MD_SYNC_LOSS) != XC_MD_SYNC_LOSS)
7706 {
7707 if(MDrv_HDMI_CheckHDMI20_Setting(enInputPort))
7708 {
7709 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7710 if(eWindow == MAIN_WINDOW)
7711 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7712 else if(eWindow == SUB_WINDOW)
7713 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7714
7715 }
7716 else
7717 {
7718 //SUPPORT_HDMI20_420
7719 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7720 //printf("[%s][%d]sXC_Sync_Status->u16Vtotal=%x, sXC_Sync_Status->u16Hperiod=%x\n",
7721 // __FUNCTION__, __LINE__, sXC_Sync_Status->u16Vtotal, sXC_Sync_Status->u16Hperiod);
7722 if((sXC_Sync_Status->u16Vtotal >= 0x8C0)
7723 &&(sXC_Sync_Status->u16Hperiod>= 0x50))
7724 {
7725 if((MDrv_HDMI_avi_infoframe_info(_BYTE_1)& 0x60) == 0x60)
7726 {
7727 //printf("@@#@@4K2K@60 420\n");
7728 // clkgen2
7729 W2BYTE(0x100a80,0x0004); // spt_l0 1: hdmi d: mhl
7730 // ipmux
7731 if(eWindow == MAIN_WINDOW)
7732 {
7733 W2BYTEMSK(0x102e02,0x00b0,BMASK(7:4)); // ipmux sel=0xb
7734 }
7735 else if(eWindow == SUB_WINDOW)
7736 {
7737 W2BYTEMSK(0x102e02,0x000b,BMASK(3:0)); // ipmux sel=0xb
7738 }
7739
7740 //BK40_SPT4k
7741 SC_W2BYTE(0, REG_SC_BK40_01_L,0x0000); // [3:0] reg_spt_ipmux_sel0
7742 // [11:8] reg_spt_ipmux_sel1
7743 SC_W2BYTE(0, REG_SC_BK40_03_L,0x0001); // [7] reg_spt_2p_oe_en [0] reg_spt_420_en
7744 SC_W2BYTE(0, REG_SC_BK40_04_L,0x0180); // [7] reg_spt_2p_oe_out_en [9] hsd_en
7745 // [8] reg_spt_2poe_out_sel 1'b0: dual ch eo in
7746 // 1'b1: dual ch LR in or 420
7747 SC_W2BYTE(0, REG_SC_BK40_30_L, 0x0003); // de_only
7748 SC_W2BYTE(0, REG_SC_BK40_0B_L, 0x0000); // gb_size
7749
7750 u16HDE_temp_size = MDrv_HDMI_GetHDE();
7751 //printf("[%s][%d]u16HDE_size=%u\n", __FUNCTION__, __LINE__,u16HDE_temp_size);
7752 if((u16HDE_temp_size >= 2028)&&(u16HDE_temp_size<= 2068))
7753 {
7754 u16HDE_size = 2048;
7755 }
7756 else //if((u16HDE_temp_size >= 1900)&&(u16HDE_temp_size<= 1940))
7757 {
7758 u16HDE_size = 1920;
7759 }
7760 SC_W2BYTE(0, REG_SC_BK40_08_L, u16HDE_size); // de_in_size
7761 SC_W2BYTE(0, REG_SC_BK40_0A_L, u16HDE_size); // de_out_with_gb_size
7762
7763 SC_W2BYTE(0, REG_SC_BK40_20_L, 0x0000); // ra
7764 SC_W2BYTE(0, REG_SC_BK40_21_L, u16HDE_size/2-2); //
7765 SC_W2BYTE(0, REG_SC_BK40_22_L, 0x0001);
7766 SC_W2BYTE(0, REG_SC_BK40_23_L, u16HDE_size/2-1);
7767
7768 SC_W2BYTE(0, REG_SC_BK40_24_L, 0x0000); // wa
7769 SC_W2BYTE(0, REG_SC_BK40_25_L, u16HDE_size/2-2);
7770 SC_W2BYTE(0, REG_SC_BK40_26_L, 0x0001);
7771 SC_W2BYTE(0, REG_SC_BK40_27_L, u16HDE_size/2-1);
7772 }
7773 else
7774 {
7775 //printf("@@#@@4K2K@30\n");
7776 /// for 4K2K@30Hz
7777 if(eWindow == MAIN_WINDOW)
7778 {
7779 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7780 }
7781 else if(eWindow == SUB_WINDOW)
7782 {
7783 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7784 }
7785 }
7786 }
7787 }
7788 }
7789 #endif
7790 }
7791
Hal_SC_Set_2pmode(void * pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)7792 void Hal_SC_Set_2pmode(void *pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)
7793 {
7794 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7795 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7796
7797 if (eWindow == MAIN_WINDOW)
7798 {
7799 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L,(benable_IP2p ? BIT(15):0), BIT(15));//reg_sprange_hdc_2p
7800 if (psXCInstPri->u32DeviceID == 0)
7801 {
7802 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_01_L,(benable_OP2p ? BIT(1):0), BIT(1));//reg_opm_2p_mode
7803 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_04_L,(benable_bypass_all_2p ? BIT(6):0), BIT(6));//reg_bypass_all_2p_f2
7804 }
7805 }
7806 }
7807
MHal_SC_set_manual_rbank_switch_cnt(void * pInstance,MS_BOOL bEnable,MS_U16 u16SwitchCnt,SCALER_WIN eWindow)7808 void MHal_SC_set_manual_rbank_switch_cnt(void *pInstance, MS_BOOL bEnable, MS_U16 u16SwitchCnt, SCALER_WIN eWindow)
7809 {
7810 if (eWindow >= MAX_WINDOW)
7811 {
7812 printf("unsupported eWindow, return!\n");
7813 return;
7814 }
7815
7816 if( eWindow == MAIN_WINDOW)
7817 {
7818 // these two registers must be set simultaneously for this feature to work
7819 // frame rate convert dependence with IP write line count
7820 SC_W2BYTEMSK(0,REG_SC_BK12_05_L, bEnable? BIT(3):0, BIT(3));
7821 // frame rate convert dependence with IP write line count FULL
7822 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15));
7823
7824 // set specific line count according to when you will change rbank switch
7825 // this line count starts at VDE rising edge, ends at u16SwitchCnt
7826 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF);
7827 }
7828 else
7829 {
7830 // these two registers must be set simultaneously for this feature to work
7831 // frame rate convert dependence with IP write line count
7832 SC_W2BYTEMSK(0,REG_SC_BK12_45_L, bEnable? BIT(3):0, BIT(3));
7833 // frame rate convert dependence with IP write line count FULL
7834 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, bEnable? BIT(15):0, BIT(15));
7835
7836 // set specific line count according to when you will change rbank switch
7837 // this line count starts at VDE rising edge, ends at u16SwitchCnt
7838 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, u16SwitchCnt, 0x1FFF);
7839 }
7840 }
7841
7842 #define IsEnableDualMode(eWindow) (gSrcInfo[eWindow].Status2.stMiuDualModCfg.bEnableMiuDualMod == TRUE)
7843 #ifdef SUPPORT_BWD
_HAL_SC_BWR_set_base_address(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)7844 static void _HAL_SC_BWR_set_base_address(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
7845 {
7846 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7847 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7848 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7849 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7850
7851 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
7852 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
7853 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
7854 {
7855 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
7856 {
7857 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
7858 break;
7859 }
7860 }
7861
7862 #ifdef SUPPORT_DUAL_MIU
7863 if (IsEnableDualMode(eWindow))
7864 {
7865 //SCMI: IPM address 0
7866 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7867 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7868 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
7869 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
7870 //SCMI: IPM address 1
7871 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7872 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7873 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
7874 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
7875 //SCMI: OPM address 0
7876 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7877 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7878 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
7879 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
7880 //SCMI: OPM address 1
7881 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7882 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7883 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
7884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
7885 }
7886 else
7887 #endif
7888 {
7889 //SCMI: IPM address 0
7890 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7891 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7892 //SCMI: IPM address 1
7893 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7894 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7895 //SCMI: OPM address 0
7896 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7897 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7898 //SCMI: OPM address 1
7899 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7900 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7901 }
7902 }
7903
_HAL_SC_BWR_set_vlen(void * pInstance,SCALER_WIN eWindow)7904 void _HAL_SC_BWR_set_vlen(void * pInstance, SCALER_WIN eWindow)
7905 {
7906 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7907 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7908
7909 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7910 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7911 //update BWR Configuration vlen,IP 3D source: LA
7912 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
7913 {
7914 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
7915 }
7916 else
7917 {
7918 //update BWR Configuration vlen, VSD
7919 if(gSrcInfo[eWindow].bPreV_ScalingDown)
7920 {
7921 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
7922 }
7923 else
7924 {
7925 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, 0, BIT(15));
7926 }
7927 }
7928 //update BWR Configuration vlen,OP 3D output: LA
7929 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
7930 {
7931 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
7932 }
7933 else
7934 {
7935 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, 0, BIT(15));
7936 }
7937
7938 }
7939
_HAL_SC_BWR_set_3d_mode(void * pInstance,SCALER_WIN eWindow)7940 static void _HAL_SC_BWR_set_3d_mode(void * pInstance, SCALER_WIN eWindow)
7941 {
7942 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7943 MS_U8 u8ChipVersion = 0;
7944 MS_BOOL b2pMode = FALSE;
7945 MS_BOOL bBwrMode = FALSE;
7946 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7947 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7948 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7949 //BWR 422 to 420 set drop mode register
7950 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
7951 {
7952 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_38_L, BIT(7), BIT(7));
7953 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, 0, BIT(2));
7954 }
7955
7956 //BWR 422 to 420 set TB mode register
7957 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
7958 {
7959 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, BIT(4), BIT(4));
7960 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
7961 }
7962
7963 //OP1 must turn off initial process
7964 u8ChipVersion = MDrv_ReadByte(REG_CHIP_REVISION);
7965 b2pMode = SC_R2BYTE(psXCInstPri->u32DeviceID,REG_SC_BK20_01_L)&0x02;
7966 bBwrMode = SC_R2BYTE(psXCInstPri->u32DeviceID,REG_SC_BK46_01_L)&0x02;
7967
7968 if(u8ChipVersion == 0)
7969 {
7970 if(((MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE))&&
7971 ((IS_INPUT_4K2K(eWindow))&&((gSrcInfo[eWindow].bVCusScaling == TRUE)&&
7972 (gSrcInfo[eWindow].u16VCusScalingSrc != gSrcInfo[eWindow].u16VCusScalingDst))))
7973 {
7974 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,BIT(12) ,BIT(12));
7975 }
7976 else
7977 {
7978 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,0 ,BIT(12));
7979 }
7980
7981 if((MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)&&(bBwrMode))
7982 {
7983 if(b2pMode)
7984 {
7985 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_29_L, 0x0101, 0x1F1F);
7986 }
7987 else
7988 {
7989 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_29_L, 0, 0x1F1F);
7990 }
7991 }
7992 else
7993 {
7994 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK20_23_L, BIT(10)))
7995 {
7996 ///6 tap mode
7997 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_29_L, 0x0404, 0x1F1F);
7998 }
7999 else
8000 {
8001 ///4 tap mode
8002 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_29_L, 0x0303, 0x1F1F);
8003 }
8004
8005 }
8006 }
8007 else if(u8ChipVersion >= 1)
8008 {
8009 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8010 {
8011 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,BIT(12) ,BIT(12));
8012 }
8013 else
8014 {
8015 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,0 ,BIT(12));
8016 }
8017 }
8018 }
8019
_HAL_SC_BWR_set_base_address_burst(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)8020 static void _HAL_SC_BWR_set_base_address_burst(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
8021 {
8022 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8023 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8024 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8025 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8026
8027 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
8028 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
8029 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
8030 {
8031 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
8032 {
8033 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
8034 break;
8035 }
8036 }
8037
8038 #ifdef SUPPORT_DUAL_MIU
8039 if (IsEnableDualMode(eWindow))
8040 {
8041 //SCMI: IPM address 0
8042 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8043 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8044
8045 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
8046 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
8047
8048 //SCMI: IPM address 1
8049 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8050 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8051
8052 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
8053 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
8054
8055 //SCMI: OPM address 0
8056 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8057 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8058
8059 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
8060 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
8061
8062 //SCMI: OPM address 1
8063 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8064 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8065
8066 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
8067 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
8068 }
8069 else // Disbale dual
8070 #endif
8071 {
8072 //SCMI: IPM address 0
8073 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8074 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8075
8076 //SCMI: IPM address 1
8077 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8078 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8079
8080 //SCMI: OPM address 0
8081 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8082 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8083
8084 //SCMI: OPM address 1
8085 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8086 Mhal_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8087 }
8088 }
8089
_HAL_SC_BWR_set_vlen_burst(void * pInstance,SCALER_WIN eWindow)8090 static void _HAL_SC_BWR_set_vlen_burst(void * pInstance, SCALER_WIN eWindow)
8091 {
8092 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8093 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8094
8095 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8096 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8097 //update BWR Configuration vlen,IP 3D source: LA
8098 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
8099 {
8100 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
8101 }
8102 else
8103 {
8104 //update BWR Configuration vlen, VSD
8105 if(gSrcInfo[eWindow].bPreV_ScalingDown)
8106 {
8107 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
8108 }
8109 else
8110 {
8111 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, 0, BIT(15));
8112 }
8113 }
8114 //update BWR Configuration vlen,OP 3D output: LA
8115 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8116 {
8117 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
8118 }
8119 else
8120 {
8121 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, 0, BIT(15));
8122 }
8123 }
8124
_HAL_SC_BWR_set_3d_mode_burst(void * pInstance,SCALER_WIN eWindow)8125 static void _HAL_SC_BWR_set_3d_mode_burst(void * pInstance, SCALER_WIN eWindow)
8126 {
8127 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8128 MS_U8 u8ChipVersion = 0;
8129 MS_BOOL b2pMode = FALSE;
8130 MS_BOOL bBwrMode = FALSE;
8131
8132 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8133
8134 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8135 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8136
8137 //BWR 422 to 420 set drop mode register
8138 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
8139 {
8140 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_38_L, BIT(7), BIT(7));
8141 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, 0, BIT(2));
8142 }
8143
8144 //BWR 422 to 420 set TB mode register
8145 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
8146 {
8147 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, BIT(4),BIT(4));
8148 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(11));
8149 }
8150
8151 //OP1 must turn off initial process
8152 u8ChipVersion = MDrv_ReadByte(REG_CHIP_REVISION);
8153 b2pMode = SC_R2BYTE(psXCInstPri->u32DeviceID,REG_SC_BK20_01_L)&0x02;
8154 bBwrMode = SC_R2BYTE(psXCInstPri->u32DeviceID,REG_SC_BK46_01_L)&0x02;
8155
8156 if(u8ChipVersion == 0)
8157 {
8158 if(((MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE))&&
8159 ((bBwrMode)&&((gSrcInfo[eWindow].bVCusScaling == TRUE)&&
8160 (gSrcInfo[eWindow].u16VCusScalingSrc != gSrcInfo[eWindow].u16VCusScalingDst))))
8161 {
8162 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(12), BIT(12));
8163 }
8164 else
8165 {
8166 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(12));
8167 }
8168 if((MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)&&(bBwrMode))
8169 {
8170 if(b2pMode)
8171 {
8172 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_29_L, 0x0101, 0x1F1F);
8173 }
8174 else
8175 {
8176 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_29_L, 0, 0x1F1F);
8177 }
8178 }
8179 else
8180 {
8181 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK20_23_L, BIT(10)))
8182 {
8183 ///6 tap mode
8184 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_29_L, 0x0404, 0x1F1F);
8185 }
8186 else
8187 {
8188 ///4 tap mode
8189 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_29_L, 0x0303, 0x1F1F);
8190 }
8191 }
8192 }
8193 else if(u8ChipVersion >= 1)
8194 {
8195 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8196 {
8197 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(12), BIT(12));
8198 }
8199 else
8200 {
8201 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(12));
8202 }
8203 }
8204 }
8205 #endif
8206
HAL_SC_set_bwr_config_burst(void * pInstance,void * pstParam,SCALER_WIN eWindow)8207 MS_BOOL HAL_SC_set_bwr_config_burst(void *pInstance, void *pstParam, SCALER_WIN eWindow)
8208 {
8209 #ifdef SUPPORT_BWD
8210 MS_U16 u16BwrMemCfgTmp = 0;
8211 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8212 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8213 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8214 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8215
8216 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
8217 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
8218 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
8219 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
8220 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
8221 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
8222 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
8223 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
8224
8225 _HAL_SC_BWR_set_vlen_burst(pInstance, eWindow);
8226 _HAL_SC_BWR_set_3d_mode_burst(pInstance, eWindow);
8227
8228 Mhal_XC_MLoad_Fire(pInstance, TRUE);
8229 return TRUE;
8230 #else
8231 return FALSE;
8232 #endif
8233 }
8234
HAL_SC_set_bwr_config(void * pInstance,void * pstParam,SCALER_WIN eWindow)8235 MS_BOOL HAL_SC_set_bwr_config(void *pInstance, void *pstParam, SCALER_WIN eWindow)
8236 {
8237 #ifdef SUPPORT_BWD
8238 MS_U16 u16BwrMemCfgTmp = 0;
8239 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8240 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8241 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8242 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8243
8244 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
8245 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
8246 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
8247 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
8248 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
8249 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
8250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
8251 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
8252
8253 _HAL_SC_BWR_set_vlen(pInstance, eWindow);
8254 _HAL_SC_BWR_set_3d_mode(pInstance, eWindow);
8255 return TRUE;
8256 #else
8257 return FALSE;
8258 #endif
8259 }
8260
Hal_SC_AdjustIpmWriteLimite(void * pInstance,MS_BOOL bIsLeft,MS_BOOL bNeedSwap,SCALER_WIN eWindow)8261 MS_BOOL Hal_SC_AdjustIpmWriteLimite(void *pInstance, MS_BOOL bIsLeft, MS_BOOL bNeedSwap, SCALER_WIN eWindow)
8262 {
8263 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8264 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8265 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8266 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8267 MS_PHY u32WLimitBase = 0x00;
8268 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
8269 {
8270 return FALSE;
8271 }
8272
8273 if (bIsLeft == TRUE)
8274 {
8275 if (bNeedSwap == TRUE)
8276 {
8277 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;;
8278 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
8279 }
8280 else
8281 {
8282 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;
8283 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
8284 }
8285 }
8286 else
8287 {
8288 if (bNeedSwap == TRUE)
8289 {
8290 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
8291 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
8292 }
8293 else
8294 {
8295 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
8296 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
8297 }
8298 }
8299 return TRUE;
8300 }
8301
Hal_SC_3D_enable_black_edge(void * pInstance,MS_BOOL b2DTo3D)8302 void Hal_SC_3D_enable_black_edge(void *pInstance, MS_BOOL b2DTo3D)
8303 {
8304 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8305 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8306 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8307 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8308
8309 MS_U16 u16GarbageWidth = 0;
8310 MS_U16 u16BlackBarEnd_L = 0;
8311 MS_U16 u16BlackBarStart_R = 0;
8312 MS_U16 u16FrameColorWidth = pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisStart - SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L);
8313 MS_U16 u16DispWinWidth = pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisEnd - pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisStart + 1;
8314
8315 if(b2DTo3D)
8316 {
8317 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._st3DHw2DTo3DPara.u16Offset>>3; //offset
8318 u16GarbageWidth = (u16GarbageWidth > 16)?(u16GarbageWidth - 16):(16 - u16GarbageWidth);
8319 u16GarbageWidth = u16GarbageWidth + (pXCResourcePrivate->stdrvXC_3D._st3DHw2DTo3DPara.u16Gain + 1) / 2;//gain
8320 }
8321 else
8322 {
8323 if(0 == pXCResourcePrivate->stdrvXC_3D._u163DHShift)
8324 {
8325 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._u163DHShift;
8326 }
8327 else if(pXCResourcePrivate->stdrvXC_3D._u163DHShift > 112)
8328 {
8329 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._u163DHShift - 112;//_u163DHShift = value on UI + 112
8330 }
8331 else
8332 {
8333 u16GarbageWidth = 0;
8334 printf("[%s,%5d] ERROR: invalid value of gain\n",__FUNCTION__,__LINE__);
8335 }
8336
8337 if((0 == u16GarbageWidth) || (16 == u16GarbageWidth))
8338 {
8339 u16GarbageWidth = 0;
8340 }
8341 else
8342 {
8343 u16GarbageWidth = (u16GarbageWidth > 16)?(u16GarbageWidth - 16):(16 - u16GarbageWidth);
8344 }
8345
8346 }
8347
8348 if(u16DispWinWidth > 1920)
8349 {
8350 u16GarbageWidth = u16GarbageWidth* 2;
8351 }
8352 else if(u16DispWinWidth > 960)
8353 {
8354 u16GarbageWidth = u16GarbageWidth;
8355 }
8356 else if(u16DispWinWidth > 480)
8357 {
8358 u16GarbageWidth = u16GarbageWidth / 2;
8359 }
8360 else
8361 {
8362 u16GarbageWidth = u16GarbageWidth / 4;
8363 }
8364
8365 u16BlackBarEnd_L = (u16FrameColorWidth + u16GarbageWidth) /2;//manhattan 2P mode
8366 u16BlackBarStart_R = (u16FrameColorWidth + u16DispWinWidth - u16GarbageWidth) / 2;//manhattan 2P mode
8367
8368 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_65_L, 0x8000, 0x8000);//enable principal black-bar
8369 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_4B_L, 0x0002, 0x0002);//enable left Right black-bar
8370 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_63_L, u16BlackBarEnd_L, 0xFFF);//Left black-bar end
8371 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_62_L, u16BlackBarStart_R, 0xFFF);//Right black-bar start
8372 }
8373
8374 #if FRC_INSIDE
MHal_XC_FRCR2_IP_PatchISR(SC_INT_SRC eIntNum,void * pParam)8375 static void MHal_XC_FRCR2_IP_PatchISR(SC_INT_SRC eIntNum, void * pParam)
8376 {
8377 void *pInstance = pu32XCInst_private;
8378 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8379 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8380 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8381 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8382
8383 MDrv_WriteByteMask(0x400640, 0x02, 0x02);
8384 MsOS_DelayTaskUs(10);
8385 MDrv_WriteByteMask(0x400640, 0x00, 0x02);
8386 }
8387
MHal_XC_FRCR2_IP_Patch(void * pInstance,SCALER_WIN eWindow)8388 void MHal_XC_FRCR2_IP_Patch(void *pInstance, SCALER_WIN eWindow)
8389 {
8390 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8391 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8392 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8393 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8394
8395 if(eWindow ==MAIN_WINDOW)
8396 {
8397 if(FALSE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL))
8398 {
8399 //enable ISR
8400 //FIXME: PATCH
8401 Mhal_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL);
8402 }
8403 }
8404
8405 }
MHal_XC_FRCR2_IP_PatchClose(void * pInstance,SCALER_WIN eWindow)8406 void MHal_XC_FRCR2_IP_PatchClose(void *pInstance, SCALER_WIN eWindow)
8407 {
8408 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8409 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8410 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8411 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8412
8413 if(eWindow ==MAIN_WINDOW)
8414 {
8415 if(TRUE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_F2_IPVS_SB, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL))
8416 {
8417 //Disable ISR
8418 Mhal_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_F2_IPVS_SB, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL);
8419 }
8420 }
8421
8422 }
8423
MHal_XC_FRCR2_OP_PatchISR(SC_INT_SRC eIntNum,void * pParam)8424 static void MHal_XC_FRCR2_OP_PatchISR(SC_INT_SRC eIntNum, void * pParam)
8425 {
8426 void *pInstance = pu32XCInst_private;
8427 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8428 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8429 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8430 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8431
8432 MDrv_WriteByteMask(0x400640, 0x04, 0x04);
8433 MsOS_DelayTaskUs(10);
8434 MDrv_WriteByteMask(0x400640, 0x00, 0x04);
8435 }
8436
MHal_XC_FRCR2_OP_Patch(void * pInstance,SCALER_WIN eWindow)8437 void MHal_XC_FRCR2_OP_Patch(void *pInstance, SCALER_WIN eWindow)
8438 {
8439 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8440 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8441 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8442 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8443
8444 if(eWindow ==MAIN_WINDOW)
8445 {
8446 if(FALSE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL))
8447 {
8448 //enable ISR
8449 //FIXME: PATCH
8450 Mhal_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL);
8451 }
8452 }
8453
8454 }
MHal_XC_FRCR2_OP_PatchClose(void * pInstance,SCALER_WIN eWindow)8455 void MHal_XC_FRCR2_OP_PatchClose(void *pInstance, SCALER_WIN eWindow)
8456 {
8457 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8458 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8459 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8460 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8461
8462 if(eWindow ==MAIN_WINDOW)
8463 {
8464 if(TRUE == Mhal_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL))
8465 {
8466 //Disable ISR
8467 Mhal_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL);
8468 }
8469 }
8470 }
8471
Hal_SC_3D_enable_FALLRR_out(void * pInstance,MS_BOOL bEnable)8472 void Hal_SC_3D_enable_FALLRR_out(void *pInstance, MS_BOOL bEnable)
8473 {
8474 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8475 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8476
8477 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_33_L, (bEnable==TRUE)?BIT(8):0, BIT(8));//OPM LLRR
8478 }
8479 #endif
8480
Hal_SC_3D_Adjust_PreHVscaling_SaveBW(void * pInstance,XC_InternalStatus * pSrcInfo,MS_BOOL * pb3DPreHScaling,MS_BOOL * pb3DPreVScaling,MS_BOOL bForcePreHScalingDown,MS_BOOL bForcePreVScalingDown,SCALER_WIN eWindow)8481 void Hal_SC_3D_Adjust_PreHVscaling_SaveBW(void *pInstance, XC_InternalStatus *pSrcInfo, MS_BOOL *pb3DPreHScaling,MS_BOOL *pb3DPreVScaling,MS_BOOL bForcePreHScalingDown,MS_BOOL bForcePreVScalingDown,SCALER_WIN eWindow)
8482 {
8483 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8484 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8485 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8486 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8487
8488 if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[eWindow] == E_XC_3D_INPUT_FRAME_PACKING)
8489 {
8490 if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode != E_XC_3D_OUTPUT_FRAME_ALTERNATIVE)
8491 {
8492 *pb3DPreHScaling = TRUE;
8493 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8494 pSrcInfo->Status2.u16PreHCusScalingDst = MAX(640, (MS_U32)MIN(1920, pSrcInfo->stDispWin.width) * 2 / 3);
8495 }
8496 else// FA out
8497 {
8498 if((pXCResourcePrivate->stdrvXC_3D._bFALLRRToFA) && (pSrcInfo->stCapWin.width == DOUBLEHD_1080X2P_HSIZE))//output FA_LLRR for 4k0.5k@240Hz
8499 {
8500 *pb3DPreHScaling = TRUE;
8501 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8502 pSrcInfo->Status2.u16PreHCusScalingDst = MAX(640, (MS_U32)MIN(1920, pSrcInfo->stDispWin.width) / 2);
8503 }
8504 }
8505 }
8506 else if((pXCResourcePrivate->stdrvXC_3D._eInput3DMode[eWindow] == E_XC_3D_INPUT_FRAME_ALTERNATIVE) && (pXCResourcePrivate->stdrvXC_3D._eOutput3DMode != E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) &&(pSrcInfo->stCapWin.width > 1280)
8507 && (MDrv_ReadRegBit(REG_CKG_FCLK, CKG_FCLK_MASK) < 24))//fclk < 320MHz may have fclk issue for fi
8508 {
8509 *pb3DPreHScaling = TRUE;
8510 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8511 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width >= 2 * pSrcInfo->stDispWin.width)
8512 {
8513 pSrcInfo->Status2.u16PreHCusScalingDst = MIN(960, pSrcInfo->stDispWin.width);
8514 }
8515 else
8516 {
8517 pSrcInfo->Status2.u16PreHCusScalingDst = MIN(1280, pSrcInfo->stDispWin.width);
8518 }
8519 }
8520 else
8521 {
8522 if(bForcePreHScalingDown)
8523 {
8524 *pb3DPreHScaling = FALSE;
8525 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8526 pSrcInfo->Status2.u16PreHCusScalingDst = pSrcInfo->u16H_SizeAfterPreScaling;
8527 }
8528
8529 if(bForcePreVScalingDown)
8530 {
8531 pb3DPreVScaling = FALSE;
8532 pSrcInfo->Status2.u16PreVCusScalingSrc = pSrcInfo->stCapWin.height;
8533 pSrcInfo->Status2.u16PreVCusScalingDst = pSrcInfo->u16V_SizeAfterPreScaling;
8534 }
8535 }
8536 }
8537
MHal_XC_GetPQPathStatus(void * pInstance,E_XC_PQ_Path_Type ePqPathType,MS_U16 u16Width,MS_U16 u16Height)8538 MS_BOOL MHal_XC_GetPQPathStatus(void* pInstance, E_XC_PQ_Path_Type ePqPathType, MS_U16 u16Width, MS_U16 u16Height)
8539 {
8540 MS_BOOL bRet = FALSE;
8541 switch (ePqPathType)
8542 {
8543 case E_XC_PQ_4K_PATH :
8544 bRet = (IS_4K2K_MODE(u16Width, u16Height)||IS_4K1K_MODE(u16Width, u16Height));
8545 break;
8546 default :
8547 printf("[%s][%d] not path type(%d)!\n", __FUNCTION__, __LINE__, ePqPathType);
8548 break;
8549 }
8550
8551 return bRet;
8552 }
8553
8554 //T3D MIU select from external
Hal_SC_Set_T3D_MiuSelectExternal(void * pInstance,MS_U8 u8MIUSel)8555 void Hal_SC_Set_T3D_MiuSelectExternal(void *pInstance, MS_U8 u8MIUSel)
8556 {
8557 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8558 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8559 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8560 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8561
8562 if(2 == u8MIUSel)//MIU2 = (10) ==> REG_SC_BK7F_18_[10] = 1 && REG_SC_BK7F_10_[10] = 0
8563 {
8564 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
8565 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0, BIT(10));//T3D MIU select low 1 bit
8566 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, BIT(10), BIT(10));//T3D MIU select hight 1 bit
8567 }
8568 else if(1 == u8MIUSel)//MIU1
8569 {
8570 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
8571 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, BIT(10), BIT(10));//T3D MIU select low 1 bit
8572 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, 0, BIT(10));//T3D MIU select hight 1 bit
8573 }
8574 else//MIU0
8575 {
8576 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
8577 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L,0, BIT(10));// T3D MIU select low 1 bit
8578 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, 0, BIT(10));//T3D MIU select hight 1 bit
8579 }
8580 }
8581
8582 //There is the hareware bug on Macan U1 Chip REG_SC_BK10_0D.
8583 //That is replaced by REG_SC_BK68 byMHal_XC_SetVopVtt function.
MHal_XC_SetVopVttByBK68(void * pInstance,MS_U16 u16Vtt,MS_BOOL bMLoadEnable)8584 void MHal_XC_SetVopVttByBK68(void* pInstance, MS_U16 u16Vtt, MS_BOOL bMLoadEnable)
8585 {
8586 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8587 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8588 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8589 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8590 MS_U16 u16temp;
8591
8592 if(bMLoadEnable)
8593 {
8594 u16temp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L);
8595 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_31_L, u16temp & ~BIT(0) & ~BIT(8) | BIT(1), 0xFFFF);
8596 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_32_L, 0xff01 , 0xFFFF);
8597 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_38_L, 0xFA, 0xFFFF);
8598
8599 //RD's suggtion, toggle BK68_33[3] before setting BK68_36 and BK68_37
8600 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_33_L, BIT(3) , BIT(3));
8601 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_33_L, 0 , BIT(3));
8602
8603 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_36_L, u16Vtt , 0xFFFF);
8604 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_37_L, u16Vtt , 0xFFFF);
8605 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_55_L, 0x10 , 0xFFFF);
8606
8607 u16temp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L);
8608 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_31_L, (u16temp & ~BIT(8))|BIT(0) | BIT(1) , 0xFFFF);
8609 Mhal_XC_MLoad_Fire(pInstance, TRUE);
8610 }
8611 else
8612 {
8613 u16temp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L);
8614 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L, u16temp & ~BIT(0) & ~BIT(8) | BIT(1), 0xFFFF);
8615 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_32_L, 0xff01 , 0xFFFF);
8616 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_38_L, 0xFA, 0xFFFF);
8617
8618 //RD's suggtion, toggle BK68_33[3] before setting BK68_36 and BK68_37
8619 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_33_L, BIT(3) , BIT(3));
8620 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_33_L, 0 , BIT(3));
8621
8622 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, u16Vtt , 0xFFFF);
8623 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_37_L, u16Vtt , 0xFFFF);
8624 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_55_L, 0x10 , 0xFFFF);
8625
8626 u16temp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L);
8627 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_31_L, (u16temp & ~BIT(8))|BIT(0) | BIT(1) , 0xFFFF);
8628 }
8629 }
8630
8631 #ifdef UFO_XC_AUTO_DOWNLOAD
_Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID,MS_U32 u32RegAddr,MS_U8 u8Bit,EN_XC_AUTODOWNLOAD_MODE enMode)8632 static E_APIXC_ReturnValue _Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID, MS_U32 u32RegAddr, MS_U8 u8Bit, EN_XC_AUTODOWNLOAD_MODE enMode)
8633 {
8634 switch (enMode)
8635 {
8636 case E_XC_AUTODOWNLOAD_TRIGGER_MODE:
8637 {
8638 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 0, BIT(u8Bit));
8639 break;
8640 }
8641 case E_XC_AUTODOWNLOAD_ENABLE_MODE:
8642 {
8643 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 1 << u8Bit, BIT(u8Bit));
8644 break;
8645 }
8646 default:
8647 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8648 }
8649
8650 return E_APIXC_RET_OK;
8651 }
8652
MHal_XC_AutoDownload_Config(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_PHY phyBaseAddr,EN_XC_AUTODOWNLOAD_MODE enMode)8653 E_APIXC_ReturnValue MHal_XC_AutoDownload_Config(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_PHY phyBaseAddr, EN_XC_AUTODOWNLOAD_MODE enMode)
8654 {
8655 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8656 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8657
8658 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8659 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8660
8661 switch(enClient)
8662 {
8663 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8664 {
8665 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
8666 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
8667 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode = enMode;
8668
8669 //set baseaddr
8670 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, phyBaseAddr & 0x0000FFFF);
8671 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8672
8673 //set work mode
8674 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, enMode);
8675 break;
8676 }
8677 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8678 {
8679 //set baseaddr
8680 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_02_L, phyBaseAddr & 0x0000FFFF);
8681 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_03_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8682
8683 //set work mode
8684 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 3, enMode);
8685 break;
8686 }
8687 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8688 {
8689 //set baseaddr
8690 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_12_L, phyBaseAddr & 0x0000FFFF);
8691 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_13_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8692
8693 //set work mode
8694 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 6, enMode);
8695 break;
8696 }
8697 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8698 {
8699 //set baseaddr
8700 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_16_L, phyBaseAddr & 0x0000FFFF);
8701 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_17_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8702
8703 //set work mode
8704 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 15, enMode);
8705 break;
8706 }
8707 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8708 {
8709 //set baseaddr
8710 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8711 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8712
8713 //set work mode
8714 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8715 break;
8716 }
8717 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8718 {
8719 //set baseaddr
8720 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8721 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8722
8723 //set work mode
8724 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8725 break;
8726 }
8727 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8728 {
8729 //set baseaddr
8730 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8731 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8732
8733 //set work mode
8734 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8735 break;
8736 }
8737 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8738 {
8739 //set baseaddr
8740 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_06_L, phyBaseAddr & 0x0000FFFF);
8741 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_07_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8742
8743 //set work mode
8744 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 5, enMode);
8745 break;
8746 }
8747 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8748 {
8749 //set baseaddr
8750 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_23_L, phyBaseAddr & 0x0000FFFF);
8751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_24_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8752
8753 //set work mode
8754 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, enMode);
8755 break;
8756 }
8757 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8758 {
8759 //set baseaddr
8760 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_33_L, phyBaseAddr & 0x0000FFFF);
8761 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_34_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8762
8763 //set work mode
8764 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, enMode);
8765 break;
8766 }
8767 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8768 {
8769 return E_APIXC_RET_FAIL;
8770 }
8771 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8772 {
8773 return E_APIXC_RET_FAIL;
8774 }
8775 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8776 {
8777 return E_APIXC_RET_FAIL;
8778 }
8779 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8780 default:
8781 {
8782 return E_APIXC_RET_FAIL;
8783 }
8784
8785 }
8786
8787 return E_APIXC_RET_OK;
8788 }
8789
MHal_XC_AutoDownload_Fire(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient)8790 E_APIXC_ReturnValue MHal_XC_AutoDownload_Fire(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient)
8791 {
8792 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8793 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8794
8795 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8796 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8797
8798 switch(enClient)
8799 {
8800 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8801 {
8802 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
8803 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
8804 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
8805 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
8806 MS_U32 u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
8807 pu8BaseAddr += 16 * u32StartAddr;
8808
8809 // set baseaddr
8810 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, (MS_PHY)MS_VA2PA((MS_VIRT)pu8BaseAddr) & 0x0000FFFF);
8811 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (MS_PHY)(MS_VA2PA((MS_VIRT)pu8BaseAddr) >> 16 & 0x0000FFFF), 0x07FF);
8812
8813 // set depth
8814 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2B_L, u32Depth);
8815 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2C_L, u32Depth);
8816
8817 // enable auto download
8818 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, BIT(0));
8819
8820 EN_XC_AUTODOWNLOAD_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode;
8821 if (enMode == E_XC_AUTODOWNLOAD_TRIGGER_MODE)
8822 {
8823 //check auto download done
8824 MS_U32 u32Delayms = 0;
8825 while(((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L) & 0x0001) != 0) && u32Delayms < 500)
8826 {
8827 MsOS_DelayTask(1);
8828 u32Delayms++;
8829 }
8830
8831 // clear buffer
8832 MS_U32 i = 0;
8833 for (i = 0; i < u32Depth; i++)
8834 {
8835 CLEAR_HDR_DATA_FORMAT_1(pu8BaseAddr + i * 16);
8836 }
8837 if (u32Delayms >= 500)
8838 {
8839 printf("Check auto download done timeout.\n");
8840 }
8841 }
8842
8843 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
8844 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
8845 break;
8846 }
8847 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8848 {
8849 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1, BIT(0));
8850 break;
8851 }
8852 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8853 {
8854 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1, BIT(0));
8855 break;
8856 }
8857 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8858 {
8859 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1 << 2, BIT(2));
8860 break;
8861 }
8862 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8863 {
8864 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 1, BIT(1));
8865 break;
8866 }
8867 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8868 {
8869 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1, BIT(0));
8870 break;
8871 }
8872 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8873 {
8874 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1 << 1, BIT(1));
8875 break;
8876 }
8877 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8878 {
8879 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 2, BIT(2));
8880 break;
8881 }
8882 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8883 {
8884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, BIT(0));
8885 break;
8886 }
8887 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8888 {
8889 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, BIT(0));
8890 break;
8891 }
8892 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8893 {
8894 return E_APIXC_RET_FAIL;
8895 }
8896 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8897 {
8898 return E_APIXC_RET_FAIL;
8899 }
8900 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8901 {
8902 return E_APIXC_RET_FAIL;
8903 }
8904 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8905 default:
8906 {
8907 return E_APIXC_RET_FAIL;
8908 }
8909
8910 }
8911
8912 return E_APIXC_RET_OK;
8913 }
8914
_Hal_XC_Auto_Download_Format_Hdr_Data(void * pInstance,EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient,MS_U8 * pu8Data,MS_U32 u32Size,MS_U16 u16StartAddr)8915 static E_APIXC_ReturnValue _Hal_XC_Auto_Download_Format_Hdr_Data(void* pInstance,
8916 EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient, MS_U8* pu8Data, MS_U32 u32Size, MS_U16 u16StartAddr)
8917 {
8918 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8919 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8920
8921 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8922 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8923
8924 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
8925 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
8926 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
8927 unsigned int i = 0;
8928 MS_U32 u32Index = u16StartAddr;
8929 MS_U32 u32WriteNum = 0;
8930 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
8931 pu8BaseAddr += 16 * u16StartAddr;
8932
8933 // update start addr of DRAM
8934 MS_U32 u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
8935 if (u32StartAddr == 0xFFFFFFFF)
8936 {
8937 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u16StartAddr;
8938 }
8939 else
8940 {
8941 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u32StartAddr > u16StartAddr ? u16StartAddr : u32StartAddr;
8942 }
8943
8944 //format&write datas into DRAM
8945 for (i = 0; i < u32Size; )
8946 {
8947 switch (enSubClient)
8948 {
8949 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
8950 {
8951 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
8952 if (u16Value & 0xF000)
8953 {
8954 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, u16Value);
8955 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8956 }
8957 WRITE_TMO_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
8958 i++;
8959 break;
8960 }
8961 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
8962 {
8963 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
8964 WRITE_GAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
8965 i++;
8966 break;
8967 }
8968 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
8969 {
8970 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + i);
8971 if (u32Value & 0xFFF80000)
8972 {
8973 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, (unsigned int)u32Value);
8974 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8975 }
8976 WRITE_DEGAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u32Value);
8977 i++;
8978 break;
8979 }
8980 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
8981 {
8982 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + i);
8983 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + i + 1);
8984 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + i + 2);
8985 MS_U16 u16Subindex = 0;
8986 if(i < _au32_3dlut_entry_num[0])
8987 {
8988 u16Subindex = 0;
8989 }
8990 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1]))
8991 {
8992 u16Subindex = 1;
8993 }
8994 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2]))
8995 {
8996 u16Subindex = 2;
8997 }
8998 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3]))
8999 {
9000 u16Subindex = 3;
9001 }
9002 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4]))
9003 {
9004 u16Subindex = 4;
9005 }
9006 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5]))
9007 {
9008 u16Subindex = 5;
9009 }
9010 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6]))
9011 {
9012 u16Subindex = 6;
9013 }
9014 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6] + _au32_3dlut_entry_num[7]))
9015 {
9016 u16Subindex = 7;
9017 }
9018 WRITE_3DLUT_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Subindex, u16RVal, u16GVal, u16BVal);
9019 i += 3;
9020 break;
9021 }
9022 }
9023 pu8BaseAddr += 16;
9024 u32WriteNum++;
9025 u32Index++;
9026 }
9027
9028 u32Depth = u32Depth > u32WriteNum ? u32Depth : u32WriteNum;
9029 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = u32Depth;
9030
9031 #if DEBUG_HDR
9032 int j = 0;
9033 int l = 0;
9034
9035 printf("\n#####################Dump Input Data####################\n");
9036 for (j = 0; j < u32Size;)
9037 {
9038 printf("The %04dth row: ", u16StartAddr++);
9039 switch (enSubClient)
9040 {
9041 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9042 {
9043 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
9044 printf("%02X \n", u16Value);
9045 j++;
9046 break;
9047 }
9048 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9049 {
9050 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
9051 printf("%02X \n", u16Value);
9052 j++;
9053 break;
9054 }
9055 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9056 {
9057 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + j);
9058 printf("%04X \n", u32Value);
9059 j++;
9060 break;
9061 }
9062 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9063 {
9064 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + j);
9065 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + j + 1);
9066 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + j + 2);
9067 printf("%02X %02X %02X \n", u16RVal, u16GVal, u16BVal);
9068 j += 3;
9069 break;
9070 }
9071 }
9072 printf("\n");
9073 }
9074 printf("\n#####################Dump End####################\n\n");
9075
9076 int k = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
9077 printf("\n#####################Dump DRAM Buffer####################\n");
9078 for (j = 0; j < k; j++)
9079 {
9080 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
9081 printf("\nThe %04dth row: ", j);
9082 for (l = 0; l < 16; l++)
9083 {
9084 switch (enSubClient)
9085 {
9086 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9087 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9088 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9089 {
9090 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
9091 break;
9092 }
9093 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9094 {
9095 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
9096 k = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR;
9097 break;
9098 }
9099 }
9100 }
9101 }
9102 printf("\n#####################Dump End####################\n");
9103 #endif
9104
9105 return E_APIXC_RET_OK;
9106 }
9107
MHal_XC_AutoDownload_Write(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_U8 * pu8Data,MS_U32 u32Size,void * pParam)9108 E_APIXC_ReturnValue MHal_XC_AutoDownload_Write(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_U8* pu8Data, MS_U32 u32Size, void* pParam)
9109 {
9110 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9111 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9112
9113 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9114 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9115
9116 switch(enClient)
9117 {
9118 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
9119 {
9120 XC_AUTODOWNLOAD_FORMAT_INFO* pstFormatInfo = (XC_AUTODOWNLOAD_FORMAT_INFO *)pParam;
9121 MS_U16 u16StartAddr = 0;
9122 MS_U32 u32MaxSize = 0;
9123 switch (pstFormatInfo->enSubClient)
9124 {
9125 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9126 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9127 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9128 {
9129 u32MaxSize = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
9130 break;
9131 }
9132 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9133 {
9134 u32MaxSize = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR * 3;
9135 break;
9136 }
9137 default:
9138 {
9139 printf("Write auto download fail, invaild paramters, subClient: %d\n", pstFormatInfo->enSubClient);
9140 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9141 }
9142 }
9143 if (pstFormatInfo->bEnableRange == TRUE)
9144 {
9145 if (pstFormatInfo->u16StartAddr <= pstFormatInfo->u16EndAddr && pstFormatInfo->u16EndAddr < u32MaxSize
9146 && (pstFormatInfo->u16StartAddr + u32Size - 1) < u32MaxSize)
9147 {
9148 u16StartAddr = pstFormatInfo->u16StartAddr;
9149 }
9150 else
9151 {
9152 printf("Write auto download fail, invaild paramters, size: %d, addr range(enable, start, end) = (%d, %d, %d)\n",
9153 (unsigned int)u32Size, pstFormatInfo->bEnableRange, pstFormatInfo->u16StartAddr, pstFormatInfo->u16EndAddr);
9154 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9155 }
9156 }
9157 else
9158 {
9159 if (u32Size > u32MaxSize)
9160 {
9161 printf("Write auto download fail, invaild paramters, size: %d\n", (unsigned int)u32Size);
9162 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9163 }
9164 }
9165 return _Hal_XC_Auto_Download_Format_Hdr_Data(pInstance, pstFormatInfo->enSubClient, pu8Data, u32Size, u16StartAddr);
9166 }
9167 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
9168 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
9169 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
9170 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
9171 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
9172 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
9173 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
9174 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
9175 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
9176 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
9177 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
9178 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
9179 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
9180 default:
9181 {
9182 return E_APIXC_RET_FAIL;
9183 }
9184
9185 }
9186
9187 return E_APIXC_RET_OK;
9188 }
9189
MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_BOOL * pbSupported)9190 E_APIXC_ReturnValue MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_BOOL *pbSupported)
9191 {
9192 switch(enClient)
9193 {
9194 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
9195 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
9196 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
9197 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
9198 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
9199 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
9200 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
9201 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
9202 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
9203 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
9204 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
9205 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
9206 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
9207 {
9208 *pbSupported = TRUE;
9209 break;
9210 }
9211 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
9212 default:
9213 {
9214 *pbSupported = FALSE;
9215 break;
9216 }
9217
9218 }
9219
9220 return E_APIXC_RET_OK;
9221 }
9222 #endif
9223
9224 #ifdef UFO_XC_HDR
9225 #if (UFO_XC_HDR_VERSION >= 2)
_Hal_XC_HDR_UpdateDMAMode(void * pInstance)9226 static E_APIXC_ReturnValue _Hal_XC_HDR_UpdateDMAMode(void* pInstance)
9227 {
9228 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9229 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9230
9231 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9232 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9233
9234 EN_XC_HDR_COLOR_FORMAT enColorFormat = pXCResourcePrivate->stdrvXC_Display._enColorFormat;
9235 EN_XC_HDR_DMA_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stDMAConfigInfo.enMode;
9236
9237 switch (enColorFormat)
9238 {
9239 case E_XC_HDR_COLOR_YUV422:
9240 {
9241 // set dma mode
9242 if (enMode == E_XC_HDR_DMA_MODE_12BIT)
9243 {
9244 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 0, 0x0003);
9245 }
9246 else if (enMode == E_XC_HDR_DMA_MODE_8BIT)
9247 {
9248 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 2, 0x0003);
9249 }
9250 else if (enMode == E_XC_HDR_DMA_MODE_10BIT)
9251 {
9252 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 3, 0x0003);
9253 }
9254 break;
9255 }
9256 case E_XC_HDR_COLOR_YUV444:
9257 {
9258 if (enMode == E_XC_HDR_DMA_MODE_10BIT)
9259 {
9260 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 1, 0x0003);
9261 }
9262 break;
9263 }
9264 case E_XC_HDR_COLOR_YUV420:
9265 case E_XC_HDR_COLOR_RGB:
9266 default:
9267 {
9268 break;
9269 }
9270 }
9271
9272 return E_APIXC_RET_OK;
9273 }
9274
MHal_XC_HDR_Control(void * pInstance,EN_XC_HDR_CTRL_TYPE enCtrlType,void * pParam)9275 E_APIXC_ReturnValue MHal_XC_HDR_Control(void* pInstance, EN_XC_HDR_CTRL_TYPE enCtrlType, void *pParam)
9276 {
9277 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9278 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9279
9280 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9281 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9282
9283 switch(enCtrlType)
9284 {
9285 case E_XC_HDR_CTRL_CONFIG_DMA:
9286 case E_XC_HDR_CTRL_SET_COLOR_FORMAT:
9287 {
9288 _Hal_XC_HDR_UpdateDMAMode(pInstance);
9289 break;
9290 }
9291 case E_XC_HDR_CTRL_INIT_DMA:
9292 {
9293 MS_U8 u8MIUSel = 0;
9294 XC_HDR_DMA_INIT_INFO stDMAInitInfo = *(XC_HDR_DMA_INIT_INFO *)pParam;
9295 _phy_to_miu_offset(u8MIUSel, stDMAInitInfo.phyBaseAddr, stDMAInitInfo.phyBaseAddr);
9296 if (stDMAInitInfo.u32Size != 0)
9297 {
9298 // set IPM/OPM addr
9299 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_08_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9300 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_09_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9301 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_10_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9302 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_11_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9303 // set miu
9304 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_05_L, u8MIUSel << 4, BMASK(5:4));
9305 // set limit addr
9306 // enable limit
9307 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_50_L, 1, BIT(0));
9308 // min addr
9309 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_52_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9310 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_53_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9311 // max addr
9312 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_54_L, (stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1);
9313 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_55_L, ((stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1) >> 16, 0x01FF);
9314 }
9315 break;
9316 }
9317 case E_XC_HDR_CTRL_ENABLE:
9318 case E_XC_HDR_CTRL_SET_TYPE:
9319 case E_XC_HDR_CTRL_SET_3DLUT:
9320 case E_XC_HDR_CTRL_SET_OTT_SHARE_MEMORY:
9321 case E_XC_HDR_CTRL_SET_OPEN_METADATA:
9322 default:
9323 {
9324 break;
9325 }
9326 }
9327
9328 return E_APIXC_RET_OK;
9329 }
9330
MHal_XC_DolbySWBonded(void * pInstance)9331 BOOL MHal_XC_DolbySWBonded(void *pInstance)
9332 {
9333 MS_U16 u16OldVal = 0;
9334 MS_U16 u16Val = 0;
9335 MS_U32 u32Count = 0;
9336 MS_U16 u16DolbySWBondStatus;
9337
9338 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9339 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9340
9341 u16OldVal = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L);
9342 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, 0x6f<<2, 0x1FFF);
9343 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, 0, BIT(15));
9344 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, BIT(13), BIT(13));
9345 u16Val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, BIT(13));
9346
9347 while (u16Val & BIT(13))
9348 {
9349 u32Count ++;
9350 MsOS_DelayTask(10);
9351
9352 if(u32Count > 10)
9353 {
9354 break;
9355 }
9356 u16Val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, BIT(13));
9357 }
9358 u16DolbySWBondStatus = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_2C_L);
9359 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_28_L, u16OldVal);
9360
9361 if(u16DolbySWBondStatus & BIT(0))
9362 {
9363 u16DolbySWBondStatus = FALSE;
9364 }
9365 else
9366 {
9367 u16DolbySWBondStatus = (u16DolbySWBondStatus & BIT(4)) > 0? TRUE : FALSE;
9368 }
9369
9370 return u16DolbySWBondStatus;
9371 }
9372
9373
9374
MHal_XC_HDR_GetCaps(void * pInstance,XC_HDR_SUPPORTED_CAPS * pstHDRCaps)9375 E_APIXC_ReturnValue MHal_XC_HDR_GetCaps(void *pInstance, XC_HDR_SUPPORTED_CAPS *pstHDRCaps)
9376 {
9377 EN_XC_HDR_TYPE enHDRType = pstHDRCaps->enHDRType;
9378
9379 switch (enHDRType)
9380 {
9381 case E_XC_HDR_TYPE_OPEN:
9382 {
9383 pstHDRCaps->bSupported = TRUE;
9384 break;
9385 }
9386 case E_XC_HDR_TYPE_DOLBY:
9387 {
9388 if(MHal_XC_DolbySWBonded(pInstance)) //SW bonded
9389 {
9390 pstHDRCaps->bSupported = FALSE;
9391 }
9392 else if (MDrv_AUTH_IPCheck(IPAUTH_DOLBY_HDR_PIN) == FALSE)
9393 {
9394 pstHDRCaps->bSupported = FALSE;
9395 }
9396 else
9397 {
9398 pstHDRCaps->bSupported = TRUE;
9399 }
9400 break;
9401 }
9402 case E_XC_HDR_TYPE_TECHNICOLOR:
9403 {
9404 pstHDRCaps->bSupported = FALSE;
9405 break;
9406 }
9407 case E_XC_HDR_TYPE_HLG:
9408 {
9409 pstHDRCaps->bSupported = FALSE;
9410 break;
9411 }
9412 default:
9413 {
9414 pstHDRCaps->bSupported = FALSE;
9415 }
9416 }
9417
9418 pstHDRCaps->s32MaxLuminanceData = -1;
9419 pstHDRCaps->s32MinLuminanceData = -1;
9420 pstHDRCaps->s32MaxFrameAveLumiance = -1;
9421
9422 return E_APIXC_RET_OK;
9423 }
9424 #endif
9425 #endif
Hal_SC_Set_YLock(void * pInstance,MS_BOOL bInterlace,MS_BOOL bFBL,MS_BOOL bR_FBL)9426 void Hal_SC_Set_YLock(void *pInstance, MS_BOOL bInterlace, MS_BOOL bFBL, MS_BOOL bR_FBL)
9427 {
9428 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9429 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9430
9431 // no matter progressive or interlace
9432 // in FB mode we set to 0x5 (originally progressive = 0x3, interlace = 0x4)
9433 // but in Open HDR mode(with MVOP DE mode)
9434 // if we set to 3 or 4 it will be too late for autodownload to work.
9435 // so we change to 5 based upon CC's experiement suggestion.
9436 //
9437 // Dolby HDR need to use DS, and DS index depth is changed to max
9438 // Then some movies will show garbage when start play
9439 // DS need more time to set more DS cmds
9440 // Joeanna's experiement suggestion:
9441 // BK1301_09[3:0] = 0xC (Y_Lock)
9442 // BK131F_10[7:4] = 0xE (DMA request)
9443 // BK131F_05[9:0] = 0x3FF (reg_ds_dma_wd_timer)
9444 if(bFBL || bR_FBL)
9445 {
9446 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0x2, BITMASK(3:0));
9447 }
9448 else
9449 {
9450 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0xC, BITMASK(3:0));
9451 }
9452 }
9453 #undef MHAL_SC_C
9454