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Searched defs:ZERO_ENABLE (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vif/hal/maxim/vif/
H A DregVIF.h369 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/macan/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/messi/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/maserati/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/mainz/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/maldives/vif/
H A DregVIF.h364 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/manhattan/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/mooney/vif/
H A DregVIF.h369 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/mustang/vif/
H A DregVIF.h369 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/kano/vif/
H A DregVIF.h361 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/M7621/vif/
H A DregVIF.h369 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro
/utopia/UTPA2-700.0.x/modules/vif/hal/M7821/vif/
H A DregVIF.h367 #define ZERO_ENABLE (DBB1_REG_BASE+0x48) macro