1
2 #define _XC_C_
3
4 #include "MsTypes.h"
5 #ifndef MSOS_TYPE_LINUX_KERNEL
6 #include <stdio.h>
7 #include <string.h>
8 #endif
9 #include "MsCommon.h"
10 #include "utopia.h"
11 #include "utopia_dapi.h"
12 #include "drvXC_IOPort.h"
13 #include "apiXC.h"
14 #include "mvideo_context.h"
15 #include "apiXC_Adc.h"
16 #include "apiXC_Auto.h"
17 #include "apiXC_ModeParse.h"
18 #include "drv_sc_display.h"
19 #include "drv_sc_isr.h"
20 #include "apiXC_PCMonitor.h"
21 #include "drvXC_HDMI_if.h"
22 #include "mhal_xc_chip_config.h"
23 #include "drv_sc_ip.h"
24 #if (LD_ENABLE==1)
25 #include "mdrv_ld.h"
26 #include "mdrv_ldalgo.h"
27 #endif
28 #include "mdrv_sc_3d.h"
29 #include "drv_sc_menuload.h"
30 #include "drvXC_ADC_Internal.h"
31 #include "mhal_sc.h"
32 #if FRC_INSIDE
33 #include "mdrv_frc.h"
34 #include "mhal_frc.h"
35 #endif
36 #include "XC_private.h"
37 #include "apiXC_v2.h"
38 #include "apiXC_Adc_v2.h"
39 #include "apiXC_Auto_v2.h"
40 #include "apiXC_ModeParse_v2.h"
41 #include "apiXC_PCMonitor_v2.h"
42 #include "drvXC_HDMI_if_v2.h"
43 #include "xc_hwreg_utility2.h"
44
45 #include "utopia_api_database.h"
46 #include "halCHIP.h"
47
48 #define XC_RES_NAME_MAX_LEN 64
49 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
50 // ========== Global definition ==========
51 void* pModuleXC = NULL;
52 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
53 extern MS_U32 u32SetWindowTime;
54 #endif
55 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
56 static MS_BOOL bIsXCRegistered = FALSE;
57 #endif
58 #ifdef MSOS_TYPE_LINUX_KERNEL
59 void* pInstanceXCStr = NULL;
XCStr(MS_U32 u32PowerState,void * pModule)60 MS_U32 XCStr(MS_U32 u32PowerState, void* pModule)
61 {
62 MS_U32 u32Return=UTOPIA_STATUS_FAIL;
63 stXC_SET_POWERSTATE XCArgs;
64
65 switch(u32PowerState)
66 {
67 case E_POWER_SUSPEND:
68 if (pInstanceXCStr == NULL)
69 {
70 if(UtopiaOpen(MODULE_XC, &pInstanceXCStr, 0, NULL) != UTOPIA_STATUS_SUCCESS)
71 {
72 printf("UtopiaOpen XC failed\n");
73 return UTOPIA_STATUS_FAIL;
74 }
75 }
76 XCArgs.enPowerState = u32PowerState;
77 XCArgs.u32ReturnValue = UTOPIA_STATUS_FAIL;
78
79 if(UtopiaIoctl(pInstanceXCStr, E_XC_CMD_SET_POWERSTATE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
80 {
81 printf("Obtain XC engine fail\n");
82 return UTOPIA_STATUS_FAIL;
83 }
84 u32Return=XCArgs.u32ReturnValue;
85 break;
86 case E_POWER_RESUME:
87 if (pInstanceXCStr == NULL)
88 {
89 if(UtopiaOpen(MODULE_XC, &pInstanceXCStr, 0, NULL) != UTOPIA_STATUS_SUCCESS)
90 {
91 printf("UtopiaOpen XC failed\n");
92 return UTOPIA_STATUS_FAIL;
93 }
94 }
95 XCArgs.enPowerState = u32PowerState;
96 XCArgs.u32ReturnValue = UTOPIA_STATUS_FAIL;
97
98 if(UtopiaIoctl(pInstanceXCStr, E_XC_CMD_SET_POWERSTATE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
99 {
100 printf("Obtain XC engine fail\n");
101 return UTOPIA_STATUS_FAIL;
102 }
103 u32Return=XCArgs.u32ReturnValue;
104 break;
105 default:
106 printf("[%s][%d] PowerState:%lx not Implement now!!!\n",__FUNCTION__,__LINE__,u32PowerState);
107 break;
108 }
109 return u32Return;
110 }
111 #endif
112
113 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
114
_XCMdbloctl_Cat_OPTEE(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)115 static void _XCMdbloctl_Cat_OPTEE(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
116 {
117 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
118 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
119 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
120 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
121 XC_RESOURCE_PRIVATE_FOR_TEE* pXCResourcePrivateForTee = NULL;
122 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivateForTee));
123
124 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler OPTEE Info -----------------\n");
125 MdbPrint(paraGetInfo->u64ReqHdl,"OPTEE REE enable : %s\n", pXCResourcePrivate->sthal_Optee.op_tee_xc[MAIN_WINDOW].isEnable==FALSE?"TRUE":"FALSE");
126 MdbPrint(paraGetInfo->u64ReqHdl,"OPTEE TEE enable : %s\n", pXCResourcePrivateForTee->sthal_Optee.op_tee_xc[MAIN_WINDOW].isEnable==TRUE?"TRUE":"FALSE");
127 MdbPrint(paraGetInfo->u64ReqHdl,"OPTEE Buffer Address : 0x%lx\n", pXCResourcePrivate->sthal_Optee.op_tee_xc[MAIN_WINDOW].drams_data[0].address);
128 MdbPrint(paraGetInfo->u64ReqHdl,"OPTEE Buffer Length : %x\n", pXCResourcePrivate->sthal_Optee.op_tee_xc[MAIN_WINDOW].drams_data[0].length);
129 }
130
_XCMdbloctl_Cat_3D(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)131 static void _XCMdbloctl_Cat_3D(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
132 {
133 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
134 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
135 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
136 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
137 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler 3D Info -----------------\n");
138 if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_FRAME_PACKING)
139 {
140 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_FRAME_PACKING\n");
141 }
142 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_FIELD_ALTERNATIVE)
143 {
144 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_FIELD_ALTERNATIVE\n");
145 }
146 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_LINE_ALTERNATIVE)
147 {
148 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_LINE_ALTERNATIVE\n");
149 }
150 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_SIDE_BY_SIDE_FULL)
151 {
152 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_SIDE_BY_SIDE_FULL\n");
153 }
154 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_L_DEPTH)
155 {
156 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_L_DEPTH\n");
157 }
158 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_L_DEPTH_GRAPHICS_GRAPHICS_DEPTH)
159 {
160 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_L_DEPTH_GRAPHICS_GRAPHICS_DEPTH\n");
161 }
162 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_TOP_BOTTOM)
163 {
164 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_TOP_BOTTOM\n");
165 }
166 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_SIDE_BY_SIDE_HALF)
167 {
168 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_SIDE_BY_SIDE_HALF\n");
169 }
170 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_CHECK_BORAD)
171 {
172 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_CHECK_BORAD\n");
173 }
174 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_MODE_USER)
175 {
176 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_MODE_USER\n");
177 }
178 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_FRAME_ALTERNATIVE)
179 {
180 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_FRAME_ALTERNATIVE\n");
181 }
182 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_SIDE_BY_SIDE_HALF_INTERLACE)
183 {
184 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_SIDE_BY_SIDE_HALF_INTERLACE\n");
185 }
186 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_FRAME_PACKING_OPT)
187 {
188 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_FRAME_PACKING_OPT\n");
189 }
190 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_TOP_BOTTOM_OPT)
191 {
192 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_TOP_BOTTOM_OPT\n");
193 }
194 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D)
195 {
196 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_NORMAL_2D\n");
197 }
198 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D_INTERLACE)
199 {
200 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_NORMAL_2D_INTERLACE\n");
201 }
202 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D_INTERLACE_PTP)
203 {
204 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_NORMAL_2D_INTERLACE_PTP\n");
205 }
206 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_SIDE_BY_SIDE_HALF_INTERLACE_OPT)
207 {
208 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_SIDE_BY_SIDE_HALF_INTERLACE_OPT\n");
209 }
210 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D_HW)
211 {
212 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_NORMAL_2D_HW\n");
213 }
214 else if(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_PIXEL_ALTERNATIVE)
215 {
216 MdbPrint(paraGetInfo->u64ReqHdl,"3D input format : E_XC_3D_INPUT_PIXEL_ALTERNATIVE\n");
217 }
218
219 if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_MODE_NONE)
220 {
221 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_MODE_NONE\n");
222 }
223 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
224 {
225 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_LINE_ALTERNATIVE\n");
226 }
227 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_TOP_BOTTOM)
228 {
229 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_TOP_BOTTOM\n");
230 }
231 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF)
232 {
233 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF\n");
234 }
235 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE)
236 {
237 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_ALTERNATIVE\n");
238 }
239 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_L)
240 {
241 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_L\n");
242 }
243 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_R)
244 {
245 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_R\n");
246 }
247 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_NOFRC)
248 {
249 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_NOFRC\n");
250 }
251 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_CHECKBOARD_HW)
252 {
253 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_CHECKBOARD_HW\n");
254 }
255 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_LINE_ALTERNATIVE_HW)
256 {
257 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_LINE_ALTERNATIVE_HW\n");
258 }
259 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_PIXEL_ALTERNATIVE_HW)
260 {
261 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_PIXEL_ALTERNATIVE_HW\n");
262 }
263 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_L_HW)
264 {
265 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_L_HW\n");
266 }
267 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_R_HW)
268 {
269 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_R_HW\n");
270 }
271 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_HW)
272 {
273 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_HW\n");
274 }
275 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
276 {
277 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_TOP_BOTTOM_HW\n");
278 }
279 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
280 {
281 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW\n");
282 }
283 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_PACKING)
284 {
285 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_PACKING\n");
286 }
287 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_LLRR)
288 {
289 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_LLRR\n");
290 }
291 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_LLRR_HW)
292 {
293 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_LLRR_HW\n");
294 }
295 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_TOP_TOP)
296 {
297 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_TOP_TOP\n");
298 }
299 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_BOTTOM_BOTTOM)
300 {
301 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_BOTTOM_BOTTOM\n");
302 }
303 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_LEFT_LEFT)
304 {
305 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_LEFT_LEFT\n");
306 }
307 else if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_RIGHT_RIGHT)
308 {
309 MdbPrint(paraGetInfo->u64ReqHdl,"3D output format : E_XC_3D_OUTPUT_RIGHT_RIGHT\n");
310 }
311
312 if(((pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D)||(pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_NORMAL_2D_HW))&&(E_XC_3D_OUTPUT_MODE_NONE != pXCResourcePrivate->stdrvXC_3D._eOutput3DMode))
313 {
314 MdbPrint(paraGetInfo->u64ReqHdl,"2D to 3D status : TRUE\n");
315 }
316 else
317 {
318 MdbPrint(paraGetInfo->u64ReqHdl,"2D to 3D status : FALSE\n");
319 }
320 MdbPrint(paraGetInfo->u64ReqHdl,"Output timing : %d_%d_%d\n", pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width,
321 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq);
322 }
323
_XCMdbloctl_Cat_TGEN(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)324 static void _XCMdbloctl_Cat_TGEN(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
325 {
326 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler TGEN Info -----------------\n");
327 MdbPrint(paraGetInfo->u64ReqHdl,"Hsync width : %d\n", MApi_XC_R2BYTEMSK(REG_SC_BK10_01_L, 0xFF));
328 MdbPrint(paraGetInfo->u64ReqHdl,"Vsync position : (%d,%d)\n", MApi_XC_R2BYTEMSK(REG_SC_BK10_02_L, 0x7FF)+(MApi_XC_R2BYTEMSK(REG_SC_BK10_02_L, 0x1000)>>1), MApi_XC_R2BYTEMSK(REG_SC_BK10_03_L, 0x1FFF));
329 MdbPrint(paraGetInfo->u64ReqHdl,"HDE position : (%d,%d)\n", MApi_XC_R2BYTEMSK(REG_SC_BK10_04_L, 0x3FFF), MApi_XC_R2BYTEMSK(REG_SC_BK10_05_L, 0x3FFF));
330 MdbPrint(paraGetInfo->u64ReqHdl,"VDE position : (%d,%d)\n", MApi_XC_R2BYTEMSK(REG_SC_BK10_06_L, 0x1FFF), MApi_XC_R2BYTEMSK(REG_SC_BK10_07_L, 0x1FFF));
331 MdbPrint(paraGetInfo->u64ReqHdl,"Vsync control mode : %s\n", MApi_XC_R2BYTEMSK(REG_SC_BK10_05_L, 0x01)==0x00?"Auto":"Manual");
332 }
333
_XCMdbloctl_Cat_HDR(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)334 static void _XCMdbloctl_Cat_HDR(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
335 {
336 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler HDR Info -----------------\n");
337 //MdbPrint(paraGetInfo->u64ReqHdl,"HDR type : \n");
338 MdbPrint(paraGetInfo->u64ReqHdl,"Gamma/Degamma autodownload status : %s\n", MApi_XC_R2BYTEMSK(REG_SC_BK7A_01_L, BIT(0))==0?"On":"Off");
339 MdbPrint(paraGetInfo->u64ReqHdl,"TMO autodownload status : %s\n", MApi_XC_R2BYTEMSK(REG_SC_BK7A_02_L, BIT(2))==0?"On":"Off");
340 MdbPrint(paraGetInfo->u64ReqHdl,"3D LUT autodownload status : %s\n", MApi_XC_R2BYTEMSK(REG_SC_BK7A_02_L, BIT(4))==0?"On":"Off");
341 MdbPrint(paraGetInfo->u64ReqHdl,"XC handshake status : %s\n", MApi_XC_R2BYTE(REG_SC_BK02_10_L)==0x25?"Off":"On");
342 /*MdbPrint(paraGetInfo->u64ReqHdl,"CRC status : \n");
343 MdbPrint(paraGetInfo->u64ReqHdl,"R2Y status : \n");
344 MdbPrint(paraGetInfo->u64ReqHdl,"Y2R status : \n");
345 MdbPrint(paraGetInfo->u64ReqHdl,"MM HDR vdec version number : \n");
346 MdbPrint(paraGetInfo->u64ReqHdl,"Autodownload fail bit : \n");
347 MdbPrint(paraGetInfo->u64ReqHdl,"Dolby Global dimming value : \n");
348 MdbPrint(paraGetInfo->u64ReqHdl,"Dolby Global dimming delay count : \n");
349 MdbPrint(paraGetInfo->u64ReqHdl,"set_HDRDS_info average time : \n");
350 MdbPrint(paraGetInfo->u64ReqHdl,"set_HDRDS_info peak time : \n");
351 MdbPrint(paraGetInfo->u64ReqHdl,"HDR HSize : \n");
352 MdbPrint(paraGetInfo->u64ReqHdl,"HDR VSize : \n");*/
353 }
354
_XCMdbloctl_Cat_MEMC(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)355 static void _XCMdbloctl_Cat_MEMC(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
356 {
357 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
358 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
359 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
360 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
361 void *pModule;
362 UtopiaInstanceGetModule(pInstance, &pModule);
363 XC_REGS_SAVE_AREA *pXCResourceStr = NULL;
364 UtopiaModuleGetSTRPrivate(pModule, (void**)&pXCResourceStr);
365 MS_U8 u8sel, u8temp = 0;
366
367 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler MEMC Info -----------------\n");
368 MdbPrint(paraGetInfo->u64ReqHdl,"FRC enable : %s\n", MApi_XC_R2BYTEMSK(REG_SC_BK68_40_L, BIT(2))==BIT(2)?"On":"Off");
369 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC level : %d\n", R2BYTE(0x422c44UL));
370 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC status : %s\n", R2BYTEMSK(0x422c80UL, BIT(0))==BIT(0)?"On":"Off");
371 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC memory size(L) : %d\n", pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_MEMC_MemSize);
372 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC memory size(R) : %d\n", pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_R2_MemSize);
373 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC memory size(PQ) : %d\n", pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_ME1_MemSize);
374 _phy_to_miu_offset(u8sel, u8temp, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_MEMC_MemAddr);
375 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC MIU number(L) : MIU%d\n", u8sel);
376 _phy_to_miu_offset(u8sel, u8temp, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_R2_MemAddr);
377 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC MIU number(R) : MIU%d\n", u8sel);
378 _phy_to_miu_offset(u8sel, u8temp, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u32FRC_ME1_MemAddr);
379 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC MIU number(PQ) : MIU%d\n", u8sel);
380 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_DUAL_MIU)
381 {
382 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC dual miu : TRUE \n");
383 }
384 else
385 {
386 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC dual miu : FALSE \n");
387 }
388 MdbPrint(paraGetInfo->u64ReqHdl,"MEMC in/out frame rate : %d:%d \n", pXCResourceStr->pTimingInfo.u16InputVFreq, gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC);
389 }
390
_XCMdbloctl_Cat_FrameLock(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)391 static void _XCMdbloctl_Cat_FrameLock(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
392 {
393 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
394 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
395 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
396 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
397 void *pModule;
398 UtopiaInstanceGetModule(pInstance, &pModule);
399 XC_REGS_SAVE_AREA *pXCResourceStr = NULL;
400 UtopiaModuleGetSTRPrivate(pModule, (void**)&pXCResourceStr);
401
402 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler Frame Lock Info -----------------\n");
403 MdbPrint(paraGetInfo->u64ReqHdl,"H total : %d\n", MApi_XC_R2BYTE(REG_SC_BK10_0C_L));
404 MdbPrint(paraGetInfo->u64ReqHdl,"V total : %d\n", MApi_XC_R2BYTE(REG_SC_BK10_0D_L));
405 MdbPrint(paraGetInfo->u64ReqHdl,"Input frame rate : %d\n", pXCResourceStr->pTimingInfo.u16InputVFreq);
406 MdbPrint(paraGetInfo->u64ReqHdl,"Output frame rate : %d\n", gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC);
407 MdbPrint(paraGetInfo->u64ReqHdl,"Lock ivs:ovs : %d:%d\n", R2BYTEMSK(0x103118UL,0x0F00)>>8, R2BYTEMSK(0x103118UL,0xF000)>>11);
408 if(R2BYTEMSK(0x1031E0UL,BIT(15))==BIT(15))
409 {
410 MdbPrint(paraGetInfo->u64ReqHdl,"Lock mode : lockvfreq\n");
411 }
412 else if(R2BYTEMSK(0x1031F0UL,BIT(12))==BIT(12))
413 {
414 MdbPrint(paraGetInfo->u64ReqHdl,"Lock mode : ivs_ovs\n");
415 }
416 else if(R2BYTEMSK(0x1031FCUL,BIT(15))==BIT(15))
417 {
418 MdbPrint(paraGetInfo->u64ReqHdl,"Lock mode : spread\n");
419 }
420 else
421 {
422 MdbPrint(paraGetInfo->u64ReqHdl,"Lock mode : lockphase\n");
423 }
424 }
_XCMdbloctl_Cat_SetWindow(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)425 static void _XCMdbloctl_Cat_SetWindow(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
426 {
427 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
428 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
429 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
430 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
431
432 MS_U32 u32address;
433 MS_U8 u8temp = 0, u8sel;
434
435 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler Setwindow Info -----------------\n");
436 MdbPrint(paraGetInfo->u64ReqHdl,"Capture window : (%d,%d) %dx%d\n", gSrcInfo[MAIN_WINDOW].stCapWin.x, gSrcInfo[MAIN_WINDOW].stCapWin.y, gSrcInfo[MAIN_WINDOW].stCapWin.width, gSrcInfo[MAIN_WINDOW].stCapWin.height);
437 MdbPrint(paraGetInfo->u64ReqHdl,"Crop window : (%d,%d) %dx%d\n", gSrcInfo[MAIN_WINDOW].stCropWin.x, gSrcInfo[MAIN_WINDOW].stCropWin.y, gSrcInfo[MAIN_WINDOW].stCropWin.width, gSrcInfo[MAIN_WINDOW].stCropWin.height);
438 MdbPrint(paraGetInfo->u64ReqHdl,"Display window : (%d,%d) %dx%d\n", gSrcInfo[MAIN_WINDOW].stDispWin.x, gSrcInfo[MAIN_WINDOW].stDispWin.y, gSrcInfo[MAIN_WINDOW].stDispWin.width, gSrcInfo[MAIN_WINDOW].stDispWin.height);
439 MdbPrint(paraGetInfo->u64ReqHdl,"Pre-H cus scaling : %s (%d->%d)\n", (gSrcInfo[MAIN_WINDOW].Status2.bPreHCusScaling==TRUE)?"TRUE":"FALSE", gSrcInfo[MAIN_WINDOW].Status2.u16PreHCusScalingSrc, gSrcInfo[MAIN_WINDOW].Status2.u16PreHCusScalingDst);
440 MdbPrint(paraGetInfo->u64ReqHdl,"Pre-V cus scaling : %s (%d->%d)\n", (gSrcInfo[MAIN_WINDOW].Status2.bPreVCusScaling==TRUE)?"TRUE":"FALSE", gSrcInfo[MAIN_WINDOW].Status2.u16PreVCusScalingSrc, gSrcInfo[MAIN_WINDOW].Status2.u16PreVCusScalingDst);
441 MdbPrint(paraGetInfo->u64ReqHdl,"Post-H cus scaling : %s (%d->%d)\n", (gSrcInfo[MAIN_WINDOW].bHCusScaling==TRUE)?"TRUE":"FALSE", gSrcInfo[MAIN_WINDOW].u16HCusScalingSrc, gSrcInfo[MAIN_WINDOW].u16HCusScalingDst);
442 MdbPrint(paraGetInfo->u64ReqHdl,"Post-V cus scaling : %s (%d->%d)\n", (gSrcInfo[MAIN_WINDOW].bVCusScaling==TRUE)?"TRUE":"FALSE", gSrcInfo[MAIN_WINDOW].u16VCusScalingSrc, gSrcInfo[MAIN_WINDOW].u16VCusScalingDst);
443 #if defined (__aarch64__)
444 MdbPrint(paraGetInfo->u64ReqHdl,"Memory size : %x\n", pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32Main_FB_Size);
445 #else
446 MdbPrint(paraGetInfo->u64ReqHdl,"Memory size : %tx\n", (ptrdiff_t)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32Main_FB_Size);
447 #endif
448 MdbPrint(paraGetInfo->u64ReqHdl,"Frame count : %d\n", MApi_XC_R2BYTEMSK(REG_SC_BK12_19_L, 0x000F));
449 MdbPrint(paraGetInfo->u64ReqHdl,"RW diff count : %d\n", (MApi_XC_R2BYTEMSK(REG_SC_BK12_07_L, 0xE000)>>13));
450 MdbPrint(paraGetInfo->u64ReqHdl,"2-steps scaling status : %s\n", (MApi_XC_IsSupport2StepScaling()==TRUE)?"TRUE":"FALSE");
451 u32address = (MS_U32)((MApi_XC_R2BYTE(REG_SC_BK12_09_L))<<16) | (MS_U32)(MApi_XC_R2BYTE(REG_SC_BK12_08_L));
452 _phy_to_miu_offset(u8sel, u8temp, u32address);
453 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler MIU number : MIU%d\n", u8sel);
454 MdbPrint(paraGetInfo->u64ReqHdl,"Memory IPM address : 0x%lx\n", u32address);
455 u32address = (MS_U32)((MApi_XC_R2BYTE(REG_SC_BK12_11_L))<<16) | (MS_U32)(MApi_XC_R2BYTE(REG_SC_BK12_10_L));
456 MdbPrint(paraGetInfo->u64ReqHdl,"Memory OPM address : 0x%lx\n", u32address);
457 MdbPrint(paraGetInfo->u64ReqHdl,"IPM Offset : %d\n", MApi_XC_R2BYTE(REG_SC_BK12_0E_L));
458 MdbPrint(paraGetInfo->u64ReqHdl,"IPM Fetch : %d\n", MApi_XC_R2BYTE(REG_SC_BK12_0F_L));
459 MdbPrint(paraGetInfo->u64ReqHdl,"OPM Offset : %d\n", MApi_XC_R2BYTE(REG_SC_BK12_16_L));
460 MdbPrint(paraGetInfo->u64ReqHdl,"OPM Fetch : %d\n", MApi_XC_R2BYTE(REG_SC_BK12_17_L));
461 MdbPrint(paraGetInfo->u64ReqHdl,"Input DE H size : %d\n", Hal_SC_ip_de_hend_info(pInstance, MAIN_WINDOW)-Hal_SC_ip_de_hstart_info(pInstance, MAIN_WINDOW)+1);
462 MdbPrint(paraGetInfo->u64ReqHdl,"Input DE V size : %d\n", Hal_SC_ip_de_vend_info(pInstance, MAIN_WINDOW)-Hal_SC_ip_de_vstart_info(pInstance, MAIN_WINDOW)+1);
463 }
464
_XCMdbloctl_Cat_PQ(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)465 static void _XCMdbloctl_Cat_PQ(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
466 {/*
467 void *pInstance, *pModule;
468 pInstance = UtopiaModuleGetLocalInstantList(MODULE_ACE, pInstance);
469 UtopiaInstanceGetModule(pInstance, &pModule);
470 ACE_REGS_SAVE_AREA *pACEResourceStr = NULL;
471 UtopiaModuleGetSTRPrivate(pModule, (void**)&pACEResourceStr);*/
472
473 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar Scaler PQ Info -----------------\n");
474 //MdbPrint(paraGetInfo->u64ReqHdl,"Brightness_R : %d, \n", pACEResourceStr->u8Brightness_R);
475 //MdbPrint(paraGetInfo->u64ReqHdl,"Brightness_G : %d, \n", pACEResourceStr->u8Brightness_G);
476 //MdbPrint(paraGetInfo->u64ReqHdl,"Brightness_B : %d, \n", pACEResourceStr->u8Brightness_B);
477 //MdbPrint(paraGetInfo->u64ReqHdl,"Contrast : %d\n", pACEResourceStr->u8Contrast);
478 //MdbPrint(paraGetInfo->u64ReqHdl,"Saturation : %d\n", pACEResourceStr->u8Saturation);
479 //MdbPrint(paraGetInfo->u64ReqHdl,"Hue : %d\n", pACEResourceStr->u8Hue);
480 MdbPrint(paraGetInfo->u64ReqHdl,"UCNR status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK2A_02_L,BIT(15))==BIT(15))?"TRUE":"FALSE");
481 MdbPrint(paraGetInfo->u64ReqHdl,"Compress mode : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK08_01_L,BIT(0))==0)?"TRUE":"FALSE");
482 MdbPrint(paraGetInfo->u64ReqHdl,"DNR status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK12_02_L,BIT(14))==BIT(14))?"TRUE":"FALSE");
483 MdbPrint(paraGetInfo->u64ReqHdl,"DLC status : %s\n", (R2BYTEMSK(0x141A08UL,BIT(7))==BIT(7))?"TRUE":"FALSE");
484 //MdbPrint(paraGetInfo->u64ReqHdl,"DLC window : \n");
485 //MdbPrint(paraGetInfo->u64ReqHdl,"PQ Source type : \n");
486 //MdbPrint(paraGetInfo->u64ReqHdl,"Gamma index : \n");
487 MdbPrint(paraGetInfo->u64ReqHdl,"PQ Gamma Enable : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK10_50_L,BIT(0))==BIT(0))?"TRUE":"FALSE");
488 MdbPrint(paraGetInfo->u64ReqHdl,"Panel Gamma Enable : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK24_26_L,BIT(3))==BIT(3))?"TRUE":"FALSE");
489 }
490
_XCMdbloctl_Cat_DISP(void * pInstance,MDBCMD_GETINFO_PARAMETER * paraGetInfo)491 static void _XCMdbloctl_Cat_DISP(void *pInstance, MDBCMD_GETINFO_PARAMETER *paraGetInfo)
492 {
493 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
494 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
495 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
496 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
497 void *pModule;
498 UtopiaInstanceGetModule(pInstance, &pModule);
499 XC_REGS_SAVE_AREA *pXCResourceStr = NULL;
500 UtopiaModuleGetSTRPrivate(pModule, (void**)&pXCResourceStr);
501
502 MdbPrint(paraGetInfo->u64ReqHdl,"---------------- Mstar DISP In Out Info -----------------\n");
503 MdbPrint(paraGetInfo->u64ReqHdl,"Window enable : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK20_10_L,BIT(0))==BIT(0))?"TRUE":"FALSE"); //main\n");
504 MdbPrint(paraGetInfo->u64ReqHdl,"Mute enable : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK10_19_L, BIT(1))==BIT(1))?"TRUE":"FALSE");
505 MdbPrint(paraGetInfo->u64ReqHdl,"Output resolution : %d_%d_%d_P\n", gSrcInfo[MAIN_WINDOW].stDispWin.width, gSrcInfo[MAIN_WINDOW].stDispWin.height, gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC);
506 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_10BIT_4LANE ||
507 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_8BIT_4LANE)
508 {
509 MdbPrint(paraGetInfo->u64ReqHdl,"Output type : VB1_4lane\n");
510 }
511 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_10BIT_8LANE ||
512 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_8BIT_8LANE)
513 {
514 MdbPrint(paraGetInfo->u64ReqHdl,"Output type : VB1_8lane\n");
515 }
516 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_10BIT_2LANE ||
517 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_VBY1_8BIT_2LANE)
518 {
519 MdbPrint(paraGetInfo->u64ReqHdl,"Output type : VB1_2lane\n");
520 }
521 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_LVDS)
522 {
523 MdbPrint(paraGetInfo->u64ReqHdl,"Output type : LVDS\n");
524 }
525
526 if(IsSrcTypeHDMI(gSrcInfo[0].enInputSourceType))
527 {
528 MdbPrint(paraGetInfo->u64ReqHdl,"Input source type : HDMI\n");
529 }
530 else if(IsSrcTypeATV(gSrcInfo[0].enInputSourceType))
531 {
532 MdbPrint(paraGetInfo->u64ReqHdl,"Input source type : ATV\n");
533 }
534 else if(IsSrcTypeDTV(gSrcInfo[0].enInputSourceType))
535 {
536 MdbPrint(paraGetInfo->u64ReqHdl,"Input source type : DTV\n");
537 }
538 else if(IsSrcTypeStorage(gSrcInfo[0].enInputSourceType))
539 {
540 MdbPrint(paraGetInfo->u64ReqHdl,"Input source type : MM\n");
541 }
542 else if(IsSrcTypeVga(gSrcInfo[0].enInputSourceType))
543 {
544 MdbPrint(paraGetInfo->u64ReqHdl,"Input source type : VGA\n");
545 }
546 MdbPrint(paraGetInfo->u64ReqHdl,"Source resolution : %d_%d_%d_%c\n", gSrcInfo[MAIN_WINDOW].stCapWin.width, gSrcInfo[MAIN_WINDOW].stCapWin.height
547 , pXCResourceStr->pTimingInfo.u16InputVFreq, (gSrcInfo[MAIN_WINDOW].bInterlace==TRUE)?'I':'P');
548 MdbPrint(paraGetInfo->u64ReqHdl,"Input I/P mode status : %s\n", (gSrcInfo[MAIN_WINDOW].bInterlace==TRUE)?"Interface":"Progressive");
549 MdbPrint(paraGetInfo->u64ReqHdl,"Memory color space : %s\n", (gSrcInfo[MAIN_WINDOW].bUseYUVSpace==TRUE)?"YUV":"RGB");
550 MdbPrint(paraGetInfo->u64ReqHdl,"Display size : %d_%d\n", MApi_XC_R2BYTE(REG_SC_BK10_09_L)-MApi_XC_R2BYTE(REG_SC_BK10_08_L)+1,
551 MApi_XC_R2BYTE(REG_SC_BK10_0B_L)-MApi_XC_R2BYTE(REG_SC_BK10_0A_L)+1);
552 MdbPrint(paraGetInfo->u64ReqHdl,"Mirror mode : %s\n", (gSrcInfo[MAIN_WINDOW].Status2.eMirrorMode == TRUE)?"TRUE":"FALSE");
553 if(R2BYTE(0x103154UL) == 0xF4 || R2BYTE(0x103154UL) == 0x1F4)
554 {
555 MdbPrint(paraGetInfo->u64ReqHdl,"Frame lock status : TURE\n");
556 }
557 else
558 {
559 MdbPrint(paraGetInfo->u64ReqHdl,"Frame lock status : FALSE\n");
560 }
561 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler dual miu : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK11_29_L,BIT(15))==BIT(15))?"TRUE":"FALSE");
562 #if (XC_SUPPORT_CMA == TRUE)
563 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler CMA : TRUE\n");
564 #else
565 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler CMA : FALSE\n");
566 #endif
567 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler auto no signal status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK01_02_L,BIT(7))==BIT(7))?"TRUE":"FALSE");
568 MdbPrint(paraGetInfo->u64ReqHdl,"DS status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK1F_11_L,BIT(9))==BIT(9) && MApi_XC_R2BYTEMSK(REG_SC_BK1F_11_L,BIT(11))==BIT(11))?"TRUE":"FALSE");
569 MdbPrint(paraGetInfo->u64ReqHdl,"Menuload status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK1F_02_L,BIT(15))==BIT(15))?"TRUE":"FALSE");
570 MdbPrint(paraGetInfo->u64ReqHdl,"2P mode status : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK01_07_L,BIT(15))==BIT(15))?"TRUE":"FALSE");
571 MdbPrint(paraGetInfo->u64ReqHdl,"HSK mode status : %s\n", (gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode==TRUE)?"TRUE":"FALSE");
572 MdbPrint(paraGetInfo->u64ReqHdl,"Window type : Main Window\n");
573 MdbPrint(paraGetInfo->u64ReqHdl,"Freeze : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK12_01_L,BIT(11))==BIT(11))?"TRUE":"FALSE");
574 MdbPrint(paraGetInfo->u64ReqHdl,"Offline detect : %s\n", (MApi_XC_R2BYTEMSK(0x257EUL,BIT(1))==0)?"TRUE":"FALSE");
575 MdbPrint(paraGetInfo->u64ReqHdl,"Setwindow time : %dus\n", u32SetWindowTime);
576 #ifdef UFO_XC_FB_LEVEL
577 if(gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL || gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI)
578 #else
579 if(gSrcInfo[MAIN_WINDOW].bFBL == TRUE || gSrcInfo[MAIN_WINDOW].bR_FBL == TRUE)
580 #endif
581 {
582 MdbPrint(paraGetInfo->u64ReqHdl,"RFBL/FBL : TRUE\n");
583 }
584 else
585 {
586 MdbPrint(paraGetInfo->u64ReqHdl,"RFBL/FBL : FALSE\n");
587 }
588 MdbPrint(paraGetInfo->u64ReqHdl,"Local dimming : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK2E_01_L,BIT(0))==BIT(0))?"TRUE":"FALSE");
589 MdbPrint(paraGetInfo->u64ReqHdl,"Disable input source : %s\n", (MApi_XC_R2BYTEMSK(REG_SC_BK01_02_L,BIT(7))==BIT(7))?"TRUE":"FALSE");
590 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler IRQ status (Bit 4) : %s (OP Vsync)\n", (MApi_XC_R2BYTEMSK(REG_SC_BK00_14_L,BIT(4))==BIT(4))?"TRUE":"FALSE");
591 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler IRQ status (Bit 11) : %s (IP1 Vsync)\n", (MApi_XC_R2BYTEMSK(REG_SC_BK00_14_L,BIT(11))==BIT(11))?"TRUE":"FALSE");
592 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler IRQ status (Bit 21) : %s (HDR DMA)\n", (MApi_XC_R2BYTEMSK(REG_SC_BK00_15_L,BIT(5))==BIT(5))?"TRUE":"FALSE");
593 MdbPrint(paraGetInfo->u64ReqHdl,"Scaler IRQ status (Bit 22) : %s (HDR Descramble)\n", (MApi_XC_R2BYTEMSK(REG_SC_BK00_15_L,BIT(6))==BIT(6))?"TRUE":"FALSE");
594
595 }
596
_XCMdbloctl_TestPattern(MS_U8 u8IP,MS_BOOL bEnable,MS_U8 u8window)597 static void _XCMdbloctl_TestPattern(MS_U8 u8IP, MS_BOOL bEnable, MS_U8 u8window)
598 {
599 if(u8IP == 0)
600 {
601 XC_SET_IPMUX_TESTPATTERN_t ipmux_test_pattern;
602 ipmux_test_pattern.bEnable = bEnable;
603 ipmux_test_pattern.u16R_CR_Data = 32;
604 ipmux_test_pattern.u16G_Y_Data = 32;
605 ipmux_test_pattern.u16B_CB_Data = 32;
606 MApi_XC_GenerateTestPattern(E_XC_IPMUX_PATTERN_MODE,(void *)&ipmux_test_pattern,sizeof(XC_SET_IPMUX_TESTPATTERN_t));
607 }
608 else if(u8IP == 1)
609 {
610 XC_SET_IP1_TESTPATTERN_t ip1_test_pattern;
611 ip1_test_pattern.u16Enable = bEnable;
612 ip1_test_pattern.u32Pattern_type = 32;
613 ip1_test_pattern.eWindow = (u8window==0)?MAIN_WINDOW:SUB_WINDOW;
614 MApi_XC_GenerateTestPattern(E_XC_IP1_PATTERN_MODE,(void*)&ip1_test_pattern,sizeof(XC_SET_IP1_TESTPATTERN_t));
615 }
616 else if(u8IP == 2)
617 {
618 XC_SET_OP_TESTPATTERN_t op_test_pattern;
619 op_test_pattern.bMiuLineBuff = bEnable;
620 op_test_pattern.bLineBuffHVSP = FALSE;
621 MApi_XC_GenerateTestPattern(E_XC_OP_PATTERN_MODE,(void*)&op_test_pattern,sizeof(XC_SET_OP_TESTPATTERN_t));
622 }
623 else if(u8IP == 3)
624 {
625 XC_SET_OP_TESTPATTERN_t op_test_pattern;
626 op_test_pattern.bMiuLineBuff = FALSE;
627 op_test_pattern.bLineBuffHVSP = bEnable;
628 MApi_XC_GenerateTestPattern(E_XC_OP_PATTERN_MODE,(void*)&op_test_pattern,sizeof(XC_SET_OP_TESTPATTERN_t));
629 }
630 else if(u8IP == 5)
631 {
632 XC_SET_VOP_TESTPATTERN_t vop_test_pattern;
633 vop_test_pattern.bEnable = bEnable;
634 MApi_XC_GenerateTestPattern(E_XC_VOP_PATTERN_MODE,(void*)&vop_test_pattern,sizeof(XC_SET_VOP_TESTPATTERN_t));
635 }
636 else if(u8IP == 4)
637 {
638 XC_SET_VOP2_TESTPATTERN_t vop2_test_pattern;
639 vop2_test_pattern.bEnable = bEnable;
640 vop2_test_pattern.u16B_CB_Data = 32;
641 vop2_test_pattern.u16G_Y_Data= 32;
642 vop2_test_pattern.u16R_CR_Data= 32;
643 MApi_XC_GenerateTestPattern(E_XC_VOP2_PATTERN_MODE,(void*)&vop2_test_pattern,sizeof(XC_SET_VOP2_TESTPATTERN_t));
644 }
645 else if(u8IP == 6)
646 {
647 XC_SET_MOD_TESTPATTERN_t mod_test_pattern;
648 mod_test_pattern.bEnable = bEnable;
649 mod_test_pattern.u16B_CB_Data = 32;
650 mod_test_pattern.u16G_Y_Data= 32;
651 mod_test_pattern.u16R_CR_Data= 32;
652 MApi_XC_GenerateTestPattern(E_XC_MOD_PATTERN_MODE,(void*)&mod_test_pattern,sizeof(XC_SET_MOD_TESTPATTERN_t));
653 }
654 }
655
_XCMdbIoctl_EchoCmd(char * pcCmdLine)656 static void _XCMdbIoctl_EchoCmd(char *pcCmdLine)
657 {
658 char pch[] = " =";
659 char* psep;
660 psep = strsep(&pcCmdLine,pch);
661
662 if(strcmp("pattern", psep) == 0)
663 {
664 MS_U8 u8IP, u8window;
665 MS_BOOL bEnable;
666 psep = strsep(&pcCmdLine,pch);
667 if(psep == NULL)
668 {
669 return;
670 }
671 psep = strsep(&pcCmdLine,pch);
672 if(psep == NULL)
673 {
674 return;
675 }
676 u8IP = (MS_U8)atoi(psep);
677
678 psep = strsep(&pcCmdLine,pch);
679 if(psep == NULL)
680 {
681 return;
682 }
683 psep = strsep(&pcCmdLine,pch);
684 if(psep == NULL)
685 {
686 return;
687 }
688 bEnable = (MS_BOOL)atoi(psep);
689
690 psep = strsep(&pcCmdLine,pch);
691 if(psep == NULL)
692 {
693 return;
694 }
695 psep = strsep(&pcCmdLine,pch);
696 if(psep == NULL)
697 {
698 return;
699 }
700 u8window = (MS_U8)atoi(psep);
701
702 _XCMdbloctl_TestPattern(u8IP, bEnable, u8window);
703 }
704 }
705
XCMdbIoctl(MS_U32 cmd,const void * const pArgs)706 MS_U32 XCMdbIoctl(MS_U32 cmd, const void* const pArgs)
707 {
708 MDBCMD_CMDLINE_PARAMETER *paraCmdLine;
709 MDBCMD_GETINFO_PARAMETER *paraGetInfo;
710 switch(cmd)
711 {
712 case MDBCMD_CMDLINE:
713 paraCmdLine = (MDBCMD_CMDLINE_PARAMETER *)pArgs;
714 /*MdbPrint(paraCmdLine->u64ReqHdl,"LINE:%d, MDBCMD_CMDLINE\n", __LINE__);
715 MdbPrint(paraCmdLine->u64ReqHdl,"u32CmdSize: %d\n", paraCmdLine->u32CmdSize);
716 MdbPrint(paraCmdLine->u64ReqHdl,"pcCmdLine: %s\n", paraCmdLine->pcCmdLine);*/
717 _XCMdbIoctl_EchoCmd(paraCmdLine->pcCmdLine);
718 paraCmdLine->result = MDBRESULT_SUCCESS_FIN;
719 break;
720 case MDBCMD_GETINFO:
721 paraGetInfo = (MDBCMD_GETINFO_PARAMETER *)pArgs;
722 //MdbPrint(paraGetInfo->u64ReqHdl,"LINE:%d, MDBCMD_GETINFO\n", __LINE__);
723 void *pInstance;
724 pInstance = UtopiaModuleGetLocalInstantList(MODULE_XC, pInstance);
725 _XCMdbloctl_Cat_DISP(pInstance, paraGetInfo);
726 _XCMdbloctl_Cat_PQ(pInstance, paraGetInfo);
727 _XCMdbloctl_Cat_SetWindow(pInstance, paraGetInfo);
728 _XCMdbloctl_Cat_FrameLock(pInstance, paraGetInfo);
729 _XCMdbloctl_Cat_MEMC(pInstance, paraGetInfo);
730 _XCMdbloctl_Cat_HDR(pInstance, paraGetInfo);
731 _XCMdbloctl_Cat_TGEN(pInstance, paraGetInfo);
732 _XCMdbloctl_Cat_3D(pInstance, paraGetInfo);
733 _XCMdbloctl_Cat_OPTEE(pInstance, paraGetInfo);
734 paraGetInfo->result = MDBRESULT_SUCCESS_FIN;
735 break;
736 default:
737 MdbPrint(paraGetInfo->u64ReqHdl,"unknown cmd\n", __LINE__);
738 break;
739 }
740 return 0;
741 }
742 #endif
743
744
XCRegisterToUtopia(FUtopiaOpen ModuleType)745 void XCRegisterToUtopia(FUtopiaOpen ModuleType)
746 {
747 MS_U32 u32ResourceStatusCheck[E_XC_POOL_ID_MAX] = {UTOPIA_STATUS_FAIL};
748
749 // 1. deal with module
750 UtopiaModuleCreate(MODULE_XC, 0, &pModuleXC);
751 UtopiaModuleRegister(pModuleXC);
752 // register func for module, after register here, then ap call UtopiaOpen/UtopiaIoctl/UtopiaClose can call to these registered standard func
753 UtopiaModuleSetupFunctionPtr(pModuleXC, (FUtopiaOpen)ModuleType, (FUtopiaClose)XCClose, (FUtopiaIOctl)XCIoctl);
754
755 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
756 UtopiaModuleRegisterMdbNode("xc", (FUtopiaMdbIoctl)XCMdbIoctl);
757 #endif
758
759 #if defined(MSOS_TYPE_LINUX_KERNEL)
760 UtopiaModuleSetupSTRFunctionPtr(pModuleXC, (FUtopiaSTR)XCStr);
761 UtopiaModuleSetSTRPrivate(pModuleXC, sizeof(XC_REGS_SAVE_AREA));
762 #endif
763 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
764 if (!bIsXCRegistered)
765 {
766 g_pDevice0Instance = NULL;
767 g_pDevice1Instance = NULL;
768 bIsXCRegistered = TRUE;
769 }
770 #endif
771 // 3. resource can allocate private for internal use
772 MS_U8 u8DeviceIndex = 0;
773 for(u8DeviceIndex = 0; u8DeviceIndex < MAX_XC_DEVICE_NUM ; u8DeviceIndex++)
774 {
775 MS_U8 u8DeviceOffset = (E_XC_POOL_ID_NUM*u8DeviceIndex);
776 void* psResource = NULL;
777
778 UtopiaModuleAddResourceStart(pModuleXC, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_MENULOAD);
779 if(u8DeviceIndex == 0)
780 {
781 u32ResourceStatusCheck[u8DeviceOffset + E_XC_POOL_ID_INTERNAL_MENULOAD] = UtopiaResourceCreate("MENULOAD", sizeof(MLOAD_RESOURCE_PRIVATE), &psResource);
782 }
783 else
784 {
785 char u8ResName[XC_RES_NAME_MAX_LEN];
786 memset(&u8ResName, 0x0, sizeof(u8ResName));
787 snprintf(u8ResName, XC_RES_NAME_MAX_LEN, "MENULOAD_%d", u8DeviceIndex);
788 u32ResourceStatusCheck[u8DeviceOffset + E_XC_POOL_ID_INTERNAL_MENULOAD] = UtopiaResourceCreate(u8ResName, sizeof(MLOAD_RESOURCE_PRIVATE), &psResource);
789 }
790 UtopiaResourceRegister(pModuleXC, psResource, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_MENULOAD);
791 UtopiaModuleAddResourceEnd(pModuleXC, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_MENULOAD);
792
793 UtopiaModuleAddResourceStart(pModuleXC, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_REGISTER);
794 if(u8DeviceIndex == 0)
795 {
796 u32ResourceStatusCheck[u8DeviceOffset + E_XC_POOL_ID_INTERNAL_REGISTER] = UtopiaResourceCreate("XC_REGISTER", 0, &psResource);
797 }
798 else
799 {
800 char u8ResName[XC_RES_NAME_MAX_LEN];
801 memset(&u8ResName, 0x0, sizeof(u8ResName));
802 snprintf(u8ResName, XC_RES_NAME_MAX_LEN, "XC_REGISTER_%d", u8DeviceIndex);
803 u32ResourceStatusCheck[u8DeviceOffset + E_XC_POOL_ID_INTERNAL_REGISTER] = UtopiaResourceCreate(u8ResName, 0, &psResource);
804 }
805 UtopiaResourceRegister(pModuleXC, psResource, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_REGISTER);
806 UtopiaModuleAddResourceEnd(pModuleXC, u8DeviceOffset + E_XC_POOL_ID_INTERNAL_REGISTER);
807
808 UtopiaModuleAddResourceStart(pModuleXC, _XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex));
809 if(u8DeviceIndex == 0)
810 {
811 #ifdef MSOS_TYPE_OPTEE
812 u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] = UtopiaResourceCreate("XC_VARIABLE", sizeof(XC_RESOURCE_PRIVATE_FOR_TEE), &psResource);
813 #else
814 u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] = UtopiaResourceCreate("XC_VARIABLE", sizeof(XC_RESOURCE_PRIVATE), &psResource);
815 #endif
816 }
817 else
818 {
819 char u8ResName[XC_RES_NAME_MAX_LEN];
820 memset(&u8ResName, 0x0, sizeof(u8ResName));
821 snprintf(u8ResName, XC_RES_NAME_MAX_LEN, "XC_VARIABLE_%d", u8DeviceIndex);
822 #ifdef MSOS_TYPE_OPTEE
823 u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] = UtopiaResourceCreate(u8ResName, sizeof(XC_RESOURCE_PRIVATE_FOR_TEE), &psResource);
824 #else
825 u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] = UtopiaResourceCreate(u8ResName, sizeof(XC_RESOURCE_PRIVATE), &psResource);
826 #endif
827 }
828 UtopiaResourceRegister(pModuleXC, psResource, _XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex));
829 UtopiaModuleAddResourceEnd(pModuleXC, _XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex));
830
831 //4. init resource private members here (aka, global variable)
832 #ifdef MSOS_TYPE_OPTEE
833 XC_RESOURCE_PRIVATE_FOR_TEE* pXCResourcePrivate = NULL;
834 UtopiaResourceGetPrivate(psResource,(void**)(&pXCResourcePrivate));
835 //pXCResourcePrivate->bResourceRegistered will automatically cleared by UtopiaResourceRegister
836 if (u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] == UTOPIA_STATUS_SHM_EXIST)
837 {
838 // do nothing, since it is already inited
839 }
840 else
841 {
842 memset(&(pXCResourcePrivate->sthal_Optee),0,sizeof(ST_HAL_OPTEE));
843 }
844 #else
845 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
846 UtopiaResourceGetPrivate(psResource,(void**)(&pXCResourcePrivate));
847
848 //pXCResourcePrivate->bResourceRegistered will automatically cleared by UtopiaResourceRegister
849 if (u32ResourceStatusCheck[_XC_SELECT_INTERNAL_VARIABLE(u8DeviceIndex)] == UTOPIA_STATUS_SHM_EXIST)
850 {
851 // do nothing, since it is already inited
852 }
853 else
854 {
855 // Init flow control related variables here. Other global variable should be
856 // inited in each of its init function relatively.
857 pXCResourcePrivate->bResourceRegistered = TRUE;
858 pXCResourcePrivate->bXCMWEStatus = FALSE;
859
860 // apiXC_Auto.c
861 pXCResourcePrivate->stapiXC_Auto.bHaltAutoGeometry = FALSE;
862 pXCResourcePrivate->stapiXC_Auto._u8ThresholdValue = 0x05;
863 pXCResourcePrivate->stapiXC_Auto.g_enCalbrationMode = E_XC_SW_CALIBRATION;
864
865 // apiXC_PCMonitor.c
866 pXCResourcePrivate->stapiXC_PCMonitor._bEnableAutoNoSignalDetect[MAIN_WINDOW] = FALSE;
867 pXCResourcePrivate->stapiXC_PCMonitor._bEnableAutoNoSignalDetect[SUB_WINDOW] = FALSE;
868 pXCResourcePrivate->stapiXC_PCMonitor.u8DeNoiseCount[MAIN_WINDOW] = 0;
869 pXCResourcePrivate->stapiXC_PCMonitor.u8DeNoiseCount[SUB_WINDOW] = 0;
870 pXCResourcePrivate->stapiXC_PCMonitor.u8DeStableCnt[MAIN_WINDOW] = 0;
871 pXCResourcePrivate->stapiXC_PCMonitor.u8DeStableCnt[SUB_WINDOW] = 0;
872 pXCResourcePrivate->stapiXC_PCMonitor._bNewModeInterlacedDetect = FALSE;
873
874 // mdrv_hdmi.c
875 pXCResourcePrivate->stdrv_HDMI._ResetDone = FALSE;
876 pXCResourcePrivate->stdrv_HDMI._bHDCP_Vsync_done = FALSE;
877 pXCResourcePrivate->stdrv_HDMI._bHDCP_Vsync_count = FALSE;
878 pXCResourcePrivate->stdrv_HDMI.u32VsyncTimer = 0;
879 pXCResourcePrivate->stdrv_HDMI._prev_enPowerState = E_POWER_MECHANICAL;
880
881 #if (LD_ENABLE==1)
882 // mdrv_ld.c
883 pXCResourcePrivate->stdrv_LD._bMDrvLD_InitFinished = FALSE;
884 pXCResourcePrivate->stdrv_LD._u16LedPos = 0;
885
886 // mdrv_ldalgo.c
887 pXCResourcePrivate->stdrv_LDALGO._u8H_Down_Ratio = 0;
888 pXCResourcePrivate->stdrv_LDALGO._u8V_Down_Ratio = 0;
889 pXCResourcePrivate->stdrv_LDALGO._u8H_Down_Ratio_3D = 0;
890 pXCResourcePrivate->stdrv_LDALGO._u8V_Down_Ratio_3D = 0;
891 pXCResourcePrivate->stdrv_LDALGO._u8Pack_Length_LD = 0;
892 pXCResourcePrivate->stdrv_LDALGO._u8Pack_Length_PWM = 0;
893 pXCResourcePrivate->stdrv_LDALGO._u8Frame_Idx = 0;
894 pXCResourcePrivate->stdrv_LDALGO._u8Frame_Idx_Final = 0;
895 pXCResourcePrivate->stdrv_LDALGO._u8Frame_Idx_Test = 0;
896 pXCResourcePrivate->stdrv_LDALGO._u8Iluma_Pre = 0;
897 pXCResourcePrivate->stdrv_LDALGO._u16Histogram_Zero = 0;
898 pXCResourcePrivate->stdrv_LDALGO._u32Lluma_Sum = 0;
899 pXCResourcePrivate->stdrv_LDALGO._u8DebugArrayDumpDummyCnt = 0;
900 pXCResourcePrivate->stdrv_LDALGO._u8Gamma_Control = 0;
901 pXCResourcePrivate->stdrv_LDALGO._u8OSDEnable = 1;
902 pXCResourcePrivate->stdrv_LDALGO._enLDBlock_Num = LD_BLOCK_DEFALUT;
903 pXCResourcePrivate->stdrv_LDALGO._bLDoff = TRUE;
904 #endif
905
906 // mdrv_sc_3d.c
907 #if HW_2DTO3D_SUPPORT
908 pXCResourcePrivate->stdrvXC_3D.bAdjustDNRSize = FALSE;
909 pXCResourcePrivate->stdrvXC_3D.u32OriginalDNRSize = 0;
910 #endif
911 pXCResourcePrivate->stdrvXC_3D.s_u8flg = 0;
912 pXCResourcePrivate->stdrvXC_3D.s_u8Ptr = 0;
913 pXCResourcePrivate->stdrvXC_3D.u8Ptr = 0;
914 pXCResourcePrivate->stdrvXC_3D.bFirstFlag = TRUE;
915 pXCResourcePrivate->stdrvXC_3D.ePreInputMode = E_XC_3D_INPUT_MODE_NONE;
916 pXCResourcePrivate->stdrvXC_3D.ePreOutputMode = E_XC_3D_OUTPUT_MODE_NONE;
917
918 #if HW_2DTO3D_SUPPORT
919 #if (HW_2DTO3D_VER >= 3) //new 2d to 3d architecture
920 pXCResourcePrivate->stdrvXC_3D._s16TBB_BGColorSelWei = 0;
921 pXCResourcePrivate->stdrvXC_3D._s16TpBGCOLOR_ValidWei = 0;//instead of TpBGCOLOR_Valid
922 pXCResourcePrivate->stdrvXC_3D._s16DnBGCOLOR_ValidWei = 0;//instead of DnBGCOLOR_Valid
923 pXCResourcePrivate->stdrvXC_3D._s16DistantViewWei = 0;// for blue sky ratio
924 pXCResourcePrivate->stdrvXC_3D._s16DistantViewWei_Bottom = 0;// for blue sky ratio
925 pXCResourcePrivate->stdrvXC_3D._s16TBA_BGColorWei = 0;
926 pXCResourcePrivate->stdrvXC_3D._s16TBB_BGColorWei = 0;
927 pXCResourcePrivate->stdrvXC_3D._s16BothTpBGSKY_COLORCnt = 0;
928 pXCResourcePrivate->stdrvXC_3D._s16BothDnBGSKY_COLORCnt = 0;
929 pXCResourcePrivate->stdrvXC_3D._s16BlueSkyRatio = 0;
930
931 pXCResourcePrivate->stdrvXC_3D._u16Y_Sep = 0; // horizontal detection
932 pXCResourcePrivate->stdrvXC_3D._u16Y_Sep_OUT = 0; // horizontal detection for output frame position
933
934 pXCResourcePrivate->stdrvXC_3D._u8Pre_BlueAndFlatBlkCnt = 0;
935 pXCResourcePrivate->stdrvXC_3D._u8Pre_BlueAndFlatBlkCnt_Dn = 0;
936
937 //keeps blueSkyRatio stable
938 pXCResourcePrivate->stdrvXC_3D._u8Pre_BlueSkyRatio1 = 0;
939 pXCResourcePrivate->stdrvXC_3D._u8Pre_BlueSkyRatio2 = 0;
940
941 //for blkbased Depth
942 pXCResourcePrivate->stdrvXC_3D._u8Lowpass_En = 1; // 1: 3x3 2: 5x5 3:7x7 4:disable bilinear
943 pXCResourcePrivate->stdrvXC_3D._u8Bilateral_En = 0;
944 pXCResourcePrivate->stdrvXC_3D._u8DepthAB = 0; //1:TableA 2:TableB 3:ABweight
945 pXCResourcePrivate->stdrvXC_3D._u8Bilinear_En = 1;
946 pXCResourcePrivate->stdrvXC_3D._s16DistantViewRatio3 = 0;
947
948 //multiview adjust dummy
949 pXCResourcePrivate->stdrvXC_3D._s8Shift_Value = 40;
950 pXCResourcePrivate->stdrvXC_3D._s8Clamp_Value = 28;
951 pXCResourcePrivate->stdrvXC_3D._s8Multi_Gain = 16;
952 pXCResourcePrivate->stdrvXC_3D._s32Depth_Control_Var_IIR = 16;
953 pXCResourcePrivate->stdrvXC_3D._s32Mean_Depth_IIR = 128;
954 pXCResourcePrivate->stdrvXC_3D._u8Horizontal_Step = 32;
955 pXCResourcePrivate->stdrvXC_3D._u8Vertical_Step = 32;
956
957 //for IIR
958 pXCResourcePrivate->stdrvXC_3D.u8IIR_En = 1;
959 pXCResourcePrivate->stdrvXC_3D.u16BL_IIRweight = 96;
960 pXCResourcePrivate->stdrvXC_3D.u16PreDistantViewRatio1 = 0;
961 pXCResourcePrivate->stdrvXC_3D.u16PreDistantViewRatio2 = 0;
962 pXCResourcePrivate->stdrvXC_3D.u16Pre_YSep = 0;
963
964 pXCResourcePrivate->stdrvXC_3D.s_bFirst = TRUE;
965
966 //for DepthDectionBLK
967 //pXCResourcePrivate->stdrvXC_3D.u8BLKblueSkyRatio1 = 0;
968 //pXCResourcePrivate->stdrvXC_3D.u8BLKblueSkyRatio2 = 0;
969 //for Trend Detection
970 pXCResourcePrivate->stdrvXC_3D.u8VerGLB_Wei =0;
971 //for DEBUGFn
972 pXCResourcePrivate->stdrvXC_3D.u8DBG_En = 0;
973 pXCResourcePrivate->stdrvXC_3D.u8Round = 0;
974 //for job-division of LUT update
975 pXCResourcePrivate->stdrvXC_3D.job_id = 0;
976 pXCResourcePrivate->stdrvXC_3D.job_freq = 0;
977 pXCResourcePrivate->stdrvXC_3D.updateSRAM_state = 1;
978 pXCResourcePrivate->stdrvXC_3D.updateSRAM_PreState = 3;
979 pXCResourcePrivate->stdrvXC_3D.NoMot_Cnt = 0;
980 pXCResourcePrivate->stdrvXC_3D.NoMot_Flg = 0;
981 //BGColorDetection
982 pXCResourcePrivate->stdrvXC_3D.BGColorBlkCntTp = 0;
983 pXCResourcePrivate->stdrvXC_3D.BGColorBlkCntBn = 0;
984 pXCResourcePrivate->stdrvXC_3D.BGColor_CbTp = 128;
985 pXCResourcePrivate->stdrvXC_3D.BGColor_CrTp = 128;
986 pXCResourcePrivate->stdrvXC_3D.BGColor_CbBn = 128;
987 pXCResourcePrivate->stdrvXC_3D.BGColor_CrBn = 128;
988 pXCResourcePrivate->stdrvXC_3D.BGColorBlkCntforTp = 0;
989 pXCResourcePrivate->stdrvXC_3D.BGColorBlkCntforBn = 0;
990 pXCResourcePrivate->stdrvXC_3D._u8TBABGColorWei = 0;
991 //for MainObj Detection
992 pXCResourcePrivate->stdrvXC_3D._u8MainObjWei = 0;
993 //for LGE ver GLOBAL depth
994 pXCResourcePrivate->stdrvXC_3D._s16BLKblueSkyRatio1 = 0;
995 pXCResourcePrivate->stdrvXC_3D._s16BLKblueSkyRatio2 = 0;
996
997 //for TrendDetection
998 pXCResourcePrivate->stdrvXC_3D.u8VerGLB_Wei = 0;
999 //for DEBUGFn
1000 pXCResourcePrivate->stdrvXC_3D.u8DBG_En = 0;
1001
1002 //for Size related settings
1003 pXCResourcePrivate->stdrvXC_3D._u16PanelWidth = 0;
1004 pXCResourcePrivate->stdrvXC_3D._u16PanelHeight = 0;
1005 pXCResourcePrivate->stdrvXC_3D._u8NBLK_DR_H = 0;
1006 pXCResourcePrivate->stdrvXC_3D._u8NBLK_DR_V = 0;
1007 #endif
1008 #endif
1009
1010 #if HW_2DTO3D_SUPPORT
1011 pXCResourcePrivate->stdrvXC_3D._u32HisWeight = 0;
1012 pXCResourcePrivate->stdrvXC_3D._u32ArtWeight = 0;
1013 pXCResourcePrivate->stdrvXC_3D._u32ReturnWeightCur = 0;
1014 pXCResourcePrivate->stdrvXC_3D._u32ReturnWeight = 0;
1015 pXCResourcePrivate->stdrvXC_3D._u32X = 0xe8c9af37;
1016 pXCResourcePrivate->stdrvXC_3D._u32RemapAvgCurSum = 0;
1017 pXCResourcePrivate->stdrvXC_3D._u32RemapAvgBseSum = 0;
1018 pXCResourcePrivate->stdrvXC_3D._u32RemapAvgCur = 0;
1019 pXCResourcePrivate->stdrvXC_3D._u32RemapAvgBse = 0;
1020 pXCResourcePrivate->stdrvXC_3D._u8RemapAvgBias = 0;
1021 pXCResourcePrivate->stdrvXC_3D._u16SBSCount = 0;
1022 pXCResourcePrivate->stdrvXC_3D._u16TBCount = 0;
1023 pXCResourcePrivate->stdrvXC_3D._u162DCount = 0;
1024 pXCResourcePrivate->stdrvXC_3D._u16TotalCount = 0;
1025 #endif
1026
1027 // mdrv_sc_display.c
1028 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE;
1029 pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode = FPLL_THRESH_MODE_IDLE_STATE;
1030 pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working = FALSE;
1031 pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Setting = FALSE;
1032 pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode = FALSE;
1033 pXCResourcePrivate->stdrvXC_Display._bForceFreerun = FALSE;
1034 pXCResourcePrivate->stdrvXC_Display._ForceVFreq = VFREQ_FROM_PANEL;
1035 pXCResourcePrivate->stdrvXC_Display._bHSyncChanged = FALSE;
1036 pXCResourcePrivate->stdrvXC_Display._bVSyncChanged = FALSE;
1037 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
1038 pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW] = FALSE;
1039 pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[SUB_WINDOW] = FALSE;
1040 pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR = FALSE;
1041 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = 0;
1042 pXCResourcePrivate->stdrvXC_Display._abSkipOPWOffInSetWindow[MAIN_WINDOW] = FALSE;
1043 pXCResourcePrivate->stdrvXC_Display._abSkipOPWOffInSetWindow[SUB_WINDOW] = FALSE;
1044 pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM = FALSE;
1045 pXCResourcePrivate->stdrvXC_Display._u8CoastClearDebounce=0;
1046 pXCResourcePrivate->stdrvXC_Display._bDisableCoastDebounce=0;
1047 pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable = FALSE;
1048 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = FALSE;
1049 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = FALSE;
1050 pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[MAIN_WINDOW] = FALSE;
1051 pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[SUB_WINDOW] = FALSE;
1052 pXCResourcePrivate->stdrvXC_Display.s_u32DelayT = 0;
1053 pXCResourcePrivate->stdrvXC_Display.s_u32InputVsyncStart = 0;
1054 pXCResourcePrivate->stdrvXC_Display.s_u16OrigPrd = 0xFFFF; // max PRD error
1055 pXCResourcePrivate->stdrvXC_Display.s_u16OrigPhase = 0xFFFF; // max phase error
1056 pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer = 0;
1057 pXCResourcePrivate->stdrvXC_Display.g_u8FrcIn = 0;
1058 pXCResourcePrivate->stdrvXC_Display.g_u8FrcOut = 0;
1059
1060 // mdrv_sc_dynamicscaling.c
1061 pXCResourcePrivate->stdrvXC_Dynamicscaling._bDSForceIndexEnable[MAIN_WINDOW] = FALSE;
1062 pXCResourcePrivate->stdrvXC_Dynamicscaling._bDSForceIndexEnable[SUB_WINDOW] = FALSE;
1063
1064 // mdrv_sc_ip.c
1065 pXCResourcePrivate->stdrvXC_IP.u8Count = 1;
1066 #if ENABLE_DEBUG_CAPTURE_N_FRAMES
1067 pXCResourcePrivate->stdrvXC_IP.bFinishedInputVSyncISR = FALSE;
1068 pXCResourcePrivate->stdrvXC_IP.u8Cnt = 0;
1069 #endif
1070
1071 // mdrv_sc_scaling.c
1072 pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[0] = 0;
1073 pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[1] = 0;
1074 pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[0] = 0;
1075 pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[1] = 0;
1076 pXCResourcePrivate->stdrvXC_Scaling._u32FRCMBaseAddr0[0] = 0;
1077 pXCResourcePrivate->stdrvXC_Scaling._u32FRCMBaseAddr0[1] = 0;
1078 pXCResourcePrivate->stdrvXC_Scaling._u32FRCMBufSize[0] = 0;
1079 pXCResourcePrivate->stdrvXC_Scaling._u32FRCMBufSize[1] = 0;
1080 pXCResourcePrivate->stdrvXC_Scaling._bHAutoFitPrescalingEna = FALSE;
1081 pXCResourcePrivate->stdrvXC_Scaling._bVAutoFitPrescalingEna = FALSE;
1082 pXCResourcePrivate->stdrvXC_Scaling._bHSizeChangedManually = FALSE;
1083 pXCResourcePrivate->stdrvXC_Scaling.u32DNRBaseOffset[0] = 0;
1084 pXCResourcePrivate->stdrvXC_Scaling.u32DNRBaseOffset[1] = 0;
1085 pXCResourcePrivate->stdrvXC_Scaling.u32FRCMBaseOffset[0] = 0;
1086 pXCResourcePrivate->stdrvXC_Scaling.u32FRCMBaseOffset[1] = 0;
1087 pXCResourcePrivate->stdrvXC_Scaling._au8StoreFrameNumFactor[0] = 0;
1088 pXCResourcePrivate->stdrvXC_Scaling._au8StoreFrameNumFactor[1] = 0;
1089 pXCResourcePrivate->stdrvXC_Scaling._bMainWinSkipWaitOutputVsync = FALSE;
1090 pXCResourcePrivate->stdrvXC_Scaling._bSubWinSkipWaitOutputVsync = FALSE;
1091 pXCResourcePrivate->stdrvXC_Scaling._bPQSetHPreScalingratio = FALSE;
1092 #ifdef ENABLE_SCALING_WO_MUTE
1093 pXCResourcePrivate->stdrvXC_Scaling._u8OPMFetchRatio[MAIN_WINDOW] = 1;
1094 pXCResourcePrivate->stdrvXC_Scaling._u8OPMFetchRatio[SUB_WINDOW] = 1;
1095 #endif
1096 pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW] = 0;
1097 pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[SUB_WINDOW] = 0;
1098 pXCResourcePrivate->stdrvXC_Scaling._au32PreFBSize[MAIN_WINDOW] = 0;
1099 pXCResourcePrivate->stdrvXC_Scaling._au32PreFBSize[SUB_WINDOW] = 0;
1100 pXCResourcePrivate->stdrvXC_Scaling._u16HScaleSrc[MAIN_WINDOW] = 0;
1101 pXCResourcePrivate->stdrvXC_Scaling._u16HScaleSrc[SUB_WINDOW] = 0;
1102 pXCResourcePrivate->stdrvXC_Scaling._u16HScaleDst[MAIN_WINDOW] = 0;
1103 pXCResourcePrivate->stdrvXC_Scaling._u16HScaleDst[SUB_WINDOW] = 0;
1104 pXCResourcePrivate->stdrvXC_Scaling._u16VScaleSrc[MAIN_WINDOW] = 0;
1105 pXCResourcePrivate->stdrvXC_Scaling._u16VScaleSrc[SUB_WINDOW] = 0;
1106 pXCResourcePrivate->stdrvXC_Scaling._u16VScaleDst[MAIN_WINDOW] = 0;
1107 pXCResourcePrivate->stdrvXC_Scaling._u16VScaleDst[SUB_WINDOW] = 0;
1108 pXCResourcePrivate->stdrvXC_Scaling._u8HSD_Idx = 0;
1109
1110 // mvideo.c
1111 pXCResourcePrivate->stdrvXC_MVideo.bNeedInitShared = TRUE;
1112 memset(&(pXCResourcePrivate->stdrvXC_MVideo._SContext), 0, sizeof(XC_Context));
1113 memset(&(pXCResourcePrivate->stdrvXC_MVideo._SCShared), 0, sizeof(XC_Context_Shared));
1114 pXCResourcePrivate->stdrvXC_MVideo.s_eMemFmt[MAIN_WINDOW] = E_MS_XC_MEM_FMT_AUTO;
1115 pXCResourcePrivate->stdrvXC_MVideo.s_eMemFmt[SUB_WINDOW] = E_MS_XC_MEM_FMT_AUTO;
1116 gSrcInfo[MAIN_WINDOW].Status2.stXCConfigCMA[CMA_XC_SELF_MEM].u32HeapID = XC_INVALID_HEAP_ID;
1117 gSrcInfo[SUB_WINDOW].Status2.stXCConfigCMA[CMA_XC_SELF_MEM].u32HeapID = XC_INVALID_HEAP_ID;
1118 gSrcInfo[MAIN_WINDOW].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID = XC_INVALID_HEAP_ID;
1119 gSrcInfo[SUB_WINDOW].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID = XC_INVALID_HEAP_ID;
1120 pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear = FALSE;
1121 pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[MAIN_WINDOW] = INPUT_SOURCE_NONE;
1122 pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[SUB_WINDOW] = INPUT_SOURCE_NONE;
1123 pXCResourcePrivate->stdrvXC_MVideo._bSkipSWReset = FALSE; ///< Flag for: If the system needs to show Logo from MBoot layer to APP layer without flashing. \n We bypass SW reset in MApi_XC_Init.
1124 pXCResourcePrivate->stdrvXC_MVideo._bDFBInit = FALSE;
1125 pXCResourcePrivate->stdrvXC_MVideo.s8HPixelShift = 0;
1126 pXCResourcePrivate->stdrvXC_MVideo.s8VPixelShift = 0;
1127 pXCResourcePrivate->stdrvXC_MVideo._bSetDualMainWinDone = FALSE;
1128 pXCResourcePrivate->stdrvXC_MVideo._bSetDualSubWinDone = FALSE;
1129
1130 #ifndef DISABLE_HW_PATTERN_FUNCTION
1131 #ifdef SUPPORT_HW_TESTPATTERN
1132 pXCResourcePrivate->stdrvXC_MVideo.bIsHWPatternEnabled = FALSE;
1133 pXCResourcePrivate->stdrvXC_MVideo.bIsMute = FALSE;
1134 pXCResourcePrivate->stdrvXC_MVideo.bIsInputSrcDisabled = FALSE;
1135 #endif
1136 #endif
1137
1138 #if SUPPORT_OP2_TEST_PATTERN
1139 pXCResourcePrivate->stdrvXC_MVideo.u16OP2_color_3x3 = 0;
1140 pXCResourcePrivate->stdrvXC_MVideo.bIsOP2TestPattern= FALSE;
1141 pXCResourcePrivate->stdrvXC_MVideo.bIsOP2InputSrcDisabled = FALSE;
1142 pXCResourcePrivate->stdrvXC_MVideo.bIsOP2Mute= FALSE;
1143 #endif
1144 #if FRC_INSIDE
1145 pXCResourcePrivate->stdrvXC_MVideo.bEnableUserMode = FALSE;
1146 #endif
1147
1148 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableLockFreqOnly = TRUE;
1149
1150 #if (ENABLE_NONSTD_INPUT_MCNR==1)
1151 pXCResourcePrivate->stdrvXC_MVideo.bIsUnStdSignal = FALSE;
1152 pXCResourcePrivate->stdrvXC_MVideo.u8StdSignalStbCnt = 0;
1153 pXCResourcePrivate->stdrvXC_MVideo.u8UnStdOutput[MAIN_WINDOW] = 0;
1154 pXCResourcePrivate->stdrvXC_MVideo.u8UnStdOutput[SUB_WINDOW] = 1;
1155 #endif
1156
1157 pXCResourcePrivate->stdrvXC_MVideo.OSDC_FREQ = 600; // default 60Hz
1158 pXCResourcePrivate->stdrvXC_MVideo._enPrevPowerState = E_POWER_MECHANICAL;
1159 pXCResourcePrivate->stdrvXC_MVideo.bSignalStableForStr = FALSE;
1160 pXCResourcePrivate->stdrvXC_MVideo.bModuleInited = FALSE;
1161 pXCResourcePrivate->stdrvXC_MVideo.bTimingUnstableForStr = FALSE;
1162 pXCResourcePrivate->stdrvXC_MVideo.u8DebounceForStr = 0;
1163
1164 // mvideo_context.c
1165 pXCResourcePrivate->stdrvXC_MVideo_Context.s_HDMISYNC_type = HDMI_SYNC_DE;
1166 pXCResourcePrivate->stdrvXC_MVideo_Context._bSupportHVMode = FALSE;
1167 #ifndef DISABLE_HW_PATTERN_FUNCTION
1168 #ifdef SUPPORT_HW_TESTPATTERN
1169 // For HW internal test pattern using
1170 pXCResourcePrivate->stdrvXC_MVideo_Context.bOP1_PatGen_Init = FALSE;
1171 #endif
1172 #endif
1173
1174 #if FRC_INSIDE
1175 pXCResourcePrivate->stdrvXC_MVideo_Context.bIsFRCInited = FALSE;
1176 pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming = E_XC_FRC_InputTiming_4K2K;
1177 #if (HW_DESIGN_4K2K_VER == 6) // For Manhattan, FSC+FRC
1178 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled = FALSE;
1179 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled = FALSE;
1180 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16GOPOffsetH = 0;
1181 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16GOPOffsetV = 0;
1182 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16MEMCLevel = MEMC_LEVEL_MID;
1183 pXCResourcePrivate->stdrvXC_MVideo_Context.bIsFRCMute = FALSE;
1184 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bIsAddrUpdated = FALSE;
1185 #endif
1186 #endif
1187 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable = FALSE;
1188 #if (HW_DESIGN_HDMITX_VER == 2)
1189 pXCResourcePrivate->stdrvXC_MVideo_Context.enHDMITXColorDepth = E_XC_HDMITX_COLORDEPTH_8BIT;
1190 #endif
1191
1192 #ifdef MSOS_TYPE_LINUX_KERNEL
1193 // xc_hwreg_utility2.h
1194 pXCResourcePrivate->stXC_Utility._XC_EventFlag = 0;
1195 pXCResourcePrivate->stXC_Utility._XC_VSyncRun = FALSE;
1196 pXCResourcePrivate->stXC_Utility._XC_VSyncCount = 0;
1197 pXCResourcePrivate->stXC_Utility._XC_VSyncMax = 0;
1198 #endif
1199
1200 // mhal_adc.c
1201 pXCResourcePrivate->sthal_ADC.bIsYPbPrLooseLPF = FALSE;
1202 pXCResourcePrivate->sthal_ADC._bSourceSwitched = FALSE;
1203 pXCResourcePrivate->sthal_ADC._bEnableHWCalibration = FALSE;
1204 pXCResourcePrivate->sthal_ADC._bUseBandgap = FALSE;
1205 pXCResourcePrivate->sthal_ADC._eCvbsOutType = ADC_CVBSOUT_DISABLE_1;
1206 pXCResourcePrivate->sthal_ADC.enLastSourceType = ADC_INPUTSOURCE_UNKNOW;
1207 pXCResourcePrivate->sthal_ADC.u16LastHtotal = 0;
1208 pXCResourcePrivate->sthal_ADC.u16LastPixelClk = 0;
1209 pXCResourcePrivate->sthal_ADC.u16LastSamplingRatio = 1;
1210
1211 // mhal_ip.c
1212 pXCResourcePrivate->sthal_IP._bSetVGASogEn = FALSE;
1213 pXCResourcePrivate->sthal_IP._u8SetSogDetectStatus = 0;
1214
1215 // mhal_sc.c
1216 pXCResourcePrivate->sthal_SC.bDynamicScalingEnable = 0;
1217 pXCResourcePrivate->sthal_SC.u16OP1_fclk_gate_en = 0;
1218 pXCResourcePrivate->sthal_SC.u16OP1_reg_ip2_clk_gate_en = 0;
1219 pXCResourcePrivate->sthal_SC.u16OP1_ficlk_status = 0;
1220 pXCResourcePrivate->sthal_SC.u32OP1_reg_pre_down_f2 = 0;
1221 pXCResourcePrivate->sthal_SC.u32OP1_reg_pre_down_f1 = 0;
1222 pXCResourcePrivate->sthal_SC.u16OP1_color_3x3 = 0;
1223 pXCResourcePrivate->sthal_SC.u16OP1_color_vip = 0;
1224 pXCResourcePrivate->sthal_SC.u16OP1_reg_di1lb_en = 0;
1225 pXCResourcePrivate->sthal_SC.u16OP1_bypass_miu = 0;
1226 pXCResourcePrivate->sthal_SC.u16OP1_vop_dualpixel = 0;
1227 pXCResourcePrivate->sthal_SC.g_u16TmpValue = 0;
1228 pXCResourcePrivate->sthal_SC.g_bCntFlg = 1;
1229 pXCResourcePrivate->sthal_SC.bVSDshift[MAIN_WINDOW] = FALSE;
1230 pXCResourcePrivate->sthal_SC.bVSDshift[SUB_WINDOW] = FALSE;
1231 pXCResourcePrivate->sthal_SC.su16OldValue = 0;
1232 pXCResourcePrivate->sthal_SC.su16OldValue_BWD_Status = 0;
1233 pXCResourcePrivate->sthal_SC.sbOldValueReaded = FALSE;
1234 // init as hw default value
1235 pXCResourcePrivate->sthal_SC.u16OldValue[E_STORE_VALUE_AUTO_TUNE_AREA_TRIG] = 0x08;
1236 pXCResourcePrivate->sthal_SC.u16OldValue[E_STORE_VALUE_DISP_AREA_TRIG] = 0x0A;
1237 pXCResourcePrivate->sthal_SC.u16NewValue[E_STORE_VALUE_AUTO_TUNE_AREA_TRIG] = 0;
1238 pXCResourcePrivate->sthal_SC.u16NewValue[E_STORE_VALUE_DISP_AREA_TRIG] = 0;
1239 pXCResourcePrivate->sthal_SC.bUsingNewValue[E_STORE_VALUE_AUTO_TUNE_AREA_TRIG] = FALSE;
1240 pXCResourcePrivate->sthal_SC.bUsingNewValue[E_STORE_VALUE_DISP_AREA_TRIG] = FALSE;
1241 #if (HW_DESIGN_4K2K_VER == 4)
1242 pXCResourcePrivate->sthal_SC.u16OldValue[E_STORE_VALUE_IP_AUTO_TUNE_AREA_TRIG] = 0x03;
1243 pXCResourcePrivate->sthal_SC.u16OldValue[E_STORE_VALUE_IP_DISP_AREA_TRIG] = 0x05;
1244 #endif
1245 pXCResourcePrivate->sthal_SC.u16OldValue[E_STORE_VALUE_INIT_CMD_NUM] = 0;
1246
1247 pXCResourcePrivate->sthal_SC.bTrig_pStored = FALSE;
1248 pXCResourcePrivate->sthal_SC.u8Time_count = 0;
1249 #if SUPPORT_SEAMLESS_ZAPPING
1250 pXCResourcePrivate->sthal_SC.u32DynamicScalingBaseAddr = 0;
1251 pXCResourcePrivate->sthal_SC.u8DynamicScalingIndexDepth = 0;
1252 pXCResourcePrivate->sthal_SC.bSeamlessZappingEnable[MAIN_WINDOW] = FALSE;
1253 pXCResourcePrivate->sthal_SC.bSeamlessZappingEnable[SUB_WINDOW] = FALSE;
1254 pXCResourcePrivate->sthal_SC.u8SeamlessZappingCurIndex[MAIN_WINDOW] = 0;
1255 pXCResourcePrivate->sthal_SC.u8SeamlessZappingCurIndex[SUB_WINDOW] = 0;
1256 pXCResourcePrivate->sthal_SC.u8SeamlessZappingNextIndex[MAIN_WINDOW] = 0;
1257 pXCResourcePrivate->sthal_SC.u8SeamlessZappingNextIndex[SUB_WINDOW] = 0;
1258 #endif
1259
1260 #if (HW_DESIGN_4K2K_VER == 7)
1261 pXCResourcePrivate->sthal_SC.bSc1HvspFilterIsSet = FALSE;
1262 #endif
1263
1264 }
1265 #endif
1266 }
1267 }
1268
1269
XC_Initialize(XC_INSTANCE_PRIVATE * psXCInstPri,const void * const pAttribute)1270 void XC_Initialize(XC_INSTANCE_PRIVATE* psXCInstPri, const void* const pAttribute)
1271 {
1272 psXCInstPri->fpXC_GetLibVer = MApi_XC_GetLibVer_U2;
1273 psXCInstPri->fpXC_GetInfo = MApi_XC_GetInfo_U2;
1274 psXCInstPri->fpXC_GetStatus = MApi_XC_GetStatus_U2;
1275 psXCInstPri->fpXC_GetStatus_nodelay = MApi_XC_GetStatusNodelay_U2;
1276 psXCInstPri->fpXC_GetStatusEx = MApi_XC_GetStatusEx_U2;
1277 psXCInstPri->fpXC_SetDbgLevel = MApi_XC_SetDbgLevel_U2;
1278 psXCInstPri->fpXC_FPLLCustomerMode = MApi_XC_FPLLCustomerMode_U2;
1279 psXCInstPri->fpXC_SetIOMapBase = MDrv_XC_SetIOMapBase_U2;
1280 psXCInstPri->fpXC_Init = MApi_XC_Init_U2;
1281 psXCInstPri->fpXC_GetConfig = MApi_XC_GetConfig_U2;
1282 psXCInstPri->fpXC_Init_MISC = MApi_XC_Init_MISC_U2;
1283 psXCInstPri->fpXC_GetMISCStatus = MApi_XC_GetMISCStatus_U2;
1284 psXCInstPri->fpXC_GetCapability = MApi_XC_GetCapability_U2;
1285 psXCInstPri->fpXC_GetChipCaps = MApi_XC_GetChipCaps_U2;
1286 psXCInstPri->fpXC_Exit = MApi_XC_Exit_U2;
1287 psXCInstPri->fpXC_SetDynamicScaling = MApi_XC_SetDynamicScaling_U2;
1288 psXCInstPri->fpXC_SetDynamicScalingFlag = MApi_XC_Set_DynamicScalingFlag_U2;
1289 psXCInstPri->fpXC_Get_DNRBaseOffset = MApi_XC_Get_DNRBaseOffset_U2;
1290 psXCInstPri->fpXC_Get_FrameNumFactor = MApi_XC_Get_FrameNumFactor_U2;
1291 psXCInstPri->fpXC_SetWindow = MApi_XC_SetWindow_U2;
1292 psXCInstPri->fpXC_SetDualWindow = MApi_XC_SetDualWindow_U2;
1293 psXCInstPri->fpXC_SetTravelingWindow = MApi_XC_SetTravelingWindow_U2;
1294 psXCInstPri->fpXC_SetInputSource = MApi_XC_SetInputSource_U2;
1295 psXCInstPri->fpXC_IsYUVSpace = MApi_XC_IsYUVSpace_U2;
1296 psXCInstPri->fpXC_IsMemoryFormat422 = MApi_XC_IsMemoryFormat422_U2;
1297 psXCInstPri->fpXC_EnableForceRGBin = MApi_XC_EnableForceRGBin_U2;
1298 psXCInstPri->fpXC_EnableMirrorModeEx = MApi_XC_EnableMirrorModeEx_U2;
1299 psXCInstPri->fpXC_GetMirrorModeTypeEx = MApi_XC_GetMirrorModeTypeEx_U2;
1300 psXCInstPri->fpXC_GetSyncStatus = MApi_XC_GetSyncStatus_U2;
1301 psXCInstPri->fpXC_ConfigCMA = MApi_XC_ConfigCMA_U2;
1302 psXCInstPri->fpXC_WaitOutputVSync = MApi_XC_WaitOutputVSync_U2;
1303 psXCInstPri->fpXC_WaitInputVSync = MApi_XC_WaitInputVSync_U2;
1304 psXCInstPri->fpXC_SetHdmiSyncMode = MApi_XC_SetHdmiSyncMode_U2;
1305 psXCInstPri->fpXC_GetHdmiSyncMode = MApi_XC_GetHdmiSyncMode_U2;
1306 psXCInstPri->fpXC_SetRepWindow = MApi_XC_SetRepWindow_U2;
1307 psXCInstPri->fpXC_SkipOPWriteOffInSetWindow = MApi_XC_SkipOPWriteOffInSetWindow_U2;
1308 psXCInstPri->fpXC_GetSkipOPWriteOffInSetWindow = MApi_XC_GetSkipOPWriteOffInSetWindow_U2;
1309 psXCInstPri->fpXC_SetSkipDisableOPWriteOffInFPLL = MApi_XC_SetSkipDisableOPWriteOffInFPLL_U2;
1310 psXCInstPri->fpXC_Set_OPWriteOffEnable = MApi_XC_Set_OPWriteOffEnable_U2;
1311 psXCInstPri->fpXC_Set_OPWriteOffEnableToReg = MApi_XC_Set_OPWriteOffEnableToReg_U2;
1312 psXCInstPri->fpXC_ForceSet_OPWriteOffEnable = MApi_XC_ForceSet_OPWriteOffEnable_U2;
1313 psXCInstPri->fpXC_Get_OPWriteOffEnable = MApi_XC_Get_OPWriteOffEnable_U2;
1314 psXCInstPri->fpXC_SetDispWinToReg = MApi_XC_SetDispWinToReg_U2;
1315 psXCInstPri->fpXC_GetDispWinFromReg = MApi_XC_GetDispWinFromReg_U2;
1316 psXCInstPri->fpXC_FreezeImg = MApi_XC_FreezeImg_U2;
1317 psXCInstPri->fpXC_IsFreezeImg = MApi_XC_IsFreezeImg_U2;
1318 psXCInstPri->fpXC_GenerateBlackVideoForBothWin = MApi_XC_GenerateBlackVideoForBothWin_U2;
1319 psXCInstPri->fpXC_Set_BLSK = MApi_XC_Set_BLSK_U2;
1320 psXCInstPri->fpXC_GenerateBlackVideo = MApi_XC_GenerateBlackVideo_U2;
1321 psXCInstPri->fpXC_IsBlackVideoEnable = MApi_XC_IsBlackVideoEnable_U2;
1322 psXCInstPri->fpXC_EnableFrameBufferLess = MApi_XC_EnableFrameBufferLess_U2;
1323 psXCInstPri->fpXC_IsCurrentFrameBufferLessMode = MApi_XC_IsCurrentFrameBufferLessMode_U2;
1324 psXCInstPri->fpXC_EnableRequest_FrameBufferLess = MApi_XC_EnableRequest_FrameBufferLess_U2;
1325 psXCInstPri->fpXC_IsCurrentRequest_FrameBufferLessMode = MApi_XC_IsCurrentRequest_FrameBufferLessMode_U2;
1326 psXCInstPri->fpXC_Get_3D_HW_Version = MApi_XC_Get_3D_HW_Version_U2;
1327 psXCInstPri->fpXC_Get_3D_IsSupportedHW2DTo3D = MApi_XC_Get_3D_IsSupportedHW2DTo3D_U2;
1328 psXCInstPri->fpXC_Set_3D_Mode = MApi_XC_Set_3D_Mode_U2;
1329 psXCInstPri->fpXC_Set_3D_MainWin_FirstMode = MApi_XC_Set_3D_MainWin_FirstMode_U2;
1330 psXCInstPri->fpXC_Set_3D_LR_Frame_Exchg = MApi_XC_Set_3D_LR_Frame_Exchg_U2;
1331 psXCInstPri->fpXC_3D_Is_LR_Frame_Exchged = MApi_XC_3D_Is_LR_Frame_Exchged_U2;
1332 psXCInstPri->fpXC_Get_3D_Input_Mode = MApi_XC_Get_3D_Input_Mode_U2;
1333 psXCInstPri->fpXC_Get_3D_Output_Mode = MApi_XC_Get_3D_Output_Mode_U2;
1334 psXCInstPri->fpXC_Get_3D_Panel_Type = MApi_XC_Get_3D_Panel_Type_U2;
1335 psXCInstPri->fpXC_Get_3D_MainWin_First = MApi_XC_Get_3D_MainWin_First_U2;
1336 psXCInstPri->fpXC_3DMainSub_IPSync = MApi_XC_3DMainSub_IPSync_U2;
1337 psXCInstPri->fpXC_Set_3D_VerVideoOffset = MApi_XC_Set_3D_VerVideoOffset_U2;
1338 psXCInstPri->fpXC_Get_3D_VerVideoOffset = MApi_XC_Get_3D_VerVideoOffset_U2;
1339 psXCInstPri->fpXC_Is3DFormatSupported = MApi_XC_Is3DFormatSupported_U2;
1340 psXCInstPri->fpXC_Set_3D_HShift = MApi_XC_Set_3D_HShift_U2;
1341 psXCInstPri->fpXC_Enable_3D_LR_Sbs2Line = MApi_XC_Enable_3D_LR_Sbs2Line_U2;
1342 psXCInstPri->fpXC_Get_3D_HShift = MApi_XC_Get_3D_HShift_U2;
1343 psXCInstPri->fpXC_Set_3D_HW2DTo3D_Buffer = MApi_XC_Set_3D_HW2DTo3D_Buffer_U2;
1344 psXCInstPri->fpXC_Set_3D_HW2DTo3D_Parameters = MApi_XC_Set_3D_HW2DTo3D_Parameters_U2;
1345 psXCInstPri->fpXC_Get_3D_HW2DTo3D_Parameters = MApi_XC_Get_3D_HW2DTo3D_Parameters_U2;
1346 psXCInstPri->fpXC_Set_3D_Detect3DFormat_Parameters = MApi_XC_Set_3D_Detect3DFormat_Parameters_U2;
1347 psXCInstPri->fpXC_Get_3D_Detect3DFormat_Parameters = MApi_XC_Get_3D_Detect3DFormat_Parameters_U2;
1348 psXCInstPri->fpXC_Detect3DFormatByContent = MApi_XC_Detect3DFormatByContent_U2;
1349 psXCInstPri->fpXC_DetectNL = MApi_XC_DetectNL_U2;
1350 psXCInstPri->fpXC_3D_PostPQSetting = MApi_XC_3D_PostPQSetting_U2;
1351 psXCInstPri->fpXC_Set_3D_FPInfo = MApi_XC_Set_3D_FPInfo_U2;
1352 psXCInstPri->fpXC_EnableAutoDetect3D = MApi_XC_EnableAutoDetect3D_U2;
1353 psXCInstPri->fpXC_GetAutoDetect3DFlag = MApi_XC_GetAutoDetect3DFlag_U2;
1354 psXCInstPri->fpXC_Set_3D_SubWinClk = MApi_XC_Set_3D_SubWinClk_U2;
1355 psXCInstPri->fpXC_3D_Is_LR_Sbs2Line = MApi_XC_3D_Is_LR_Sbs2Line_U2;
1356 psXCInstPri->fpSC_3D_Is_Skip_Default_LR_Flag = MApi_SC_3D_Is_Skip_Default_LR_Flag_U2;
1357 psXCInstPri->fpXC_3D_Enable_Skip_Default_LR_Flag = MApi_XC_3D_Enable_Skip_Default_LR_Flag_U2;
1358 psXCInstPri->fpXC_Mux_Init = MApi_XC_Mux_Init_U2;
1359 psXCInstPri->fpXC_Mux_SourceMonitor = MApi_XC_Mux_SourceMonitor_U2;
1360 psXCInstPri->fpXC_Mux_CreatePath = MApi_XC_Mux_CreatePath_U2;
1361 psXCInstPri->fpXC_Mux_DeletePath = MApi_XC_Mux_DeletePath_U2;
1362 psXCInstPri->fpXC_Mux_EnablePath = MApi_XC_Mux_EnablePath_U2;
1363 psXCInstPri->fpXC_Mux_TriggerPathSyncEvent = MApi_XC_Mux_TriggerPathSyncEvent_U2;
1364 psXCInstPri->fpXC_Mux_TriggerDestOnOffEvent = MApi_XC_Mux_TriggerDestOnOffEvent_U2;
1365 psXCInstPri->fpXC_Mux_OnOffPeriodicHandler = MApi_XC_Mux_OnOffPeriodicHandler_U2;
1366 psXCInstPri->fpXC_Mux_GetPathInfo = MApi_XC_Mux_GetPathInfo_U2;
1367 psXCInstPri->fpXC_Mux_SetSupportMhlPathInfo = MApi_XC_Mux_SetSupportMhlPathInfo_U2;
1368 psXCInstPri->fpXC_Mux_SetMhlHotPlugInverseInfo = MApi_XC_Mux_SetMhlHotPlugInverseInfo_U2;
1369 psXCInstPri->fpXC_Mux_GetHDMIPort = MApi_XC_Mux_GetHDMIPort_U2;
1370 psXCInstPri->fpXC_Mux_GetMappingTab = MApi_XC_Mux_GetPortMappingMatrix_U2;
1371 psXCInstPri->fpXC_MUX_MApinputSourceToVDYMuxPORT = MApi_XC_MUX_MapInputSourceToVDYMuxPORT_U2;
1372 psXCInstPri->fpXC_Set_NR = MApi_XC_Set_NR_U2;
1373 psXCInstPri->fpXC_FilmMode_P = MApi_XC_FilmMode_P_U2;
1374 psXCInstPri->fpXC_GetUCEnabled = MApi_XC_GetUCEnabled_U2;
1375 psXCInstPri->fpXC_GenSpecificTiming = MApi_XC_GenSpecificTiming_U2;
1376 psXCInstPri->fpXC_GetDEBypassMode = MApi_XC_GetDEBypassMode_U2;
1377 psXCInstPri->fpXC_GetDEWindow = MApi_XC_GetDEWindow_U2;
1378 psXCInstPri->fpXC_GetDEWidthHeightInDEByPassMode = MApi_XC_GetDEWidthHeightInDEByPassMode_U2;
1379 psXCInstPri->fpXC_GetCaptureWindow = MApi_XC_GetCaptureWindow_U2;
1380 psXCInstPri->fpXC_SetCaptureWindowVstart = MApi_XC_SetCaptureWindowVstart_U2;
1381 psXCInstPri->fpXC_SetCaptureWindowHstart = MApi_XC_SetCaptureWindowHstart_U2;
1382 psXCInstPri->fpXC_SetCaptureWindowVsize = MApi_XC_SetCaptureWindowVsize_U2;
1383 psXCInstPri->fpXC_SetCaptureWindowHsize = MApi_XC_SetCaptureWindowHsize_U2;
1384 psXCInstPri->fpXC_SoftwareReset = MApi_XC_SoftwareReset_U2;
1385 psXCInstPri->fpXC_CalculateHFreqx10 = MApi_XC_CalculateHFreqx10_U2;
1386 psXCInstPri->fpXC_CalculateHFreqx1K = MApi_XC_CalculateHFreqx1K_U2;
1387 psXCInstPri->fpXC_CalculateVFreqx10 = MApi_XC_CalculateVFreqx10_U2;
1388 psXCInstPri->fpXC_CalculateVFreqx1K = MApi_XC_CalculateVFreqx1K_U2;
1389 psXCInstPri->fpXC_GetAccurateVFreqx1K = MApi_XC_GetAccurateVFreqx1K_U2;
1390 psXCInstPri->fpXC_InterruptAttach = MApi_XC_InterruptAttach_U2;
1391 psXCInstPri->fpXC_InterruptDeAttach = MApi_XC_InterruptDeAttach_U2;
1392 psXCInstPri->fpXC_DisableInputSource = MApi_XC_DisableInputSource_U2;
1393 psXCInstPri->fpXC_IsInputSourceDisabled = MApi_XC_IsInputSourceDisabled_U2;
1394 psXCInstPri->fpXC_ChangePanelType = MApi_XC_ChangePanelType_U2;
1395 psXCInstPri->fpXC_GetCurrentReadBank = MApi_XC_GetCurrentReadBank_U2;
1396 psXCInstPri->fpXC_GetCurrentWriteBank = MApi_XC_GetCurrentWriteBank_U2;
1397 psXCInstPri->fpXC_SetAutoPreScaling = MApi_XC_SetAutoPreScaling_U2;
1398 psXCInstPri->fpXC_GetVSyncWidth = MApi_XC_GetVSyncWidth_U2;
1399 psXCInstPri->fpXC_set_GOP_Enable = MApi_XC_set_GOP_Enable_U2;
1400 psXCInstPri->fpXC_ip_sel_for_gop = MApi_XC_ip_sel_for_gop_U2;
1401 psXCInstPri->fpXC_SetVOPNBL = MApi_XC_SetVOPNBL_U2;
1402 psXCInstPri->fpXC_GetDstInfo = MApi_XC_GetDstInfo_U2;
1403 psXCInstPri->fpXC_Set_FD_Mask_ByWin = MApi_XC_Set_FD_Mask_ByWin_U2;
1404 psXCInstPri->fpXC_Get_FD_Mask_ByWin = MApi_XC_Get_FD_Mask_ByWin_U2;
1405 psXCInstPri->fpXC_Get_FD_Mask_Status = MApi_XC_Get_FD_Mask_Status_U2;
1406 psXCInstPri->fpXC_SetIP1TestPattern = MApi_XC_SetIP1TestPattern_U2;
1407 #ifdef UFO_XC_TEST_PATTERN
1408 psXCInstPri->fpXC_GenerateTestPattern = MApi_XC_GenerateTestPattern_U2;
1409 #endif
1410 psXCInstPri->fpXC_InitIPForInternalTiming = MApi_XC_InitIPForInternalTiming_U2;
1411 psXCInstPri->fpXC_SetIPMux = MApi_XC_SetIPMux_U2;
1412 psXCInstPri->fpXC_Is_H_Sync_Active = MApi_XC_Is_H_Sync_Active_U2;
1413 psXCInstPri->fpXC_Is_V_Sync_Active = MApi_XC_Is_V_Sync_Active_U2;
1414 psXCInstPri->fpXC_GetAutoPositionWindow = MApi_XC_GetAutoPositionWindow_U2;
1415 psXCInstPri->fpXC_SetFrameBufferAddress = MApi_XC_SetFrameBufferAddress_U2;
1416 psXCInstPri->fpXC_SetFRCMFrameBufferAddress = MApi_XC_SetFRCMFrameBufferAddress_U2;
1417 psXCInstPri->fpXC_IsFrameBufferEnoughForCusScaling = MApi_XC_IsFrameBufferEnoughForCusScaling_U2;
1418 psXCInstPri->fpXC_SetScalerMemoryRequest = MApi_XC_SetScalerMemoryRequest_U2;
1419 psXCInstPri->fpXC_Get_PixelData = MApi_XC_Get_PixelData_U2;
1420 psXCInstPri->fpXC_GetAvailableSize = MApi_XC_GetAvailableSize_U2;
1421 psXCInstPri->fpXC_SetFrameColor = MApi_XC_SetFrameColor_U2;
1422 psXCInstPri->fpXC_SetDispWindowColor = MApi_XC_SetDispWindowColor_U2;
1423 psXCInstPri->fpXC_SupportSourceToVE = MApi_XC_SupportSourceToVE_U2;
1424 psXCInstPri->fpXC_SetOutputCapture = MApi_XC_SetOutputCapture_U2;
1425 psXCInstPri->fpXC_SetGammaOnOff = MApi_XC_SetGammaOnOff_U2;
1426 psXCInstPri->fpXC_SetPreGammaGain = MApi_XC_SetPreGammaGain_U2;
1427 psXCInstPri->fpXC_SetPreGammaOffset = MApi_XC_SetPreGammaOffset_U2;
1428 psXCInstPri->fpXC_SetPanelTiming = MApi_XC_SetPanelTiming_U2;
1429 psXCInstPri->fpXC_SetOutTimingMode = MApi_XC_SetOutTimingMode_U2;
1430 psXCInstPri->fpXC_SetFreeRunTiming = MApi_XC_SetFreeRunTiming_U2;
1431 psXCInstPri->fpXC_Set_CustomerSyncInfo = MApi_XC_Set_CustomerSyncInfo_U2;
1432 psXCInstPri->fpXC_WaitFPLLDone = MApi_XC_WaitFPLLDone_U2;
1433 psXCInstPri->fpXC_GetOutputVFreqX100 = MApi_XC_GetOutputVFreqX100_U2;
1434 psXCInstPri->fpXC_GetOP1OutputVFreqX100 = MApi_XC_GetOP1OutputVFreqX100_U2;
1435 psXCInstPri->fpXC_FrameLockCheck = MApi_XC_FrameLockCheck_U2;
1436 psXCInstPri->fpXC_CustomizeFRCTable = MApi_XC_CustomizeFRCTable_U2;
1437 psXCInstPri->fpXC_OutputFrameCtrl = MApi_XC_OutputFrameCtrl_U2;
1438 psXCInstPri->fpSC_Enable_FPLL_FSM = MApi_SC_Enable_FPLL_FSM_U2;
1439 psXCInstPri->fpSC_ForceFreerun = MApi_SC_ForceFreerun_U2;
1440 psXCInstPri->fpSC_IsForceFreerun = MApi_SC_IsForceFreerun_U2;
1441 psXCInstPri->fpSC_SetFreerunVFreq = MApi_SC_SetFreerunVFreq_U2;
1442 psXCInstPri->fpXC_SetExPanelInfo = MApi_XC_SetExPanelInfo_U2;
1443 psXCInstPri->fpXC_Enable_FPLL_Thresh_Mode = MApi_XC_Enable_FPLL_Thresh_Mode_U2;
1444 psXCInstPri->fpXC_Get_FPLL_Thresh_Mode = MApi_XC_Get_FPLL_Thresh_Mode_U2;
1445 psXCInstPri->fpXC_EnableIPAutoNoSignal = MApi_XC_EnableIPAutoNoSignal_U2;
1446 psXCInstPri->fpXC_GetIPAutoNoSignal = MApi_XC_GetIPAutoNoSignal_U2;
1447 psXCInstPri->fpXC_EnableIPAutoCoast = MApi_XC_EnableIPAutoCoast_U2;
1448 psXCInstPri->fpXC_EnableIPCoastDebounce = MApi_XC_EnableIPCoastDebounce_U2;
1449 psXCInstPri->fpXC_ClearIPCoastStatus = MApi_XC_ClearIPCoastStatus_U2;
1450 psXCInstPri->fpXC_EnableFpllManualSetting = MApi_XC_EnableFpllManualSetting_U2;
1451 psXCInstPri->fpXC_FpllBoundaryTest = MApi_XC_FpllBoundaryTest_U2;
1452 psXCInstPri->fpXC_SetOffLineDetection = MApi_XC_SetOffLineDetection_U2;
1453 psXCInstPri->fpXC_GetOffLineDetection = MApi_XC_GetOffLineDetection_U2;
1454 psXCInstPri->fpXC_SetOffLineSogThreshold = MApi_XC_SetOffLineSogThreshold_U2;
1455 psXCInstPri->fpXC_SetOffLineSogBW = MApi_XC_SetOffLineSogBW_U2;
1456 psXCInstPri->fpXC_OffLineInit = MApi_XC_OffLineInit_U2;
1457 psXCInstPri->fpXC_Set_Extra_fetch_adv_line = MApi_XC_Set_Extra_fetch_adv_line_U2;
1458 psXCInstPri->fpXC_SetVGASogEn = MApi_XC_SetVGASogEn_U2;
1459 psXCInstPri->fpXC_EnableWindow = MApi_XC_EnableWindow_U2;
1460 psXCInstPri->fpXC_Is_SubWindowEanble = MApi_XC_Is_SubWindowEanble_U2;
1461 psXCInstPri->fpXC_SetBorderFormat = MApi_XC_SetBorderFormat_U2;
1462 psXCInstPri->fpXC_EnableBorder = MApi_XC_EnableBorder_U2;
1463 psXCInstPri->fpXC_ZorderMainWindowFirst = MApi_XC_ZorderMainWindowFirst_U2;
1464 psXCInstPri->fpXC_PQ_LoadFunction = MApi_XC_PQ_LoadFunction_U2;
1465 psXCInstPri->fpXC_Check_HNonLinearScaling = MApi_XC_Check_HNonLinearScaling_U2;
1466 psXCInstPri->fpXC_EnableEuroHdtvSupport = MApi_XC_EnableEuroHdtvSupport_U2;
1467 psXCInstPri->fpXC_EnableEuroHdtvDetection = MApi_XC_EnableEuroHdtvDetection_U2;
1468 psXCInstPri->fpXC_ReadByte = MApi_XC_ReadByte_U2;
1469 psXCInstPri->fpXC_WriteByte = MApi_XC_WriteByte_U2;
1470 psXCInstPri->fpXC_WriteByteMask = MApi_XC_WriteByteMask_U2;
1471 psXCInstPri->fpXC_Write2ByteMask = MApi_XC_Write2ByteMask_U2;
1472 psXCInstPri->fpXC_W2BYTE = MApi_XC_W2BYTE_U2;
1473 psXCInstPri->fpXC_R2BYTE = MApi_XC_R2BYTE_U2;
1474 psXCInstPri->fpXC_W4BYTE = MApi_XC_W4BYTE_U2;
1475 psXCInstPri->fpXC_R4BYTE = MApi_XC_R4BYTE_U2;
1476 psXCInstPri->fpXC_R2BYTEMSK = MApi_XC_R2BYTEMSK_U2;
1477 psXCInstPri->fpXC_W2BYTEMSK = MApi_XC_W2BYTEMSK_U2;
1478 psXCInstPri->fpXC_MLoad_Init = MApi_XC_MLoad_Init_U2;
1479 psXCInstPri->fpXC_MLoad_Enable = MApi_XC_MLoad_Enable_U2;
1480 psXCInstPri->fpXC_MLoad_Cus_Init = MApi_XC_MLoad_Cus_Init_U2;
1481 psXCInstPri->fpXC_MLoad_Cus_Enable = MApi_XC_MLoad_Cus_Enable_U2;
1482 psXCInstPri->fpXC_MLoad_GetStatus = MApi_XC_MLoad_GetStatus_U2;
1483 psXCInstPri->fpXC_MLoad_WriteCmd_And_Fire = MApi_XC_MLoad_WriteCmd_And_Fire_U2;
1484 psXCInstPri->fpXC_MLoad_WriteCmds_And_Fire = MApi_XC_MLoad_WriteCmds_And_Fire_U2;
1485 psXCInstPri->fpXC_MLoad_Combine_Enable = MApi_XC_Combine_MLoadEn_U2;
1486 psXCInstPri->fpXC_MLG_Init = MApi_XC_MLG_Init_U2;
1487 psXCInstPri->fpXC_MLG_Enable = MApi_XC_MLG_Enable_U2;
1488 psXCInstPri->fpXC_MLG_GetCaps = MApi_XC_MLG_GetCaps_U2;
1489 psXCInstPri->fpXC_MLG_GetStatus = MApi_XC_MLG_GetStatus_U2;
1490 psXCInstPri->fpXC_SetOSD2VEMode = MApi_XC_SetOSD2VEMode_U2;
1491 psXCInstPri->fpXC_IP2_PreFilter_Enable = MApi_XC_IP2_PreFilter_Enable_U2;
1492 psXCInstPri->fpXC_Get_Pixel_RGB = MApi_XC_Get_Pixel_RGB_U2;
1493 psXCInstPri->fpXC_KeepPixelPointerAppear = MApi_XC_KeepPixelPointerAppear_U2;
1494 psXCInstPri->fpXC_Set_MemFmtEx = MApi_XC_Set_MemFmtEx_U2;
1495 psXCInstPri->fpXC_IsRequestFrameBufferLessMode = MApi_XC_IsRequestFrameBufferLessMode_U2;
1496 psXCInstPri->fpXC_SkipSWReset = MApi_XC_SkipSWReset_U2;
1497 psXCInstPri->fpXC_EnableRepWindowForFrameColor = MApi_XC_EnableRepWindowForFrameColor_U2;
1498 psXCInstPri->fpXC_SetOSDLayer = MApi_XC_SetOSDLayer_U2;
1499 psXCInstPri->fpXC_GetOSDLayer = MApi_XC_GetOSDLayer_U2;
1500 psXCInstPri->fpXC_SetVideoAlpha = MApi_XC_SetVideoAlpha_U2;
1501 psXCInstPri->fpXC_GetVideoAlpha = MApi_XC_GetVideoAlpha_U2;
1502 psXCInstPri->fpXC_SkipWaitVsync = MApi_XC_SkipWaitVsync_U2;
1503 psXCInstPri->fpXC_SetCMAHeapID = MApi_XC_SetCMAHeapID_U2;
1504 psXCInstPri->fpXC_OP2VOPDESel = MApi_XC_OP2VOPDESel_U2;
1505 psXCInstPri->fpXC_FRC_SetWindow = MApi_XC_FRC_SetWindow_U2;
1506 psXCInstPri->fpXC_Enable_TwoInitFactor = MApi_XC_Enable_TwoInitFactor_U2;
1507 psXCInstPri->fpXC_IsFieldPackingModeSupported = MApi_XC_IsFieldPackingModeSupported_U2;
1508 psXCInstPri->fpXC_PreInit = MApi_XC_PreInit_U2;
1509 psXCInstPri->fpXC_Get_BufferData = MApi_XC_Get_BufferData_U2;
1510 psXCInstPri->fpXC_Set_BufferData = MApi_XC_Set_BufferData_U2;
1511 psXCInstPri->fpXC_EnableMainWindow = MApi_XC_EnableMainWindow_U2;
1512 psXCInstPri->fpXC_EnableSubWindow = MApi_XC_EnableSubWindow_U2;
1513 psXCInstPri->fpXC_DisableSubWindow = MApi_XC_DisableSubWindow_U2;
1514 psXCInstPri->fpXC_SetPixelShift = MApi_XC_SetPixelShift_U2;
1515 psXCInstPri->fpXC_SetVideoOnOSD = MApi_XC_SetVideoOnOSD_U2;
1516 psXCInstPri->fpXC_SetOSDLayerBlending = MApi_XC_SetOSDLayerBlending_U2;
1517 psXCInstPri->fpXC_SetOSDLayerAlpha = MApi_XC_SetOSDLayerAlpha_U2;
1518 psXCInstPri->fpXC_SetOSDBlendingFormula = MApi_XC_SetOSDBlendingFormula_U2;
1519 psXCInstPri->fpXC_ReportPixelInfo = MApi_XC_ReportPixelInfo_U2;
1520 psXCInstPri->fpXC_SetScaling = MApi_XC_SetScaling_U2;
1521 psXCInstPri->fpXC_SetMCDIBufferAddress = MApi_XC_SetMCDIBufferAddress_U2;
1522 psXCInstPri->fpXC_EnableMCDI = MApi_XC_EnableMCDI_U2;
1523 psXCInstPri->fpXC_SendCmdToFRC = MApi_XC_SendCmdToFRC_U2;
1524 psXCInstPri->fpXC_GetMsgFromFRC = MApi_XC_GetMsgFromFRC_U2;
1525 psXCInstPri->fpXC_EnableRWBankAuto = MApi_XC_EnableRWBankAuto_U2;
1526 psXCInstPri->fpXC_SetWRBankMappingNum = MApi_XC_SetWRBankMappingNum_U2;
1527 psXCInstPri->fpXC_GetWRBankMappingNum = MApi_XC_GetWRBankMappingNum_U2;
1528 psXCInstPri->fpXC_GetWRBankMappingNumForZap = MApi_XC_GetWRBankMappingNumForZap_U2;
1529 psXCInstPri->fpXC_SetBOBMode = MApi_XC_SetBOBMode_U2;
1530 psXCInstPri->fpXC_SetForceReadBank = MApi_XC_SetForceReadBank_U2;
1531 psXCInstPri->fpXC_SetLockPoint = MApi_XC_SetLockPoint_U2;
1532 psXCInstPri->fpXC_LD_Init = MApi_XC_LD_Init_U2;
1533 psXCInstPri->fpXC_LD_SetMemoryAddress = MApi_XC_LD_SetMemoryAddress_U2;
1534 psXCInstPri->fpXC_LD_Get_Value = MApi_XC_LD_Get_Value_U2;
1535 psXCInstPri->fpXC_LD_SetLevel = MApi_XC_LD_SetLevel_U2;
1536 psXCInstPri->fpSet_TurnoffLDBL = MApi_Set_TurnoffLDBL_U2;
1537 psXCInstPri->fpSet_notUpdateSPIDataFlags = MApi_Set_notUpdateSPIDataFlags_U2;
1538 psXCInstPri->fpSet_UsermodeLDFlags = MApi_Set_UsermodeLDFlags_U2;
1539 psXCInstPri->fpSet_BLLevel = MApi_Set_BLLevel_U2;
1540 psXCInstPri->fpXC_Set_BWS_Mode = MApi_XC_Set_BWS_Mode_U2;
1541 psXCInstPri->fpXC_FRC_ColorPathCtrl = MApi_XC_FRC_ColorPathCtrl_U2;
1542 psXCInstPri->fpXC_FRC_OP2_SetRGBGain = MApi_XC_FRC_OP2_SetRGBGain_U2;
1543 psXCInstPri->fpXC_FRC_OP2_SetRGBOffset = MApi_XC_FRC_OP2_SetRGBOffset_U2;
1544 psXCInstPri->fpXC_FRC_OP2_SetDither = MApi_XC_FRC_OP2_SetDither_U2;
1545 psXCInstPri->fpXC_FRC_BypassMFC = MApi_XC_FRC_BypassMFC_U2;
1546 psXCInstPri->fpXC_FRC_Mute = MApi_XC_FRC_Mute_U2;
1547 psXCInstPri->fpXC_ForceReadFrame = MApi_XC_ForceReadFrame_U2;
1548 psXCInstPri->fpXC_SetCsc = MApi_XC_SetCsc_U2;
1549 psXCInstPri->fpXC_RegisterPQSetFPLLThreshMode = MApi_XC_RegisterPQSetFPLLThreshMode_U2;
1550 psXCInstPri->fpXC_GetFreeRunStatus = MApi_XC_GetFreeRunStatus_U2;
1551 psXCInstPri->fpXC_BYPASS_SetCSC = MApi_XC_BYPASS_SetCSC_U2;
1552 psXCInstPri->fpXC_Get_DSForceIndexSupported = MApi_XC_Get_DSForceIndexSupported_U2;
1553 psXCInstPri->fpXC_Set_DSForceIndex = MApi_XC_Set_DSForceIndex_U2;
1554 psXCInstPri->fpXC_Set_DSIndexSourceSelect = MApi_XC_Set_DSIndexSourceSelect_U2;
1555 psXCInstPri->fpXC_GetDynamicScalingStatus = MApi_XC_GetDynamicScalingStatus_U2;
1556 psXCInstPri->fpXC_OSDC_InitSetting = MApi_XC_OSDC_InitSetting_U2;
1557 psXCInstPri->fpXC_OSDC_SetOutVfreqx10 = MApi_XC_OSDC_SetOutVfreqx10_U2;
1558 psXCInstPri->fpXC_OSDC_Control = MApi_XC_OSDC_Control_U2;
1559 psXCInstPri->fpXC_OSDC_GetDstInfo = MApi_XC_OSDC_GetDstInfo_U2;
1560 psXCInstPri->fpXC_Set_PowerState = MApi_XC_SetPowerState_U2;
1561 psXCInstPri->fpXC_BYPASS_SetOSDVsyncPos = MApi_XC_BYPASS_SetOSDVsyncPos_U2;
1562 psXCInstPri->fpXC_BYPASS_SetInputSrc = MApi_XC_BYPASS_SetInputSrc_U2;
1563 psXCInstPri->fpXC_SetSeamlessZapping = MApi_XC_SetSeamlessZapping_U2;
1564 psXCInstPri->fpXC_GetSeamlessZappingStatus = MApi_XC_GetSeamlessZappingStatus_U2;
1565 psXCInstPri->fpXC_Vtrack_SetPayloadData = MApi_XC_Vtrack_SetPayloadData_U2;
1566 psXCInstPri->fpXC_Vtrack_SetUserDefindedSetting = MApi_XC_Vtrack_SetUserDefindedSetting_U2;
1567 psXCInstPri->fpXC_Vtrack_Enable = MApi_XC_Vtrack_Enable_U2;
1568 psXCInstPri->fpXC_PreSetPQInfo = MApi_XC_PreSetPQInfo_U2;
1569 psXCInstPri->fpXC_Is_OP1_TestPattern_Enabled = MApi_XC_Is_OP1_TestPattern_Enabled_U2;
1570 psXCInstPri->fpXC_Set_OP1_TestPattern = MApi_XC_Set_OP1_TestPattern_U2;
1571 psXCInstPri->fpXC_Set_OP2_TestPattern = MApi_XC_Set_OP2_Pattern_U2;
1572 psXCInstPri->fpXC_Check_WhiteBalance_Pattern_Mode = MApi_XC_CheckWhiteBalancePatternModeSupport_U2;
1573 psXCInstPri->fpXC_Set_HLinearScaling = MApi_XC_SetHLinearScaling_U2;
1574 psXCInstPri->fpXC_EnableT3D = MApi_XC_EnableT3D_U2;
1575 psXCInstPri->fpXC_Set_FRC_InputTiming = MApi_XC_Set_FRC_InputTiming_U2;
1576 psXCInstPri->fpXC_Get_FRC_InputTiming = MApi_XC_Get_FRC_InputTiming_U2;
1577 psXCInstPri->fpXC_Get_VirtualBox_Info = MApi_XC_Get_VirtualBox_Info_U2;
1578 psXCInstPri->fpXC_Set_OSD_DETECT = MApi_XC_Set_OSD_Detect_U2;
1579 psXCInstPri->fpXC_Get_OSD_DETECT = MApi_XC_Get_OSD_Detect_U2;
1580 psXCInstPri->fpXC_Enable_LockFreqOnly = MApi_XC_Enable_LockFreqOnly_U2;
1581 psXCInstPri->fpXC_Is2K2KToFrcMode = MApi_XC_Is2K2KToFrcMode_U2;
1582 psXCInstPri->fpXC_SetXCVOPdata = MApi_XC_Set_XC_VOP_U2;
1583 psXCInstPri->fpXC_GetSWDSIndex = MApi_XC_GetSWDSIndex_U2;
1584 psXCInstPri->fpXC_Get_Is_SupportSWDS = MApi_XC_Is_SupportSWDS_U2;
1585 psXCInstPri->fpXC_Get_FRCM_FrameNum = MApi_XC_Get_FRCM_FrameNum_U2;
1586 psXCInstPri->fpXC_SetPixelShiftFeatures = MApi_XC_SetPixelShiftFeatures_U2;
1587 psXCInstPri->fpXC_SetForceWrite = MApi_XC_SetForceWrite_U2;
1588 psXCInstPri->fpXC_GetForceWrite = MApi_XC_GetForceWrite_U2;
1589 #ifdef UFO_XC_PQ_PATH
1590 psXCInstPri->fpXC_GetPQPathStatus = MApi_XC_GetPQPathStatus_U2;
1591 #endif
1592 #ifdef UFO_XC_AUTO_DOWNLOAD
1593 psXCInstPri->fpXC_AutoDownloadConfig = MApi_XC_AutoDownload_Config_U2;
1594 psXCInstPri->fpXC_AutoDownloadWrite = MApi_XC_AutoDownload_Write_U2;
1595 psXCInstPri->fpXC_AutoDownloadFire = MApi_XC_AutoDownload_Fire_U2;
1596 #endif
1597 #ifdef UFO_XC_HDR
1598 #if (UFO_XC_HDR_VERSION == 2)
1599 psXCInstPri->fpXC_HDRControl = MApi_XC_HDR_Control_U2;
1600 #endif
1601 #endif
1602 psXCInstPri->fpXC_OPTEE_Ctrl = MApi_XC_OPTEE_Control_U2;
1603 psXCInstPri->fpXC_OPTEE_CheckRBase = MApi_XC_OPTEE_CheckRBase_U2;
1604 psXCInstPri->fpXC_OPTEE_Mux = MApi_XC_OPTEE_Mux_U2;
1605 psXCInstPri->fpXC_GetResourceByPipeID = MApi_XC_GetResourceByPipeID_U2;
1606 psXCInstPri->fpXC_ConfigPipe = MApi_XC_ConfigPipe_U2;
1607 psXCInstPri->fpXC_CheckPipe = MApi_XC_CheckPipe_U2;
1608
1609 #ifdef UFO_XC_SET_DSINFO_V0
1610 psXCInstPri->fpXC_SetDSInfo = MApi_XC_SetDSInfo_U2;
1611 #endif
1612 //** OBSELETE FUNCTIONS **//
1613 psXCInstPri->fpsc_get_output_vfreq = mvideo_sc_get_output_vfreq_U2;
1614 psXCInstPri->fpXC_Get_Current_OutputVFreqX100 = MApi_XC_Get_Current_OutputVFreqX100_U2;
1615 psXCInstPri->fpXC_SetMemoryWriteRequest = MApi_XC_SetMemoryWriteRequest_U2;
1616 psXCInstPri->fpXC_Set_MemFmt = MApi_XC_Set_MemFmt_U2;
1617 psXCInstPri->fpXC_SetOutputAdjustSetting = MApi_XC_SetOutputAdjustSetting_U2;
1618 psXCInstPri->fsScaler_FPLL_FSM = msAPI_Scaler_FPLL_FSM_U2;
1619 psXCInstPri->fpXC_EnableMirrorMode = MApi_XC_EnableMirrorMode_U2;
1620 psXCInstPri->fpXC_EnableMirrorMode2 = MApi_XC_EnableMirrorMode2_U2;
1621 #ifdef SUPPORT_BWD
1622 psXCInstPri->fpXC_SetBwdConfig = MApi_XC_SetBwdConfig_U2;
1623 #endif
1624 //** OBSELETE FUNCTIONS**//
1625 psXCInstPri->fpXC_dump_shm = MApi_XC_Dump_SHM_U2;
1626 psXCInstPri->fpXC_IsSupport2StepScaling = MApi_XC_IsSupport2StepScaling_U2;
1627 psXCInstPri->fpXC_VideoPlaybackCtrl = MApi_XC_VideoPlaybackCtrl_U2;
1628
1629 #ifdef UFO_XC_SETBLACKVIDEOBYMODE
1630 psXCInstPri->fpXC_GenerateBlackVideoByMode = MApi_XC_GenerateBlackVideoByMode_U2;
1631 #endif
1632 psXCInstPri->fpXC_swds_fire = MApi_SWDS_Fire_U2;
1633
1634 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1635 psXCInstPri->fpXC_enableDualMode = MApi_XC_EnableMiuDualMode_U2;
1636 #endif
1637
1638 #ifdef UFO_XC_GET_3D_FORMAT
1639 psXCInstPri->fpXC_Get3DFormat = MApi_XC_Get3DFormat_U2;
1640 #endif
1641
1642 #ifdef UFO_XC_FB_LEVEL
1643 psXCInstPri->fpXC_SetFBLevel = MApi_XC_Set_FB_Level_U2;
1644 psXCInstPri->fpXC_GetFBLevel = MApi_XC_Get_FB_Level_U2;
1645 #endif
1646 psXCInstPri->fpXC_Set_SWDR_Info = MApi_XC_SetSWDRInfo_U2;
1647 psXCInstPri->fpXC_Get_SWDR_Info = MApi_XC_GetSWDRInfo_U2;
1648 #ifdef UFO_XC_SUPPORT_HDMI_DOWNSCALE_OUTPUT_POLICY
1649 psXCInstPri->fpXC_GetHDMIPolicy = MApi_XC_GetHDMIPolicy_U2;
1650 #endif
1651 }
1652
XC_U1_U2_RELATION(void ** ppInstance,const void * const pAttribute)1653 void XC_U1_U2_RELATION(void** ppInstance, const void* const pAttribute)
1654 {
1655 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1656 UtopiaInstanceGetPrivate(*ppInstance, (void**)&psXCInstPri);
1657 psXCInstPri->u32DeviceID = 0;
1658
1659 #define URELATION(a,b,c) psXCInstPri->_URELATION_ASSIGN(a,b,c)
1660 URELATION(fpXC_GetLibVer,(IOCTL_XC_GETLIBVER)MApi_XC_GetLibVer_U2,MApi_XC_GetLibVer)
1661 URELATION(fpXC_GetInfo,(IOCTL_XC_GETINFO)MApi_XC_GetInfo_U2,MApi_XC_GetInfo)
1662 URELATION(fpXC_GetStatus,(IOCTL_XC_GETSTATUS)MApi_XC_GetStatus_U2,MApi_XC_GetStatus)
1663 URELATION(fpXC_GetStatus_nodelay,(IOCTL_XC_GETSTATUS_NODELAY)MApi_XC_GetStatusNodelay_U2,MApi_XC_GetStatusNodelay)
1664 URELATION(fpXC_GetStatusEx,(IOCTL_XC_GETSTATUSEX)MApi_XC_GetStatusEx_U2,MApi_XC_GetStatusEx)
1665 URELATION(fpXC_SetDbgLevel,(IOCTL_XC_SETDBGLEVEL)MApi_XC_SetDbgLevel_U2,MApi_XC_SetDbgLevel)
1666 URELATION(fpXC_FPLLCustomerMode,(IOCTL_XC_FPLLCUSTOMERMODE)MApi_XC_FPLLCustomerMode_U2,MApi_XC_FPLLCustomerMode)
1667 URELATION(fpXC_SetIOMapBase,(IOCTL_XC_SETIOMAPBASE)MDrv_XC_SetIOMapBase_U2,MDrv_XC_SetIOMapBase)
1668 URELATION(fpXC_Init,(IOCTL_XC_INIT)MApi_XC_Init_U2,MApi_XC_Init)
1669 URELATION(fpXC_GetConfig,(IOCTL_XC_GETCONFIG)MApi_XC_GetConfig_U2,MApi_XC_GetConfig)
1670 URELATION(fpXC_Init_MISC,(IOCTL_XC_INIT_MISC)MApi_XC_Init_MISC_U2,MApi_XC_Init_MISC)
1671 URELATION(fpXC_GetMISCStatus,(IOCTL_XC_GETMISCSTATUS)MApi_XC_GetMISCStatus_U2,MApi_XC_GetMISCStatus)
1672 URELATION(fpXC_GetCapability,(IOCTL_XC_GETCAPABILITY)MApi_XC_GetCapability_U2,MApi_XC_GetCapability)
1673 URELATION(fpXC_GetChipCaps,(IOCTL_XC_GETCHIPCAPS)MApi_XC_GetChipCaps_U2,MApi_XC_GetChipCaps)
1674 URELATION(fpXC_Exit,(IOCTL_XC_EXIT)MApi_XC_Exit_U2,MApi_XC_Exit)
1675 URELATION(fpXC_SetDynamicScaling,(IOCTL_XC_SETDYNAMICSCALING)MApi_XC_SetDynamicScaling_U2,MApi_XC_SetDynamicScaling)
1676 URELATION(fpXC_SetDynamicScalingFlag,(IOCTL_XC_SETDYNAMICSCALING_FLAG)MApi_XC_Set_DynamicScalingFlag_U2,MApi_XC_Set_DynamicScalingFlag)
1677 URELATION(fpXC_Get_DNRBaseOffset,(IOCTL_XC_GET_DNRBASEOFFSET)MApi_XC_Get_DNRBaseOffset_U2,MApi_XC_Get_DNRBaseOffset)
1678 URELATION(fpXC_Get_FrameNumFactor,(IOCTL_XC_GET_FRAMENUMFACTOR)MApi_XC_Get_FrameNumFactor_U2,MApi_XC_Get_FrameNumFactor)
1679 URELATION(fpXC_SetWindow,(IOCTL_XC_SETWINDOW)MApi_XC_SetWindow_U2,MApi_XC_SetWindow)
1680 URELATION(fpXC_SetDualWindow,(IOCTL_XC_SETDUALWINDOW)MApi_XC_SetDualWindow_U2,MApi_XC_SetDualWindow)
1681 URELATION(fpXC_SetTravelingWindow,(IOCTL_XC_SETTRAVELINGWINDOW)MApi_XC_SetTravelingWindow_U2,MApi_XC_SetTravelingWindow)
1682 URELATION(fpXC_SetInputSource,(IOCTL_XC_SETINPUTSOURCE)MApi_XC_SetInputSource_U2,MApi_XC_SetInputSource)
1683 URELATION(fpXC_IsYUVSpace,(IOCTL_XC_ISYUVSPACE)MApi_XC_IsYUVSpace_U2,MApi_XC_IsYUVSpace)
1684 URELATION(fpXC_IsMemoryFormat422,(IOCTL_XC_ISMEMORYFORMAT422)MApi_XC_IsMemoryFormat422_U2,MApi_XC_IsMemoryFormat422)
1685 URELATION(fpXC_EnableForceRGBin,(IOCTL_XC_ENABLEFORCERGBIN)MApi_XC_EnableForceRGBin_U2,MApi_XC_EnableForceRGBin)
1686 URELATION(fpXC_EnableMirrorModeEx,(IOCTL_XC_ENABLEMIRRORMODEEX)MApi_XC_EnableMirrorModeEx_U2,MApi_XC_EnableMirrorModeEx)
1687 URELATION(fpXC_GetMirrorModeTypeEx,(IOCTL_XC_GETMIRRORMODETYPEEX)MApi_XC_GetMirrorModeTypeEx_U2,MApi_XC_GetMirrorModeTypeEx)
1688 URELATION(fpXC_GetSyncStatus,(IOCTL_XC_GETSYNCSTATUS)MApi_XC_GetSyncStatus_U2,MApi_XC_GetSyncStatus)
1689 URELATION(fpXC_ConfigCMA,(IOCTL_XC_CONFIGCMA)MApi_XC_ConfigCMA_U2,MApi_XC_ConfigCMA)
1690 URELATION(fpXC_WaitOutputVSync,(IOCTL_XC_WAITOUTPUTVSYNC)MApi_XC_WaitOutputVSync_U2,MApi_XC_WaitOutputVSync)
1691 URELATION(fpXC_WaitInputVSync,(IOCTL_XC_WAITINPUTVSYNC)MApi_XC_WaitInputVSync_U2,MApi_XC_WaitInputVSync)
1692 URELATION(fpXC_SetHdmiSyncMode,(IOCTL_XC_SETHDMISYNCMODE)MApi_XC_SetHdmiSyncMode_U2,MApi_XC_SetHdmiSyncMode)
1693 URELATION(fpXC_GetHdmiSyncMode,(IOCTL_XC_GETHDMISYNCMODE)MApi_XC_GetHdmiSyncMode_U2,MApi_XC_GetHdmiSyncMode)
1694 URELATION(fpXC_SetRepWindow,(IOCTL_XC_SETREPWINDOW)MApi_XC_SetRepWindow_U2,MApi_XC_SetRepWindow)
1695 URELATION(fpXC_SkipOPWriteOffInSetWindow,(IOCTL_XC_SET_SKIP_OPWRITEOFF_IN_SETWINDOW)MApi_XC_SkipOPWriteOffInSetWindow_U2,MApi_XC_SkipOPWriteOffInSetWindow)
1696 URELATION(fpXC_GetSkipOPWriteOffInSetWindow,(IOCTL_XC_GET_SKIP_OPWRITEOFF_IN_SETWINDOW)MApi_XC_GetSkipOPWriteOffInSetWindow_U2,MApi_XC_GetSkipOPWriteOffInSetWindow)
1697 URELATION(fpXC_SetSkipDisableOPWriteOffInFPLL,(IOCTL_XC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL)MApi_XC_SetSkipDisableOPWriteOffInFPLL_U2,MApi_XC_SetSkipDisableOPWriteOffInFPLL)
1698 URELATION(fpXC_Set_OPWriteOffEnable,(IOCTL_XC_SET_OPWRITEOFFENABLE)MApi_XC_Set_OPWriteOffEnable_U2,MApi_XC_Set_OPWriteOffEnable)
1699 URELATION(fpXC_Set_OPWriteOffEnableToReg,(IOCTL_XC_SET_OPWRITEOFF_ENABLE_TO_REG)MApi_XC_Set_OPWriteOffEnableToReg_U2,MApi_XC_Set_OPWriteOffEnableToReg)
1700 URELATION(fpXC_ForceSet_OPWriteOffEnable,(IOCTL_XC_FORCESET_OPWRITEOFF_ENABLE)MApi_XC_ForceSet_OPWriteOffEnable_U2,MApi_XC_ForceSet_OPWriteOffEnable)
1701 URELATION(fpXC_Get_OPWriteOffEnable,(IOCTL_XC_GET_OPWRITEOFFENABLE)MApi_XC_Get_OPWriteOffEnable_U2,MApi_XC_Get_OPWriteOffEnable)
1702 URELATION(fpXC_SetDispWinToReg,(IOCTL_XC_SETDISPWINTOREG)MApi_XC_SetDispWinToReg_U2,MApi_XC_SetDispWinToReg)
1703 URELATION(fpXC_GetDispWinFromReg,(IOCTL_XC_GETDISPWINFROMREG)MApi_XC_GetDispWinFromReg_U2,MApi_XC_GetDispWinFromReg)
1704 URELATION(fpXC_FreezeImg,(IOCTL_XC_FREEZEIMG)MApi_XC_FreezeImg_U2,MApi_XC_FreezeImg)
1705 URELATION(fpXC_IsFreezeImg,(IOCTL_XC_ISFREEZEIMG)MApi_XC_IsFreezeImg_U2,MApi_XC_IsFreezeImg)
1706 URELATION(fpXC_GenerateBlackVideoForBothWin,(IOCTL_XC_GENERATEBLACKVIDEOFORBOTHWIN)MApi_XC_GenerateBlackVideoForBothWin_U2,MApi_XC_GenerateBlackVideoForBothWin)
1707 URELATION(fpXC_Set_BLSK,(IOCTL_XC_SET_BLSK)MApi_XC_Set_BLSK_U2,MApi_XC_Set_BLSK)
1708 URELATION(fpXC_GenerateBlackVideo,(IOCTL_XC_GENERATEBLACKVIDEO)MApi_XC_GenerateBlackVideo_U2,MApi_XC_GenerateBlackVideo)
1709 URELATION(fpXC_IsBlackVideoEnable,(IOCTL_XC_ISBLACKVIDEOENABLE)MApi_XC_IsBlackVideoEnable_U2,MApi_XC_IsBlackVideoEnable)
1710 URELATION(fpXC_EnableFrameBufferLess,(IOCTL_XC_ENABLEFRAMEBUFFERLESS)MApi_XC_EnableFrameBufferLess_U2,MApi_XC_EnableFrameBufferLess)
1711 URELATION(fpXC_IsCurrentFrameBufferLessMode,(IOCTL_XC_ISCURRENTFRAMEBUFFERLESSMODE)MApi_XC_IsCurrentFrameBufferLessMode_U2,MApi_XC_IsCurrentFrameBufferLessMode)
1712 URELATION(fpXC_EnableRequest_FrameBufferLess,(IOCTL_XC_ENABLEREQUEST_FRAMEBUFFERLESS)MApi_XC_EnableRequest_FrameBufferLess_U2,MApi_XC_EnableRequest_FrameBufferLess)
1713 URELATION(fpXC_IsCurrentRequest_FrameBufferLessMode,(IOCTL_XC_ISCURRENTREQUEST_FRAMEBUFFERLESSMODE)MApi_XC_IsCurrentRequest_FrameBufferLessMode_U2,MApi_XC_IsCurrentRequest_FrameBufferLessMode)
1714 URELATION(fpXC_Get_3D_HW_Version,(IOCTL_XC_GET_3D_HW_VERSION)MApi_XC_Get_3D_HW_Version_U2,MApi_XC_Get_3D_HW_Version)
1715 URELATION(fpXC_Get_3D_IsSupportedHW2DTo3D,(IOCTL_XC_GET_3D_ISSUPPORTEDHW2DTO3D)MApi_XC_Get_3D_IsSupportedHW2DTo3D_U2,MApi_XC_Get_3D_IsSupportedHW2DTo3D)
1716 URELATION(fpXC_Set_3D_Mode,(IOCTL_XC_SET_3D_MODE)MApi_XC_Set_3D_Mode_U2,MApi_XC_Set_3D_Mode)
1717 URELATION(fpXC_Set_3D_MainWin_FirstMode,(IOCTL_XC_SET_3D_MAINWIN_FIRSTMODE)MApi_XC_Set_3D_MainWin_FirstMode_U2,MApi_XC_Set_3D_MainWin_FirstMode)
1718 URELATION(fpXC_Set_3D_LR_Frame_Exchg,(IOCTL_XC_SET_3D_LR_FRAME_EXCHG)MApi_XC_Set_3D_LR_Frame_Exchg_U2,MApi_XC_Set_3D_LR_Frame_Exchg)
1719 URELATION(fpXC_3D_Is_LR_Frame_Exchged,(IOCTL_XC_3D_IS_LR_FRAME_EXCHGED)MApi_XC_3D_Is_LR_Frame_Exchged_U2,MApi_XC_3D_Is_LR_Frame_Exchged)
1720 URELATION(fpXC_Get_3D_Input_Mode,(IOCTL_XC_GET_3D_INPUT_MODE)MApi_XC_Get_3D_Input_Mode_U2,MApi_XC_Get_3D_Input_Mode)
1721 URELATION(fpXC_Get_3D_Output_Mode,(IOCTL_XC_GET_3D_OUTPUT_MODE)MApi_XC_Get_3D_Output_Mode_U2,MApi_XC_Get_3D_Output_Mode)
1722 URELATION(fpXC_Get_3D_Panel_Type,(IOCTL_XC_GET_3D_PANEL_TYPE)MApi_XC_Get_3D_Panel_Type_U2,MApi_XC_Get_3D_Panel_Type)
1723 URELATION(fpXC_Get_3D_MainWin_First,(IOCTL_XC_GET_3D_MAINWIN_FIRST)MApi_XC_Get_3D_MainWin_First_U2,MApi_XC_Get_3D_MainWin_First)
1724 URELATION(fpXC_3DMainSub_IPSync,(IOCTL_XC_3DMAINSUB_IPSYNC)MApi_XC_3DMainSub_IPSync_U2,MApi_XC_3DMainSub_IPSync)
1725 URELATION(fpXC_Set_3D_VerVideoOffset,(IOCTL_XC_SET_3D_VERVIDEOOFFSET)MApi_XC_Set_3D_VerVideoOffset_U2,MApi_XC_Set_3D_VerVideoOffset)
1726 URELATION(fpXC_Get_3D_VerVideoOffset,(IOCTL_XC_GET_3D_VERVIDEOOFFSET)MApi_XC_Get_3D_VerVideoOffset_U2,MApi_XC_Get_3D_VerVideoOffset)
1727 URELATION(fpXC_Is3DFormatSupported,(IOCTL_XC_IS3DFORMATSUPPORTED)MApi_XC_Is3DFormatSupported_U2,MApi_XC_Is3DFormatSupported)
1728 URELATION(fpXC_Set_3D_HShift,(IOCTL_XC_SET_3D_HSHIFT)MApi_XC_Set_3D_HShift_U2,MApi_XC_Set_3D_HShift)
1729 URELATION(fpXC_Enable_3D_LR_Sbs2Line,(IOCTL_XC_ENABLE_3D_LR_SBS2LINE)MApi_XC_Enable_3D_LR_Sbs2Line_U2,MApi_XC_Enable_3D_LR_Sbs2Line)
1730 URELATION(fpXC_Get_3D_HShift,(IOCTL_XC_GET_3D_HSHIFT)MApi_XC_Get_3D_HShift_U2,MApi_XC_Get_3D_HShift)
1731 URELATION(fpXC_Set_3D_HW2DTo3D_Buffer,(IOCTL_XC_SET_3D_HW2DTO3D_BUFFER)MApi_XC_Set_3D_HW2DTo3D_Buffer_U2,MApi_XC_Set_3D_HW2DTo3D_Buffer)
1732 URELATION(fpXC_Set_3D_HW2DTo3D_Parameters,(IOCTL_XC_SET_3D_HW2DTO3D_PARAMETERS)MApi_XC_Set_3D_HW2DTo3D_Parameters_U2,MApi_XC_Set_3D_HW2DTo3D_Parameters)
1733 URELATION(fpXC_Get_3D_HW2DTo3D_Parameters,(IOCTL_XC_GET_3D_HW2DTO3D_PARAMETERS)MApi_XC_Get_3D_HW2DTo3D_Parameters_U2,MApi_XC_Get_3D_HW2DTo3D_Parameters)
1734 URELATION(fpXC_Set_3D_Detect3DFormat_Parameters,(IOCTL_XC_SET_3D_DETECT3DFORMAT_PARAMETERS)MApi_XC_Set_3D_Detect3DFormat_Parameters_U2,MApi_XC_Set_3D_Detect3DFormat_Parameters)
1735 URELATION(fpXC_Get_3D_Detect3DFormat_Parameters,(IOCTL_XC_GET_3D_DETECT3DFORMAT_PARAMETERS)MApi_XC_Get_3D_Detect3DFormat_Parameters_U2,MApi_XC_Get_3D_Detect3DFormat_Parameters)
1736 URELATION(fpXC_Detect3DFormatByContent,(IOCTL_XC_DETECT3DFORMATBYCONTENT)MApi_XC_Detect3DFormatByContent_U2,MApi_XC_Detect3DFormatByContent)
1737 URELATION(fpXC_DetectNL,(IOCTL_XC_DETECTNL)MApi_XC_DetectNL_U2,MApi_XC_DetectNL)
1738 URELATION(fpXC_3D_PostPQSetting,(IOCTL_XC_3D_POSTPQSETTING)MApi_XC_3D_PostPQSetting_U2,MApi_XC_3D_PostPQSetting)
1739 URELATION(fpXC_Set_3D_FPInfo,(IOCTL_XC_SET_3D_FPINFO)MApi_XC_Set_3D_FPInfo_U2,MApi_XC_Set_3D_FPInfo)
1740 URELATION(fpXC_EnableAutoDetect3D,(IOCTL_XC_ENABLEAUTODETECT3D)MApi_XC_EnableAutoDetect3D_U2,MApi_XC_EnableAutoDetect3D)
1741 URELATION(fpXC_GetAutoDetect3DFlag,(IOCTL_XC_GETAUTODETECT3DFLAG)MApi_XC_GetAutoDetect3DFlag_U2,MApi_XC_GetAutoDetect3DFlag)
1742 URELATION(fpXC_Set_3D_SubWinClk,(IOCTL_XC_SET_3D_SUBWINCLK)MApi_XC_Set_3D_SubWinClk_U2,MApi_XC_Set_3D_SubWinClk)
1743 URELATION(fpXC_3D_Is_LR_Sbs2Line,(IOCTL_XC_3D_IS_LR_SBS2LINE)MApi_XC_3D_Is_LR_Sbs2Line_U2,MApi_XC_3D_Is_LR_Sbs2Line)
1744 URELATION(fpSC_3D_Is_Skip_Default_LR_Flag,(IOCTL_SC_3D_IS_SKIP_DEFAULT_LR_FLAG)MApi_SC_3D_Is_Skip_Default_LR_Flag_U2,MApi_SC_3D_Is_Skip_Default_LR_Flag)
1745 URELATION(fpXC_3D_Enable_Skip_Default_LR_Flag,(IOCTL_XC_3D_ENABLE_SKIP_DEFAULT_LR_FLAG)MApi_XC_3D_Enable_Skip_Default_LR_Flag_U2,MApi_XC_3D_Enable_Skip_Default_LR_Flag)
1746 URELATION(fpXC_Mux_Init,(IOCTL_XC_MUX_INIT)MApi_XC_Mux_Init_U2,MApi_XC_Mux_Init)
1747 URELATION(fpXC_Mux_SourceMonitor,(IOCTL_XC_MUX_SOURCEMONITOR)MApi_XC_Mux_SourceMonitor_U2,MApi_XC_Mux_SourceMonitor)
1748 URELATION(fpXC_Mux_CreatePath,(IOCTL_XC_MUX_CREATEPATH)MApi_XC_Mux_CreatePath_U2,MApi_XC_Mux_CreatePath)
1749 URELATION(fpXC_Mux_DeletePath,(IOCTL_XC_MUX_DELETEPATH)MApi_XC_Mux_DeletePath_U2,MApi_XC_Mux_DeletePath)
1750 URELATION(fpXC_Mux_EnablePath,(IOCTL_XC_MUX_ENABLEPATH)MApi_XC_Mux_EnablePath_U2,MApi_XC_Mux_EnablePath)
1751 URELATION(fpXC_Mux_TriggerPathSyncEvent,(IOCTL_XC_MUX_TRIGGERPATHSYNCEVENT)MApi_XC_Mux_TriggerPathSyncEvent_U2,MApi_XC_Mux_TriggerPathSyncEvent)
1752 URELATION(fpXC_Mux_TriggerDestOnOffEvent,(IOCTL_XC_MUX_TRIGGERDESTONOFFEVENT)MApi_XC_Mux_TriggerDestOnOffEvent_U2,MApi_XC_Mux_TriggerDestOnOffEvent)
1753 URELATION(fpXC_Mux_OnOffPeriodicHandler,(IOCTL_XC_MUX_ONOFFPERIODICHANDLER)MApi_XC_Mux_OnOffPeriodicHandler_U2,MApi_XC_Mux_OnOffPeriodicHandler)
1754 URELATION(fpXC_Mux_GetPathInfo,(IOCTL_XC_MUX_GETPATHINFO)MApi_XC_Mux_GetPathInfo_U2,MApi_XC_Mux_GetPathInfo)
1755 URELATION(fpXC_Mux_SetSupportMhlPathInfo,(IOCTL_XC_MUX_SETSUPPORTMHLPATHINFO)MApi_XC_Mux_SetSupportMhlPathInfo_U2,MApi_XC_Mux_SetSupportMhlPathInfo)
1756 URELATION(fpXC_Mux_SetMhlHotPlugInverseInfo,(IOCTL_XC_MUX_SETMHLHOTPLUGINVERSEINFO)MApi_XC_Mux_SetMhlHotPlugInverseInfo_U2,MApi_XC_Mux_SetMhlHotPlugInverseInfo)
1757 URELATION(fpXC_Mux_GetHDMIPort,(IOCTL_XC_MUX_GETHDMIPORT)MApi_XC_Mux_GetHDMIPort_U2,MApi_XC_Mux_GetHDMIPort)
1758 URELATION(fpXC_Mux_GetMappingTab,(IOCTL_XC_MUX_GETMAPPINGTAB)MApi_XC_Mux_GetPortMappingMatrix_U2,MApi_XC_Mux_GetPortMappingMatrix)
1759 URELATION(fpXC_MUX_MApinputSourceToVDYMuxPORT,(IOCTL_XC_MUX_MAPINPUTSOURCETOVDYMUXPORT)MApi_XC_MUX_MapInputSourceToVDYMuxPORT_U2,MApi_XC_MUX_MapInputSourceToVDYMuxPORT)
1760 URELATION(fpXC_Set_NR,(IOCTL_XC_SET_NR)MApi_XC_Set_NR_U2,MApi_XC_Set_NR)
1761 URELATION(fpXC_FilmMode_P,(IOCTL_XC_FILMMODE_P)MApi_XC_FilmMode_P_U2,MApi_XC_FilmMode_P)
1762 URELATION(fpXC_GetUCEnabled,(IOCTL_XC_GETUCENABLED)MApi_XC_GetUCEnabled_U2,MApi_XC_GetUCEnabled)
1763 URELATION(fpXC_GenSpecificTiming,(IOCTL_XC_GENSPECIFICTIMING)MApi_XC_GenSpecificTiming_U2,MApi_XC_GenSpecificTiming)
1764 URELATION(fpXC_GetDEBypassMode,(IOCTL_XC_GETDEBYPASSMODE)MApi_XC_GetDEBypassMode_U2,MApi_XC_GetDEBypassMode)
1765 URELATION(fpXC_GetDEWindow,(IOCTL_XC_GETDEWINDOW)MApi_XC_GetDEWindow_U2,MApi_XC_GetDEWindow)
1766 URELATION(fpXC_GetDEWidthHeightInDEByPassMode,(IOCTL_XC_GETDEWIDTHHEIGHTINDEBYPASSMODE)MApi_XC_GetDEWidthHeightInDEByPassMode_U2,MApi_XC_GetDEWidthHeightInDEByPassMode)
1767 URELATION(fpXC_GetCaptureWindow,(IOCTL_XC_GETCAPTUREWINDOW)MApi_XC_GetCaptureWindow_U2,MApi_XC_GetCaptureWindow)
1768 URELATION(fpXC_SetCaptureWindowVstart,(IOCTL_XC_SETCAPTUREWINDOWVSTART)MApi_XC_SetCaptureWindowVstart_U2,MApi_XC_SetCaptureWindowVstart)
1769 URELATION(fpXC_SetCaptureWindowHstart,(IOCTL_XC_SETCAPTUREWINDOWHSTART)MApi_XC_SetCaptureWindowHstart_U2,MApi_XC_SetCaptureWindowHstart)
1770 URELATION(fpXC_SetCaptureWindowVsize,(IOCTL_XC_SETCAPTUREWINDOWVSIZE)MApi_XC_SetCaptureWindowVsize_U2,MApi_XC_SetCaptureWindowVsize)
1771 URELATION(fpXC_SetCaptureWindowHsize,(IOCTL_XC_SETCAPTUREWINDOWHSIZE)MApi_XC_SetCaptureWindowHsize_U2,MApi_XC_SetCaptureWindowHsize)
1772 URELATION(fpXC_SoftwareReset,(IOCTL_XC_SOFTWARERESET)MApi_XC_SoftwareReset_U2,MApi_XC_SoftwareReset)
1773 URELATION(fpXC_CalculateHFreqx10,(IOCTL_XC_CALCULATEHFREQX10)MApi_XC_CalculateHFreqx10_U2,MApi_XC_CalculateHFreqx10)
1774 URELATION(fpXC_CalculateHFreqx1K,(IOCTL_XC_CALCULATEHFREQX1K)MApi_XC_CalculateHFreqx1K_U2,MApi_XC_CalculateHFreqx1K)
1775 URELATION(fpXC_CalculateVFreqx10,(IOCTL_XC_CALCULATEVFREQX10)MApi_XC_CalculateVFreqx10_U2,MApi_XC_CalculateVFreqx10)
1776 URELATION(fpXC_CalculateVFreqx1K,(IOCTL_XC_CALCULATEVFREQX1K)MApi_XC_CalculateVFreqx1K_U2,MApi_XC_CalculateVFreqx1K)
1777 URELATION(fpXC_GetAccurateVFreqx1K,(IOCTL_XC_GETACCURATEVFREQX1K)MApi_XC_GetAccurateVFreqx1K_U2,MApi_XC_GetAccurateVFreqx1K)
1778 URELATION(fpXC_InterruptAttach,(IOCTL_XC_INTERRUPTATTACH)MApi_XC_InterruptAttach_U2,MApi_XC_InterruptAttach)
1779 URELATION(fpXC_InterruptDeAttach,(IOCTL_XC_INTERRUPTDEATTACH)MApi_XC_InterruptDeAttach_U2,MApi_XC_InterruptDeAttach)
1780 URELATION(fpXC_DisableInputSource,(IOCTL_XC_DISABLEINPUTSOURCE)MApi_XC_DisableInputSource_U2,MApi_XC_DisableInputSource)
1781 URELATION(fpXC_IsInputSourceDisabled,(IOCTL_XC_ISINPUTSOURCEDISABLED)MApi_XC_IsInputSourceDisabled_U2,MApi_XC_IsInputSourceDisabled)
1782 URELATION(fpXC_ChangePanelType,(IOCTL_XC_CHANGEPANELTYPE)MApi_XC_ChangePanelType_U2,MApi_XC_ChangePanelType)
1783 URELATION(fpXC_GetCurrentReadBank,(IOCTL_XC_GETCURRENTREADBANK)MApi_XC_GetCurrentReadBank_U2,MApi_XC_GetCurrentReadBank)
1784 URELATION(fpXC_GetCurrentWriteBank,(IOCTL_XC_GETCURRENTWRITEBANK)MApi_XC_GetCurrentWriteBank_U2,MApi_XC_GetCurrentWriteBank)
1785 URELATION(fpXC_SetAutoPreScaling,(IOCTL_XC_SETAUTOPRESCALING)MApi_XC_SetAutoPreScaling_U2,MApi_XC_SetAutoPreScaling)
1786 URELATION(fpXC_GetVSyncWidth,(IOCTL_XC_GETVSYNCWIDTH)MApi_XC_GetVSyncWidth_U2,MApi_XC_GetVSyncWidth)
1787 URELATION(fpXC_set_GOP_Enable,(IOCTL_XC_SET_GOP_ENABLE)MApi_XC_set_GOP_Enable_U2,MApi_XC_set_GOP_Enable)
1788 URELATION(fpXC_ip_sel_for_gop,(IOCTL_XC_IP_SEL_FOR_GOP)MApi_XC_ip_sel_for_gop_U2,MApi_XC_ip_sel_for_gop)
1789 URELATION(fpXC_SetVOPNBL,(IOCTL_XC_SETVOPNBL)MApi_XC_SetVOPNBL_U2,MApi_XC_SetVOPNBL)
1790 URELATION(fpXC_GetDstInfo,(IOCTL_XC_GETDSTINFO)MApi_XC_GetDstInfo_U2,MApi_XC_GetDstInfo)
1791 URELATION(fpXC_Set_FD_Mask_ByWin,(IOCTL_XC_SET_FD_MASK_BYWIN)MApi_XC_Set_FD_Mask_ByWin_U2,MApi_XC_set_FD_Mask_byWin)
1792 URELATION(fpXC_Get_FD_Mask_ByWin,(IOCTL_XC_GET_FD_MASK_BYWIN)MApi_XC_Get_FD_Mask_ByWin_U2,MApi_XC_Get_FD_Mask_byWin)
1793 URELATION(fpXC_Get_FD_Mask_Status,(IOCTL_XC_GET_FD_MASK_STATUS)MApi_XC_Get_FD_Mask_Status_U2,MApi_XC_Get_FD_Mask_Status)
1794 URELATION(fpXC_SetIP1TestPattern,(IOCTL_XC_SETIP1TESTPATTERN)MApi_XC_SetIP1TestPattern_U2,MApi_XC_SetIP1TestPattern)
1795 URELATION(fpXC_InitIPForInternalTiming,(IOCTL_XC_INITIPFORINTERNALTIMING)MApi_XC_InitIPForInternalTiming_U2,MApi_XC_InitIPForInternalTiming)
1796 URELATION(fpXC_SetIPMux,(IOCTL_XC_SETIPMUX)MApi_XC_SetIPMux_U2,MApi_XC_SetIPMux)
1797 URELATION(fpXC_Is_H_Sync_Active,(IOCTL_XC_IS_H_SYNC_ACTIVE)MApi_XC_Is_H_Sync_Active_U2,MApi_XC_Is_H_Sync_Active)
1798 URELATION(fpXC_Is_V_Sync_Active,(IOCTL_XC_IS_V_SYNC_ACTIVE)MApi_XC_Is_V_Sync_Active_U2,MApi_XC_Is_V_Sync_Active)
1799 URELATION(fpXC_GetAutoPositionWindow,(IOCTL_XC_GETAUTOPOSITIONWINDOW)MApi_XC_GetAutoPositionWindow_U2,MApi_XC_GetAutoPositionWindow)
1800 URELATION(fpXC_SetFrameBufferAddress,(IOCTL_XC_SETFRAMEBUFFERADDRESS)MApi_XC_SetFrameBufferAddress_U2,MApi_XC_SetFrameBufferAddress)
1801 URELATION(fpXC_SetFRCMFrameBufferAddress,(IOCTL_XC_SETFRCMFRAMEBUFFERADDRESS)MApi_XC_SetFRCMFrameBufferAddress_U2,MApi_XC_SetFRCMFrameBufferAddress)
1802 URELATION(fpXC_IsFrameBufferEnoughForCusScaling,(IOCTL_XC_ISFRAMEBUFFERENOUGHFORCUSSCALING)MApi_XC_IsFrameBufferEnoughForCusScaling_U2,MApi_XC_IsFrameBufferEnoughForCusScaling)
1803 URELATION(fpXC_SetScalerMemoryRequest,(IOCTL_XC_SETSCALERMEMORYREQUEST)MApi_XC_SetScalerMemoryRequest_U2,MApi_XC_SetScalerMemoryRequest)
1804 URELATION(fpXC_Get_PixelData,(IOCTL_XC_GET_PIXELDATA)MApi_XC_Get_PixelData_U2,MApi_XC_Get_PixelData)
1805 URELATION(fpXC_GetAvailableSize,(IOCTL_XC_GETAVAILABLESIZE)MApi_XC_GetAvailableSize_U2,MApi_XC_GetAvailableSize)
1806 URELATION(fpXC_SetFrameColor,(IOCTL_XC_SETFRAMECOLOR)MApi_XC_SetFrameColor_U2,MApi_XC_SetFrameColor)
1807 URELATION(fpXC_SetDispWindowColor,(IOCTL_XC_SETDISPWINDOWCOLOR)MApi_XC_SetDispWindowColor_U2,MApi_XC_SetDispWindowColor)
1808 URELATION(fpXC_SupportSourceToVE,(IOCTL_XC_SUPPORTSOURCETOVE)MApi_XC_SupportSourceToVE_U2,MApi_XC_SupportSourceToVE)
1809 URELATION(fpXC_SetOutputCapture,(IOCTL_XC_SETOUTPUTCAPTURE)MApi_XC_SetOutputCapture_U2,MApi_XC_SetOutputCapture)
1810 URELATION(fpXC_SetGammaOnOff,(IOCTL_XC_SETGAMMAONOFF)MApi_XC_SetGammaOnOff_U2,MApi_XC_SetGammaOnOff)
1811 URELATION(fpXC_SetPreGammaGain,(IOCTL_XC_SETPREGAMMAGAIN)MApi_XC_SetPreGammaGain_U2,MApi_XC_SetPreGammaGain)
1812 URELATION(fpXC_SetPreGammaOffset,(IOCTL_XC_SETPREGAMMAOFFSET)MApi_XC_SetPreGammaOffset_U2,MApi_XC_SetPreGammaOffset)
1813 URELATION(fpXC_SetPanelTiming,(IOCTL_XC_SETPANELTIMING)MApi_XC_SetPanelTiming_U2,MApi_XC_SetPanelTiming)
1814 URELATION(fpXC_SetOutTimingMode,(IOCTL_XC_SETOUTTIMINGMODE)MApi_XC_SetOutTimingMode_U2,MApi_XC_SetOutTimingMode)
1815 URELATION(fpXC_SetFreeRunTiming,(IOCTL_XC_SETFREERUNTIMING)MApi_XC_SetFreeRunTiming_U2,MApi_XC_SetFreeRunTiming)
1816 URELATION(fpXC_Set_CustomerSyncInfo,(IOCTL_XC_SET_CUSTOMERSYNCINFO)MApi_XC_Set_CustomerSyncInfo_U2,MApi_XC_Set_CustomerSyncInfo)
1817 URELATION(fpXC_WaitFPLLDone,(IOCTL_XC_WAITFPLLDONE)MApi_XC_WaitFPLLDone_U2,MApi_XC_WaitFPLLDone)
1818 URELATION(fpXC_GetOutputVFreqX100,(IOCTL_XC_GETOUTPUTVFREQX100)MApi_XC_GetOutputVFreqX100_U2,MApi_XC_GetOutputVFreqX100)
1819 URELATION(fpXC_GetOP1OutputVFreqX100,(IOCTL_XC_GETOP1OUTPUTVFREQX100)MApi_XC_GetOP1OutputVFreqX100_U2,MApi_XC_GetOP1OutputVFreqX100)
1820 URELATION(fpXC_FrameLockCheck,(IOCTL_XC_FRAMELOCKCHECK)MApi_XC_FrameLockCheck_U2,MApi_XC_FrameLockCheck)
1821 URELATION(fpXC_CustomizeFRCTable,(IOCTL_XC_CUSTOMIZEFRCTABLE)MApi_XC_CustomizeFRCTable_U2,MApi_XC_CustomizeFRCTable)
1822 URELATION(fpXC_OutputFrameCtrl,(IOCTL_XC_OUTPUTFRAMECTRL)MApi_XC_OutputFrameCtrl_U2,MApi_XC_OutputFrameCtrl)
1823 URELATION(fpSC_Enable_FPLL_FSM,(IOCTL_SC_ENABLE_FPLL_FSM)MApi_SC_Enable_FPLL_FSM_U2,MApi_SC_Enable_FPLL_FSM)
1824 URELATION(fpSC_ForceFreerun,(IOCTL_SC_FORCEFREERUN)MApi_SC_ForceFreerun_U2,MApi_SC_ForceFreerun)
1825 URELATION(fpSC_IsForceFreerun,(IOCTL_SC_ISFORCEFREERUN)MApi_SC_IsForceFreerun_U2,MApi_SC_IsForceFreerun)
1826 URELATION(fpSC_SetFreerunVFreq,(IOCTL_SC_SETFREERUNVFREQ)MApi_SC_SetFreerunVFreq_U2,MApi_SC_SetFreerunVFreq)
1827 URELATION(fpXC_SetExPanelInfo,(IOCTL_XC_SETEXPANELINFO)MApi_XC_SetExPanelInfo_U2,MApi_XC_SetExPanelInfo)
1828 URELATION(fpXC_Enable_FPLL_Thresh_Mode,(IOCTL_XC_ENABLE_FPLL_THRESH_MODE)MApi_XC_Enable_FPLL_Thresh_Mode_U2,MApi_XC_Enable_FPLL_Thresh_Mode)
1829 URELATION(fpXC_Get_FPLL_Thresh_Mode,(IOCTL_XC_GET_FPLL_THRESH_MODE)MApi_XC_Get_FPLL_Thresh_Mode_U2,MApi_XC_Get_FPLL_Thresh_Mode)
1830 URELATION(fpXC_EnableIPAutoNoSignal,(IOCTL_XC_ENABLEIPAUTONOSIGNAL)MApi_XC_EnableIPAutoNoSignal_U2,MApi_XC_EnableIPAutoNoSignal)
1831 URELATION(fpXC_GetIPAutoNoSignal,(IOCTL_XC_GETIPAUTONOSIGNAL)MApi_XC_GetIPAutoNoSignal_U2,MApi_XC_GetIPAutoNoSignal)
1832 URELATION(fpXC_EnableIPAutoCoast,(IOCTL_XC_ENABLEIPAUTOCOAST)MApi_XC_EnableIPAutoCoast_U2,MApi_XC_EnableIPAutoCoast)
1833 URELATION(fpXC_EnableIPCoastDebounce,(IOCTL_XC_ENABLEIPCOASTDEBOUNCE)MApi_XC_EnableIPCoastDebounce_U2,MApi_XC_EnableIPCoastDebounce)
1834 URELATION(fpXC_ClearIPCoastStatus,(IOCTL_XC_CLEARIPCOASTSTATUS)MApi_XC_ClearIPCoastStatus_U2,MApi_XC_ClearIPCoastStatus)
1835 URELATION(fpXC_EnableFpllManualSetting,(IOCTL_XC_ENABLEFPLLMANUALSETTING)MApi_XC_EnableFpllManualSetting_U2,MApi_XC_EnableFpllManualSetting)
1836 URELATION(fpXC_FpllBoundaryTest,(IOCTL_XC_FPLLBOUNDARYTEST)MApi_XC_FpllBoundaryTest_U2,MApi_XC_FpllBoundaryTest)
1837 URELATION(fpXC_SetOffLineDetection,(IOCTL_XC_SETOFFLINEDETECTION)MApi_XC_SetOffLineDetection_U2,MApi_XC_SetOffLineDetection)
1838 URELATION(fpXC_GetOffLineDetection,(IOCTL_XC_GETOFFLINEDETECTION)MApi_XC_GetOffLineDetection_U2,MApi_XC_GetOffLineDetection)
1839 URELATION(fpXC_SetOffLineSogThreshold,(IOCTL_XC_SETOFFLINESOGTHRESHOLD)MApi_XC_SetOffLineSogThreshold_U2,MApi_XC_SetOffLineSogThreshold)
1840 URELATION(fpXC_SetOffLineSogBW,(IOCTL_XC_SETOFFLINESOGBW)MApi_XC_SetOffLineSogBW_U2,MApi_XC_SetOffLineSogBW)
1841 URELATION(fpXC_OffLineInit,(IOCTL_XC_OFFLINEINIT)MApi_XC_OffLineInit_U2,MApi_XC_OffLineInit)
1842 URELATION(fpXC_Set_Extra_fetch_adv_line,(IOCTL_XC_SET_EXTRA_FETCH_ADV_LINE)MApi_XC_Set_Extra_fetch_adv_line_U2,MApi_XC_Set_Extra_fetch_adv_line)
1843 URELATION(fpXC_SetVGASogEn,(IOCTL_XC_SETVGASOGEN)MApi_XC_SetVGASogEn_U2,MApi_XC_SetVGASogEn)
1844 URELATION(fpXC_EnableWindow,(IOCTL_XC_ENABLEWINDOW)MApi_XC_EnableWindow_U2,MApi_XC_EnableWindow)
1845 URELATION(fpXC_Is_SubWindowEanble,(IOCTL_XC_IS_SUBWINDOWEANBLE)MApi_XC_Is_SubWindowEanble_U2,MApi_XC_Is_SubWindowEanble)
1846 URELATION(fpXC_SetBorderFormat,(IOCTL_XC_SETBORDERFORMAT)MApi_XC_SetBorderFormat_U2,MApi_XC_SetBorderFormat)
1847 URELATION(fpXC_EnableBorder,(IOCTL_XC_ENABLEBORDER)MApi_XC_EnableBorder_U2,MApi_XC_EnableBorder)
1848 URELATION(fpXC_ZorderMainWindowFirst,(IOCTL_XC_ZORDERMAINWINDOWFIRST)MApi_XC_ZorderMainWindowFirst_U2,MApi_XC_ZorderMainWindowFirst)
1849 URELATION(fpXC_PQ_LoadFunction,(IOCTL_XC_PQ_LOADFUNCTION)MApi_XC_PQ_LoadFunction_U2,MApi_XC_PQ_LoadFunction)
1850 URELATION(fpXC_Check_HNonLinearScaling,(IOCTL_XC_CHECK_HNONLINEARSCALING)MApi_XC_Check_HNonLinearScaling_U2,MApi_XC_Check_HNonLinearScaling)
1851 URELATION(fpXC_EnableEuroHdtvSupport,(IOCTL_XC_ENABLEEUROHDTVSUPPORT)MApi_XC_EnableEuroHdtvSupport_U2,MApi_XC_EnableEuroHdtvSupport)
1852 URELATION(fpXC_EnableEuroHdtvDetection,(IOCTL_XC_ENABLEEUROHDTVDETECTION)MApi_XC_EnableEuroHdtvDetection_U2,MApi_XC_EnableEuroHdtvDetection)
1853 URELATION(fpXC_ReadByte,(IOCTL_XC_READBYTE)MApi_XC_ReadByte_U2,MApi_XC_ReadByte)
1854 URELATION(fpXC_WriteByte,(IOCTL_XC_WRITEBYTE)MApi_XC_WriteByte_U2,MApi_XC_WriteByte)
1855 URELATION(fpXC_WriteByteMask,(IOCTL_XC_WRITEBYTEMASK)MApi_XC_WriteByteMask_U2,MApi_XC_WriteByteMask)
1856 URELATION(fpXC_Write2ByteMask,(IOCTL_XC_WRITE2BYTEMASK)MApi_XC_Write2ByteMask_U2,MApi_XC_Write2ByteMask)
1857 URELATION(fpXC_W2BYTE,(IOCTL_XC_W2BYTE)MApi_XC_W2BYTE_U2,MApi_XC_W2BYTE)
1858 URELATION(fpXC_R2BYTE,(IOCTL_XC_R2BYTE)MApi_XC_R2BYTE_U2,MApi_XC_R2BYTE)
1859 URELATION(fpXC_W4BYTE,(IOCTL_XC_W4BYTE)MApi_XC_W4BYTE_U2,MApi_XC_W4BYTE)
1860 URELATION(fpXC_R4BYTE,(IOCTL_XC_R4BYTE)MApi_XC_R4BYTE_U2,MApi_XC_R4BYTE)
1861 URELATION(fpXC_R2BYTEMSK,(IOCTL_XC_R2BYTEMSK)MApi_XC_R2BYTEMSK_U2,MApi_XC_R2BYTEMSK)
1862 URELATION(fpXC_W2BYTEMSK,(IOCTL_XC_W2BYTEMSK)MApi_XC_W2BYTEMSK_U2,MApi_XC_W2BYTEMSK)
1863 URELATION(fpXC_MLoad_Init,(IOCTL_XC_MLOAD_INIT)MApi_XC_MLoad_Init_U2,MApi_XC_MLoad_Init)
1864 URELATION(fpXC_MLoad_Enable,(IOCTL_XC_MLOAD_ENABLE)MApi_XC_MLoad_Enable_U2,MApi_XC_MLoad_Enable)
1865 URELATION(fpXC_MLoad_Cus_Init,(IOCTL_XC_MLOAD_CUS_INIT)MApi_XC_MLoad_Cus_Init_U2,MApi_XC_MLoad_Cus_Init)
1866 URELATION(fpXC_MLoad_Cus_Enable,(IOCTL_XC_MLOAD_CUS_ENABLE)MApi_XC_MLoad_Cus_Enable_U2,MApi_XC_MLoad_Cus_Enable)
1867 URELATION(fpXC_MLoad_GetStatus,(IOCTL_XC_MLOAD_GETSTATUS)MApi_XC_MLoad_GetStatus_U2,MApi_XC_MLoad_GetStatus)
1868 URELATION(fpXC_MLoad_WriteCmd_And_Fire,(IOCTL_XC_MLOAD_WRITECMD_AND_FIRE)MApi_XC_MLoad_WriteCmd_And_Fire_U2,MApi_XC_MLoad_WriteCmd_And_Fire)
1869 URELATION(fpXC_MLoad_WriteCmds_And_Fire,(IOCTL_XC_MLOAD_WRITECMDS_AND_FIRE)MApi_XC_MLoad_WriteCmds_And_Fire_U2,MApi_XC_MLoad_WriteCmds_And_Fire)
1870 URELATION(fpXC_MLoad_Combine_Enable,(IOCTL_XC_MLOAD_COMBINE)MApi_XC_Combine_MLoadEn_U2,MApi_XC_Combine_MLoadEn)
1871 URELATION(fpXC_MLG_Init,(IOCTL_XC_MLG_INIT)MApi_XC_MLG_Init_U2,MApi_XC_MLG_Init)
1872 URELATION(fpXC_MLG_Enable,(IOCTL_XC_MLG_ENABLE)MApi_XC_MLG_Enable_U2,MApi_XC_MLG_Enable)
1873 URELATION(fpXC_MLG_GetCaps,(IOCTL_XC_MLG_GETCAPS)MApi_XC_MLG_GetCaps_U2,MApi_XC_MLG_GetCaps)
1874 URELATION(fpXC_MLG_GetStatus,(IOCTL_XC_MLG_GETSTATUS)MApi_XC_MLG_GetStatus_U2,MApi_XC_MLG_GetStatus)
1875 URELATION(fpXC_SetOSD2VEMode,(IOCTL_XC_SETOSD2VEMODE)MApi_XC_SetOSD2VEMode_U2,MApi_XC_SetOSD2VEMode)
1876 URELATION(fpXC_IP2_PreFilter_Enable,(IOCTL_XC_IP2_PREFILTER_ENABLE)MApi_XC_IP2_PreFilter_Enable_U2,MApi_XC_IP2_PreFilter_Enable)
1877 URELATION(fpXC_Get_Pixel_RGB,(IOCTL_XC_GET_PIXEL_RGB)MApi_XC_Get_Pixel_RGB_U2,MApi_XC_Get_Pixel_RGB)
1878 URELATION(fpXC_KeepPixelPointerAppear,(IOCTL_XC_KEEPPIXELPOINTERAPPEAR)MApi_XC_KeepPixelPointerAppear_U2,MApi_XC_KeepPixelPointerAppear)
1879 URELATION(fpXC_Set_MemFmtEx,(IOCTL_XC_SET_MEMFMTEX)MApi_XC_Set_MemFmtEx_U2,MApi_XC_Set_MemFmtEx)
1880 URELATION(fpXC_IsRequestFrameBufferLessMode,(IOCTL_XC_ISREQUESTFRAMEBUFFERLESSMODE)MApi_XC_IsRequestFrameBufferLessMode_U2,MApi_XC_IsRequestFrameBufferLessMode)
1881 URELATION(fpXC_SkipSWReset,(IOCTL_XC_SKIPSWRESET)MApi_XC_SkipSWReset_U2,MApi_XC_SkipSWReset)
1882 URELATION(fpXC_EnableRepWindowForFrameColor,(IOCTL_XC_ENABLEREPWINDOWFORFRAMECOLOR)MApi_XC_EnableRepWindowForFrameColor_U2,MApi_XC_EnableRepWindowForFrameColor)
1883 URELATION(fpXC_SetOSDLayer,(IOCTL_XC_SETOSDLAYER)MApi_XC_SetOSDLayer_U2,MApi_XC_SetOSDLayer)
1884 URELATION(fpXC_GetOSDLayer,(IOCTL_XC_GETOSDLAYER)MApi_XC_GetOSDLayer_U2,MApi_XC_GetOSDLayer)
1885 URELATION(fpXC_SetVideoAlpha,(IOCTL_XC_SETVIDEOALPHA)MApi_XC_SetVideoAlpha_U2,MApi_XC_SetVideoAlpha)
1886 URELATION(fpXC_GetVideoAlpha,(IOCTL_XC_GETVIDEOALPHA)MApi_XC_GetVideoAlpha_U2,MApi_XC_GetVideoAlpha)
1887 URELATION(fpXC_SkipWaitVsync,(IOCTL_XC_SKIPWAITVSYNC)MApi_XC_SkipWaitVsync_U2,MApi_XC_SkipWaitVsync)
1888 URELATION(fpXC_SetCMAHeapID,(IOCTL_XC_SETCMAHEAPID)MApi_XC_SetCMAHeapID_U2,MApi_XC_SetCMAHeapID)
1889 URELATION(fpXC_OP2VOPDESel,(IOCTL_XC_OP2VOPDESEL)MApi_XC_OP2VOPDESel_U2,MApi_XC_OP2VOPDESel)
1890 URELATION(fpXC_FRC_SetWindow,(IOCTL_XC_FRC_SETWINDOW)MApi_XC_FRC_SetWindow_U2,MApi_XC_FRC_SetWindow)
1891 URELATION(fpXC_Enable_TwoInitFactor,(IOCTL_XC_ENABLE_TWOINITFACTOR)MApi_XC_Enable_TwoInitFactor_U2,MApi_XC_Enable_TwoInitFactor)
1892 URELATION(fpXC_IsFieldPackingModeSupported,(IOCTL_XC_ISFIELDPACKINGMODESUPPORTED)MApi_XC_IsFieldPackingModeSupported_U2,MApi_XC_IsFieldPackingModeSupported)
1893 URELATION(fpXC_PreInit,(IOCTL_XC_PREINIT)MApi_XC_PreInit_U2,MApi_XC_PreInit)
1894 URELATION(fpXC_Get_BufferData,(IOCTL_XC_GET_BUFFERDATA)MApi_XC_Get_BufferData_U2,MApi_XC_Get_BufferData)
1895 URELATION(fpXC_Set_BufferData,(IOCTL_XC_SET_BUFFERDATA)MApi_XC_Set_BufferData_U2,MApi_XC_Set_BufferData)
1896 URELATION(fpXC_EnableMainWindow,(IOCTL_XC_ENABLEMAINWINDOW)MApi_XC_EnableMainWindow_U2,MApi_XC_EnableMainWindow)
1897 URELATION(fpXC_EnableSubWindow,(IOCTL_XC_ENABLESUBWINDOW)MApi_XC_EnableSubWindow_U2,MApi_XC_EnableSubWindow)
1898 URELATION(fpXC_DisableSubWindow,(IOCTL_XC_DISABLESUBWINDOW)MApi_XC_DisableSubWindow_U2,MApi_XC_DisableSubWindow)
1899 URELATION(fpXC_SetPixelShift,(IOCTL_XC_SETPIXELSHIFT)MApi_XC_SetPixelShift_U2,MApi_XC_SetPixelShift)
1900 URELATION(fpXC_SetVideoOnOSD,(IOCTL_XC_SETVIDEOONOSD)MApi_XC_SetVideoOnOSD_U2,MApi_XC_SetVideoOnOSD)
1901 URELATION(fpXC_SetOSDLayerBlending,(IOCTL_XC_SETOSDLAYERBLENDING)MApi_XC_SetOSDLayerBlending_U2,MApi_XC_SetOSDLayerBlending)
1902 URELATION(fpXC_SetOSDLayerAlpha,(IOCTL_XC_SETOSDLAYERALPHA)MApi_XC_SetOSDLayerAlpha_U2,MApi_XC_SetOSDLayerAlpha)
1903 URELATION(fpXC_SetOSDBlendingFormula,(IOCTL_XC_SETOSDBLENDINGFORMULA)MApi_XC_SetOSDBlendingFormula_U2,MApi_XC_SetOSDBlendingFormula)
1904 URELATION(fpXC_ReportPixelInfo,(IOCTL_XC_REPORTPIXELINFO)MApi_XC_ReportPixelInfo_U2,MApi_XC_ReportPixelInfo)
1905 URELATION(fpXC_SetScaling,(IOCTL_XC_SETSCALING)MApi_XC_SetScaling_U2,MApi_XC_SetScaling)
1906 URELATION(fpXC_SetMCDIBufferAddress,(IOCTL_XC_SETMCDIBUFFERADDRESS)MApi_XC_SetMCDIBufferAddress_U2,MApi_XC_SetMCDIBufferAddress)
1907 URELATION(fpXC_EnableMCDI,(IOCTL_XC_ENABLEMCDI)MApi_XC_EnableMCDI_U2,MApi_XC_EnableMCDI)
1908 URELATION(fpXC_SendCmdToFRC,(IOCTL_XC_SENDCMDTOFRC)MApi_XC_SendCmdToFRC_U2,MApi_XC_SendCmdToFRC)
1909 URELATION(fpXC_GetMsgFromFRC,(IOCTL_XC_GETMSGFROMFRC)MApi_XC_GetMsgFromFRC_U2,MApi_XC_GetMsgFromFRC)
1910 URELATION(fpXC_EnableRWBankAuto,(IOCTL_XC_ENABLERWBANKAUTO)MApi_XC_EnableRWBankAuto_U2,MApi_XC_EnableRWBankAuto)
1911 URELATION(fpXC_SetWRBankMappingNum,(IOCTL_XC_SETWRBANKMAPPINGNUM)MApi_XC_SetWRBankMappingNum_U2,MApi_XC_SetWRBankMappingNum)
1912 URELATION(fpXC_GetWRBankMappingNum,(IOCTL_XC_GETWRBANKMAPPINGNUM)MApi_XC_GetWRBankMappingNum_U2,MApi_XC_GetWRBankMappingNum)
1913 URELATION(fpXC_GetWRBankMappingNumForZap,(IOCTL_XC_GETWRBANKMAPPINGNUMFORZAP)MApi_XC_GetWRBankMappingNumForZap_U2,MApi_XC_GetWRBankMappingNumForZap)
1914 URELATION(fpXC_SetBOBMode,(IOCTL_XC_SET_BOBMODE)MApi_XC_SetBOBMode_U2,MApi_XC_SetBOBMode)
1915 URELATION(fpXC_SetForceReadBank,(IOCTL_XC_SET_FORCE_READBANK)MApi_XC_SetForceReadBank_U2,MApi_XC_SetForceReadBank)
1916 URELATION(fpXC_SetLockPoint,(IOCTL_XC_SET_LOCK_POINT)MApi_XC_SetLockPoint_U2,MApi_XC_SetLockPoint)
1917 URELATION(fpXC_LD_Init,(IOCTL_XC_LD_INIT)MApi_XC_LD_Init_U2,MApi_XC_LD_Init)
1918 URELATION(fpXC_LD_SetMemoryAddress,(IOCTL_XC_LD_SETMEMORYADDRESS)MApi_XC_LD_SetMemoryAddress_U2,MApi_XC_LD_SetMemoryAddress)
1919 URELATION(fpXC_LD_Get_Value,(IOCTL_XC_LD_GET_VALUE)MApi_XC_LD_Get_Value_U2,MApi_XC_LD_Get_Value)
1920 URELATION(fpXC_LD_SetLevel,(IOCTL_XC_LD_SETLEVEL)MApi_XC_LD_SetLevel_U2,MApi_XC_LD_SetLevel)
1921 URELATION(fpSet_TurnoffLDBL,(IOCTL_SET_TURNOFFLDBL)MApi_Set_TurnoffLDBL_U2,MApi_Set_TurnoffLDBL)
1922 URELATION(fpSet_notUpdateSPIDataFlags,(IOCTL_SET_NOTUPDATESPIDATAFLAGS)MApi_Set_notUpdateSPIDataFlags_U2,MApi_Set_notUpdateSPIDataFlags)
1923 URELATION(fpSet_UsermodeLDFlags,(IOCTL_SET_USERMODELDFLAGS)MApi_Set_UsermodeLDFlags_U2,MApi_Set_UsermodeLDFlags)
1924 URELATION(fpSet_BLLevel,(IOCTL_SET_BLLEVEL)MApi_Set_BLLevel_U2,MApi_Set_BLLevel)
1925 URELATION(fpXC_Set_BWS_Mode,(IOCTL_XC_SET_BWS_MODE)MApi_XC_Set_BWS_Mode_U2,MApi_XC_Set_BWS_Mode)
1926 URELATION(fpXC_FRC_ColorPathCtrl,(IOCTL_XC_FRC_COLORPATHCTRL)MApi_XC_FRC_ColorPathCtrl_U2,MApi_XC_FRC_ColorPathCtrl)
1927 URELATION(fpXC_FRC_OP2_SetRGBGain,(IOCTL_XC_FRC_OP2_SETRGBGAIN)MApi_XC_FRC_OP2_SetRGBGain_U2,MApi_XC_FRC_OP2_SetRGBGain)
1928 URELATION(fpXC_FRC_OP2_SetRGBOffset,(IOCTL_XC_FRC_OP2_SETRGBOFFSET)MApi_XC_FRC_OP2_SetRGBOffset_U2,MApi_XC_FRC_OP2_SetRGBOffset)
1929 URELATION(fpXC_FRC_OP2_SetDither,(IOCTL_XC_FRC_OP2_SETDITHER)MApi_XC_FRC_OP2_SetDither_U2,MApi_XC_FRC_OP2_SetDither)
1930 URELATION(fpXC_FRC_BypassMFC,(IOCTL_XC_FRC_BYPASSMFC)MApi_XC_FRC_BypassMFC_U2,MApi_XC_FRC_BypassMFC)
1931 URELATION(fpXC_FRC_Mute,(IOCTL_XC_FRC_MUTE)MApi_XC_FRC_Mute_U2,MApi_XC_FRC_Mute)
1932 URELATION(fpXC_ForceReadFrame,(IOCTL_XC_FORCEREADFRAME)MApi_XC_ForceReadFrame_U2,MApi_XC_ForceReadFrame)
1933 URELATION(fpXC_SetCsc,(IOCTL_XC_SETCSC)MApi_XC_SetCsc_U2,MApi_XC_SetCsc)
1934 URELATION(fpXC_RegisterPQSetFPLLThreshMode,(IOCTL_XC_REGISTERPQSETFPLLTHRESHMODE)MApi_XC_RegisterPQSetFPLLThreshMode_U2,MApi_XC_RegisterPQSetFPLLThreshMode)
1935 URELATION(fpXC_GetFreeRunStatus,(IOCTL_XC_GETFREERUNSTATUS)MApi_XC_GetFreeRunStatus_U2,MApi_XC_GetFreeRunStatus)
1936 URELATION(fpXC_BYPASS_SetCSC,(IOCTL_XC_SET_BYPASS_CSC)MApi_XC_BYPASS_SetCSC_U2,MApi_XC_BYPASS_SetCSC)
1937 URELATION(fpXC_Get_DSForceIndexSupported,(IOCTL_XC_GET_DSFORCEINDEXSUPPORTED)MApi_XC_Get_DSForceIndexSupported_U2,MApi_XC_Get_DSForceIndexSupported)
1938 URELATION(fpXC_Set_DSForceIndex,(IOCTL_XC_SET_DSFORCEINDEX)MApi_XC_Set_DSForceIndex_U2,MApi_XC_Set_DSForceIndex)
1939 URELATION(fpXC_Set_DSIndexSourceSelect,(IOCTL_XC_SET_DSINDEXSOURCESELECT)MApi_XC_Set_DSIndexSourceSelect_U2,MApi_XC_Set_DSIndexSourceSelect)
1940 URELATION(fpXC_GetDynamicScalingStatus,(IOCTL_XC_GET_DYNAMICSCALINGSTATUS)MApi_XC_GetDynamicScalingStatus_U2,MApi_XC_GetDynamicScalingStatus)
1941 URELATION(fpXC_OSDC_InitSetting,(IOCTL_XC_OSDC_INITSETTING)MApi_XC_OSDC_InitSetting_U2,MApi_XC_OSDC_InitSetting)
1942 URELATION(fpXC_OSDC_SetOutVfreqx10,(IOCTL_XC_OSDC_SET_OUTPUTVFREQX10)MApi_XC_OSDC_SetOutVfreqx10_U2,MApi_XC_OSDC_SetOutVfreqx10)
1943 URELATION(fpXC_OSDC_Control,(IOCTL_XC_OSDC_CONTROL)MApi_XC_OSDC_Control_U2,MApi_XC_OSDC_Control)
1944 URELATION(fpXC_OSDC_GetDstInfo,(IOCTL_XC_OSDC_GETDSTINFO)MApi_XC_OSDC_GetDstInfo_U2,MApi_XC_OSDC_GetDstInfo)
1945 URELATION(fpXC_Set_PowerState,(IOCTL_XC_SET_POWERSTATE)MApi_XC_SetPowerState_U2,MApi_XC_SetPowerState)
1946 URELATION(fpXC_BYPASS_SetOSDVsyncPos,(IOCTL_XC_SET_BYPASS_OSDVSYNC_POS)MApi_XC_BYPASS_SetOSDVsyncPos_U2,MApi_XC_BYPASS_SetOSDVsyncPos)
1947 URELATION(fpXC_BYPASS_SetInputSrc,(IOCTL_XC_SET_BYPASS_INPUTSRC)MApi_XC_BYPASS_SetInputSrc_U2,MApi_XC_BYPASS_SetInputSrc)
1948 URELATION(fpXC_SetSeamlessZapping,(IOCTL_XC_SET_SEAMELESS_ZAPPING)MApi_XC_SetSeamlessZapping_U2,MApi_XC_SetSeamlessZapping)
1949 URELATION(fpXC_GetSeamlessZappingStatus,(IOCTL_XC_GET_SEAMELESS_ZAPPING_STATUS)MApi_XC_GetSeamlessZappingStatus_U2,MApi_XC_GetSeamlessZappingStatus)
1950 URELATION(fpXC_Vtrack_SetPayloadData,(IOCTL_XC_SET_VTRACK_PAYLOADDATA)MApi_XC_Vtrack_SetPayloadData_U2,MApi_XC_Vtrack_SetPayloadData)
1951 URELATION(fpXC_Vtrack_SetUserDefindedSetting,(IOCTL_XC_SET_VTRACK_USERDEFINED_SETTING)MApi_XC_Vtrack_SetUserDefindedSetting_U2,MApi_XC_Vtrack_SetUserDefindedSetting)
1952 URELATION(fpXC_Vtrack_Enable,(IOCTL_XC_SET_VTRACK_ENABLE)MApi_XC_Vtrack_Enable_U2,MApi_XC_Vtrack_Enable)
1953 URELATION(fpXC_PreSetPQInfo,(IOCTL_XC_PRESET_PQINFO)MApi_XC_PreSetPQInfo_U2,MApi_XC_PreSetPQInfo)
1954 URELATION(fpXC_Is_OP1_TestPattern_Enabled,(IOCTL_XC_GET_OP1_TESTPATTERN_ENABLED)MApi_XC_Is_OP1_TestPattern_Enabled_U2,MApi_XC_Is_OP1_TestPattern_Enabled)
1955 URELATION(fpXC_Set_OP1_TestPattern,(IOCTL_XC_SET_OP1_TESTPATTERN)MApi_XC_Set_OP1_TestPattern_U2,MApi_XC_Set_OP1_TestPattern)
1956 URELATION(fpXC_Set_OP2_TestPattern,(IOCTL_XC_SET_OP2_TESTPATTERN)MApi_XC_Set_OP2_Pattern_U2,MApi_XC_Set_OP2_Pattern)
1957 URELATION(fpXC_Check_WhiteBalance_Pattern_Mode,(IOCTL_XC_CHECK_WHITEBALANCE_PATTERN_MODE)MApi_XC_CheckWhiteBalancePatternModeSupport_U2,MApi_XC_CheckWhiteBalancePatternModeSupport)
1958 URELATION(fpXC_Set_HLinearScaling,(IOCTL_XC_SET_HLINEARSCALING)MApi_XC_SetHLinearScaling_U2,MApi_XC_SetHLinearScaling)
1959 URELATION(fpXC_EnableT3D,(IOCTL_XC_ENABLE_T3D)MApi_XC_EnableT3D_U2,MApi_XC_EnableT3D)
1960 URELATION(fpXC_Set_FRC_InputTiming,(IOCTL_XC_SET_FRC_INPUTTIMING)MApi_XC_Set_FRC_InputTiming_U2,MApi_XC_Set_FRC_InputTiming)
1961 URELATION(fpXC_Get_FRC_InputTiming,(IOCTL_XC_GET_FRC_INPUTTIMING)MApi_XC_Get_FRC_InputTiming_U2,MApi_XC_Get_FRC_InputTiming)
1962 URELATION(fpXC_Get_VirtualBox_Info,(IOCTL_XC_GET_VBOX_INFO)MApi_XC_Get_VirtualBox_Info_U2,MApi_XC_Get_VirtualBox_Info)
1963 URELATION(fpXC_Set_OSD_DETECT,(IOCTL_XC_SET_OSD_DETECT)MApi_XC_Set_OSD_Detect_U2,MApi_XC_Set_OSD_Detect)
1964 URELATION(fpXC_Get_OSD_DETECT,(IOCTL_XC_GET_OSD_DETECT)MApi_XC_Get_OSD_Detect_U2,MApi_XC_Get_OSD_Detect)
1965 URELATION(fpXC_Enable_LockFreqOnly,(IOCTL_XC_ENABLE_LOCKFREQONLY)MApi_XC_Enable_LockFreqOnly_U2,MApi_XC_Enable_LockFreqOnly)
1966 URELATION(fpXC_Is2K2KToFrcMode,(IOCTL_XC_IS2K2KTOFRCMODE)MApi_XC_Is2K2KToFrcMode_U2,MApi_XC_Is2K2KToFrcMode)
1967 URELATION(fpXC_SetXCVOPdata,(IOCTL_XC_SET_XC_VOP_DATA)MApi_XC_Set_XC_VOP_U2,MApi_XC_Set_XC_VOP)
1968 URELATION(fpXC_GetSWDSIndex,(IOCTL_XC_GETSWDSINDEX)MApi_XC_GetSWDSIndex_U2,MApi_XC_GetSWDSIndex)
1969 URELATION(fpXC_Get_Is_SupportSWDS,(IOCTL_XC_GET_Is_SupportSWDS)MApi_XC_Is_SupportSWDS_U2,MApi_XC_Is_SupportSWDS)
1970 URELATION(fpXC_Get_FRCM_FrameNum,(IOCTL_XC_GET_FRCM_FRAMENUM)MApi_XC_Get_FRCM_FrameNum_U2,MApi_XC_Get_FRCMFrameNum)
1971 URELATION(fpXC_SetPixelShiftFeatures,(IOCTL_XC_SET_PIXELSHIFT_FEATURES)MApi_XC_SetPixelShiftFeatures_U2,MApi_XC_SetPixelShiftFeatures)
1972 URELATION(fpXC_SetForceWrite,(IOCTL_XC_SETFORCEWRITE)MApi_XC_SetForceWrite_U2,MApi_XC_SetForceWrite)
1973 URELATION(fpXC_GetForceWrite,(IOCTL_XC_GETFORCEWRITE)MApi_XC_GetForceWrite_U2,MApi_XC_GetForceWrite)
1974 #ifdef UFO_XC_PQ_PATH
1975 URELATION(fpXC_GetPQPathStatus,(IOCTL_XC_CMD_GET_PQ_PATH_STATUS)MApi_XC_GetPQPathStatus_U2,MApi_XC_GetPQPathStatus)
1976 #endif
1977 URELATION(fpXC_AutoDownloadConfig,(IOCTL_XC_AUTODOWNLOAD_CONFIG_CTRL)MApi_XC_AutoDownload_Config_U2,MApi_XC_AutoDownload_Config)
1978 URELATION(fpXC_AutoDownloadWrite,(IOCTL_XC_AUTODOWNLOAD_WRITE_CTRL)MApi_XC_AutoDownload_Write_U2,MApi_XC_AutoDownload_Write)
1979 URELATION(fpXC_AutoDownloadFire,(IOCTL_XC_AUTODOWNLOAD_FIRE_CTRL)MApi_XC_AutoDownload_Fire_U2,MApi_XC_AutoDownload_Fire)
1980 URELATION(fpXC_HDRControl,(IOCTL_XC_HDR_CTRL)MApi_XC_HDR_Control_U2,MApi_XC_HDR_Control)
1981 URELATION(fpXC_OPTEE_Ctrl,(IOCTL_XC_OPTEE_CTRL)MApi_XC_OPTEE_Control_U2,MApi_XC_OPTEE_Control)
1982 URELATION(fpXC_OPTEE_Mux,(IOCTL_XC_OPTEE_MUX)MApi_XC_OPTEE_Mux_U2,MApi_XC_OPTEE_Mux)
1983 URELATION(fpXC_GetResourceByPipeID,(IOCTL_XC_GET_RES_BY_PIPE)MApi_XC_GetResourceByPipeID_U2,MApi_XC_GetResourceByPipeID)
1984 URELATION(fpXC_ConfigPipe,(IOCTL_XC_CONFIG_PIPE)MApi_XC_ConfigPipe_U2,MApi_XC_ConfigPipe)
1985 URELATION(fpXC_CheckPipe,(IOCTL_XC_CHECK_PIPE)MApi_XC_CheckPipe_U2,MApi_XC_CheckPipe)
1986 URELATION(fpXC_SetDSInfo,(IOCTL_XC_SETDSINFO)MApi_XC_SetDSInfo_U2,MApi_XC_SetDSInfo)
1987 URELATION(fpsc_get_output_vfreq,(IOCTL_SC_GET_OUTPUT_VFREQ)mvideo_sc_get_output_vfreq_U2,mvideo_sc_get_output_vfreq)
1988 URELATION(fpXC_Get_Current_OutputVFreqX100,(IOCTL_XC_GET_CURRENT_OUTPUTVFREQX100)MApi_XC_Get_Current_OutputVFreqX100_U2,MApi_XC_Get_Current_OutputVFreqX100)
1989 URELATION(fpXC_SetMemoryWriteRequest,(IOCTL_XC_SETMEMORYWRITEREQUEST)MApi_XC_SetMemoryWriteRequest_U2,MApi_XC_SetMemoryWriteRequest)
1990 URELATION(fpXC_Set_MemFmt,(IOCTL_XC_SET_MEMFMT)MApi_XC_Set_MemFmt_U2,MApi_XC_Set_MemFmt)
1991 URELATION(fpXC_SetOutputAdjustSetting,(IOCTL_XC_SETOUTPUTADJUSTSETTING)MApi_XC_SetOutputAdjustSetting_U2,MApi_XC_SetOutputAdjustSetting)
1992 URELATION(fsScaler_FPLL_FSM,(IOCTL_SCALER_FPLL_FSM)msAPI_Scaler_FPLL_FSM_U2,msAPI_Scaler_FPLL_FSM)
1993 URELATION(fpXC_EnableMirrorMode,(IOCTL_XC_ENABLEMIRRORMODE)MApi_XC_EnableMirrorMode_U2,MApi_XC_EnableMirrorMode)
1994 URELATION(fpXC_EnableMirrorMode2,(IOCTL_XC_ENABLEMIRRORMODE2)MApi_XC_EnableMirrorMode2_U2,MApi_XC_EnableMirrorMode2)
1995 #ifdef SUPPORT_BWD
1996 URELATION(fpXC_SetBwdConfig,(IOCTL_XC_SET_BWD_CONFIG)MApi_XC_SetBwdConfig_U2,MApi_XC_SetBwdConfig)
1997 #endif
1998 URELATION(fpXC_dump_shm,(IOCTL_DUMP_SHM)MApi_XC_Dump_SHM_U2,MApi_XC_Dump_SHM)
1999 URELATION(fpXC_IsSupport2StepScaling,(IOCTL_XC_CMD_IS_SUPPORT_2_STEP_SCALING)MApi_XC_IsSupport2StepScaling_U2,MApi_XC_IsSupport2StepScaling)
2000 URELATION(fpXC_VideoPlaybackCtrl,(IOCTL_XC_VIDEO_PLAYBACK_CTRL)MApi_XC_VideoPlaybackCtrl_U2,MApi_XC_VideoPlaybackCtrl)
2001 #ifdef UFO_XC_SETBLACKVIDEOBYMODE
2002 URELATION(fpXC_GenerateBlackVideoByMode,(IOCTL_XC_GENERATEBLACKVIDEOBYMODE)MApi_XC_GenerateBlackVideoByMode_U2,MApi_XC_GenerateBlackVideoByMode)
2003 #endif
2004 URELATION(fpXC_swds_fire,(IOCTL_SWDS_Fire)MApi_SWDS_Fire_U2,MApi_SWDS_Fire)
2005 URELATION(fpXC_ADC_SetCVBSOut,(IOCTL_XC_ADC_SETCVBSOUT)MApi_XC_ADC_SetCVBSOut_U2,MApi_XC_ADC_SetCVBSOut)
2006 URELATION(fpXC_ADC_IsCVBSOutEnabled,(IOCTL_XC_ADC_ISCVBSOUTENABLED)MApi_XC_ADC_IsCVBSOutEnabled_U2,MApi_XC_ADC_IsCVBSOutEnabled)
2007 URELATION(fpXC_ADC_SetPcClock,(IOCTL_XC_ADC_SETPCCLOCK)MApi_XC_ADC_SetPcClock_U2,MApi_XC_ADC_SetPcClock)
2008 URELATION(fpXC_ADC_SetPhase,(IOCTL_XC_ADC_SETPHASE)MApi_XC_ADC_SetPhase_U2,MApi_XC_ADC_SetPhase)
2009 URELATION(fpXC_ADC_SetPhaseEx,(IOCTL_XC_ADC_SETPHASEEX)MApi_XC_ADC_SetPhaseEx_U2,MApi_XC_ADC_SetPhaseEx)
2010 URELATION(fpXC_ADC_GetPhaseRange,(IOCTL_XC_ADC_GETPHASERANGE)MApi_XC_ADC_GetPhaseRange_U2,MApi_XC_ADC_GetPhaseRange)
2011 URELATION(fpXC_ADC_GetPhase,(IOCTL_XC_ADC_GETPHASE)MApi_XC_ADC_GetPhase_U2,MApi_XC_ADC_GetPhase)
2012 URELATION(fpXC_ADC_GetPhaseEx,(IOCTL_XC_ADC_GETPHASEEX)MApi_XC_ADC_GetPhaseEx_U2,MApi_XC_ADC_GetPhaseEx)
2013 URELATION(fpXC_ADC_IsScartRGB,(IOCTL_XC_ADC_ISSCARTRGB)MApi_XC_ADC_IsScartRGB_U2,MApi_XC_ADC_IsScartRGB)
2014 URELATION(fpXC_ADC_GetPcClock,(IOCTL_XC_ADC_GETPCCLOCK)MApi_XC_ADC_GetPcClock_U2,MApi_XC_ADC_GetPcClock)
2015 URELATION(fpXC_ADC_GetSoGLevelRange,(IOCTL_XC_ADC_GETSOGLEVELRANGE)MApi_XC_ADC_GetSoGLevelRange_U2,MApi_XC_ADC_GetSoGLevelRange)
2016 URELATION(fpXC_ADC_SetSoGLevel,(IOCTL_XC_ADC_SETSOGLEVEL)MApi_XC_ADC_SetSoGLevel_U2,MApi_XC_ADC_SetSoGLevel)
2017 URELATION(fpXC_ADC_PowerOff,(IOCTL_XC_ADC_POWEROFF)MApi_XC_ADC_PowerOff_U2,MApi_XC_ADC_PowerOff)
2018 URELATION(fpXC_ADC_GetDefaultGainOffset,(IOCTL_XC_ADC_GETDEFAULTGAINOFFSET)MApi_XC_ADC_GetDefaultGainOffset_U2,MApi_XC_ADC_GetDefaultGainOffset)
2019 URELATION(fpXC_ADC_GetMaximalOffsetValue,(IOCTL_XC_ADC_GETMAXIMALOFFSETVALUE)MApi_XC_ADC_GetMaximalOffsetValue_U2,MApi_XC_ADC_GetMaximalOffsetValue)
2020 URELATION(fpXC_ADC_GetMaximalGainValue,(IOCTL_XC_ADC_GETMAXIMALGAINVALUE)MApi_XC_ADC_GetMaximalGainValue_U2,MApi_XC_ADC_GetMaximalGainValue)
2021 URELATION(fpXC_ADC_GetCenterGain,(IOCTL_XC_ADC_GETCENTERGAIN)MApi_XC_ADC_GetCenterGain_U2,MApi_XC_ADC_GetCenterGain)
2022 URELATION(fpXC_ADC_GetCenterOffset,(IOCTL_XC_ADC_GETCENTEROFFSET)MApi_XC_ADC_GetCenterOffset_U2,MApi_XC_ADC_GetCenterOffset)
2023 URELATION(fpXC_ADC_SetGain,(IOCTL_XC_ADC_SETGAIN)MApi_XC_ADC_SetGain_U2,MApi_XC_ADC_SetGain)
2024 URELATION(fpXC_ADC_SetOffset,(IOCTL_XC_ADC_SETOFFSET)MApi_XC_ADC_SetOffset_U2,MApi_XC_ADC_SetOffset)
2025 URELATION(fpXC_ADC_AdjustGainOffset,(IOCTL_XC_ADC_ADJUSTGAINOFFSET)MApi_XC_ADC_AdjustGainOffset_U2,MApi_XC_ADC_AdjustGainOffset)
2026 URELATION(fpXC_ADC_Source_Calibrate,(IOCTL_XC_ADC_SOURCE_CALIBRATE)MApi_XC_ADC_Source_Calibrate_U2,MApi_XC_ADC_Source_Calibrate)
2027 URELATION(fpXC_ADC_SetSoGCal,(IOCTL_XC_ADC_SETSOGCAL)MApi_XC_ADC_SetSoGCal_U2,MApi_XC_ADC_SetSoGCal)
2028 URELATION(fpXC_ADC_SetRGB_PIPE_Delay,(IOCTL_XC_ADC_SETRGB_PIPE_DELAY)MApi_XC_ADC_SetRGB_PIPE_Delay_U2,MApi_XC_ADC_SetRGB_PIPE_Delay)
2029 URELATION(fpXC_ADC_ScartRGB_SOG_ClampDelay,(IOCTL_XC_ADC_SCARTRGB_SOG_CLAMPDELAY)MApi_XC_ADC_ScartRGB_SOG_ClampDelay_U2,MApi_XC_ADC_ScartRGB_SOG_ClampDelay)
2030 URELATION(fpXC_ADC_Set_YPbPrLooseLPF,(IOCTL_XC_ADC_SET_YPBPRLOOSELPF)MApi_XC_ADC_Set_YPbPrLooseLPF_U2,MApi_XC_ADC_Set_YPbPrLooseLPF)
2031 URELATION(fpXC_ADC_Set_SOGBW,(IOCTL_XC_ADC_SET_SOGBW)MApi_XC_ADC_Set_SOGBW_U2,MApi_XC_ADC_Set_SOGBW)
2032 URELATION(fpXC_ADC_SetClampDuration,(IOCTL_XC_ADC_SETCLAMPDURATION)MApi_XC_ADC_SetClampDuration_U2,MApi_XC_ADC_SetClampDuration)
2033 URELATION(fpXC_ADC_EnableHWCalibration,(IOCTL_XC_ADC_ENABLEHWCALIBRATION)MApi_XC_ADC_EnableHWCalibration_U2,MApi_XC_ADC_EnableHWCalibration)
2034 URELATION(fpXC_ADC_SetIdacCurrentMode,(IOCTL_XC_ADC_SETIDACCURRENTMODE)MApi_XC_ADC_SetIdacCurrentMode_U2,MApi_XC_ADC_SetIdacCurrentMode)
2035 URELATION(fpXC_ADC_GetIdacCurrentMode,(IOCTL_XC_ADC_GETIDACCURRENTMODE)MApi_XC_ADC_GetIdacCurrentMode_U2,MApi_XC_ADC_GetIdacCurrentMode)
2036 URELATION(fpXC_Auto_Geometry,(IOCTL_XC_AUTO_GEOMETRY) MApi_XC_Auto_Geometry_U2, MApi_XC_Auto_Geometry)
2037 URELATION(fpXC_Auto_Geometry_Ex,(IOCTL_XC_AUTO_GEOMETRY_EX) MApi_XC_Auto_Geometry_Ex_U2, MApi_XC_Auto_Geometry_Ex)
2038 URELATION(fpXC_Auto_StopAutoGeometry,(IOCTL_XC_AUTO_STOPAUTOGEOMETRY) MApi_XC_Auto_StopAutoGeometry_U2, MApi_XC_Auto_StopAutoGeometry)
2039 URELATION(fpXC_Auto_GainOffset,(IOCTL_XC_AUTO_GAINOFFSET) MApi_XC_Auto_GainOffset_U2, MApi_XC_Auto_GainOffset)
2040 URELATION(fpXC_Auto_GetHWFixedGainOffset,(IOCTL_XC_AUTO_GETHWFIXEDGAINOFFSET) MApi_XC_Auto_GetHWFixedGainOffset_U2, MApi_XC_Auto_GetHWFixedGainOffset)
2041 URELATION(fpXC_Auto_SetValidData,(IOCTL_XC_AUTO_SETVALIDDATA) MApi_XC_Auto_SetValidData_U2, MApi_XC_Auto_SetValidData)
2042 URELATION(fpXC_Auto_AutoOffset,(IOCTL_XC_AUTO_AUTOOFFSET) MApi_XC_Auto_AutoOffset_U2, MApi_XC_Auto_AutoOffset)
2043 URELATION(fpXC_Auto_DetectWidth,(IOCTL_XC_AUTO_DETECTWIDTH) MApi_XC_Auto_DetectWidth_U2, MApi_XC_Auto_DetectWidth)
2044 URELATION(fpXC_Auto_SetCalibrationMode,(IOCTL_XC_AUTO_SETCALIBRATIONMODE) MApi_XC_Auto_SetCalibrationMode_U2, MApi_XC_Auto_SetCalibrationMode)
2045 URELATION(fpXC_Auto_GetCalibrationMode,(IOCTL_XC_AUTO_GETCALIBRATIONMODE) MApi_XC_Auto_GetCalibrationMode_U2, MApi_XC_Auto_GetCalibrationMode)
2046 URELATION(fpXC_Auto_GetSyncInfo,(IOCTL_XC_AUTO_GETSYNCINFO) MApi_XC_AUTO_GetSyncInfo_U2, MApi_XC_AUTO_GetSyncInfo)
2047 URELATION(fpXC_ModeParse_Init,(IOCTL_XC_MODEPARSE_INIT)MApi_XC_ModeParse_Init_U2,MApi_XC_ModeParse_Init)
2048 URELATION(fpXC_ModeParse_MatchMode,(IOCTL_XC_MODEPARSE_MATCHMODE)MApi_XC_ModeParse_MatchMode_U2,MApi_XC_ModeParse_MatchMode)
2049 URELATION(fpXC_ModeParse_MatchModeEx,(IOCTL_XC_MODEPARSE_MATCHMODEEX)MApi_XC_ModeParse_MatchModeEx_U2,MApi_XC_ModeParse_MatchModeEx)
2050 URELATION(fpXC_PCMonitor_Init,(IOCTL_XC_PCMONITOR_INIT) MApi_XC_PCMonitor_Init_U2, MApi_XC_PCMonitor_Init)
2051 URELATION(fpXC_PCMonitor_Restart,(IOCTL_XC_PCMONITOR_RESTART) MApi_XC_PCMonitor_Restart_U2, MApi_XC_PCMonitor_Restart)
2052 URELATION(fpXC_PCMonitor_SetTimingCount,(IOCTL_XC_PCMONITOR_SETTIMINGCOUNT) MApi_XC_PCMonitor_SetTimingCount_U2, MApi_XC_PCMonitor_SetTimingCount)
2053 URELATION(fpXC_PCMonitor,(IOCTL_XC_PCMONITOR) MApi_XC_PCMonitor_U2, MApi_XC_PCMonitor)
2054 URELATION(fpXC_PCMonitor_GetCurrentState,(IOCTL_XC_PCMONITOR_GETCURRENTSTATE) MApi_XC_PCMonitor_GetCurrentState_U2, MApi_XC_PCMonitor_GetCurrentState)
2055 URELATION(fpXC_PCMonitor_GetSyncStatus,(IOCTL_XC_PCMONITOR_GETSYNCSTATUS) MApi_XC_PCMonitor_GetSyncStatus_U2, MApi_XC_PCMonitor_GetSyncStatus)
2056 URELATION(fpXC_PCMonitor_Get_HFreqx10,(IOCTL_XC_PCMONITOR_GET_HFREQX10) MApi_XC_PCMonitor_Get_HFreqx10_U2, MApi_XC_PCMonitor_Get_HFreqx10)
2057 URELATION(fpXC_PCMonitor_Get_HFreqx1K,(IOCTL_XC_PCMONITOR_GET_HFREQX1K) MApi_XC_PCMonitor_Get_HFreqx1K_U2, MApi_XC_PCMonitor_Get_HFreqx1K)
2058 URELATION(fpXC_PCMonitor_Get_VFreqx10,(IOCTL_XC_PCMONITOR_GET_VFREQX10) MApi_XC_PCMonitor_Get_VFreqx10_U2, MApi_XC_PCMonitor_Get_VFreqx10)
2059 URELATION(fpXC_PCMonitor_Get_VFreqx1K,(IOCTL_XC_PCMONITOR_GET_VFREQX1K) MApi_XC_PCMonitor_Get_VFreqx1K_U2, MApi_XC_PCMonitor_Get_VFreqx1K)
2060 URELATION(fpXC_PCMonitor_Get_Vtotal,(IOCTL_XC_PCMONITOR_GET_VTOTAL) MApi_XC_PCMonitor_Get_Vtotal_U2, MApi_XC_PCMonitor_Get_Vtotal)
2061 URELATION(fpXC_PCMonitor_Get_Dvi_Hdmi_De_Info,(IOCTL_XC_PCMONITOR_GET_DVI_HDMI_DE_INFO) MApi_XC_PCMonitor_Get_Dvi_Hdmi_De_Info_U2, MApi_XC_PCMonitor_Get_Dvi_Hdmi_De_Info)
2062 URELATION(fpXC_PCMonitor_SyncLoss,(IOCTL_XC_PCMONITOR_SYNCLOSS) MApi_XC_PCMonitor_SyncLoss_U2, MApi_XC_PCMonitor_SyncLoss)
2063 URELATION(fpXC_PCMonitor_InvalidTimingDetect,(IOCTL_XC_PCMONITOR_INVALIDTIMINGDETECT) MApi_XC_PCMonitor_InvalidTimingDetect_U2, MApi_XC_PCMonitor_InvalidTimingDetect)
2064 URELATION(fpXC_PCMonitor_SetTimingCountEx,(IOCTL_XC_PCMONITOR_SETTIMINGCOUNTEX) MApi_XC_PCMonitor_SetTimingCountEx_U2, MApi_XC_PCMonitor_SetTimingCountEx)
2065 URELATION(fpHDMI_Func_Caps,(IOCTL_HDMI_FUNC_CAPS)MDrv_HDMI_Func_Caps_U2,MDrv_HDMI_Func_Caps)
2066 URELATION(fpHDMI_init,(IOCTL_HDMI_INIT)MDrv_HDMI_init_U2,MDrv_HDMI_init)
2067 URELATION(fpHDMI_Exit,(IOCTL_HDMI_EXIT)MDrv_HDMI_Exit_U2,MDrv_HDMI_Exit)
2068 URELATION(fpHDMI_pkt_reset,(IOCTL_HDMI_PKT_RESET)MDrv_HDMI_pkt_reset_U2,MDrv_HDMI_pkt_reset)
2069 URELATION(fpHDMI_pullhpd,(IOCTL_HDMI_PULLHPD)MDrv_HDMI_pullhpd_U2,MDrv_HDMI_pullhpd)
2070 URELATION(fpHDMI_GC_Info,(IOCTL_HDMI_GC_INFO)MDrv_HDMI_GC_Info_U2,MDrv_HDMI_GC_Info)
2071 URELATION(fpHDMI_Packet_Received,(IOCTL_HDMI_PACKET_RECEIVED)MDrv_HDMI_Packet_Received_U2,MDrv_HDMI_Packet_Received)
2072 URELATION(fpHDMI_Get_ColorFormat,(IOCTL_HDMI_GET_COLORFORMAT)MDrv_HDMI_Get_ColorFormat_U2,MDrv_HDMI_Get_ColorFormat)
2073 URELATION(fpHDMI_Get_ColorRange,(IOCTL_HDMI_GET_COLORRANGE)MDrv_HDMI_Get_ColorRange_U2,MDrv_HDMI_Get_ColorRange)
2074 URELATION(fpHDMI_Set_EQ,(IOCTL_HDMI_SET_EQ)MDrv_HDMI_Set_EQ_U2,MDrv_HDMI_Set_EQ)
2075 URELATION(fpHDMI_Set_EQ_To_Port,(IOCTL_HDMI_SET_EQ_TO_PORT)MDrv_HDMI_Set_EQ_To_Port_U2,MDrv_HDMI_Set_EQ_To_Port)
2076 URELATION(fpHDMI_Audio_MUTE_Enable,(IOCTL_HDMI_AUDIO_MUTE_ENABLE)MDrv_HDMI_Audio_MUTE_Enable_U2,MDrv_HDMI_Audio_MUTE_Enable)
2077 URELATION(fpHDMI_Audio_Status_Clear,(IOCTL_HDMI_AUDIO_STATUS_CLEAR)MDrv_HDMI_Audio_Status_Clear_U2,MDrv_HDMI_Audio_Status_Clear)
2078 URELATION(fpHDMI_Get_AspectRatio,(IOCTL_HDMI_GET_ASPECTRATIO)MDrv_HDMI_Get_AspectRatio_U2,MDrv_HDMI_Get_AspectRatio)
2079 URELATION(fpHDMI_Get_ActiveFormat_AspectRatio,(IOCTL_HDMI_GET_ACTIVEFORMAT_ASPECTRATIO)MDrv_HDMI_Get_ActiveFormat_AspectRatio_U2,MDrv_HDMI_Get_ActiveFormat_AspectRatio)
2080 URELATION(fpHDMI_Get_AVIInfoFrameVer,(IOCTL_HDMI_GET_AVIINFOFRAMEVER)MDrv_HDMI_Get_AVIInfoFrameVer_U2,MDrv_HDMI_Get_AVIInfoFrameVer)
2081 URELATION(fpHDMI_err_status_update,(IOCTL_HDMI_ERR_STATUS_UPDATE)MDrv_HDMI_err_status_update_U2,MDrv_HDMI_err_status_update)
2082 URELATION(fpHDMI_Get_TMDS_freq,(IOCTL_HDMI_GET_TMDS_FREQ)MDrv_HDMI_GetTMDSFreq_U2,MDrv_HDMI_GetTMDSFreq)
2083 URELATION(fpHDMI_Get_PollingStatus,(IOCTL_HDMI_GET_POLLINGSTATUS)MDrv_HDMI_Get_PollingStatus_U2,MDrv_HDMI_Get_PollingStatus)
2084 URELATION(fpHDMI_IsHDMI_Mode,(IOCTL_HDMI_ISHDMI_MODE)MDrv_HDMI_IsHDMI_Mode_U2,MDrv_HDMI_IsHDMI_Mode)
2085 URELATION(fpHDMI_Get_MID_info,(IOCTL_HDMI_GET_MID_INFO)MDrv_HDMI_Get_MID_info_U2,MDrv_HDMI_Get_MID_info)
2086 URELATION(fpHDMI_get_packet_value,(IOCTL_HDMI_GET_PACKET_VALUE)MDrv_HDMI_get_packet_value_U2,MDrv_HDMI_get_packet_value)
2087 URELATION(fpDVI_ChannelPhaseStatus,(IOCTL_DVI_CHANNELPHASESTATUS)MDrv_DVI_ChannelPhaseStatus_U2,MDrv_DVI_ChannelPhaseStatus)
2088 URELATION(fpDVI_SoftwareReset,(IOCTL_DVI_SOFTWARERESET)MDrv_DVI_SoftwareReset_U2,MDrv_DVI_SoftwareReset)
2089 URELATION(fpdvi_reset,(IOCTL_DVI_RESET)mdrv_dvi_reset_U2,mdrv_dvi_reset)
2090 URELATION(fpHDMI_Get_AVIInfoActiveInfoPresent,(IOCTL_HDMI_AVIINFO_ACTIVEINFOPRESENT)MDrv_HDMI_Get_AVIInfoActiveInfoPresent_U2,MDrv_HDMI_Get_AVIInfoActiveInfoPresent)
2091 URELATION(fpDVI_ClkPullLow,(IOCTL_DVI_CLKPULLLOW)MDrv_DVI_ClkPullLow_U2,MDrv_DVI_ClkPullLow)
2092 URELATION(fpDVI_SwitchSrc,(IOCTL_DVI_SWITCHSRC)MDrv_DVI_SwitchSrc_U2,MDrv_DVI_SwitchSrc)
2093 URELATION(fpHDMI_SetForClockLessThan70Mhz,(IOCTL_HDMI_SETFORCLOCKLESSTHAN70MHZ)MDrv_HDMI_SetForClockLessThan70Mhz_U2,MDrv_HDMI_SetForClockLessThan70Mhz)
2094 URELATION(fpHDMI_dvi_adjust,(IOCTL_HDMI_DVI_ADJUST)MDrv_HDMI_dvi_adjust_U2,MDrv_HDMI_dvi_adjust)
2095 URELATION(fpHDMI_SetUpdatePhaseLineCount,(IOCTL_HDMI_SETUPDATEPHASELINECOUNT)MDrv_HDMI_SetUpdatePhaseLineCount_U2,MDrv_HDMI_SetUpdatePhaseLineCount)
2096 URELATION(fpHDCP_Enable,(IOCTL_HDCP_ENABLE)MDrv_HDCP_Enable_U2,MDrv_HDCP_Enable)
2097 URELATION(fpHDMI_SetHdcpEnable,(IOCTL_HDMI_SETHDCPENABLE)MDrv_HDMI_SetHdcpEnable_U2,MDrv_HDMI_SetHdcpEnable)
2098 URELATION(fpHDCP_ClearStatus,(IOCTL_HDCP_CLEARSTATUS)MDrv_HDCP_ClearStatus_U2,MDrv_HDCP_ClearStatus)
2099 URELATION(fpHDCP_initproductionkey,(IOCTL_HDCP_INITPRODUCTIONKEY)MDrv_HDCP_initproductionkey_U2,MDrv_HDCP_initproductionkey)
2100 URELATION(fpHDCP_GetStatus,(IOCTL_HDCP_GETSTATUS)MDrv_HDCP_GetStatus_U2,MDrv_HDCP_GetStatus)
2101 URELATION(fpHDCP_Vsync_end_en,(IOCTL_HDCP_VSYNC_END_EN)MDrv_HDCP_Vsync_end_en_U2,MDrv_HDCP_Vsync_end_en)
2102 URELATION(fpHDMI_audio_output,(IOCTL_HDMI_AUDIO_OUTPUT)MDrv_HDMI_audio_output_U2,MDrv_HDMI_audio_output)
2103 URELATION(fpHDMI_audio_cp_hdr_info,(IOCTL_HDMI_AUDIO_CP_HDR_INFO)MDrv_HDMI_audio_cp_hdr_info_U2,MDrv_HDMI_audio_cp_hdr_info)
2104 URELATION(fpHDMI_audio_channel_status,(IOCTL_HDMI_AUDIO_CHANNEL_STATUS)MDrv_HDMI_audio_channel_status_U2,MDrv_HDMI_audio_channel_status)
2105 URELATION(fpHDMI_GetLibVer,(IOCTL_HDMI_GETLIBVER)MDrv_HDMI_GetLibVer_U2,MDrv_HDMI_GetLibVer)
2106 URELATION(fpHDMI_GetInfo,(IOCTL_HDMI_GETINFO)MDrv_HDMI_GetInfo_U2,MDrv_HDMI_GetInfo)
2107 URELATION(fpHDMI_GetStatus,(IOCTL_HDMI_GETSTATUS)MDrv_HDMI_GetStatus_U2,MDrv_HDMI_GetStatus)
2108 URELATION(fpHDMI_READ_DDCRAM,(IOCTL_HDMI_READ_DDCRAM)MDrv_HDMI_READ_DDCRAM_U2,MDrv_HDMI_READ_DDCRAM)
2109 URELATION(fpHDMI_PROG_DDCRAM,(IOCTL_HDMI_PROG_DDCRAM)MDrv_HDMI_PROG_DDCRAM_U2,MDrv_HDMI_PROG_DDCRAM)
2110 URELATION(fpHDMI_Get_Ext_Colorimetry,(IOCTL_HDMI_GET_EXT_COLORIMETRY)MDrv_HDMI_Get_ExtColorimetry_U2,MDrv_HDMI_Get_ExtColorimetry)
2111 URELATION(fpHDMI_Get_Content_Type,(IOCTL_HDMI_GET_CONTENT_TYPE)MDrv_HDMI_Get_Content_Type_U2,MDrv_HDMI_Get_Content_Type)
2112 URELATION(fpHDMI_Get_Pixel_Repetition,(IOCTL_HDMI_GET_PIXEL_REPETITION)MDrv_HDMI_Get_Pixel_Repetition_U2,MDrv_HDMI_Get_Pixel_Repetition)
2113 URELATION(fpHDMI_Check4K2K,(IOCTL_HDMI_CHECK_4K2K)MDrv_HDMI_Check4K2K_U2,MDrv_HDMI_Check4K2K)
2114 URELATION(fpHDMI_3D_4Kx2K_Process,(IOCTL_HDMI_3D_4KX2K_PROCESS)MDrv_HDMI_3D_4Kx2K_Process_U2,MDrv_HDMI_3D_4Kx2K_Process)
2115 URELATION(fpHDMI_AVG_ScaleringDown,(IOCTL_HDMI_AVG_SCALERINGDOWN)MDrv_HDMI_AVG_ScaleringDown_U2,MDrv_HDMI_AVG_ScaleringDown)
2116 URELATION(fpHDMI_Check_Additional_Format,(IOCTL_HDMI_CHECK_ADDITIONAL_FORMAT)MDrv_HDMI_Check_Additional_Format_U2,MDrv_HDMI_Check_Additional_Format)
2117 URELATION(fpHDMI_Get_3D_Structure,(IOCTL_HDMI_GET_3D_STRUCTURE)MDrv_HDMI_Get_3D_Structure_U2,MDrv_HDMI_Get_3D_Structure)
2118 URELATION(fpHDMI_Get_3D_Ext_Data,(IOCTL_HDMI_GET_3D_EXT_DATA)MDrv_HDMI_Get_3D_Ext_Data_U2,MDrv_HDMI_Get_3D_Ext_Data)
2119 URELATION(fpHDMI_Get_3D_Meta_Field,(IOCTL_HDMI_GET_3D_META_FIELD)MDrv_HDMI_Get_3D_Meta_Field_U2,MDrv_HDMI_Get_3D_Meta_Field)
2120 URELATION(fpHDMI_Get_VIC_Code,(IOCTL_HDMI_GET_VIC_CODE)MDrv_HDMI_Get_VIC_Code_U2,MDrv_HDMI_Get_VIC_Code)
2121 URELATION(fpHDMI_Get_4Kx2K_VIC_Code,(IOCTL_HDMI_GET_4KX2K_VIC_CODE)MDrv_HDMI_Get_4Kx2K_VIC_Code_U2,MDrv_HDMI_Get_4Kx2K_VIC_Code)
2122 URELATION(fpHDMI_ARC_PINControl,(IOCTL_HDMI_ARC_PINCONTROL)MDrv_HDMI_ARC_PINControl_U2,MDrv_HDMI_ARC_PINControl)
2123 URELATION(fpDVI_Software_Reset,(IOCTL_DVI_SOFTWARE_RESET)MDrv_DVI_Software_Reset_U2,MDrv_DVI_Software_Reset)
2124 URELATION(fpHDMI_Set_PowerState,(IOCTL_HDMI_SET_POWERSTATE)MDrv_HDMI_SetPowerState_U2,MDrv_HDMI_SetPowerState)
2125 URELATION(fpHDMI_dvi_hf_adjust,(IOCTL_HDMI_DVI_HF_ADJUST)MDrv_DVI_HF_adjust_U2,MDrv_DVI_HF_adjust)
2126 URELATION(fpHDMI_checkhdmi20_setting,(IOCTL_HDMI_CHECKHDMI20_SETTING)MDrv_HDMI_CheckHDMI20_Setting_U2,MDrv_HDMI_CheckHDMI20_Setting)
2127 URELATION(fpHDMI_Set5VDetectGPIOSelect,(IOCTL_HDMI_SET_5V_DETECT_GPIO_SELECT)MDrv_HDMI_Set5VDetectGPIOSelect_U2,MDrv_HDMI_Set5VDetectGPIOSelect)
2128 URELATION(fpHDMI_Ctrl,(IOCTL_HDMI_CTRL)MDrv_HDMI_Ctrl_U2,MDrv_HDMI_Ctrl)
2129 URELATION(fpHDMI_GetDataInfo,(IOCTL_HDMI_GET_DATA_INFO)MDrv_HDMI_GetDataInfo_U2,MDrv_HDMI_GetDataInfo)
2130 #ifdef UFO_XC_VMARK
2131 URELATION(fpXC_VMark_SetParameters,(IOCTL_XC_VMARK_SET_PARAMETERS)MApi_XC_VMark_SetParameters_U2,MApi_XC_VMark_SetParameters)
2132 #endif
2133 URELATION(fpXC_Set_SWDR_Info,(IOCTL_XC_SET_SWDR_INFO)MApi_XC_SetSWDRInfo_U2,MApi_XC_SetSWDRInfo)
2134 URELATION(fpXC_Get_SWDR_Info,(IOCTL_XC_GET_SWDR_INFO)MApi_XC_GetSWDRInfo_U2,MApi_XC_GetSWDRInfo)
2135 #ifdef UFO_XC_SUPPORT_HDMI_DOWNSCALE_OUTPUT_POLICY
2136 URELATION(fpXC_GetHDMIPolicy,(IOCTL_XC_GET_HDMI_POLICY)MApi_XC_GetHDMIPolicy_U2,MApi_XC_GetHDMIPolicy)
2137 #endif
2138 #undef URELEATION
2139 }
2140
XCOpenFull(void ** ppInstance,const void * const pAttribute)2141 MS_U32 XCOpenFull(void** ppInstance, const void* const pAttribute)
2142 {
2143 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2144 XC_INSTANT_ATTRIBUTE *pstXCInstAttr = (XC_INSTANT_ATTRIBUTE*)pAttribute;
2145
2146 if (UtopiaInstanceCreate(sizeof(XC_INSTANCE_PRIVATE), ppInstance) != UTOPIA_STATUS_SUCCESS)
2147 {
2148 printf("[%s,%5d] Create Instance Failed\n",__FUNCTION__,__LINE__);
2149 return UTOPIA_STATUS_FAIL;
2150 }
2151
2152 UtopiaInstanceGetPrivate(*ppInstance, (void**)&psXCInstPri);
2153 psXCInstPri->u32DeviceID = 0;
2154 if(pAttribute != NULL)
2155 {
2156 psXCInstPri->u32DeviceID = pstXCInstAttr->u32DeviceID;
2157 }
2158 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2159 if((pstXCInstAttr == NULL) // Default: eXCType = E_XC_INSTANT_TYPE_XC
2160 ||(pstXCInstAttr->eXCType == E_XC_INSTANT_TYPE_XC)
2161 )
2162 {
2163 if (psXCInstPri->u32DeviceID == 1)
2164 {
2165 g_pDevice1Instance = *ppInstance;
2166 }
2167 else
2168 {
2169 g_pDevice0Instance = *ppInstance;
2170 }
2171 }
2172 #endif
2173
2174 #ifdef CONFIG_UTOPIA_SIZE_CUSTOMER
2175 XC_U1_U2_RELATION(ppInstance,pAttribute);
2176 #else
2177 // init Instance private members here
2178 XC_Initialize(psXCInstPri, pAttribute);
2179 ADC_Initialize(psXCInstPri, pAttribute);
2180 AUTO_Initialize(psXCInstPri, pAttribute);
2181
2182 MODEPARSE_Initialize(psXCInstPri, pAttribute);
2183 PCMONITOR_Initialize(psXCInstPri, pAttribute);
2184 HDMI_IF_Initialize(psXCInstPri, pAttribute);
2185 #endif
2186
2187 #ifdef UFO_XC_VMARK
2188 VMARK_Initialize(psXCInstPri, pAttribute);
2189 #endif
2190 return UTOPIA_STATUS_SUCCESS;
2191 }
2192
2193
2194 // this is for those who has code size problem and needs the minimum set of functions.
XCOpenMinimum(void ** ppInstance,const void * const pAttribute)2195 MS_U32 XCOpenMinimum(void** ppInstance, const void* const pAttribute)
2196 {
2197 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2198
2199 if (UtopiaInstanceCreate(sizeof(XC_INSTANCE_PRIVATE), ppInstance) != UTOPIA_STATUS_SUCCESS)
2200 {
2201 printf("[%s,%5d] Create Instance Failed\n",__FUNCTION__,__LINE__);
2202 return UTOPIA_STATUS_FAIL;
2203 }
2204
2205 UtopiaInstanceGetPrivate(*ppInstance, (void**)&psXCInstPri);
2206
2207 if(pAttribute != NULL)
2208 {
2209 MS_U32* u32Attr = (MS_U32*)pAttribute;
2210 psXCInstPri->u32DeviceID = *u32Attr;
2211 }
2212 else
2213 {
2214 psXCInstPri->u32DeviceID = 0;
2215 }
2216 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2217 if(psXCInstPri->u32DeviceID == 1)
2218 {
2219 g_pDevice1Instance = *ppInstance;
2220 }
2221 else
2222 {
2223 g_pDevice0Instance = *ppInstance;
2224 }
2225 #endif
2226 psXCInstPri->fpXC_GetCapability = MApi_XC_GetCapability_U2;
2227 psXCInstPri->fpXC_PreInit = MApi_XC_PreInit_U2;
2228 psXCInstPri->fpXC_Init_MISC = MApi_XC_Init_MISC_U2;
2229 psXCInstPri->fpXC_Init = MApi_XC_Init_U2;
2230 psXCInstPri->fpXC_SetExPanelInfo = MApi_XC_SetExPanelInfo_U2;
2231 psXCInstPri->fpXC_FRC_Mute = MApi_XC_FRC_Mute_U2;
2232 psXCInstPri->fpXC_ADC_SetCVBSOut = MApi_XC_ADC_SetCVBSOut_U2;
2233 psXCInstPri->fpXC_SetOutputCapture = MApi_XC_SetOutputCapture_U2;
2234 psXCInstPri->fpXC_SetDispWindowColor = MApi_XC_SetDispWindowColor_U2;
2235 psXCInstPri->fpXC_OSDC_InitSetting = MApi_XC_OSDC_InitSetting_U2;
2236 psXCInstPri->fpXC_OSDC_SetOutVfreqx10 = MApi_XC_OSDC_SetOutVfreqx10_U2;
2237 psXCInstPri->fpXC_OSDC_Control = MApi_XC_OSDC_Control_U2;
2238 psXCInstPri->fpXC_SetFrameColor = MApi_XC_SetFrameColor_U2;
2239 psXCInstPri->fpXC_WriteByteMask = MApi_XC_WriteByteMask_U2;
2240 psXCInstPri->fpXC_Write2ByteMask = MApi_XC_Write2ByteMask_U2;
2241 psXCInstPri->fpXC_W2BYTE = MApi_XC_W2BYTE_U2;
2242 psXCInstPri->fpXC_W4BYTE = MApi_XC_W4BYTE_U2;
2243 psXCInstPri->fpXC_W2BYTEMSK = MApi_XC_W2BYTEMSK_U2;
2244 psXCInstPri->fpXC_MLG_GetStatus = MApi_XC_MLG_GetStatus_U2;
2245 psXCInstPri->fpXC_SkipSWReset = MApi_XC_SkipSWReset_U2;
2246 psXCInstPri->fpXC_GenerateBlackVideo = MApi_XC_GenerateBlackVideo_U2;
2247 psXCInstPri->fpXC_Mux_Init = MApi_XC_Mux_Init_U2;
2248 psXCInstPri->fpXC_Mux_CreatePath = MApi_XC_Mux_CreatePath_U2;
2249 psXCInstPri->fpXC_Mux_EnablePath = MApi_XC_Mux_EnablePath_U2;
2250 psXCInstPri->fpXC_SetInputSource = MApi_XC_SetInputSource_U2;
2251 psXCInstPri->fpXC_DisableInputSource = MApi_XC_DisableInputSource_U2;
2252 psXCInstPri->fpXC_SkipWaitVsync = MApi_XC_SkipWaitVsync_U2;
2253 psXCInstPri->fpXC_SetWindow = MApi_XC_SetWindow_U2;
2254 psXCInstPri->fpXC_GetMISCStatus = MApi_XC_GetMISCStatus_U2;
2255 psXCInstPri->fpXC_SetOSD2VEMode = MApi_XC_SetOSD2VEMode_U2;
2256 return UTOPIA_STATUS_SUCCESS;
2257 }
2258
XCOpenForTEE(void ** ppInstance,const void * const pAttribute)2259 MS_U32 XCOpenForTEE(void** ppInstance, const void* const pAttribute)
2260 {
2261 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2262
2263 if (UtopiaInstanceCreate(sizeof(XC_INSTANCE_PRIVATE), ppInstance) != UTOPIA_STATUS_SUCCESS)
2264 {
2265 printf("[%s,%5d] Create Instance Failed\n",__FUNCTION__,__LINE__);
2266 return UTOPIA_STATUS_FAIL;
2267 }
2268
2269 UtopiaInstanceGetPrivate(*ppInstance, (void**)&psXCInstPri);
2270
2271 if(pAttribute != NULL)
2272 {
2273 MS_U32* u32Attr = (MS_U32*)pAttribute;
2274 psXCInstPri->u32DeviceID = *u32Attr;
2275 }
2276 else
2277 {
2278 psXCInstPri->u32DeviceID = 0;
2279 }
2280 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2281 if(psXCInstPri->u32DeviceID == 1)
2282 {
2283 g_pDevice1Instance = *ppInstance;
2284 }
2285 else
2286 {
2287 g_pDevice0Instance = *ppInstance;
2288 }
2289 #endif
2290 psXCInstPri->fpXC_Init = MApi_XC_Init_U2;
2291 psXCInstPri->fpXC_OPTEE_Ctrl = MApi_XC_OPTEE_Control_U2;
2292 psXCInstPri->fpXC_OPTEE_CheckRBase = MApi_XC_OPTEE_CheckRBase_U2;
2293 psXCInstPri->fpXC_OPTEE_Mux = MApi_XC_OPTEE_Mux_U2;
2294 psXCInstPri->fpXC_GetResourceByPipeID = MApi_XC_GetResourceByPipeID_U2;
2295 psXCInstPri->fpXC_ConfigPipe = MApi_XC_ConfigPipe_U2;
2296 psXCInstPri->fpXC_CheckPipe = MApi_XC_CheckPipe_U2;
2297 psXCInstPri->fpXC_SetDispWinToReg = MApi_XC_SetDispWinToReg_U2;
2298 psXCInstPri->fpXC_GetDispWinFromReg = MApi_XC_GetDispWinFromReg_U2;
2299 psXCInstPri->fpXC_Vtrack_SetPayloadData = MApi_XC_Vtrack_SetPayloadData_U2;
2300 psXCInstPri->fpXC_Vtrack_SetUserDefindedSetting = MApi_XC_Vtrack_SetUserDefindedSetting_U2;
2301 psXCInstPri->fpXC_Vtrack_Enable = MApi_XC_Vtrack_Enable_U2;
2302 psXCInstPri->fpXC_GetStatus = MApi_XC_GetStatus_U2;
2303 psXCInstPri->fpXC_GenerateBlackVideo = MApi_XC_GenerateBlackVideo_U2;
2304 #ifdef UFO_XC_VMARK
2305 VMARK_Initialize(psXCInstPri, pAttribute);
2306 #endif
2307 psXCInstPri->fpXC_Set_PowerState = MApi_XC_SetPowerState_U2;
2308
2309 return UTOPIA_STATUS_SUCCESS;
2310 }
2311
XCIoctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)2312 MS_U32 XCIoctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
2313 {
2314 E_XC_IOCTL_CMDS eCmds = (E_XC_IOCTL_CMDS) u32Cmd;
2315
2316 if( eCmds >= E_XC_CMD_NUM )
2317 {
2318 printf(" IOCTL command out of bounds, please check!\n");
2319 return UTOPIA_STATUS_NOT_SUPPORTED;
2320 }
2321
2322 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
2323 // APIXC
2324 // E_XC_CMD_NONE = 0 so eCmds can not compare with E_XC_CMD_NONE
2325 // eCmds is unsigned value, can not compare with 0
2326 if (eCmds <= E_XC_CMD_MAX)
2327 {
2328 u32Return = _XCIoctl(pInstance, u32Cmd, pArgs);
2329 }
2330 // APIXC_ADC
2331 else if((eCmds >= E_XC_ADC_CMD_NONE)
2332 && (eCmds <= E_XC_ADC_CMD_MAX))
2333 {
2334 u32Return = _ADCIoctl(pInstance, u32Cmd, pArgs);
2335 }
2336 // APIXC_AUTO
2337 else if((eCmds >= E_XC_AUTO_CMD_NONE)
2338 && (eCmds <= E_XC_AUTO_CMD_MAX))
2339 {
2340 u32Return = _AUTOIoctl(pInstance, u32Cmd, pArgs);
2341 }
2342
2343 // APIXC_MODEPARSE
2344 else if((eCmds >= E_XC_MODEPARSE_CMD_NONE)
2345 && (eCmds <= E_XC_MODEPARSE_CMD_MAX))
2346 {
2347 u32Return = _MODEPARSEIoctl(pInstance, u32Cmd, pArgs);
2348 }
2349 // APIXC_PCMONITOR
2350 else if((eCmds >= E_XC_PCMONITOR_CMD_NONE)
2351 && (eCmds <= E_XC_PCMONITOR_CMD_MAX))
2352 {
2353 u32Return = _PCMONITORIoctl(pInstance, u32Cmd, pArgs);
2354 }
2355 // DRVXC_HDMI_IF
2356 else if((eCmds >= E_XC_HDMI_IF_CMD_NONE)
2357 && (eCmds <= E_XC_HDMI_IF_CMD_MAX))
2358 {
2359 u32Return = _HDMI_IF_Ioctl(pInstance, u32Cmd, pArgs);
2360 }
2361 #ifdef UFO_XC_VMARK
2362 else if((eCmds >= E_XC_VMARK_CMD_NONE)
2363 && (eCmds <= E_XC_VMARK_CMD_MAX))
2364 {
2365 u32Return = _VMARKIoctl(pInstance, u32Cmd, pArgs);
2366 }
2367 #endif
2368 return u32Return;
2369 }
2370
_XCIoctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)2371 MS_U32 _XCIoctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
2372 {
2373 //void* pModule = NULL;
2374 //void* pResource = NULL;
2375 XC_INSTANCE_PRIVATE* psXCInstPri = NULL;
2376
2377 //UtopiaInstanceGetModule(pInstance, &pModule);
2378
2379 if(UtopiaInstanceGetPrivate(pInstance, (void*)&psXCInstPri)!=UTOPIA_STATUS_SUCCESS)
2380 {
2381 printf("[%s,%5d] Instance Get Private failed\n",__FUNCTION__,__LINE__);
2382 }
2383
2384 if(psXCInstPri->u32DeviceID == 0)
2385 {
2386 pu32XCInst_private = pInstance;
2387 }
2388 else if(psXCInstPri->u32DeviceID == 1)
2389 {
2390 pu32XCInst_1_private = pInstance;
2391 }
2392
2393 //printf("[%s,%5d] u32Cmd type = %ld\n",__FUNCTION__,__LINE__,u32Cmd);
2394 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
2395 switch(u32Cmd)
2396 {
2397 case E_XC_CMD_GET_LIB_VERSION:
2398 {
2399 pstXC_GET_LIB_VER pXCArgs = (pstXC_GET_LIB_VER) pArgs;
2400 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetLibVer(pInstance, pXCArgs->ppVersion);
2401
2402 u32Return = UTOPIA_STATUS_SUCCESS;
2403 break;
2404 }
2405
2406
2407 case E_XC_CMD_GET_INFO:
2408 {
2409
2410 pstXC_CMD_GET_INFO pXCArgs = (pstXC_CMD_GET_INFO) pArgs;
2411 #ifndef MSOS_TYPE_LINUX_KERNEL
2412 pXCArgs->stReturnValue = psXCInstPri->fpXC_GetInfo(pInstance);
2413 #else
2414 memcpy(pXCArgs->stReturnValue,psXCInstPri->fpXC_GetInfo(pInstance),sizeof(XC_ApiInfo));
2415 #endif
2416
2417 u32Return = UTOPIA_STATUS_SUCCESS;
2418 break;
2419 }
2420
2421
2422 case E_XC_CMD_GET_STATUS:
2423 {
2424
2425 pstXC_GET_STATUS pXCArgs = (pstXC_GET_STATUS) pArgs;
2426 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2427 USE_OTHER_SC_AS_SUB_WINDOW();
2428 #endif
2429 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetStatus(pInstance,pXCArgs->pDrvStatus, pXCArgs->eWindow);
2430
2431 u32Return = UTOPIA_STATUS_SUCCESS;
2432 break;
2433 }
2434
2435 case E_XC_CMD_GET_STATUS_NODELAY:
2436 {
2437
2438 PST_XC_GET_STATUS_NODELAY pXCArgs = (PST_XC_GET_STATUS_NODELAY) pArgs;
2439 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2440 USE_OTHER_SC_AS_SUB_WINDOW();
2441 #endif
2442 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetStatus_nodelay(pInstance,pXCArgs->pDrvStatus, pXCArgs->eWindow);
2443
2444 u32Return = UTOPIA_STATUS_SUCCESS;
2445 break;
2446 }
2447
2448
2449 case E_XC_CMD_GET_STATUS_EX:
2450 {
2451
2452 pstXC_GET_STATUS_EX pXCArgs = (pstXC_GET_STATUS_EX) pArgs;
2453 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2454 USE_OTHER_SC_AS_SUB_WINDOW();
2455 #endif
2456 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetStatusEx(pInstance,pXCArgs->pDrvStatusEx, pXCArgs->eWindow);
2457
2458 u32Return = UTOPIA_STATUS_SUCCESS;
2459 break;
2460 }
2461
2462
2463 case E_XC_CMD_SET_DBG_LEVEL:
2464 {
2465
2466 pstXC_SET_DBG_LEVEL pXCArgs = (pstXC_SET_DBG_LEVEL) pArgs;
2467 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetDbgLevel(pInstance,pXCArgs->u16DbgSwitch);
2468
2469 u32Return = UTOPIA_STATUS_SUCCESS;
2470 break;
2471 }
2472
2473 case E_XC_CMD_SET_FPLL_CUSTOMERMODE:
2474 {
2475
2476 pstXC_SET_FPLL_CUSTOMERMODE pXCArgs = (pstXC_SET_FPLL_CUSTOMERMODE) pArgs;
2477 psXCInstPri->fpXC_FPLLCustomerMode(pInstance,pXCArgs->eMode, pXCArgs->eFlag, pXCArgs->u32Data);
2478
2479 u32Return = UTOPIA_STATUS_SUCCESS;
2480 break;
2481 }
2482
2483
2484 case E_XC_CMD_SET_IOMAPBASE:
2485
2486 {
2487
2488 pstXC_CMD_SET_IOMAPBASE pXCArgs = (pstXC_CMD_SET_IOMAPBASE) pArgs;
2489 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetIOMapBase(pInstance);
2490
2491 u32Return = UTOPIA_STATUS_SUCCESS;
2492 break;
2493 }
2494
2495
2496 case E_XC_CMD_INIT:
2497 {
2498
2499 pstXC_INIT pXCArgs = (pstXC_INIT) pArgs;
2500 pXCArgs->bReturnValue = psXCInstPri->fpXC_Init(pInstance,pXCArgs->pXC_InitData, pXCArgs->u32InitDataLen);
2501 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2502 CHECK_DEVICE1_INSTANCE();
2503 //because use sc1 main as sc0 sub, sc1 mian use sc0 sub frame buffer
2504 if (pXCArgs->pXC_InitData != NULL)
2505 {
2506 pXCArgs->pXC_InitData->u32Main_FB_Start_Addr = pXCArgs->pXC_InitData->u32Sub_FB_Start_Addr;
2507 pXCArgs->pXC_InitData->u32Main_FB_Size = pXCArgs->pXC_InitData->u32Sub_FB_Size;
2508 }
2509 pXCArgs->bReturnValue = psXCInstPri->fpXC_Init(g_pDevice1Instance,pXCArgs->pXC_InitData, pXCArgs->u32InitDataLen);
2510 #endif
2511 u32Return = UTOPIA_STATUS_SUCCESS;
2512 break;
2513 }
2514
2515
2516 case E_XC_CMD_INIT_MISC:
2517 {
2518
2519 pstXC_INIT_MISC pXCArgs = (pstXC_INIT_MISC) pArgs;
2520 pXCArgs->eReturnValue = psXCInstPri->fpXC_Init_MISC(pInstance,pXCArgs->pXC_Init_Misc, pXCArgs->u32InitMiscDataLen);
2521
2522 u32Return = UTOPIA_STATUS_SUCCESS;
2523 break;
2524 }
2525
2526
2527 case E_XC_CMD_GET_MISC_STATUS:
2528 {
2529
2530 pstXC_GET_MISC_STATUS pXCArgs = (pstXC_GET_MISC_STATUS) pArgs;
2531 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetMISCStatus(pInstance,pXCArgs->pXC_Init_Misc);
2532
2533 u32Return = UTOPIA_STATUS_SUCCESS;
2534 break;
2535 }
2536
2537
2538 case E_XC_CMD_GET_CAPABILITY:
2539 {
2540
2541 pstXC_GET_CAPABILITY pXCArgs = (pstXC_GET_CAPABILITY) pArgs;
2542 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_GetCapability(pInstance,pXCArgs->u32Id);
2543
2544 u32Return = UTOPIA_STATUS_SUCCESS;
2545 break;
2546 }
2547
2548
2549 case E_XC_CMD_GET_CHIPCAPS:
2550 {
2551
2552
2553 pstXC_GET_CHIP_CAPS pXCArgs = (pstXC_GET_CHIP_CAPS) pArgs;
2554 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetChipCaps(pInstance,pXCArgs->eCapType, pXCArgs->pRet, pXCArgs->ret_size);
2555
2556
2557 u32Return = UTOPIA_STATUS_SUCCESS;
2558 break;
2559 }
2560
2561
2562 case E_XC_CMD_EXIT:
2563 {
2564
2565 pstXC_EXIT pXCArgs = (pstXC_EXIT) pArgs;
2566 pXCArgs->bReturnValue = psXCInstPri->fpXC_Exit(pInstance);
2567 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2568 CHECK_DEVICE1_INSTANCE();
2569 pXCArgs->bReturnValue = psXCInstPri->fpXC_Exit(g_pDevice1Instance);
2570 #endif
2571 printf("XC Exited\n");
2572
2573 u32Return = UTOPIA_STATUS_SUCCESS;
2574 break;
2575 }
2576
2577
2578 case E_XC_CMD_SET_DYNAMIC_SCALING:
2579 {
2580
2581 pstXC_SET_DYNAMIC_SCALING pXCArgs = (pstXC_SET_DYNAMIC_SCALING) pArgs;
2582 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2583 USE_OTHER_SC_AS_SUB_WINDOW();
2584 #endif
2585 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetDynamicScaling(pInstance,pXCArgs->pstDSInfo, pXCArgs->u32DSInfoLen, pXCArgs->eWindow);
2586
2587 u32Return = UTOPIA_STATUS_SUCCESS;
2588 break;
2589 }
2590
2591 case E_XC_CMD_SET_DYNAMIC_SCALING_FLAG:
2592 {
2593
2594 pstXC_SET_DYNAMIC_SCALING_FLAG pXCArgs = (pstXC_SET_DYNAMIC_SCALING_FLAG) pArgs;
2595 psXCInstPri->fpXC_SetDynamicScalingFlag(pInstance,pXCArgs->bEnable);
2596 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2597 CHECK_DEVICE1_INSTANCE();
2598 psXCInstPri->fpXC_SetDynamicScalingFlag(g_pDevice1Instance,pXCArgs->bEnable);
2599 #endif
2600
2601 break;
2602 }
2603
2604 case E_XC_CMD_GET_DNR_BASEOFFSET:
2605 {
2606
2607 pstXC_GET_DNR_BASEOFFSET pXCArgs = (pstXC_GET_DNR_BASEOFFSET) pArgs;
2608 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2609 USE_OTHER_SC_AS_SUB_WINDOW();
2610 #endif
2611 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_Get_DNRBaseOffset(pInstance, pXCArgs->eWindow);
2612
2613 u32Return = UTOPIA_STATUS_SUCCESS;
2614 break;
2615 }
2616
2617
2618 case E_XC_CMD_GET_STORE_FRAMENUM:
2619 case E_XC_CMD_GET_FRAMENUM_FACTOR:
2620 {
2621
2622 pstXC_GET_FRAMENUM_FACTOR pXCArgs = (pstXC_GET_FRAMENUM_FACTOR) pArgs;
2623 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2624 USE_OTHER_SC_AS_SUB_WINDOW();
2625 #endif
2626 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_Get_FrameNumFactor(pInstance, pXCArgs->eWindow);
2627
2628 u32Return = UTOPIA_STATUS_SUCCESS;
2629 break;
2630 }
2631
2632
2633 case E_XC_CMD_SET_WINDOW:
2634 {
2635 pstXC_SET_WINDOW pXCArgs = (pstXC_SET_WINDOW) pArgs;
2636 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2637 USE_OTHER_SC_AS_SUB_WINDOW();
2638 #endif
2639 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetWindow(pInstance, pXCArgs->pstXC_SetWin_Info, pXCArgs->u32InitDataLen, pXCArgs->eWindow);
2640
2641 u32Return = UTOPIA_STATUS_SUCCESS;
2642 break;
2643 }
2644
2645 case E_XC_CMD_SET_DUALWINDOW:
2646 {
2647 pstXC_SET_DUALWINDOW pXCArgs = (pstXC_SET_DUALWINDOW) pArgs;
2648 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetDualWindow(pInstance, pXCArgs->pstXC_SetWin_Info_Main, pXCArgs->pstXC_SetWin_Info_Sub);
2649
2650 u32Return = UTOPIA_STATUS_SUCCESS;
2651 break;
2652 }
2653
2654 case E_XC_CMD_SET_TRAVELING_WINDOW:
2655 {
2656
2657
2658 pstXC_SET_TRAVELING_WINDOW pXCArgs = (pstXC_SET_TRAVELING_WINDOW) pArgs;
2659 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2660 USE_OTHER_SC_AS_SUB_WINDOW();
2661 #endif
2662 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetTravelingWindow(pInstance, pXCArgs->pstXC_SetWin_Info, pXCArgs->u32InitDataLen, pXCArgs->eWindow);
2663
2664
2665 u32Return = UTOPIA_STATUS_SUCCESS;
2666 break;
2667 }
2668
2669
2670 case E_XC_CMD_SET_INPUTSOURCE:
2671 {
2672
2673 pstXC_SET_INPUTSOURCE pXCArgs = (pstXC_SET_INPUTSOURCE) pArgs;
2674 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2675 USE_OTHER_SC_AS_SUB_WINDOW();
2676 #endif
2677 psXCInstPri->fpXC_SetInputSource(pInstance, pXCArgs->enInputSourceType, pXCArgs->eWindow);
2678
2679 u32Return = UTOPIA_STATUS_SUCCESS;
2680
2681 break;
2682 }
2683
2684
2685 case E_XC_CMD_CHECK_YUVSPACE:
2686 {
2687
2688
2689 pstXC_CHECK_YUVSPACE pXCArgs = (pstXC_CHECK_YUVSPACE) pArgs;
2690 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2691 USE_OTHER_SC_AS_SUB_WINDOW();
2692 #endif
2693 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsYUVSpace(pInstance, pXCArgs->eWindow);
2694
2695
2696 u32Return = UTOPIA_STATUS_SUCCESS;
2697 break;
2698 }
2699
2700
2701 case E_XC_CMD_CHECK_MEMORYFORMAT422:
2702 {
2703
2704
2705 pstXC_CHECK_MEMORYFORMAT422 pXCArgs = (pstXC_CHECK_MEMORYFORMAT422) pArgs;
2706 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2707 USE_OTHER_SC_AS_SUB_WINDOW();
2708 #endif
2709 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsMemoryFormat422(pInstance, pXCArgs->eWindow);
2710
2711
2712 u32Return = UTOPIA_STATUS_SUCCESS;
2713 break;
2714 }
2715
2716
2717 case E_XC_CMD_SET_FORCE_RGBIN:
2718 {
2719
2720
2721 pstXC_SET_FORCE_RGBIN pXCArgs = (pstXC_SET_FORCE_RGBIN) pArgs;
2722 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2723 USE_OTHER_SC_AS_SUB_WINDOW();
2724 #endif
2725 psXCInstPri->fpXC_EnableForceRGBin(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2726
2727
2728 u32Return = UTOPIA_STATUS_SUCCESS;
2729 break;
2730 }
2731
2732
2733 case E_XC_CMD_SET_MIRRORMODE_EX:
2734 {
2735
2736
2737 pstXC_SET_MIRRORMODE_EX pXCArgs = (pstXC_SET_MIRRORMODE_EX) pArgs;
2738 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2739 USE_OTHER_SC_AS_SUB_WINDOW();
2740 #endif
2741 pXCArgs->bReturnValue = psXCInstPri->fpXC_EnableMirrorModeEx(pInstance, pXCArgs->eMirrorMode, pXCArgs->eWindow);
2742
2743
2744 u32Return = UTOPIA_STATUS_SUCCESS;
2745 break;
2746 }
2747
2748
2749 case E_XC_CMD_GET_MIRRORMODE_TYPEEX:
2750 {
2751
2752
2753 pstXC_GET_MIRRORMODE_TYPEEX pXCArgs = (pstXC_GET_MIRRORMODE_TYPEEX) pArgs;
2754 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2755 USE_OTHER_SC_AS_SUB_WINDOW();
2756 #endif
2757 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetMirrorModeTypeEx(pInstance, pXCArgs->eWindow);
2758
2759
2760 u32Return = UTOPIA_STATUS_SUCCESS;
2761 break;
2762 }
2763
2764
2765 case E_XC_CMD_GET_SYNC_STATUS:
2766 {
2767
2768
2769 pstXC_GET_SYNC_STATUS pXCArgs = (pstXC_GET_SYNC_STATUS) pArgs;
2770 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2771 USE_OTHER_SC_AS_SUB_WINDOW();
2772 #endif
2773 psXCInstPri->fpXC_GetSyncStatus(pInstance, pXCArgs->eCurrentSrc, pXCArgs->sXC_Sync_Status, pXCArgs->eWindow);
2774
2775
2776 u32Return = UTOPIA_STATUS_SUCCESS;
2777 break;
2778 }
2779
2780 case E_XC_CMD_CONFIG_CMA:
2781 {
2782
2783
2784 pstXC_CONFIG_CMA pXCArgs = (pstXC_CONFIG_CMA) pArgs;
2785 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2786 USE_OTHER_SC_AS_SUB_WINDOW();
2787 #endif
2788 psXCInstPri->fpXC_ConfigCMA(pInstance, pXCArgs->pstXC_CMA_Config, pXCArgs->enCmaClient, pXCArgs->u32InitDataLen, pXCArgs->eWindow);
2789
2790
2791 u32Return = UTOPIA_STATUS_SUCCESS;
2792 break;
2793 }
2794
2795 case E_XC_CMD_SET_WAIT_OUTPUT_VSYNC:
2796 {
2797
2798
2799 pstXC_SET_WAIT_OUTPUT_VSYNC pXCArgs = (pstXC_SET_WAIT_OUTPUT_VSYNC) pArgs;
2800 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2801 USE_OTHER_SC_AS_SUB_WINDOW();
2802 #endif
2803 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_WaitOutputVSync(pInstance, pXCArgs->u8NumVSyncs, pXCArgs->u16Timeout, pXCArgs->eWindow);
2804
2805
2806 u32Return = UTOPIA_STATUS_SUCCESS;
2807 break;
2808 }
2809
2810
2811 case E_XC_CMD_SET_WAIT_INPUT_VSYNC:
2812 {
2813
2814
2815 pstXC_SET_WAIT_INPUT_VSYNC pXCArgs = (pstXC_SET_WAIT_INPUT_VSYNC) pArgs;
2816 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2817 USE_OTHER_SC_AS_SUB_WINDOW();
2818 #endif
2819 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_WaitInputVSync(pInstance, pXCArgs->u8NumVSyncs, pXCArgs->u16Timeout, pXCArgs->eWindow);
2820
2821
2822
2823 u32Return = UTOPIA_STATUS_SUCCESS;
2824 break;
2825 }
2826
2827
2828 case E_XC_CMD_SET_HDMI_SYNCMODE:
2829 {
2830
2831
2832 pstXC_SET_HDMI_SYNCMODE pXCArgs = (pstXC_SET_HDMI_SYNCMODE) pArgs;
2833 psXCInstPri->fpXC_SetHdmiSyncMode(pInstance, pXCArgs->eSynctype);
2834 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2835 CHECK_DEVICE1_INSTANCE();
2836 psXCInstPri->fpXC_SetHdmiSyncMode(g_pDevice1Instance, pXCArgs->eSynctype);
2837 #endif
2838
2839 u32Return = UTOPIA_STATUS_SUCCESS;
2840 break;
2841 }
2842
2843
2844 case E_XC_CMD_GET_HDMI_SYNCMODE:
2845 {
2846
2847
2848 pstXC_GET_HDMI_SYNCMODE pXCArgs = (pstXC_GET_HDMI_SYNCMODE) pArgs;
2849 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetHdmiSyncMode(pInstance);
2850
2851
2852 u32Return = UTOPIA_STATUS_SUCCESS;
2853 break;
2854 }
2855
2856
2857 case E_XC_CMD_SET_REPORT_WINDOW:
2858 {
2859 pstXC_SET_REPORT_WINDOW pXCArgs = (pstXC_SET_REPORT_WINDOW) pArgs;
2860 psXCInstPri->fpXC_SetRepWindow(pInstance, pXCArgs->bEnable, pXCArgs->Window, pXCArgs->u8Color);
2861 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2862 CHECK_DEVICE1_INSTANCE();
2863 psXCInstPri->fpXC_SetRepWindow(g_pDevice1Instance, pXCArgs->bEnable, pXCArgs->Window, pXCArgs->u8Color);
2864 #endif
2865 u32Return = UTOPIA_STATUS_SUCCESS;
2866 break;
2867 }
2868
2869 case E_XC_CMD_SET_SKIP_OPWRITEOFF_IN_SETWINDOW:
2870 {
2871 pstXC_SET_SKIP_OPWRITEOFF_IN_SETWINDOW pXCArgs = (pstXC_SET_SKIP_OPWRITEOFF_IN_SETWINDOW) pArgs;
2872 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2873 USE_OTHER_SC_AS_SUB_WINDOW();
2874 #endif
2875 psXCInstPri->fpXC_SkipOPWriteOffInSetWindow(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2876
2877 u32Return = UTOPIA_STATUS_SUCCESS;
2878 break;
2879 }
2880
2881 case E_XC_CMD_GET_SKIP_OPWRITEOFF_IN_SETWINDOW:
2882 {
2883 pstXC_GET_SKIP_OPWRITEOFF_IN_SETWINDOW pXCArgs = (pstXC_GET_SKIP_OPWRITEOFF_IN_SETWINDOW) pArgs;
2884 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2885 USE_OTHER_SC_AS_SUB_WINDOW();
2886 #endif
2887 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetSkipOPWriteOffInSetWindow(pInstance,pXCArgs->eWindow);
2888
2889 u32Return = UTOPIA_STATUS_SUCCESS;
2890 break;
2891 }
2892
2893 case E_XC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL:
2894 {
2895 pstXC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL pXCArgs = (pstXC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL) pArgs;
2896 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2897 USE_OTHER_SC_AS_SUB_WINDOW();
2898 #endif
2899 psXCInstPri->fpXC_SetSkipDisableOPWriteOffInFPLL(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2900
2901 u32Return = UTOPIA_STATUS_SUCCESS;
2902 break;
2903 }
2904
2905 case E_XC_CMD_SET_OPWRITEOFF_ENABLE:
2906 {
2907 pstXC_SET_OPWRITEOFF_ENABLE pXCArgs = (pstXC_SET_OPWRITEOFF_ENABLE) pArgs;
2908 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2909 USE_OTHER_SC_AS_SUB_WINDOW();
2910 #endif
2911 psXCInstPri->fpXC_Set_OPWriteOffEnable(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2912
2913 u32Return = UTOPIA_STATUS_SUCCESS;
2914 break;
2915 }
2916
2917 case E_XC_CMD_SET_OPWRITEOFF_ENABLE_TO_REG:
2918 {
2919 pstXC_SET_OPWRITEOFF_ENABLE_TO_REG pXCArgs = (pstXC_SET_OPWRITEOFF_ENABLE_TO_REG) pArgs;
2920 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2921 USE_OTHER_SC_AS_SUB_WINDOW();
2922 #endif
2923 psXCInstPri->fpXC_Set_OPWriteOffEnableToReg(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2924
2925 u32Return = UTOPIA_STATUS_SUCCESS;
2926 break;
2927 }
2928
2929 case E_XC_CMD_FORCESET_OPWRITEOFF_ENABLE:
2930 {
2931 pstXC_FORCESET_OPWRITEOFF_ENABLE pXCArgs = (pstXC_FORCESET_OPWRITEOFF_ENABLE) pArgs;
2932 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2933 USE_OTHER_SC_AS_SUB_WINDOW();
2934 #endif
2935 psXCInstPri->fpXC_ForceSet_OPWriteOffEnable(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2936
2937 u32Return = UTOPIA_STATUS_SUCCESS;
2938 break;
2939 }
2940
2941 case E_XC_CMD_GET_OPWRITEOFF_ENABLE:
2942 {
2943 pstXC_GET_OPWRITEOFF_ENABLE pXCArgs = (pstXC_GET_OPWRITEOFF_ENABLE) pArgs;
2944 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2945 USE_OTHER_SC_AS_SUB_WINDOW();
2946 #endif
2947 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_OPWriteOffEnable(pInstance, pXCArgs->eWindow);
2948
2949 u32Return = UTOPIA_STATUS_SUCCESS;
2950 break;
2951 }
2952
2953 case E_XC_CMD_SET_DISPLAY_WIN_TO_REG:
2954 {
2955 pstXC_SET_DISPLAY_WIN_TO_REG pXCArgs = (pstXC_SET_DISPLAY_WIN_TO_REG) pArgs;
2956 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2957 USE_OTHER_SC_AS_SUB_WINDOW();
2958 #endif
2959 psXCInstPri->fpXC_SetDispWinToReg(pInstance, pXCArgs->pstDspwin, pXCArgs->eWindow);
2960
2961
2962 u32Return = UTOPIA_STATUS_SUCCESS;
2963 break;
2964 }
2965
2966
2967 case E_XC_CMD_GET_DISPLAY_WIN_FROM_REG:
2968 {
2969
2970
2971 pstXC_GET_DISPLAY_WIN_FROM_REG pXCArgs = (pstXC_GET_DISPLAY_WIN_FROM_REG) pArgs;
2972 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2973 USE_OTHER_SC_AS_SUB_WINDOW();
2974 #endif
2975 psXCInstPri->fpXC_GetDispWinFromReg(pInstance, pXCArgs->pstDspwin, pXCArgs->eWindow);
2976
2977
2978 u32Return = UTOPIA_STATUS_SUCCESS;
2979 break;
2980 }
2981
2982
2983 case E_XC_CMD_SET_FREEZEIMG:
2984 {
2985
2986 pstXC_SET_FREEZEIMG pXCArgs = (pstXC_SET_FREEZEIMG) pArgs;
2987 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2988 USE_OTHER_SC_AS_SUB_WINDOW();
2989 #endif
2990 psXCInstPri->fpXC_FreezeImg(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
2991
2992 u32Return = UTOPIA_STATUS_SUCCESS;
2993 break;
2994 }
2995 case E_XC_CMD_CHECK_FREEZEIMG:
2996 {
2997
2998
2999 pstXC_CHECK_FREEZEIMG pXCArgs = (pstXC_CHECK_FREEZEIMG) pArgs;
3000 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3001 USE_OTHER_SC_AS_SUB_WINDOW();
3002 #endif
3003 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsFreezeImg(pInstance, pXCArgs->eWindow);
3004
3005
3006 u32Return = UTOPIA_STATUS_SUCCESS;
3007 break;
3008 }
3009
3010 case E_XC_CMD_SET_BOTHWINDOW_BLACKVIDEO:
3011 {
3012
3013
3014 pstXC_SET_BOTHWINDOW_BLACKVIDEO pXCArgs = (pstXC_SET_BOTHWINDOW_BLACKVIDEO) pArgs;
3015 psXCInstPri->fpXC_GenerateBlackVideoForBothWin(pInstance, pXCArgs->bEnable);
3016
3017
3018 u32Return = UTOPIA_STATUS_SUCCESS;
3019 break;
3020 }
3021
3022
3023 case E_XC_CMD_SET_BLACKSCREEN:
3024 {
3025
3026
3027 pstXC_SET_BLACKSCREEN pXCArgs = (pstXC_SET_BLACKSCREEN) pArgs;
3028 psXCInstPri->fpXC_Set_BLSK(pInstance, pXCArgs->bEnable);
3029 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3030 CHECK_DEVICE1_INSTANCE();
3031 psXCInstPri->fpXC_Set_BLSK(g_pDevice1Instance, pXCArgs->bEnable);
3032 #endif
3033 u32Return = UTOPIA_STATUS_SUCCESS;
3034 break;
3035 }
3036
3037
3038 case E_XC_CMD_SET_BLACKVIDEO:
3039 {
3040
3041
3042 pstXC_SET_BLACKVIDEO pXCArgs = (pstXC_SET_BLACKVIDEO) pArgs;
3043 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3044 USE_OTHER_SC_AS_SUB_WINDOW();
3045 #endif
3046 psXCInstPri->fpXC_GenerateBlackVideo(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
3047
3048
3049 u32Return = UTOPIA_STATUS_SUCCESS;
3050 break;
3051 }
3052
3053
3054 case E_XC_CMD_CHECK_BLACKVIDEO_ENABLE:
3055 {
3056
3057 pstXC_CHECK_BLACKVIDEO_ENABLE pXCArgs = (pstXC_CHECK_BLACKVIDEO_ENABLE) pArgs;
3058 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3059 USE_OTHER_SC_AS_SUB_WINDOW();
3060 #endif
3061 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsBlackVideoEnable(pInstance, pXCArgs->eWindow);
3062
3063
3064 u32Return = UTOPIA_STATUS_SUCCESS;
3065 break;
3066 }
3067
3068
3069 case E_XC_CMD_SET_FRAMEBUFFERLESS:
3070 {
3071
3072
3073 pstXC_SET_FRAMEBUFFERLESS pXCArgs = (pstXC_SET_FRAMEBUFFERLESS) pArgs;
3074 psXCInstPri->fpXC_EnableFrameBufferLess(pInstance, pXCArgs->bEnable);
3075 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3076 CHECK_DEVICE1_INSTANCE();
3077 psXCInstPri->fpXC_EnableFrameBufferLess(g_pDevice1Instance, pXCArgs->bEnable);
3078 #endif
3079
3080 u32Return = UTOPIA_STATUS_SUCCESS;
3081 break;
3082 }
3083
3084
3085 case E_XC_CMD_CHECK_FRAMEBUFFERLESS:
3086 {
3087
3088
3089 pstXC_CHECK_FRAMEBUFFERLESS pXCArgs = (pstXC_CHECK_FRAMEBUFFERLESS) pArgs;
3090 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsCurrentFrameBufferLessMode(pInstance);
3091
3092
3093 u32Return = UTOPIA_STATUS_SUCCESS;
3094 break;
3095 }
3096
3097
3098 case E_XC_CMD_SET_REQUEST_FRAMEBUFFERLESS:
3099 {
3100
3101
3102 pstXC_SET_REQUEST_FRAMEBUFFERLESS pXCArgs = (pstXC_SET_REQUEST_FRAMEBUFFERLESS) pArgs;
3103 psXCInstPri->fpXC_EnableRequest_FrameBufferLess(pInstance, pXCArgs->bEnable);
3104 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3105 CHECK_DEVICE1_INSTANCE();
3106 psXCInstPri->fpXC_EnableRequest_FrameBufferLess(g_pDevice1Instance, pXCArgs->bEnable);
3107 #endif
3108 u32Return = UTOPIA_STATUS_SUCCESS;
3109 break;
3110 }
3111
3112
3113 case E_XC_CMD_CHECK_REQUEST_FRAMEBUFFERLESS:
3114 {
3115
3116
3117 pstXC_CHECK_REQUEST_FRAMEBUFFERLESS pXCArgs = (pstXC_CHECK_REQUEST_FRAMEBUFFERLESS) pArgs;
3118 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsCurrentRequest_FrameBufferLessMode(pInstance);
3119
3120
3121 u32Return = UTOPIA_STATUS_SUCCESS;
3122 break;
3123 }
3124
3125
3126 case E_XC_CMD_GET_3D_HWVERSION:
3127 {
3128
3129
3130 pstXC_GET_3D_HWVERSION pXCArgs = (pstXC_GET_3D_HWVERSION) pArgs;
3131 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_Get_3D_HW_Version(pInstance);
3132
3133
3134 u32Return = UTOPIA_STATUS_SUCCESS;
3135 break;
3136 }
3137
3138
3139 case E_XC_CMD_CHECK_3D_SUPPORT_HW2DTO3D:
3140 {
3141
3142
3143 pstXC_CHECK_3D_SUPPORT_HW2DTO3D pXCArgs = (pstXC_CHECK_3D_SUPPORT_HW2DTO3D) pArgs;
3144 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_3D_IsSupportedHW2DTo3D(pInstance);
3145
3146
3147 u32Return = UTOPIA_STATUS_SUCCESS;
3148 break;
3149 }
3150
3151
3152 case E_XC_CMD_SET_3D_MODE:
3153 {
3154
3155
3156 pstXC_SET_3D_MODE pXCArgs = (pstXC_SET_3D_MODE) pArgs;
3157 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3158 USE_OTHER_SC_AS_SUB_WINDOW();
3159 #endif
3160 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_Mode(pInstance,
3161 pXCArgs->e3dInputMode,
3162 pXCArgs->e3dOutputMode,
3163 pXCArgs->e3dPanelType,
3164 pXCArgs->eWindow);
3165
3166
3167 u32Return = UTOPIA_STATUS_SUCCESS;
3168 break;
3169 }
3170
3171
3172 case E_XC_CMD_SET_3D_MAINWIN_FIRST:
3173 {
3174
3175
3176 pstXC_SET_3D_MAINWIN_FIRST pXCArgs = (pstXC_SET_3D_MAINWIN_FIRST) pArgs;
3177 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_MainWin_FirstMode(pInstance, pXCArgs->bMainFirst);
3178
3179
3180 u32Return = UTOPIA_STATUS_SUCCESS;
3181 break;
3182 }
3183
3184
3185 case E_XC_CMD_SET_3D_LR_EXCHANGE:
3186 {
3187
3188
3189 pstXC_SET_3D_LR_EXCHANGE pXCArgs = (pstXC_SET_3D_LR_EXCHANGE) pArgs;
3190 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3191 USE_OTHER_SC_AS_SUB_WINDOW();
3192 #endif
3193 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_LR_Frame_Exchg(pInstance, pXCArgs->eWindow);
3194
3195
3196 u32Return = UTOPIA_STATUS_SUCCESS;
3197 break;
3198 }
3199
3200
3201 case E_XC_CMD_CHECK_3D_LR_EXCHANGED:
3202 {
3203
3204
3205 pstXC_CHECK_3D_LR_EXCHANGED pXCArgs = (pstXC_CHECK_3D_LR_EXCHANGED) pArgs;
3206 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3207 USE_OTHER_SC_AS_SUB_WINDOW();
3208 #endif
3209 pXCArgs->bReturnValue = psXCInstPri->fpXC_3D_Is_LR_Frame_Exchged(pInstance, pXCArgs->eWindow);
3210
3211
3212 u32Return = UTOPIA_STATUS_SUCCESS;
3213 break;
3214 }
3215
3216
3217 case E_XC_CMD_GET_3D_INPUT_MODE:
3218 {
3219
3220
3221 pstXC_GET_3D_INPUT_MODE pXCArgs = (pstXC_GET_3D_INPUT_MODE) pArgs;
3222 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3223 USE_OTHER_SC_AS_SUB_WINDOW();
3224 #endif
3225 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_3D_Input_Mode(pInstance, pXCArgs->eWindow);
3226
3227
3228 u32Return = UTOPIA_STATUS_SUCCESS;
3229 break;
3230 }
3231
3232
3233 case E_XC_CMD_GET_3D_OUTPUT_MODE:
3234 {
3235
3236
3237 pstXC_GET_3D_OUTPUT_MODE pXCArgs = (pstXC_GET_3D_OUTPUT_MODE) pArgs;
3238 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_3D_Output_Mode(pInstance);
3239
3240
3241 u32Return = UTOPIA_STATUS_SUCCESS;
3242 break;
3243 }
3244
3245
3246 #ifdef UFO_XC_GET_3D_FORMAT
3247 case E_XC_CMD_GET3DFORMAT:
3248 {
3249
3250
3251 pstXC_GET3DFORMAT pXCArgs = (pstXC_GET3DFORMAT) pArgs;
3252 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get3DFormat(pInstance, pXCArgs->e3DAttrType, pXCArgs->para, pXCArgs->p3DFormat);
3253
3254
3255 u32Return = UTOPIA_STATUS_SUCCESS;
3256 break;
3257 }
3258 #endif
3259
3260
3261 case E_XC_CMD_GET_3D_PANELTYPE:
3262 {
3263
3264
3265 pstXC_GET_3D_PANELTYPE pXCArgs = (pstXC_GET_3D_PANELTYPE) pArgs;
3266 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_3D_Panel_Type(pInstance);
3267
3268
3269 u32Return = UTOPIA_STATUS_SUCCESS;
3270 break;
3271 }
3272
3273
3274 case E_XC_CMD_GET_3D_MAINWIN_FIRST:
3275 {
3276
3277
3278 pstXC_GET_3D_MAINWIN_FIRST pXCArgs = (pstXC_GET_3D_MAINWIN_FIRST) pArgs;
3279 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_3D_MainWin_First(pInstance);
3280
3281
3282 u32Return = UTOPIA_STATUS_SUCCESS;
3283 break;
3284 }
3285
3286
3287 case E_XC_CMD_CHECK_3D_MAINSUB_IPSYNC:
3288 {
3289
3290
3291 pstXC_CHECK_3D_MAINSUB_IPSYNC pXCArgs = (pstXC_CHECK_3D_MAINSUB_IPSYNC) pArgs;
3292 pXCArgs->bReturnValue = psXCInstPri->fpXC_3DMainSub_IPSync(pInstance);
3293
3294
3295 u32Return = UTOPIA_STATUS_SUCCESS;
3296 break;
3297 }
3298
3299
3300 case E_XC_CMD_SET_3D_VERTICALVIDEO_OFFSET:
3301 {
3302
3303
3304 pstXC_SET_3D_VERTICALVIDEO_OFFSET pXCArgs = (pstXC_SET_3D_VERTICALVIDEO_OFFSET) pArgs;
3305 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_VerVideoOffset(pInstance, pXCArgs->u163DVerVideoOffset);
3306
3307
3308 u32Return = UTOPIA_STATUS_SUCCESS;
3309 break;
3310 }
3311
3312
3313 case E_XC_CMD_GET_3D_VERTICALVIDEO_OFFSET:
3314 {
3315
3316
3317 pstXC_GET_3D_VERTICALVIDEO_OFFSET pXCArgs = (pstXC_GET_3D_VERTICALVIDEO_OFFSET) pArgs;
3318 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_Get_3D_VerVideoOffset(pInstance);
3319
3320
3321 u32Return = UTOPIA_STATUS_SUCCESS;
3322 break;
3323 }
3324
3325
3326 case E_XC_CMD_CHECK_3D_FORMAT_SUPPORTED:
3327 {
3328
3329
3330 pstXC_CHECK_3D_FORMAT_SUPPORTED pXCArgs = (pstXC_CHECK_3D_FORMAT_SUPPORTED) pArgs;
3331 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is3DFormatSupported(pInstance, pXCArgs->e3dInputMode, pXCArgs->e3dOutputMode);
3332
3333
3334 u32Return = UTOPIA_STATUS_SUCCESS;
3335 break;
3336 }
3337
3338
3339 case E_XC_CMD_SET_3D_HORIZONTAL_SHIFT:
3340 {
3341
3342
3343 pstXC_SET_3D_HORIZONTAL_SHIFT pXCArgs = (pstXC_SET_3D_HORIZONTAL_SHIFT) pArgs;
3344 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_HShift(pInstance, pXCArgs->u16HShift);
3345
3346
3347 u32Return = UTOPIA_STATUS_SUCCESS;
3348 break;
3349 }
3350
3351
3352 case E_XC_CMD_SET_3D_LR_SBS2LINE:
3353 {
3354
3355
3356 pstXC_SET_3D_LR_SBS2LINE pXCArgs = (pstXC_SET_3D_LR_SBS2LINE) pArgs;
3357 pXCArgs->bReturnValue = psXCInstPri->fpXC_Enable_3D_LR_Sbs2Line(pInstance, pXCArgs->bEnable);
3358
3359
3360 u32Return = UTOPIA_STATUS_SUCCESS;
3361 break;
3362 }
3363
3364
3365 case E_XC_CMD_GET_3D_HORIZONTAL_SHIFT:
3366 {
3367
3368
3369 pstXC_GET_3D_HORIZONTAL_SHIFT pXCArgs = (pstXC_GET_3D_HORIZONTAL_SHIFT) pArgs;
3370 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_Get_3D_HShift(pInstance);
3371
3372
3373 u32Return = UTOPIA_STATUS_SUCCESS;
3374 break;
3375 }
3376
3377
3378 case E_XC_CMD_SET_3D_HW2DTO3D_BUFFER:
3379 {
3380
3381
3382 pstXC_SET_3D_HW2DTO3D_BUFFER pXCArgs = (pstXC_SET_3D_HW2DTO3D_BUFFER) pArgs;
3383 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_HW2DTo3D_Buffer(pInstance, pXCArgs->u32HW2DTO3D_DD_Buf, pXCArgs->u32HW2DTO3D_DR_Buf);
3384
3385
3386 u32Return = UTOPIA_STATUS_SUCCESS;
3387 break;
3388 }
3389
3390
3391 case E_XC_CMD_SET_3D_HW2DTO3D_PARAMETERS:
3392 {
3393
3394
3395 pstXC_SET_3D_HW2DTO3D_PARAMETERS pXCArgs = (pstXC_SET_3D_HW2DTO3D_PARAMETERS) pArgs;
3396 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_HW2DTo3D_Parameters(pInstance, pXCArgs->st3DHw2DTo3DPara);
3397
3398
3399 u32Return = UTOPIA_STATUS_SUCCESS;
3400 break;
3401 }
3402
3403
3404 case E_XC_CMD_GET_3D_HW2DTO3D_PARAMETERS:
3405 {
3406
3407
3408 pstXC_GET_3D_HW2DTO3D_PARAMETERS pXCArgs = (pstXC_GET_3D_HW2DTO3D_PARAMETERS) pArgs;
3409 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_3D_HW2DTo3D_Parameters(pInstance, pXCArgs->pst3DHw2DTo3DPara);
3410
3411
3412 u32Return = UTOPIA_STATUS_SUCCESS;
3413 break;
3414 }
3415
3416
3417 case E_XC_CMD_SET_3D_DETECT_3DFORMAT_PARAMETERS:
3418 {
3419
3420
3421 pstXC_SET_3D_DETECT_3DFORMAT_PARAMETERS pXCArgs = (pstXC_SET_3D_DETECT_3DFORMAT_PARAMETERS) pArgs;
3422 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_Detect3DFormat_Parameters(pInstance, pXCArgs->pstDetect3DFormatPara);
3423
3424
3425 u32Return = UTOPIA_STATUS_SUCCESS;
3426 break;
3427 }
3428
3429
3430 case E_XC_CMD_GET_3D_DETECT_3DFORMAT_PARAMETERS:
3431 {
3432
3433
3434 pstXC_GET_3D_DETECT_3DFORMAT_PARAMETERS pXCArgs = (pstXC_GET_3D_DETECT_3DFORMAT_PARAMETERS) pArgs;
3435 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_3D_Detect3DFormat_Parameters(pInstance, pXCArgs->pstDetect3DFormatPara);
3436
3437
3438 u32Return = UTOPIA_STATUS_SUCCESS;
3439 break;
3440 }
3441
3442
3443 case E_XC_CMD_GET_3D_FORMAT_DETECTED_BY_CONTENT:
3444 {
3445
3446
3447 pstXC_GET_3D_FORMAT_DETECTED_BY_CONTENT pXCArgs = (pstXC_GET_3D_FORMAT_DETECTED_BY_CONTENT) pArgs;
3448 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3449 USE_OTHER_SC_AS_SUB_WINDOW();
3450 #endif
3451 pXCArgs->eReturnValue = psXCInstPri->fpXC_Detect3DFormatByContent(pInstance, pXCArgs->eWindow);
3452
3453
3454 u32Return = UTOPIA_STATUS_SUCCESS;
3455 break;
3456 }
3457
3458
3459 case E_XC_CMD_SET_NINELATTICE:
3460 {
3461
3462
3463 pstXC_SET_NINELATTICE pXCArgs = (pstXC_SET_NINELATTICE) pArgs;
3464 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3465 USE_OTHER_SC_AS_SUB_WINDOW();
3466 #endif
3467 pXCArgs->bReturnValue = psXCInstPri->fpXC_DetectNL(pInstance, pXCArgs->eWindow, pXCArgs->pstDetectNLatticePara);
3468
3469
3470 u32Return = UTOPIA_STATUS_SUCCESS;
3471 break;
3472 }
3473
3474
3475 case E_XC_CMD_SET_3D_POST_PQSETTING:
3476 {
3477
3478
3479 pstXC_SET_3D_POST_PQSETTING pXCArgs = (pstXC_SET_3D_POST_PQSETTING) pArgs;
3480 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3481 USE_OTHER_SC_AS_SUB_WINDOW();
3482 #endif
3483 pXCArgs->bReturnValue = psXCInstPri->fpXC_3D_PostPQSetting(pInstance, pXCArgs->eWindow);
3484
3485
3486 u32Return = UTOPIA_STATUS_SUCCESS;
3487 break;
3488 }
3489
3490
3491 case E_XC_CMD_SET_3D_FRAMEPACKING_INFO:
3492 {
3493
3494
3495 pstXC_SET_3D_FRAMEPACKING_INFO pXCArgs = (pstXC_SET_3D_FRAMEPACKING_INFO) pArgs;
3496 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_FPInfo(pInstance, pXCArgs->pstFPInfoPara);
3497
3498
3499 u32Return = UTOPIA_STATUS_SUCCESS;
3500 break;
3501 }
3502
3503
3504 case E_XC_CMD_SET_3D_AUTODETECT:
3505 {
3506
3507
3508 pstXC_SET_3D_AUTODETECT pXCArgs = (pstXC_SET_3D_AUTODETECT) pArgs;
3509 pXCArgs->bReturnValue = psXCInstPri->fpXC_EnableAutoDetect3D(pInstance, pXCArgs->bEnable, pXCArgs->enDetectMethod);
3510
3511
3512 u32Return = UTOPIA_STATUS_SUCCESS;
3513 break;
3514 }
3515
3516
3517 case E_XC_CMD_GET_3D_AUTODETECT_3DFLAG:
3518 {
3519
3520
3521 pstXC_GET_3D_AUTODETECT_3DFLAG pXCArgs = (pstXC_GET_3D_AUTODETECT_3DFLAG) pArgs;
3522 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetAutoDetect3DFlag(pInstance, pXCArgs->penDetectMethod, pXCArgs->pbEnable);
3523
3524
3525 u32Return = UTOPIA_STATUS_SUCCESS;
3526 break;
3527 }
3528
3529
3530 case E_XC_CMD_SET_3D_SUBWINCLOCK:
3531 {
3532
3533
3534 pstXC_SET_3D_SUBWINCLOCK pXCArgs = (pstXC_SET_3D_SUBWINCLOCK) pArgs;
3535 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_3D_SubWinClk(pInstance);
3536
3537
3538 u32Return = UTOPIA_STATUS_SUCCESS;
3539 break;
3540 }
3541
3542
3543 case E_XC_CMD_CHECK_3D_LR_SBS2LINE:
3544 {
3545
3546
3547 pstXC_CHECK_3D_LR_SBS2LINE pXCArgs = (pstXC_CHECK_3D_LR_SBS2LINE) pArgs;
3548 pXCArgs->bReturnValue = psXCInstPri->fpXC_3D_Is_LR_Sbs2Line(pInstance);
3549
3550
3551 u32Return = UTOPIA_STATUS_SUCCESS;
3552 break;
3553 }
3554
3555
3556 case E_XC_CMD_CHECK_3D_SKIP_DEFAULT_LR_FLAG:
3557 {
3558
3559
3560 pstXC_CHECK_3D_SKIP_DEFAULT_LR_FLAG pXCArgs = (pstXC_CHECK_3D_SKIP_DEFAULT_LR_FLAG) pArgs;
3561 pXCArgs->bReturnValue = psXCInstPri->fpSC_3D_Is_Skip_Default_LR_Flag(pInstance);
3562
3563
3564 u32Return = UTOPIA_STATUS_SUCCESS;
3565 break;
3566 }
3567
3568
3569 case E_XC_CMD_SET_3D_SKIP_DEFAULT_LR_FLAG:
3570 {
3571
3572
3573 pstXC_SET_3D_SKIP_DEFAULT_LR_FLAG pXCArgs = (pstXC_SET_3D_SKIP_DEFAULT_LR_FLAG) pArgs;
3574 pXCArgs->bReturnValue = psXCInstPri->fpXC_3D_Enable_Skip_Default_LR_Flag(pInstance, pXCArgs->bEnable);
3575
3576
3577 u32Return = UTOPIA_STATUS_SUCCESS;
3578 break;
3579 }
3580
3581
3582 case E_XC_CMD_SET_MUX_INIT:
3583 {
3584
3585
3586 pstXC_SET_MUX_INIT pXCArgs = (pstXC_SET_MUX_INIT) pArgs;
3587 psXCInstPri->fpXC_Mux_Init(pInstance, pXCArgs->input_source_to_input_port);
3588 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3589 CHECK_DEVICE1_INSTANCE();
3590 psXCInstPri->fpXC_Mux_Init(g_pDevice1Instance, pXCArgs->input_source_to_input_port);
3591 #endif
3592 u32Return = UTOPIA_STATUS_SUCCESS;
3593 break;
3594 }
3595
3596
3597 case E_XC_CMD_SET_MUX_SOURCE_MONITOR:
3598 {
3599
3600
3601 pstXC_SET_MUX_SOURCE_MONITOR pXCArgs = (pstXC_SET_MUX_SOURCE_MONITOR) pArgs;
3602 psXCInstPri->fpXC_Mux_SourceMonitor(pInstance, pXCArgs->bRealTimeMonitorOnly);
3603 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3604 CHECK_DEVICE1_INSTANCE();
3605 psXCInstPri->fpXC_Mux_SourceMonitor(g_pDevice1Instance, pXCArgs->bRealTimeMonitorOnly);
3606 #endif
3607 u32Return = UTOPIA_STATUS_SUCCESS;
3608 break;
3609 }
3610
3611
3612 case E_XC_CMD_SET_MUX_CREATE_PATH:
3613 {
3614
3615
3616 pstXC_SET_MUX_CREATE_PATH pXCArgs = (pstXC_SET_MUX_CREATE_PATH) pArgs;
3617 pXCArgs->s16ReturnValue = psXCInstPri->fpXC_Mux_CreatePath(pInstance, pXCArgs->Path_Info, pXCArgs->u32InitDataLen);
3618 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3619 CHECK_DEVICE1_INSTANCE();
3620 psXCInstPri->fpXC_Mux_CreatePath(g_pDevice1Instance, pXCArgs->Path_Info, pXCArgs->u32InitDataLen);
3621 #endif
3622 u32Return = UTOPIA_STATUS_SUCCESS;
3623 break;
3624 }
3625
3626
3627 case E_XC_CMD_SET_MUX_DELETE_PATH:
3628 {
3629
3630 pstXC_SET_MUX_DELETE_PATH pXCArgs = (pstXC_SET_MUX_DELETE_PATH) pArgs;
3631 pXCArgs->s16ReturnValue = psXCInstPri->fpXC_Mux_DeletePath(pInstance, pXCArgs->src, pXCArgs->dest);
3632 u32Return = UTOPIA_STATUS_SUCCESS;
3633 break;
3634 }
3635
3636
3637 case E_XC_CMD_SET_MUX_ENABLE_PATH:
3638 {
3639
3640
3641 pstXC_SET_MUX_ENABLE_PATH pXCArgs = (pstXC_SET_MUX_ENABLE_PATH) pArgs;
3642 pXCArgs->s16ReturnValue = psXCInstPri->fpXC_Mux_EnablePath(pInstance, pXCArgs->PathId);
3643 u32Return = UTOPIA_STATUS_SUCCESS;
3644 break;
3645 }
3646
3647
3648 case E_XC_CMD_SET_MUX_TRIGGER_PATH_SYNC_EVENT:
3649 {
3650
3651
3652 pstXC_SET_MUX_TRIGGER_PATH_SYNC_EVENT pXCArgs = (pstXC_SET_MUX_TRIGGER_PATH_SYNC_EVENT) pArgs;
3653 psXCInstPri->fpXC_Mux_TriggerPathSyncEvent(pInstance, pXCArgs->src, pXCArgs->para);
3654 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3655 CHECK_DEVICE1_INSTANCE();
3656 psXCInstPri->fpXC_Mux_TriggerPathSyncEvent(g_pDevice1Instance, pXCArgs->src, pXCArgs->para);
3657 #endif
3658 u32Return = UTOPIA_STATUS_SUCCESS;
3659 break;
3660 }
3661
3662
3663 case E_XC_CMD_SET_MUX_TRIGGER_DEST_ONOFF_EVENT:
3664 {
3665
3666
3667 pstXC_SET_MUX_TRIGGER_DEST_ONOFF_EVENT pXCArgs = (pstXC_SET_MUX_TRIGGER_DEST_ONOFF_EVENT) pArgs;
3668 psXCInstPri->fpXC_Mux_TriggerDestOnOffEvent(pInstance, pXCArgs->src, pXCArgs->para);
3669 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3670 CHECK_DEVICE1_INSTANCE();
3671 psXCInstPri->fpXC_Mux_TriggerDestOnOffEvent(g_pDevice1Instance, pXCArgs->src, pXCArgs->para);
3672 #endif
3673 u32Return = UTOPIA_STATUS_SUCCESS;
3674 break;
3675 }
3676
3677
3678 case E_XC_CMD_SET_MUX_ONOFF_PERIODIC_HANDLER:
3679 {
3680
3681
3682 pstXC_SET_MUX_ONOFF_PERIODIC_HANDLER pXCArgs = (pstXC_SET_MUX_ONOFF_PERIODIC_HANDLER) pArgs;
3683 pXCArgs->s16ReturnValue = psXCInstPri->fpXC_Mux_OnOffPeriodicHandler(pInstance, pXCArgs->src, pXCArgs->bEnable);
3684 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3685 CHECK_DEVICE1_INSTANCE();
3686 psXCInstPri->fpXC_Mux_OnOffPeriodicHandler(g_pDevice1Instance, pXCArgs->src, pXCArgs->bEnable);
3687 #endif
3688 u32Return = UTOPIA_STATUS_SUCCESS;
3689 break;
3690 }
3691
3692
3693 case E_XC_CMD_GET_MUX_PATHINFO:
3694 {
3695
3696
3697 pstXC_GET_MUX_PATHINFO pXCArgs = (pstXC_GET_MUX_PATHINFO) pArgs;
3698 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_Mux_GetPathInfo(pInstance, pXCArgs->Paths);
3699 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3700 CHECK_DEVICE1_INSTANCE();
3701 psXCInstPri->fpXC_Mux_GetPathInfo(g_pDevice1Instance, pXCArgs->Paths);
3702 #endif
3703 u32Return = UTOPIA_STATUS_SUCCESS;
3704 break;
3705 }
3706
3707
3708 case E_XC_CMD_SET_MUX_SUPPORT_MHL_PATHINFO:
3709 {
3710
3711
3712 pstXC_SET_MUX_SUPPORT_MHL_PATHINFO pXCArgs = (pstXC_SET_MUX_SUPPORT_MHL_PATHINFO) pArgs;
3713 pXCArgs->eReturnValue = psXCInstPri->fpXC_Mux_SetSupportMhlPathInfo(pInstance, pXCArgs->u8MhlSupportInfo);
3714 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3715 CHECK_DEVICE1_INSTANCE();
3716 psXCInstPri->fpXC_Mux_SetSupportMhlPathInfo(g_pDevice1Instance, pXCArgs->u8MhlSupportInfo);
3717 #endif
3718
3719 u32Return = UTOPIA_STATUS_SUCCESS;
3720 break;
3721 }
3722
3723
3724 case E_XC_CMD_SET_MUX_MHL_HOTPLUG_INVERSE_INFO:
3725 {
3726
3727
3728 pstXC_SET_MUX_MHL_HOTPLUG_INVERSE_INFO pXCArgs = (pstXC_SET_MUX_MHL_HOTPLUG_INVERSE_INFO) pArgs;
3729 pXCArgs->eReturnValue = psXCInstPri->fpXC_Mux_SetMhlHotPlugInverseInfo(pInstance, pXCArgs->bIsMhlHotPlugInverse);
3730 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3731 CHECK_DEVICE1_INSTANCE();
3732 psXCInstPri->fpXC_Mux_SetMhlHotPlugInverseInfo(g_pDevice1Instance, pXCArgs->bIsMhlHotPlugInverse);
3733 #endif
3734 u32Return = UTOPIA_STATUS_SUCCESS;
3735 break;
3736 }
3737
3738
3739 case E_XC_CMD_GET_MUX_HDMIPORT:
3740 {
3741
3742
3743 pstXC_GET_MUX_HDMIPORT pXCArgs = (pstXC_GET_MUX_HDMIPORT) pArgs;
3744 pXCArgs->eReturnValue = psXCInstPri->fpXC_Mux_GetHDMIPort(pInstance, pXCArgs->src);
3745 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3746 CHECK_DEVICE1_INSTANCE();
3747 psXCInstPri->fpXC_Mux_GetHDMIPort(g_pDevice1Instance, pXCArgs->src);
3748 #endif
3749 u32Return = UTOPIA_STATUS_SUCCESS;
3750 break;
3751 }
3752
3753 case E_XC_CMD_GET_MUX_MAPPINGTAB:
3754 {
3755 pstXC_GET_MUX_MAPPINGTAB pXCArgs = (pstXC_GET_MUX_MAPPINGTAB) pArgs;
3756 psXCInstPri->fpXC_Mux_GetMappingTab(pInstance, pXCArgs->mapping_tab,pXCArgs->length);
3757 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3758 CHECK_DEVICE1_INSTANCE();
3759 psXCInstPri->fpXC_Mux_GetMappingTab(g_pDevice1Instance, pXCArgs->mapping_tab,pXCArgs->length);
3760 #endif
3761 u32Return = UTOPIA_STATUS_SUCCESS;
3762 break;
3763 }
3764
3765 case E_XC_CMD_GET_MUX_INPUTSOURCE2VDYMUXPORT:
3766 {
3767
3768
3769 pstXC_GET_MUX_INPUTSOURCE2VDYMUXPORT pXCArgs = (pstXC_GET_MUX_INPUTSOURCE2VDYMUXPORT) pArgs;
3770 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_MUX_MApinputSourceToVDYMuxPORT(pInstance, pXCArgs->u8InputSourceType);
3771
3772
3773 u32Return = UTOPIA_STATUS_SUCCESS;
3774 break;
3775 }
3776
3777
3778 case E_XC_CMD_SET_NR:
3779 {
3780
3781
3782 pstXC_SET_NR pXCArgs = (pstXC_SET_NR) pArgs;
3783 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3784 USE_OTHER_SC_AS_SUB_WINDOW();
3785 #endif
3786 psXCInstPri->fpXC_Set_NR(pInstance, pXCArgs->bEn, pXCArgs->eWindow);
3787
3788
3789 u32Return = UTOPIA_STATUS_SUCCESS;
3790 break;
3791 }
3792
3793
3794 case E_XC_CMD_SET_FILM_MODE_PATCH:
3795 {
3796
3797
3798 psXCInstPri->fpXC_FilmMode_P(pInstance);
3799
3800
3801 u32Return = UTOPIA_STATUS_SUCCESS;
3802 break;
3803 }
3804
3805
3806 case E_XC_CMD_CHECK_UC_ENABLED:
3807 {
3808
3809
3810 pstXC_CHECK_UC_ENABLED pXCArgs = (pstXC_CHECK_UC_ENABLED) pArgs;
3811 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3812 USE_OTHER_SC_AS_SUB_WINDOW();
3813 #endif
3814 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetUCEnabled(pInstance, pXCArgs->eWindow);
3815
3816
3817 u32Return = UTOPIA_STATUS_SUCCESS;
3818 break;
3819 }
3820
3821
3822 case E_XC_CMD_SET_GENERATE_SPECIFIC_TIMING:
3823 {
3824
3825
3826 pstXC_SET_GENERATE_SPECIFIC_TIMING pXCArgs = (pstXC_SET_GENERATE_SPECIFIC_TIMING) pArgs;
3827 psXCInstPri->fpXC_GenSpecificTiming(pInstance, pXCArgs->timingtype);
3828
3829
3830 u32Return = UTOPIA_STATUS_SUCCESS;
3831 break;
3832 }
3833
3834
3835 case E_XC_CMD_GET_DE_BYPASS_MODE:
3836 {
3837
3838
3839 pstXC_GET_DE_BYPASS_MODE pXCArgs = (pstXC_GET_DE_BYPASS_MODE) pArgs;
3840 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3841 USE_OTHER_SC_AS_SUB_WINDOW();
3842 #endif
3843 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetDEBypassMode(pInstance, pXCArgs->eWindow);
3844
3845
3846 u32Return = UTOPIA_STATUS_SUCCESS;
3847 break;
3848 }
3849
3850
3851 case E_XC_CMD_GET_DE_WINDOW:
3852 {
3853
3854
3855 pstXC_GET_DE_WINDOW pXCArgs = (pstXC_GET_DE_WINDOW) pArgs;
3856 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3857 USE_OTHER_SC_AS_SUB_WINDOW();
3858 #endif
3859 psXCInstPri->fpXC_GetDEWindow(pInstance, pXCArgs->psWin, pXCArgs->eWindow);
3860
3861
3862 u32Return = UTOPIA_STATUS_SUCCESS;
3863 break;
3864 }
3865
3866
3867 case E_XC_CMD_GET_DE_WIN_WIDTH_HEIGHT_IN_DE_BYPASS_MODE:
3868 {
3869
3870
3871 pstXC_GET_DE_WIN_WIDTH_HEIGHT_IN_DE_BYPASS_MODE pXCArgs = (pstXC_GET_DE_WIN_WIDTH_HEIGHT_IN_DE_BYPASS_MODE) pArgs;
3872 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3873 USE_OTHER_SC_AS_SUB_WINDOW();
3874 #endif
3875 psXCInstPri->fpXC_GetDEWidthHeightInDEByPassMode(pInstance, pXCArgs->pu16Width, pXCArgs->pu16Height, pXCArgs->eWindow);
3876
3877
3878 u32Return = UTOPIA_STATUS_SUCCESS;
3879 break;
3880 }
3881
3882
3883 case E_XC_CMD_GET_CAPTURE_WINDOW:
3884 {
3885
3886
3887 pstXC_GET_CAPTURE_WINDOW pXCArgs = (pstXC_GET_CAPTURE_WINDOW) pArgs;
3888 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3889 USE_OTHER_SC_AS_SUB_WINDOW();
3890 #endif
3891 psXCInstPri->fpXC_GetCaptureWindow(pInstance, pXCArgs->capture_win, pXCArgs->eWindow);
3892
3893
3894 u32Return = UTOPIA_STATUS_SUCCESS;
3895 break;
3896 }
3897
3898
3899 case E_XC_CMD_SET_CAPTURE_WINDOW_VSTART:
3900 {
3901
3902
3903 pstXC_SET_CAPTURE_WINDOW_VSTART pXCArgs = (pstXC_SET_CAPTURE_WINDOW_VSTART) pArgs;
3904 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3905 USE_OTHER_SC_AS_SUB_WINDOW();
3906 #endif
3907 psXCInstPri->fpXC_SetCaptureWindowVstart(pInstance, pXCArgs->u16Vstart, pXCArgs->eWindow);
3908
3909
3910 u32Return = UTOPIA_STATUS_SUCCESS;
3911 break;
3912 }
3913
3914
3915 case E_XC_CMD_SET_CAPTURE_WINDOW_HSTART:
3916 {
3917
3918
3919 pstXC_SET_CAPTURE_WINDOW_HSTART pXCArgs = (pstXC_SET_CAPTURE_WINDOW_HSTART) pArgs;
3920 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3921 USE_OTHER_SC_AS_SUB_WINDOW();
3922 #endif
3923 psXCInstPri->fpXC_SetCaptureWindowHstart(pInstance, pXCArgs->u16Hstart, pXCArgs->eWindow);
3924
3925
3926 u32Return = UTOPIA_STATUS_SUCCESS;
3927 break;
3928 }
3929
3930
3931 case E_XC_CMD_SET_CAPTURE_WINDOW_VSIZE:
3932 {
3933
3934
3935 pstXC_SET_CAPTURE_WINDOW_VSIZE pXCArgs = (pstXC_SET_CAPTURE_WINDOW_VSIZE) pArgs;
3936 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3937 USE_OTHER_SC_AS_SUB_WINDOW();
3938 #endif
3939 psXCInstPri->fpXC_SetCaptureWindowVsize(pInstance, pXCArgs->u16Vsize, pXCArgs->eWindow);
3940
3941
3942 u32Return = UTOPIA_STATUS_SUCCESS;
3943 break;
3944 }
3945
3946
3947 case E_XC_CMD_SET_CAPTURE_WINDOW_HSIZE:
3948 {
3949
3950
3951 pstXC_SET_CAPTURE_WINDOW_HSIZE pXCArgs = (pstXC_SET_CAPTURE_WINDOW_HSIZE) pArgs;
3952 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3953 USE_OTHER_SC_AS_SUB_WINDOW();
3954 #endif
3955 psXCInstPri->fpXC_SetCaptureWindowHsize(pInstance, pXCArgs->u16Hsize, pXCArgs->eWindow);
3956
3957
3958 u32Return = UTOPIA_STATUS_SUCCESS;
3959 break;
3960 }
3961
3962
3963 case E_XC_CMD_SET_SOFTWARE_RESET:
3964 {
3965
3966
3967 pstXC_SET_SOFTWARE_RESET pXCArgs = (pstXC_SET_SOFTWARE_RESET) pArgs;
3968 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3969 USE_OTHER_SC_AS_SUB_WINDOW();
3970 #endif
3971 psXCInstPri->fpXC_SoftwareReset(pInstance, pXCArgs->u8Reset, pXCArgs->eWindow);
3972
3973
3974 u32Return = UTOPIA_STATUS_SUCCESS;
3975 break;
3976 }
3977
3978
3979 case E_XC_CMD_GET_HFREQX10:
3980 {
3981
3982
3983 pstXC_GET_HFREQX10 pXCArgs = (pstXC_GET_HFREQX10) pArgs;
3984 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_CalculateHFreqx10(pInstance, pXCArgs->u16HPeriod);
3985
3986
3987 u32Return = UTOPIA_STATUS_SUCCESS;
3988 break;
3989 }
3990
3991
3992 case E_XC_CMD_GET_HFREQX1K:
3993 {
3994
3995
3996 pstXC_GET_HFREQX1K pXCArgs = (pstXC_GET_HFREQX1K) pArgs;
3997 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_CalculateHFreqx1K(pInstance, pXCArgs->u16HPeriod);
3998
3999
4000 u32Return = UTOPIA_STATUS_SUCCESS;
4001 break;
4002 }
4003
4004
4005 case E_XC_CMD_GET_VFREQX10:
4006 {
4007
4008
4009 pstXC_GET_VFREQX10 pXCArgs = (pstXC_GET_VFREQX10) pArgs;
4010 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_CalculateVFreqx10(pInstance, pXCArgs->u16HFreq, pXCArgs->u16VTotal);
4011
4012
4013 u32Return = UTOPIA_STATUS_SUCCESS;
4014 break;
4015 }
4016
4017
4018 case E_XC_CMD_GET_VFREQX1K:
4019 {
4020
4021
4022 pstXC_GET_VFREQX1K pXCArgs = (pstXC_GET_VFREQX1K) pArgs;
4023 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_CalculateVFreqx1K(pInstance, pXCArgs->u32HFreqx1K, pXCArgs->u16VTotal);
4024
4025
4026 u32Return = UTOPIA_STATUS_SUCCESS;
4027 break;
4028 }
4029
4030
4031 case E_XC_CMD_GET_ACCURATE_VFREQX1k:
4032 {
4033
4034
4035 pstXC_GET_ACCURATE_VFREQX1k pXCArgs = (pstXC_GET_ACCURATE_VFREQX1k) pArgs;
4036 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4037 USE_OTHER_SC_AS_SUB_WINDOW();
4038 #endif
4039 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_GetAccurateVFreqx1K(pInstance, pXCArgs->eWindow);
4040
4041
4042 u32Return = UTOPIA_STATUS_SUCCESS;
4043 break;
4044 }
4045
4046
4047 case E_XC_CMD_SET_INTERRUPT_ATTACH:
4048 {
4049
4050
4051 pstXC_SET_INTERRUPT_ATTACH pXCArgs = (pstXC_SET_INTERRUPT_ATTACH) pArgs;
4052 pXCArgs->bReturnValue = psXCInstPri->fpXC_InterruptAttach(pInstance, pXCArgs->eIntNum, pXCArgs->pIntCb, pXCArgs->pParam);
4053
4054
4055 u32Return = UTOPIA_STATUS_SUCCESS;
4056 break;
4057 }
4058
4059
4060 case E_XC_CMD_SET_INTERRUPT_DEATTACH:
4061 {
4062
4063
4064 pstXC_SET_INTERRUPT_DEATTACH pXCArgs = (pstXC_SET_INTERRUPT_DEATTACH) pArgs;
4065 pXCArgs->bReturnValue = psXCInstPri->fpXC_InterruptDeAttach(pInstance, pXCArgs->eIntNum, pXCArgs->pIntCb, pXCArgs->pParam);
4066
4067
4068 u32Return = UTOPIA_STATUS_SUCCESS;
4069 break;
4070 }
4071
4072
4073 case E_XC_CMD_SET_DISABLE_INPUTSOURCE:
4074 {
4075
4076
4077 pstXC_SET_DISABLE_INPUTSOURCE pXCArgs = (pstXC_SET_DISABLE_INPUTSOURCE) pArgs;
4078 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4079 if(!MDrv_XC_GetMWEStatus(pInstance))
4080 {
4081 USE_OTHER_SC_AS_SUB_WINDOW();
4082 }
4083 #endif
4084 psXCInstPri->fpXC_DisableInputSource(pInstance, pXCArgs->bDisable, pXCArgs->eWindow);
4085
4086
4087 u32Return = UTOPIA_STATUS_SUCCESS;
4088 break;
4089 }
4090
4091
4092 case E_XC_CMD_CHECK_INPUTSOURCE_DISABLED:
4093 {
4094
4095
4096 pstXC_CHECK_INPUTSOURCE_DISABLED pXCArgs = (pstXC_CHECK_INPUTSOURCE_DISABLED) pArgs;
4097 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4098 USE_OTHER_SC_AS_SUB_WINDOW();
4099 #endif
4100 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsInputSourceDisabled(pInstance, pXCArgs->eWindow);
4101
4102
4103 u32Return = UTOPIA_STATUS_SUCCESS;
4104 break;
4105 }
4106
4107
4108 case E_XC_CMD_SET_CHANGE_PANELTYPE:
4109 {
4110
4111
4112 pstXC_SET_CHANGE_PANELTYPE pXCArgs = (pstXC_SET_CHANGE_PANELTYPE) pArgs;
4113 psXCInstPri->fpXC_ChangePanelType(pInstance, pXCArgs->pstPanelInfo);
4114
4115
4116 u32Return = UTOPIA_STATUS_SUCCESS;
4117 break;
4118 }
4119
4120
4121 case E_XC_CMD_GET_CURRENT_READBANK:
4122 {
4123
4124
4125 pstXC_GET_CURRENT_READBANK pXCArgs = (pstXC_GET_CURRENT_READBANK) pArgs;
4126 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4127 USE_OTHER_SC_AS_SUB_WINDOW();
4128 #endif
4129 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetCurrentReadBank(pInstance, pXCArgs->eWindow);
4130
4131
4132 u32Return = UTOPIA_STATUS_SUCCESS;
4133 break;
4134 }
4135
4136
4137 case E_XC_CMD_GET_CURRENT_WRITEBANK:
4138 {
4139
4140
4141 pstXC_GET_CURRENT_WRITEBANK pXCArgs = (pstXC_GET_CURRENT_WRITEBANK) pArgs;
4142 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4143 USE_OTHER_SC_AS_SUB_WINDOW();
4144 #endif
4145 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetCurrentWriteBank(pInstance, pXCArgs->eWindow);
4146
4147
4148 u32Return = UTOPIA_STATUS_SUCCESS;
4149 break;
4150 }
4151
4152
4153 case E_XC_CMD_SET_AUTO_PRESCALING:
4154 {
4155
4156
4157 pstXC_SET_AUTO_PRESCALING pXCArgs = (pstXC_SET_AUTO_PRESCALING) pArgs;
4158 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4159 USE_OTHER_SC_AS_SUB_WINDOW();
4160 #endif
4161 psXCInstPri->fpXC_SetAutoPreScaling(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
4162
4163
4164 u32Return = UTOPIA_STATUS_SUCCESS;
4165 break;
4166 }
4167
4168
4169 case E_XC_CMD_GET_VSYNC_WIDTH:
4170 {
4171
4172
4173 pstXC_GET_VSYNC_WIDTH pXCArgs = (pstXC_GET_VSYNC_WIDTH) pArgs;
4174 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4175 USE_OTHER_SC_AS_SUB_WINDOW();
4176 #endif
4177 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_GetVSyncWidth(pInstance, pXCArgs->eWindow);
4178
4179
4180 u32Return = UTOPIA_STATUS_SUCCESS;
4181 break;
4182 }
4183
4184
4185 case E_XC_CMD_SET_GOP_ENABLE:
4186 {
4187
4188
4189 pstXC_SET_GOP_ENABLE pXCArgs = (pstXC_SET_GOP_ENABLE) pArgs;
4190 pXCArgs->bReturnValue = psXCInstPri->fpXC_set_GOP_Enable(pInstance, pXCArgs->MaxGOP, pXCArgs->UseNum, pXCArgs->u8MuxNum, pXCArgs->bEnable);
4191
4192
4193 u32Return = UTOPIA_STATUS_SUCCESS;
4194 break;
4195 }
4196
4197
4198 case E_XC_CMD_SET_SELECT_IP_FOR_GOP:
4199 {
4200
4201
4202 pstXC_SET_SELECT_IP_FOR_GOP pXCArgs = (pstXC_SET_SELECT_IP_FOR_GOP) pArgs;
4203 psXCInstPri->fpXC_ip_sel_for_gop(pInstance, pXCArgs->u8MuxNum, pXCArgs->ipSelGop);
4204
4205
4206 u32Return = UTOPIA_STATUS_SUCCESS;
4207 break;
4208 }
4209
4210
4211 case E_XC_CMD_SET_VOP_NEW_BLENDING_LEVEL:
4212 {
4213
4214
4215 psXCInstPri->fpXC_SetVOPNBL(pInstance);
4216
4217
4218 u32Return = UTOPIA_STATUS_SUCCESS;
4219 break;
4220 }
4221
4222
4223 case E_XC_CMD_GET_DESTINATION_INFO:
4224 {
4225
4226
4227 pstXC_GET_DESTINATION_INFO pXCArgs = (pstXC_GET_DESTINATION_INFO) pArgs;
4228 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetDstInfo(pInstance, pXCArgs->pDstInfo, pXCArgs->u32SizeofDstInfo, pXCArgs->XCDstType);
4229
4230
4231 u32Return = UTOPIA_STATUS_SUCCESS;
4232 break;
4233 }
4234
4235
4236 case E_XC_CMD_SET_FDMASK_BYWIN:
4237 {
4238
4239
4240 pstXC_SET_FDMASK_BYWIN pXCArgs = (pstXC_SET_FDMASK_BYWIN) pArgs;
4241 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4242 USE_OTHER_SC_AS_SUB_WINDOW();
4243 #endif
4244 psXCInstPri->fpXC_Set_FD_Mask_ByWin(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
4245
4246
4247 u32Return = UTOPIA_STATUS_SUCCESS;
4248 break;
4249 }
4250
4251
4252 case E_XC_CMD_GET_FDMASK_BYWIN:
4253 {
4254
4255
4256 pstXC_GET_FDMASK_BYWIN pXCArgs = (pstXC_GET_FDMASK_BYWIN) pArgs;
4257 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4258 USE_OTHER_SC_AS_SUB_WINDOW();
4259 #endif
4260 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_FD_Mask_ByWin(pInstance, pXCArgs->eWindow);
4261
4262
4263 u32Return = UTOPIA_STATUS_SUCCESS;
4264 break;
4265 }
4266
4267
4268 case E_XC_CMD_SET_IP1_TESTPATTERN:
4269 {
4270
4271
4272 pstXC_SET_IP1_TESTPATTERN pXCArgs = (pstXC_SET_IP1_TESTPATTERN) pArgs;
4273 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4274 USE_OTHER_SC_AS_SUB_WINDOW();
4275 #endif
4276 psXCInstPri->fpXC_SetIP1TestPattern(pInstance, pXCArgs->u8Enable, pXCArgs->u6Pattern_type, pXCArgs->eWindow);
4277
4278
4279 u32Return = UTOPIA_STATUS_SUCCESS;
4280 break;
4281 }
4282 #ifdef UFO_XC_TEST_PATTERN
4283 case E_XC_CMD_SET_TESTPATTERN:
4284 {
4285
4286
4287 pstXC_SET_TESTPATTERN pXCArgs = (pstXC_SET_TESTPATTERN) pArgs;
4288 psXCInstPri->fpXC_GenerateTestPattern(pInstance, pXCArgs->ePatternMode,pXCArgs->para, pXCArgs->u16Length);
4289
4290
4291 u32Return = UTOPIA_STATUS_SUCCESS;
4292 break;
4293 }
4294 #endif
4295 case E_XC_CMD_SET_INIT_IP_FOR_INTERNAL_TIMING:
4296 {
4297
4298
4299 pstXC_SET_INIT_IP_FOR_INTERNAL_TIMING pXCArgs = (pstXC_SET_INIT_IP_FOR_INTERNAL_TIMING) pArgs;
4300 psXCInstPri->fpXC_InitIPForInternalTiming(pInstance, pXCArgs->timingtype);
4301
4302
4303 u32Return = UTOPIA_STATUS_SUCCESS;
4304 break;
4305 }
4306
4307
4308 case E_XC_CMD_SET_IPMUX:
4309 {
4310
4311
4312 pstXC_SET_IPMUX pXCArgs = (pstXC_SET_IPMUX) pArgs;
4313 psXCInstPri->fpXC_SetIPMux(pInstance, pXCArgs->u8Val);
4314
4315
4316 u32Return = UTOPIA_STATUS_SUCCESS;
4317 break;
4318 }
4319
4320
4321 case E_XC_CMD_CHECK_HSYNC_ACTIVE:
4322 {
4323
4324
4325 pstXC_CHECK_HSYNC_ACTIVE pXCArgs = (pstXC_CHECK_HSYNC_ACTIVE) pArgs;
4326 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4327 USE_OTHER_SC_AS_SUB_WINDOW();
4328 #endif
4329 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is_H_Sync_Active(pInstance, pXCArgs->eWindow);
4330
4331
4332 u32Return = UTOPIA_STATUS_SUCCESS;
4333 break;
4334 }
4335
4336
4337 case E_XC_CMD_CHECK_VSYNC_ACTIVE:
4338 {
4339
4340
4341 pstXC_CHECK_VSYNC_ACTIVE pXCArgs = (pstXC_CHECK_VSYNC_ACTIVE) pArgs;
4342 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4343 USE_OTHER_SC_AS_SUB_WINDOW();
4344 #endif
4345 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is_V_Sync_Active(pInstance, pXCArgs->eWindow);
4346
4347
4348 u32Return = UTOPIA_STATUS_SUCCESS;
4349 break;
4350 }
4351
4352
4353 case E_XC_CMD_GET_AUTO_POSITION_WINDOW:
4354 {
4355
4356
4357 pstXC_GET_AUTO_POSITION_WINDOW pXCArgs = (pstXC_GET_AUTO_POSITION_WINDOW) pArgs;
4358 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4359 USE_OTHER_SC_AS_SUB_WINDOW();
4360 #endif
4361 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetAutoPositionWindow(pInstance, pXCArgs->u8ValidData, pXCArgs->eWindow, pXCArgs->pstAutoPositionWindow);
4362
4363
4364 u32Return = UTOPIA_STATUS_SUCCESS;
4365 break;
4366 }
4367
4368
4369 case E_XC_CMD_SET_FRAMEBUFFER_ADDRESS:
4370 {
4371
4372
4373 pstXC_SET_FRAMEBUFFER_ADDRESS pXCArgs = (pstXC_SET_FRAMEBUFFER_ADDRESS) pArgs;
4374 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4375 USE_OTHER_SC_AS_SUB_WINDOW();
4376 #endif
4377 psXCInstPri->fpXC_SetFrameBufferAddress(pInstance, pXCArgs->u32FBAddress, pXCArgs->u32FBSize, pXCArgs->eWindow);
4378
4379
4380 u32Return = UTOPIA_STATUS_SUCCESS;
4381 break;
4382 }
4383
4384 case E_XC_CMD_SET_FRCM_FRAMEBUFFER_ADDRESS:
4385 {
4386
4387 pstXC_SET_FRAMEBUFFER_ADDRESS pXCArgs = (pstXC_SET_FRAMEBUFFER_ADDRESS) pArgs;
4388 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4389 USE_OTHER_SC_AS_SUB_WINDOW();
4390 #endif
4391 psXCInstPri->fpXC_SetFRCMFrameBufferAddress(pInstance, pXCArgs->u32FBAddress, pXCArgs->u32FBSize, pXCArgs->eWindow);
4392
4393
4394 u32Return = UTOPIA_STATUS_SUCCESS;
4395 break;
4396 }
4397 case E_XC_CMD_CHECK_FRAMEBUFFER_ENOUGH_FOR_CUSSCALING:
4398 {
4399
4400
4401 pstXC_CHECK_FRAMEBUFFER_ENOUGH_FOR_CUSSCALING pXCArgs = (pstXC_CHECK_FRAMEBUFFER_ENOUGH_FOR_CUSSCALING) pArgs;
4402 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4403 USE_OTHER_SC_AS_SUB_WINDOW();
4404 #endif
4405 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsFrameBufferEnoughForCusScaling(pInstance, pXCArgs->pstXC_SetWin_Info, pXCArgs->eWindow);
4406
4407
4408 u32Return = UTOPIA_STATUS_SUCCESS;
4409 break;
4410 }
4411
4412
4413 case E_XC_CMD_SET_SCALER_MEMORY_REQUEST:
4414 {
4415
4416
4417 pstXC_SET_SCALER_MEMORY_REQUEST pXCArgs = (pstXC_SET_SCALER_MEMORY_REQUEST) pArgs;
4418 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4419 USE_OTHER_SC_AS_SUB_WINDOW();
4420 #endif
4421 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetScalerMemoryRequest(pInstance, pXCArgs->bEnable, pXCArgs->eRequestType, pXCArgs->eWindow);
4422
4423
4424 u32Return = UTOPIA_STATUS_SUCCESS;
4425 break;
4426 }
4427
4428
4429 case E_XC_CMD_GET_PIXEL_DATA:
4430 {
4431
4432
4433 pstXC_GET_PIXEL_DATA pXCArgs = (pstXC_GET_PIXEL_DATA) pArgs;
4434 psXCInstPri->fpXC_Get_PixelData(pInstance, pXCArgs->u16CorX, pXCArgs->u16CorY, pXCArgs->pixel);
4435
4436
4437 u32Return = UTOPIA_STATUS_SUCCESS;
4438 break;
4439 }
4440
4441
4442 case E_XC_CMD_GET_AVAILABLE_SIZE:
4443 {
4444
4445
4446 pstXC_GET_AVAILABLE_SIZE pXCArgs = (pstXC_GET_AVAILABLE_SIZE) pArgs;
4447 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4448 USE_OTHER_SC_AS_SUB_WINDOW();
4449 #endif
4450 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_GetAvailableSize(pInstance, pXCArgs->eWindow, pXCArgs->u8FBNum, pXCArgs->u32InputSize);
4451
4452
4453 u32Return = UTOPIA_STATUS_SUCCESS;
4454 break;
4455 }
4456
4457
4458 case E_XC_CMD_SET_FRAME_COLOR:
4459 {
4460
4461
4462 pstXC_SET_FRAME_COLOR pXCArgs = (pstXC_SET_FRAME_COLOR) pArgs;
4463 psXCInstPri->fpXC_SetFrameColor(pInstance, pXCArgs->u32aRGB);
4464
4465
4466 u32Return = UTOPIA_STATUS_SUCCESS;
4467 break;
4468 }
4469
4470
4471 case E_XC_CMD_SET_DISPLAY_WINDOW_COLOR:
4472 {
4473
4474
4475 pstXC_SET_DISPLAY_WINDOW_COLOR pXCArgs = (pstXC_SET_DISPLAY_WINDOW_COLOR) pArgs;
4476 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4477 USE_OTHER_SC_AS_SUB_WINDOW();
4478 #endif
4479 psXCInstPri->fpXC_SetDispWindowColor(pInstance, pXCArgs->u8Color, pXCArgs->eWindow);
4480
4481
4482 u32Return = UTOPIA_STATUS_SUCCESS;
4483 break;
4484 }
4485
4486
4487 case E_XC_CMD_GET_SUPPORT_SOURCE_TO_VE:
4488 {
4489
4490
4491 pstXC_GET_SUPPORT_SOURCE_TO_VE pXCArgs = (pstXC_GET_SUPPORT_SOURCE_TO_VE) pArgs;
4492 pXCArgs->eReturnValue = psXCInstPri->fpXC_SupportSourceToVE(pInstance, pXCArgs->pOutputCapability);
4493
4494
4495 u32Return = UTOPIA_STATUS_SUCCESS;
4496 break;
4497 }
4498
4499
4500 case E_XC_CMD_SET_OUTPUT_CAPTURE:
4501 {
4502
4503
4504 pstXC_SET_OUTPUT_CAPTURE pXCArgs = (pstXC_SET_OUTPUT_CAPTURE) pArgs;
4505 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOutputCapture(pInstance, pXCArgs->bEnable, pXCArgs->eSourceToVE);
4506
4507
4508 u32Return = UTOPIA_STATUS_SUCCESS;
4509 break;
4510 }
4511
4512
4513 case E_XC_CMD_SET_GAMMA_ONOFF:
4514 {
4515
4516
4517 pstXC_SET_GAMMA_ONOFF pXCArgs = (pstXC_SET_GAMMA_ONOFF) pArgs;
4518 psXCInstPri->fpXC_SetGammaOnOff(pInstance, pXCArgs->bEnable);
4519 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4520 CHECK_DEVICE1_INSTANCE();
4521 psXCInstPri->fpXC_SetGammaOnOff(g_pDevice1Instance, pXCArgs->bEnable);
4522 #endif
4523
4524 u32Return = UTOPIA_STATUS_SUCCESS;
4525 break;
4526 }
4527
4528
4529 case E_XC_CMD_SET_PREGAMMA_GAIN:
4530 {
4531
4532
4533 pstXC_SET_PREGAMMA_GAIN pXCArgs = (pstXC_SET_PREGAMMA_GAIN) pArgs;
4534 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4535 USE_OTHER_SC_AS_SUB_WINDOW();
4536 #endif
4537 psXCInstPri->fpXC_SetPreGammaGain(pInstance, pXCArgs->eWindow, pXCArgs->eVop_Channel, pXCArgs->u16Val);
4538
4539
4540 u32Return = UTOPIA_STATUS_SUCCESS;
4541 break;
4542 }
4543
4544
4545 case E_XC_CMD_SET_PREGAMMA_OFFSET:
4546 {
4547
4548
4549 pstXC_SET_PREGAMMA_OFFSET pXCArgs = (pstXC_SET_PREGAMMA_OFFSET) pArgs;
4550 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4551 USE_OTHER_SC_AS_SUB_WINDOW();
4552 #endif
4553 psXCInstPri->fpXC_SetPreGammaOffset(pInstance, pXCArgs->eWindow, pXCArgs->eVop_Channel, pXCArgs->u16Val);
4554
4555
4556 u32Return = UTOPIA_STATUS_SUCCESS;
4557 break;
4558 }
4559
4560
4561 case E_XC_CMD_SET_PANEL_TIMING:
4562 {
4563
4564
4565 pstXC_SET_PANEL_TIMING pXCArgs = (pstXC_SET_PANEL_TIMING) pArgs;
4566 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4567 USE_OTHER_SC_AS_SUB_WINDOW();
4568 #endif
4569 psXCInstPri->fpXC_SetPanelTiming(pInstance, pXCArgs->pTimingInfo, pXCArgs->eWindow);
4570
4571
4572 u32Return = UTOPIA_STATUS_SUCCESS;
4573 break;
4574 }
4575
4576
4577 case E_XC_CMD_SET_OUTPUT_TIMING_MODE:
4578 {
4579
4580
4581 pstXC_SET_OUTPUT_TIMING_MODE pXCArgs = (pstXC_SET_OUTPUT_TIMING_MODE) pArgs;
4582 psXCInstPri->fpXC_SetOutTimingMode(pInstance, pXCArgs->enPnl_Out_Timing_Mode);
4583 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4584 CHECK_DEVICE1_INSTANCE();
4585 psXCInstPri->fpXC_SetOutTimingMode(g_pDevice1Instance, pXCArgs->enPnl_Out_Timing_Mode);
4586 #endif
4587
4588 u32Return = UTOPIA_STATUS_SUCCESS;
4589 break;
4590 }
4591
4592
4593 case E_XC_CMD_SET_FREERUN_TIMING:
4594 {
4595
4596
4597 psXCInstPri->fpXC_SetFreeRunTiming(pInstance);
4598
4599
4600 u32Return = UTOPIA_STATUS_SUCCESS;
4601 break;
4602 }
4603
4604
4605 case E_XC_CMD_SET_CUSTOMER_SYNC_INFO:
4606 {
4607
4608
4609 pstXC_SET_CUSTOMER_SYNC_INFO pXCArgs = (pstXC_SET_CUSTOMER_SYNC_INFO) pArgs;
4610 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_CustomerSyncInfo(pInstance,
4611 pXCArgs->u16FrontPorch,
4612 pXCArgs->u16SyncWidth,
4613 pXCArgs->u16OutputVfreq);
4614
4615 u32Return = UTOPIA_STATUS_SUCCESS;
4616 break;
4617 }
4618
4619
4620 case E_XC_CMD_GET_WAIT_FPLL_DONE:
4621 {
4622
4623
4624 pstXC_GET_WAIT_FPLL_DONE pXCArgs = (pstXC_GET_WAIT_FPLL_DONE) pArgs;
4625 pXCArgs->bReturnValue = psXCInstPri->fpXC_WaitFPLLDone(pInstance);
4626
4627
4628 u32Return = UTOPIA_STATUS_SUCCESS;
4629 break;
4630 }
4631
4632
4633 case E_XC_CMD_GET_OUTPUT_VFREQX100:
4634 {
4635
4636
4637 pstXC_GET_OUTPUT_VFREQX100 pXCArgs = (pstXC_GET_OUTPUT_VFREQX100) pArgs;
4638 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetOutputVFreqX100(pInstance);
4639
4640
4641 u32Return = UTOPIA_STATUS_SUCCESS;
4642 break;
4643 }
4644
4645 case E_XC_CMD_GET_OP1_OUTPUT_VFREQX100:
4646 {
4647
4648
4649 pstXC_GET_OP1_OUTPUT_VFREQX100 pXCArgs = (pstXC_GET_OP1_OUTPUT_VFREQX100) pArgs;
4650 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_GetOP1OutputVFreqX100(pInstance);
4651
4652
4653 u32Return = UTOPIA_STATUS_SUCCESS;
4654 break;
4655 }
4656
4657
4658 case E_XC_CMD_CHECK_FRAMELOCK:
4659 {
4660
4661
4662 pstXC_CHECK_FRAMELOCK pXCArgs = (pstXC_CHECK_FRAMELOCK) pArgs;
4663 pXCArgs->bReturnValue = psXCInstPri->fpXC_FrameLockCheck(pInstance);
4664
4665
4666 u32Return = UTOPIA_STATUS_SUCCESS;
4667 break;
4668 }
4669
4670
4671 case E_XC_CMD_SET_CUSTOMIZE_FRC_TABLE:
4672 {
4673
4674
4675 pstXC_SET_CUSTOMIZE_FRC_TABLE pXCArgs = (pstXC_SET_CUSTOMIZE_FRC_TABLE) pArgs;
4676 pXCArgs->eReturnValue = psXCInstPri->fpXC_CustomizeFRCTable(pInstance, pXCArgs->stFRCTable);
4677 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4678 CHECK_DEVICE1_INSTANCE();
4679 pXCArgs->eReturnValue = psXCInstPri->fpXC_CustomizeFRCTable(g_pDevice1Instance, pXCArgs->stFRCTable);
4680 #endif
4681
4682 u32Return = UTOPIA_STATUS_SUCCESS;
4683 break;
4684 }
4685
4686
4687 case E_XC_CMD_SET_OUTPUT_FRAME_CONTROL:
4688 {
4689
4690
4691 pstXC_SET_OUTPUT_FRAME_CONTROL pXCArgs = (pstXC_SET_OUTPUT_FRAME_CONTROL) pArgs;
4692 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4693 USE_OTHER_SC_AS_SUB_WINDOW();
4694 #endif
4695 pXCArgs->eReturnValue = psXCInstPri->fpXC_OutputFrameCtrl(pInstance, pXCArgs->bEnable, pXCArgs->pstOutFrameInfo, pXCArgs->eWindow);
4696
4697
4698 u32Return = UTOPIA_STATUS_SUCCESS;
4699 break;
4700 }
4701
4702
4703 case E_XC_CMD_SET_FPLL_FSM_ENABLE:
4704 {
4705
4706
4707 pstXC_SET_FPLL_FSM_ENABLE pXCArgs = (pstXC_SET_FPLL_FSM_ENABLE) pArgs;
4708 psXCInstPri->fpSC_Enable_FPLL_FSM(pInstance, pXCArgs->bTrue);
4709 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4710 CHECK_DEVICE1_INSTANCE();
4711 psXCInstPri->fpSC_Enable_FPLL_FSM(g_pDevice1Instance, pXCArgs->bTrue);
4712 #endif
4713
4714 u32Return = UTOPIA_STATUS_SUCCESS;
4715 break;
4716 }
4717
4718
4719 case E_XC_CMD_SET_FORCE_FREERUN:
4720 {
4721
4722
4723 pstXC_SET_FORCE_FREERUN pXCArgs = (pstXC_SET_FORCE_FREERUN) pArgs;
4724 psXCInstPri->fpSC_ForceFreerun(pInstance, pXCArgs->bEnable);
4725 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4726 CHECK_DEVICE1_INSTANCE();
4727 psXCInstPri->fpSC_ForceFreerun(g_pDevice1Instance, pXCArgs->bEnable);
4728 #endif
4729
4730 u32Return = UTOPIA_STATUS_SUCCESS;
4731 break;
4732 }
4733
4734
4735 case E_XC_CMD_CHECK_FORCE_FREERUN:
4736 {
4737
4738
4739 pstXC_CHECK_FORCE_FREERUN pXCArgs = (pstXC_CHECK_FORCE_FREERUN) pArgs;
4740 pXCArgs->bReturnValue = psXCInstPri->fpSC_IsForceFreerun(pInstance);
4741
4742
4743 u32Return = UTOPIA_STATUS_SUCCESS;
4744 break;
4745 }
4746
4747
4748 case E_XC_CMD_SET_FREERUN_FREQ:
4749 {
4750
4751
4752 pstXC_SET_FREERUN_FREQ pXCArgs = (pstXC_SET_FREERUN_FREQ) pArgs;
4753 psXCInstPri->fpSC_SetFreerunVFreq(pInstance, pXCArgs->VFreq);
4754 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4755 CHECK_DEVICE1_INSTANCE();
4756 psXCInstPri->fpSC_SetFreerunVFreq(g_pDevice1Instance, pXCArgs->VFreq);
4757 #endif
4758 u32Return = UTOPIA_STATUS_SUCCESS;
4759 break;
4760 }
4761
4762
4763 case E_XC_CMD_SET_EXPANEL_INFO:
4764 {
4765
4766
4767 pstXC_SET_EXPANEL_INFO pXCArgs = (pstXC_SET_EXPANEL_INFO) pArgs;
4768 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetExPanelInfo(pInstance, pXCArgs->bEnable, pXCArgs->pPanelInfoEx);
4769
4770
4771 u32Return = UTOPIA_STATUS_SUCCESS;
4772 break;
4773 }
4774
4775
4776 case E_XC_CMD_SET_FPLL_THRESHMODE:
4777 {
4778
4779 pstXC_SET_FPLL_THRESHMODE pXCArgs = (pstXC_SET_FPLL_THRESHMODE) pArgs;
4780 psXCInstPri->fpXC_Enable_FPLL_Thresh_Mode(pInstance, pXCArgs->bEnable);
4781 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4782 CHECK_DEVICE1_INSTANCE();
4783 psXCInstPri->fpXC_Enable_FPLL_Thresh_Mode(g_pDevice1Instance, pXCArgs->bEnable);
4784 #endif
4785
4786 u32Return = UTOPIA_STATUS_SUCCESS;
4787 break;
4788 }
4789
4790 case E_XC_CMD_GET_FPLL_THRESHMODE:
4791 {
4792 pstXC_GET_FPLL_THRESHMODE pXCArgs = (pstXC_GET_FPLL_THRESHMODE) pArgs;
4793 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_FPLL_Thresh_Mode(pInstance);
4794
4795 u32Return = UTOPIA_STATUS_SUCCESS;
4796 break;
4797 }
4798
4799 case E_XC_CMD_SET_IPAUTONOSIGNAL:
4800 {
4801
4802
4803 pstXC_SET_IPAUTONOSIGNAL pXCArgs = (pstXC_SET_IPAUTONOSIGNAL) pArgs;
4804 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4805 USE_OTHER_SC_AS_SUB_WINDOW();
4806 #endif
4807 pXCArgs->eReturnValue = psXCInstPri->fpXC_EnableIPAutoNoSignal(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
4808
4809
4810 u32Return = UTOPIA_STATUS_SUCCESS;
4811 break;
4812 }
4813
4814
4815 case E_XC_CMD_GET_IPAUTONOSIGNAL:
4816 {
4817
4818 pstXC_GET_IPAUTONOSIGNAL pXCArgs = (pstXC_GET_IPAUTONOSIGNAL) pArgs;
4819 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4820 USE_OTHER_SC_AS_SUB_WINDOW();
4821 #endif
4822 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetIPAutoNoSignal(pInstance, pXCArgs->eWindow);
4823
4824
4825 u32Return = UTOPIA_STATUS_SUCCESS;
4826 break;
4827 }
4828
4829
4830 case E_XC_CMD_SET_IPAUTOCOAST:
4831 {
4832
4833
4834 pstXC_SET_IPAUTOCOAST pXCArgs = (pstXC_SET_IPAUTOCOAST) pArgs;
4835 psXCInstPri->fpXC_EnableIPAutoCoast(pInstance, pXCArgs->bEnable);
4836 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4837 CHECK_DEVICE1_INSTANCE();
4838 psXCInstPri->fpXC_EnableIPAutoCoast(g_pDevice1Instance, pXCArgs->bEnable);
4839 #endif
4840
4841 u32Return = UTOPIA_STATUS_SUCCESS;
4842 break;
4843 }
4844
4845
4846 case E_XC_CMD_SET_IPCOAST_DEBOUNCE_ENABLE:
4847 {
4848
4849
4850 psXCInstPri->fpXC_EnableIPCoastDebounce(pInstance);
4851 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4852 CHECK_DEVICE1_INSTANCE();
4853 psXCInstPri->fpXC_EnableIPCoastDebounce(g_pDevice1Instance);
4854 #endif
4855
4856 u32Return = UTOPIA_STATUS_SUCCESS;
4857 break;
4858 }
4859
4860
4861 case E_XC_CMD_SET_CLEAR_IPCOAST_STATUS:
4862 {
4863
4864
4865 psXCInstPri->fpXC_ClearIPCoastStatus(pInstance);
4866 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4867 CHECK_DEVICE1_INSTANCE();
4868 psXCInstPri->fpXC_ClearIPCoastStatus(g_pDevice1Instance);
4869 #endif
4870
4871 u32Return = UTOPIA_STATUS_SUCCESS;
4872 break;
4873 }
4874
4875
4876 case E_XC_CMD_SET_FPLL_MANUAL_SETTING_ENABLE:
4877 {
4878
4879
4880 pstXC_SET_FPLL_MANUAL_SETTING_ENABLE pXCArgs = (pstXC_SET_FPLL_MANUAL_SETTING_ENABLE) pArgs;
4881 psXCInstPri->fpXC_EnableFpllManualSetting(pInstance, pXCArgs->bEnable);
4882 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4883 CHECK_DEVICE1_INSTANCE();
4884 psXCInstPri->fpXC_EnableFpllManualSetting(g_pDevice1Instance, pXCArgs->bEnable);
4885 #endif
4886
4887 u32Return = UTOPIA_STATUS_SUCCESS;
4888 break;
4889 }
4890
4891
4892 case E_XC_CMD_SET_FPLL_BOUNDARY_TEST:
4893 {
4894
4895
4896 pstXC_SET_FPLL_BOUNDARY_TEST pXCArgs = (pstXC_SET_FPLL_BOUNDARY_TEST) pArgs;
4897 psXCInstPri->fpXC_FpllBoundaryTest(pInstance, pXCArgs->u32FpllSetOffset, pXCArgs->u16TestCnt);
4898
4899
4900 u32Return = UTOPIA_STATUS_SUCCESS;
4901 break;
4902 }
4903
4904
4905 case E_XC_CMD_SET_OFFLINE_DETECTION:
4906 {
4907
4908
4909 pstXC_SET_OFFLINE_DETECTION pXCArgs = (pstXC_SET_OFFLINE_DETECTION) pArgs;
4910 psXCInstPri->fpXC_SetOffLineDetection(pInstance, pXCArgs->u8InputSourceType);
4911
4912
4913 u32Return = UTOPIA_STATUS_SUCCESS;
4914 break;
4915 }
4916
4917
4918 case E_XC_CMD_GET_OFFLINE_DETECTION:
4919 {
4920
4921
4922 pstXC_GET_OFFLINE_DETECTION pXCArgs = (pstXC_GET_OFFLINE_DETECTION) pArgs;
4923 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_GetOffLineDetection(pInstance, pXCArgs->u8InputSourceType);
4924
4925
4926 u32Return = UTOPIA_STATUS_SUCCESS;
4927 break;
4928 }
4929
4930
4931 case E_XC_CMD_SET_OFFLINE_SOG_THRESHOLD:
4932 {
4933
4934
4935 pstXC_SET_OFFLINE_SOG_THRESHOLD pXCArgs = (pstXC_SET_OFFLINE_SOG_THRESHOLD) pArgs;
4936 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetOffLineSogThreshold(pInstance, pXCArgs->u8Threshold);
4937
4938
4939 u32Return = UTOPIA_STATUS_SUCCESS;
4940 break;
4941 }
4942
4943
4944 case E_XC_CMD_SET_OFFLINE_SOG_BW:
4945 {
4946
4947
4948 pstXC_SET_OFFLINE_SOG_BW pXCArgs = (pstXC_SET_OFFLINE_SOG_BW) pArgs;
4949 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetOffLineSogBW(pInstance, pXCArgs->u8BW);
4950
4951
4952 u32Return = UTOPIA_STATUS_SUCCESS;
4953 break;
4954 }
4955
4956
4957 case E_XC_CMD_SET_OFFLINE_INIT:
4958 {
4959
4960
4961 pstXC_SET_OFFLINE_INIT pXCArgs = (pstXC_SET_OFFLINE_INIT) pArgs;
4962 pXCArgs->bReturnValue = psXCInstPri->fpXC_OffLineInit(pInstance);
4963
4964
4965 u32Return = UTOPIA_STATUS_SUCCESS;
4966 break;
4967 }
4968
4969
4970 case E_XC_CMD_SET_EXTRA_FETCH_ADV_LINE:
4971 {
4972
4973
4974 pstXC_SET_EXTRA_FETCH_ADV_LINE pXCArgs = (pstXC_SET_EXTRA_FETCH_ADV_LINE) pArgs;
4975 psXCInstPri->fpXC_Set_Extra_fetch_adv_line(pInstance, pXCArgs->u8val);
4976
4977
4978 u32Return = UTOPIA_STATUS_SUCCESS;
4979 break;
4980 }
4981
4982
4983 case E_XC_CMD_SET_VGA_SOG_ENABLE:
4984 {
4985
4986
4987 pstXC_SET_VGA_SOG_ENABLE pXCArgs = (pstXC_SET_VGA_SOG_ENABLE) pArgs;
4988 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetVGASogEn(pInstance, pXCArgs->bVGASogEn);
4989
4990
4991 u32Return = UTOPIA_STATUS_SUCCESS;
4992 break;
4993 }
4994
4995
4996 case E_XC_CMD_SET_WINDOW_ENABLE:
4997 {
4998
4999
5000 pstXC_SET_WINDOW_ENABLE pXCArgs = (pstXC_SET_WINDOW_ENABLE) pArgs;
5001 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5002 if(!MDrv_XC_GetMWEStatus(pInstance))
5003 {
5004 USE_OTHER_SC_AS_SUB_WINDOW();
5005 }
5006 #endif
5007 psXCInstPri->fpXC_EnableWindow(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5008
5009
5010 u32Return = UTOPIA_STATUS_SUCCESS;
5011 break;
5012 }
5013
5014
5015 case E_XC_CMD_CHECK_SUBWINDOW_ENABLE:
5016 {
5017
5018
5019 pstXC_CHECK_SUBWINDOW_ENABLE pXCArgs = (pstXC_CHECK_SUBWINDOW_ENABLE) pArgs;
5020 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0)
5021 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is_SubWindowEanble(pInstance);
5022 #else
5023 if(!MDrv_XC_GetMWEStatus(pInstance))
5024 {
5025 CHECK_DEVICE1_INSTANCE();
5026 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is_SubWindowEanble(g_pDevice1Instance);
5027 }
5028 else
5029 {
5030 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is_SubWindowEanble(pInstance);
5031 }
5032 #endif
5033
5034 u32Return = UTOPIA_STATUS_SUCCESS;
5035 break;
5036 }
5037
5038
5039 case E_XC_CMD_SET_BORDER_FORMAT:
5040 {
5041
5042
5043 pstXC_SET_BORDER_FORMAT pXCArgs = (pstXC_SET_BORDER_FORMAT) pArgs;
5044 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5045 USE_OTHER_SC_AS_SUB_WINDOW();
5046 #endif
5047 psXCInstPri->fpXC_SetBorderFormat(pInstance,
5048 pXCArgs->u8Left,
5049 pXCArgs->u8Right,
5050 pXCArgs->u8Up,
5051 pXCArgs->u8Down,
5052 pXCArgs->u8color,
5053 pXCArgs->eWindow);
5054
5055
5056 u32Return = UTOPIA_STATUS_SUCCESS;
5057 break;
5058 }
5059
5060
5061 case E_XC_CMD_SET_BORDER_ENABLE:
5062 {
5063
5064
5065 pstXC_SET_BORDER_ENABLE pXCArgs = (pstXC_SET_BORDER_ENABLE) pArgs;
5066 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5067 USE_OTHER_SC_AS_SUB_WINDOW();
5068 #endif
5069 psXCInstPri->fpXC_EnableBorder(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5070
5071
5072 u32Return = UTOPIA_STATUS_SUCCESS;
5073 break;
5074 }
5075
5076
5077 case E_XC_CMD_SET_ZORDER_MAINWINDOW_FIRST:
5078 {
5079 pstXC_SET_ZORDER_MAINWINDOW_FIRST pXCArgs = (pstXC_SET_ZORDER_MAINWINDOW_FIRST) pArgs;
5080 psXCInstPri->fpXC_ZorderMainWindowFirst(pInstance, pXCArgs->bMainFirst);
5081 u32Return = UTOPIA_STATUS_SUCCESS;
5082 break;
5083 }
5084
5085
5086 case E_XC_CMD_SET_PQ_LOADFUNCTION:
5087 {
5088
5089
5090 pstXC_SET_PQ_LOADFUNCTION pXCArgs = (pstXC_SET_PQ_LOADFUNCTION) pArgs;
5091 psXCInstPri->fpXC_PQ_LoadFunction(pInstance, pXCArgs->function_Info, pXCArgs->u32InitDataLen);
5092 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5093 CHECK_DEVICE1_INSTANCE();
5094 psXCInstPri->fpXC_PQ_LoadFunction(g_pDevice1Instance, pXCArgs->function_Info, pXCArgs->u32InitDataLen);
5095 #endif
5096
5097 u32Return = UTOPIA_STATUS_SUCCESS;
5098 break;
5099 }
5100
5101
5102 case E_XC_CMD_CHECK_H_NONLINEAR_SCALING:
5103 {
5104
5105
5106 pstXC_CHECK_H_NONLINEAR_SCALING pXCArgs = (pstXC_CHECK_H_NONLINEAR_SCALING) pArgs;
5107 pXCArgs->bReturnValue = psXCInstPri->fpXC_Check_HNonLinearScaling(pInstance);
5108
5109
5110 u32Return = UTOPIA_STATUS_SUCCESS;
5111 break;
5112 }
5113
5114
5115 case E_XC_CMD_SET_EUROHDTV_SUPPORT_ENABLE:
5116 {
5117
5118
5119 pstXC_SET_EUROHDTV_SUPPORT_ENABLE pXCArgs = (pstXC_SET_EUROHDTV_SUPPORT_ENABLE) pArgs;
5120 psXCInstPri->fpXC_EnableEuroHdtvSupport(pInstance, pXCArgs->bEnable);
5121 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5122 CHECK_DEVICE1_INSTANCE();
5123 psXCInstPri->fpXC_EnableEuroHdtvSupport(g_pDevice1Instance, pXCArgs->bEnable);
5124 #endif
5125 u32Return = UTOPIA_STATUS_SUCCESS;
5126 break;
5127 }
5128
5129
5130 case E_XC_CMD_SET_EUROHDTV_DETECTION_ENABLE:
5131 {
5132
5133
5134 pstXC_SET_EUROHDTV_DETECTION_ENABLE pXCArgs = (pstXC_SET_EUROHDTV_DETECTION_ENABLE) pArgs;
5135 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5136 USE_OTHER_SC_AS_SUB_WINDOW();
5137 #endif
5138 psXCInstPri->fpXC_EnableEuroHdtvDetection(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5139
5140
5141 u32Return = UTOPIA_STATUS_SUCCESS;
5142 break;
5143 }
5144
5145
5146 case E_XC_CMD_READBYTE:
5147 {
5148
5149
5150 pstXC_READBYTE pXCArgs = (pstXC_READBYTE) pArgs;
5151 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_ReadByte(pInstance, pXCArgs->u32Reg);
5152
5153
5154 u32Return = UTOPIA_STATUS_SUCCESS;
5155 break;
5156 }
5157
5158
5159 case E_XC_CMD_WRITEBYTE:
5160 {
5161
5162
5163 pstXC_WRITEBYTE pXCArgs = (pstXC_WRITEBYTE) pArgs;
5164 psXCInstPri->fpXC_WriteByte(pInstance, pXCArgs->u32Reg, pXCArgs->u8Val);
5165
5166
5167 u32Return = UTOPIA_STATUS_SUCCESS;
5168 break;
5169 }
5170
5171
5172 case E_XC_CMD_WRITEBYTEMSK:
5173 {
5174
5175 pstXC_WRITEBYTEMSK pXCArgs = (pstXC_WRITEBYTEMSK) pArgs;
5176 psXCInstPri->fpXC_WriteByteMask(pInstance, pXCArgs->u32Reg, pXCArgs->u8Val, pXCArgs->u8Msk);
5177
5178
5179 u32Return = UTOPIA_STATUS_SUCCESS;
5180 break;
5181 }
5182
5183
5184 case E_XC_CMD_WRITE2BYTEMSK:
5185 {
5186
5187
5188 pstXC_WRITE2BYTEMSK pXCArgs = (pstXC_WRITE2BYTEMSK) pArgs;
5189 psXCInstPri->fpXC_Write2ByteMask(pInstance, pXCArgs->u32Reg, pXCArgs->u16val, pXCArgs->u16Mask);
5190
5191
5192 u32Return = UTOPIA_STATUS_SUCCESS;
5193 break;
5194 }
5195
5196
5197 case E_XC_CMD_W2BYTE:
5198 {
5199
5200
5201 pstXC_W2BYTE pXCArgs = (pstXC_W2BYTE) pArgs;
5202 psXCInstPri->fpXC_W2BYTE(pInstance, pXCArgs->u32Reg, pXCArgs->u16Val);
5203
5204
5205 u32Return = UTOPIA_STATUS_SUCCESS;
5206 break;
5207 }
5208
5209
5210 case E_XC_CMD_R2BYTE:
5211 {
5212
5213
5214 pstXC_R2BYTE pXCArgs = (pstXC_R2BYTE) pArgs;
5215 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_R2BYTE(pInstance, pXCArgs->u32Reg);
5216
5217
5218 u32Return = UTOPIA_STATUS_SUCCESS;
5219 break;
5220 }
5221
5222
5223 case E_XC_CMD_W4BYTE:
5224 {
5225
5226
5227 pstXC_W4BYTE pXCArgs = (pstXC_W4BYTE) pArgs;
5228 psXCInstPri->fpXC_W4BYTE(pInstance, pXCArgs->u32Reg, pXCArgs->u32Val);
5229
5230
5231 u32Return = UTOPIA_STATUS_SUCCESS;
5232 break;
5233 }
5234
5235
5236 case E_XC_CMD_R4BYTE:
5237 {
5238
5239
5240 pstXC_R4BYTE pXCArgs = (pstXC_R4BYTE) pArgs;
5241 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_R4BYTE(pInstance, pXCArgs->u32Reg);
5242
5243
5244 u32Return = UTOPIA_STATUS_SUCCESS;
5245 break;
5246 }
5247
5248
5249 case E_XC_CMD_R2BYTEMSK:
5250 {
5251
5252
5253 pstXC_R2BYTEMSK pXCArgs = (pstXC_R2BYTEMSK) pArgs;
5254 pXCArgs->u16ReturnValue = psXCInstPri->fpXC_R2BYTEMSK(pInstance, pXCArgs->u32Reg, pXCArgs->u16mask);
5255
5256
5257 u32Return = UTOPIA_STATUS_SUCCESS;
5258 break;
5259 }
5260
5261
5262 case E_XC_CMD_W2BYTEMSK:
5263 {
5264
5265
5266 pstXC_W2BYTEMSK pXCArgs = (pstXC_W2BYTEMSK) pArgs;
5267 psXCInstPri->fpXC_W2BYTEMSK(pInstance, pXCArgs->u32Reg, pXCArgs->u16Val, pXCArgs->u16mask);
5268
5269
5270 u32Return = UTOPIA_STATUS_SUCCESS;
5271 break;
5272 }
5273
5274
5275 case E_XC_CMD_MLOAD_INIT:
5276 {
5277 pstXC_MLOAD_INIT pXCArgs = (pstXC_MLOAD_INIT) pArgs;
5278 MS_U32 u32MloadBufLen = pXCArgs->u32BufByteLen;
5279 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5280 u32MloadBufLen = pXCArgs->u32BufByteLen/2;
5281 #endif
5282 psXCInstPri->fpXC_MLoad_Init(pInstance, pXCArgs->PhyAddr, u32MloadBufLen);
5283 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5284 CHECK_DEVICE1_INSTANCE();
5285 psXCInstPri->fpXC_MLoad_Init(g_pDevice1Instance, pXCArgs->PhyAddr + u32MloadBufLen, u32MloadBufLen);
5286 #endif
5287 u32Return = UTOPIA_STATUS_SUCCESS;
5288 break;
5289 }
5290
5291
5292 case E_XC_CMD_MLOAD_ENABLE:
5293 {
5294
5295
5296 pstXC_MLOAD_ENABLE pXCArgs = (pstXC_MLOAD_ENABLE) pArgs;
5297 psXCInstPri->fpXC_MLoad_Enable(pInstance, pXCArgs->bEnable);
5298 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5299 CHECK_DEVICE1_INSTANCE();
5300 psXCInstPri->fpXC_MLoad_Enable(g_pDevice1Instance, pXCArgs->bEnable);
5301 #endif
5302
5303 u32Return = UTOPIA_STATUS_SUCCESS;
5304 break;
5305 }
5306 case E_XC_CMD_MLOAD_CUS_INIT:
5307 {
5308 pstXC_MLOAD_CUS_INIT pXCArgs = (pstXC_MLOAD_CUS_INIT) pArgs;
5309
5310 psXCInstPri->fpXC_MLoad_Cus_Init(pInstance, pXCArgs->eMloadSelect, pXCArgs->PhyAddr, pXCArgs->u32BufByteLen);
5311
5312 u32Return = UTOPIA_STATUS_SUCCESS;
5313 break;
5314 }
5315
5316 case E_XC_CMD_MLOAD_CUS_ENABLE:
5317 {
5318 pstXC_MLOAD_CUS_ENABLE pXCArgs = (pstXC_MLOAD_CUS_ENABLE) pArgs;
5319 psXCInstPri->fpXC_MLoad_Cus_Enable(pInstance, pXCArgs->eMloadSelect, pXCArgs->bEnable);
5320 u32Return = UTOPIA_STATUS_SUCCESS;
5321 break;
5322 }
5323 case E_XC_CMD_MLOAD_GETSTATUS:
5324 {
5325
5326
5327 pstXC_MLOAD_GETSTATUS pXCArgs = (pstXC_MLOAD_GETSTATUS) pArgs;
5328 pXCArgs->eReturnValue = psXCInstPri->fpXC_MLoad_GetStatus(pInstance);
5329
5330
5331 u32Return = UTOPIA_STATUS_SUCCESS;
5332 break;
5333 }
5334
5335
5336 case E_XC_CMD_MLOAD_WRITE_CMD_AND_FIRE:
5337 {
5338
5339
5340 pstXC_MLOAD_WRITE_CMD_AND_FIRE pXCArgs = (pstXC_MLOAD_WRITE_CMD_AND_FIRE) pArgs;
5341 pXCArgs->bReturnValue = psXCInstPri->fpXC_MLoad_WriteCmd_And_Fire(pInstance, pXCArgs->u32Addr, pXCArgs->u16Data, pXCArgs->u16Mask);
5342
5343
5344 u32Return = UTOPIA_STATUS_SUCCESS;
5345 break;
5346 }
5347
5348
5349 case E_XC_CMD_MLOAD_WRITE_CMDS_AND_FIRE:
5350 {
5351
5352
5353 pstXC_MLOAD_WRITE_CMDS_AND_FIRE pXCArgs = (pstXC_MLOAD_WRITE_CMDS_AND_FIRE) pArgs;
5354 pXCArgs->bReturnValue = psXCInstPri->fpXC_MLoad_WriteCmds_And_Fire(pInstance, pXCArgs->pu32Addr, pXCArgs->pu16Data, pXCArgs->pu16Mask, pXCArgs->u16CmdCnt);
5355
5356
5357 u32Return = UTOPIA_STATUS_SUCCESS;
5358 break;
5359 }
5360
5361 case E_XC_CMD_MLOAD_COMBINE:
5362 {
5363 pstXC_MLOAD_COMBINE pXCArgs = (pstXC_MLOAD_COMBINE) pArgs;
5364 pXCArgs->eReturnValue = psXCInstPri->fpXC_MLoad_Combine_Enable(pInstance, pXCArgs->bEn);
5365 u32Return = UTOPIA_STATUS_SUCCESS;
5366 break;
5367 }
5368
5369 case E_XC_CMD_MLG_INIT:
5370 {
5371
5372
5373 pstXC_MLG_INIT pXCArgs = (pstXC_MLG_INIT) pArgs;
5374 psXCInstPri->fpXC_MLG_Init(pInstance, pXCArgs->PhyAddr, pXCArgs->u32BufByteLen);
5375
5376
5377 u32Return = UTOPIA_STATUS_SUCCESS;
5378 break;
5379 }
5380
5381
5382 case E_XC_CMD_MLG_ENABLE:
5383 {
5384
5385
5386 pstXC_MLG_ENABLE pXCArgs = (pstXC_MLG_ENABLE) pArgs;
5387 psXCInstPri->fpXC_MLG_Enable(pInstance, pXCArgs->bEnable);
5388
5389
5390 u32Return = UTOPIA_STATUS_SUCCESS;
5391 break;
5392 }
5393
5394
5395 case E_XC_CMD_MLG_GET_CAPS:
5396 {
5397
5398
5399 pstXC_MLG_GET_CAPS pXCArgs = (pstXC_MLG_GET_CAPS) pArgs;
5400 pXCArgs->bReturnValue = psXCInstPri->fpXC_MLG_GetCaps(pInstance);
5401
5402
5403 u32Return = UTOPIA_STATUS_SUCCESS;
5404 break;
5405 }
5406
5407
5408 case E_XC_CMD_MLG_GETSTATUS:
5409 {
5410
5411
5412 pstXC_MLG_GETSTATUS pXCArgs = (pstXC_MLG_GETSTATUS) pArgs;
5413 pXCArgs->eReturnValue = psXCInstPri->fpXC_MLG_GetStatus(pInstance);
5414
5415
5416 u32Return = UTOPIA_STATUS_SUCCESS;
5417 break;
5418 }
5419
5420
5421 case E_XC_CMD_SET_OSD2VEMODE:
5422 {
5423
5424
5425 pstXC_SET_OSD2VEMODE pXCArgs = (pstXC_SET_OSD2VEMODE) pArgs;
5426 psXCInstPri->fpXC_SetOSD2VEMode(pInstance, pXCArgs->eVOPSelOSD_MUX);
5427
5428
5429 u32Return = UTOPIA_STATUS_SUCCESS;
5430 break;
5431 }
5432
5433
5434 case E_XC_CMD_SET_IP2_PREFILTER_ENABLE:
5435 {
5436
5437
5438 pstXC_SET_IP2_PREFILTER_ENABLE pXCArgs = (pstXC_SET_IP2_PREFILTER_ENABLE) pArgs;
5439 psXCInstPri->fpXC_IP2_PreFilter_Enable(pInstance, pXCArgs->bEnable);
5440 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5441 CHECK_DEVICE1_INSTANCE();
5442 psXCInstPri->fpXC_IP2_PreFilter_Enable(g_pDevice1Instance, pXCArgs->bEnable);
5443 #endif
5444
5445 u32Return = UTOPIA_STATUS_SUCCESS;
5446 break;
5447 }
5448
5449
5450 case E_XC_CMD_GET_PIXELRGB:
5451 {
5452
5453
5454 pstXC_GET_PIXELRGB pXCArgs = (pstXC_GET_PIXELRGB) pArgs;
5455 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5456 USE_OTHER_SC_AS_SUB_WINDOW();
5457 #endif
5458 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_Pixel_RGB(pInstance, pXCArgs->pData, pXCArgs->eWindow);
5459
5460
5461 u32Return = UTOPIA_STATUS_SUCCESS;
5462 break;
5463 }
5464
5465
5466 case E_XC_CMD_SET_KEEP_PIXELPOINTER_APPEAR:
5467 {
5468
5469
5470 pstXC_SET_KEEP_PIXELPOINTER_APPEAR pXCArgs = (pstXC_SET_KEEP_PIXELPOINTER_APPEAR) pArgs;
5471 psXCInstPri->fpXC_KeepPixelPointerAppear(pInstance, pXCArgs->bEnable);
5472 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5473 CHECK_DEVICE1_INSTANCE();
5474 psXCInstPri->fpXC_KeepPixelPointerAppear(g_pDevice1Instance, pXCArgs->bEnable);
5475 #endif
5476
5477 u32Return = UTOPIA_STATUS_SUCCESS;
5478 break;
5479 }
5480
5481
5482 case E_XC_CMD_SET_MEMORY_FORMAT_EX:
5483 {
5484
5485
5486 pstXC_SET_MEMORY_FORMAT_EX pXCArgs = (pstXC_SET_MEMORY_FORMAT_EX) pArgs;
5487 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5488 USE_OTHER_SC_AS_SUB_WINDOW();
5489 #endif
5490 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_MemFmtEx(pInstance, pXCArgs->eMemFmt, pXCArgs->eWindow);
5491
5492
5493 u32Return = UTOPIA_STATUS_SUCCESS;
5494 break;
5495 }
5496
5497
5498 case E_XC_CMD_CHECK_REQUEST_FRAMEBUFFERLESS_MODE:
5499 {
5500
5501
5502 pstXC_CHECK_REQUEST_FRAMEBUFFERLESS_MODE pXCArgs = (pstXC_CHECK_REQUEST_FRAMEBUFFERLESS_MODE) pArgs;
5503 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsRequestFrameBufferLessMode(pInstance);
5504
5505
5506 u32Return = UTOPIA_STATUS_SUCCESS;
5507 break;
5508 }
5509
5510
5511 case E_XC_CMD_SET_SKIP_SWRESET:
5512 {
5513
5514
5515 pstXC_SET_SKIP_SWRESET pXCArgs = (pstXC_SET_SKIP_SWRESET) pArgs;
5516 pXCArgs->eReturnValue = psXCInstPri->fpXC_SkipSWReset(pInstance, pXCArgs->bFlag);
5517 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5518 CHECK_DEVICE1_INSTANCE();
5519 pXCArgs->eReturnValue = psXCInstPri->fpXC_SkipSWReset(g_pDevice1Instance, pXCArgs->bFlag);
5520 #endif
5521
5522 u32Return = UTOPIA_STATUS_SUCCESS;
5523 break;
5524 }
5525
5526
5527 case E_XC_CMD_SET_REPORTWINDOW_FOR_FRAMECOLOR:
5528 {
5529
5530
5531 pstXC_SET_REPORTWINDOW_FOR_FRAMECOLOR pXCArgs = (pstXC_SET_REPORTWINDOW_FOR_FRAMECOLOR) pArgs;
5532 psXCInstPri->fpXC_EnableRepWindowForFrameColor(pInstance, pXCArgs->bEnable);
5533
5534
5535 u32Return = UTOPIA_STATUS_SUCCESS;
5536 break;
5537 }
5538
5539
5540 case E_XC_CMD_SET_OSDLAYER:
5541 {
5542
5543
5544 pstXC_SET_OSDLAYER pXCArgs = (pstXC_SET_OSDLAYER) pArgs;
5545 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5546 USE_OTHER_SC_AS_SUB_WINDOW();
5547 #endif
5548 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOSDLayer(pInstance, pXCArgs->eVOPOSDLayer, pXCArgs->eWindow);
5549
5550
5551 u32Return = UTOPIA_STATUS_SUCCESS;
5552 break;
5553 }
5554
5555
5556 case E_XC_CMD_GET_OSDLAYER:
5557 {
5558
5559
5560 pstXC_GET_OSDLAYER pXCArgs = (pstXC_GET_OSDLAYER) pArgs;
5561 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5562 USE_OTHER_SC_AS_SUB_WINDOW();
5563 #endif
5564 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetOSDLayer(pInstance, pXCArgs->eWindow);
5565
5566
5567 u32Return = UTOPIA_STATUS_SUCCESS;
5568 break;
5569 }
5570
5571
5572 case E_XC_CMD_SET_VIDEO_ALPHA:
5573 {
5574
5575
5576 pstXC_SET_VIDEO_ALPHA pXCArgs = (pstXC_SET_VIDEO_ALPHA) pArgs;
5577 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5578 USE_OTHER_SC_AS_SUB_WINDOW();
5579 #endif
5580 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetVideoAlpha(pInstance, pXCArgs->u8Val, pXCArgs->eWindow);
5581
5582
5583 u32Return = UTOPIA_STATUS_SUCCESS;
5584 break;
5585 }
5586
5587
5588 case E_XC_CMD_GET_VIDEO_ALPHA:
5589 {
5590
5591
5592 pstXC_GET_VIDEO_ALPHA pXCArgs = (pstXC_GET_VIDEO_ALPHA) pArgs;
5593 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5594 USE_OTHER_SC_AS_SUB_WINDOW();
5595 #endif
5596 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetVideoAlpha(pInstance, pXCArgs->pu8Val, pXCArgs->eWindow);
5597
5598
5599 u32Return = UTOPIA_STATUS_SUCCESS;
5600 break;
5601 }
5602
5603
5604 case E_XC_CMD_SKIP_WAIT_VSYNC:
5605 {
5606
5607
5608 pstXC_SKIP_WAIT_VSYNC pXCArgs = (pstXC_SKIP_WAIT_VSYNC) pArgs;
5609 pXCArgs->eReturnValue = psXCInstPri->fpXC_SkipWaitVsync(pInstance, pXCArgs->eWindow, pXCArgs->bIsSkipWaitVsyn);
5610
5611
5612 u32Return = UTOPIA_STATUS_SUCCESS;
5613 break;
5614 }
5615
5616
5617 case E_XC_CMD_SET_CMA_HEAP_ID:
5618 {
5619
5620
5621 pstXC_SET_CMA_HEAP_ID pXCArgs = (pstXC_SET_CMA_HEAP_ID) pArgs;
5622 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5623 USE_OTHER_SC_AS_SUB_WINDOW();
5624 #endif
5625 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetCMAHeapID(pInstance, pXCArgs->u8CMAHeapID, pXCArgs->eWindow);
5626
5627
5628 u32Return = UTOPIA_STATUS_SUCCESS;
5629 break;
5630 }
5631
5632
5633 case E_XC_CMD_SET_OP2VOP_DE_SELECTION:
5634 {
5635
5636
5637 pstXC_SET_OP2VOP_DE_SELECTION pXCArgs = (pstXC_SET_OP2VOP_DE_SELECTION) pArgs;
5638 pXCArgs->eReturnValue = psXCInstPri->fpXC_OP2VOPDESel(pInstance, pXCArgs->eVopDESel);
5639 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5640 CHECK_DEVICE1_INSTANCE();
5641 pXCArgs->eReturnValue = psXCInstPri->fpXC_OP2VOPDESel(g_pDevice1Instance, pXCArgs->eVopDESel);
5642 #endif
5643
5644 u32Return = UTOPIA_STATUS_SUCCESS;
5645 break;
5646 }
5647
5648
5649 case E_XC_CMD_SET_FRC_WINDOW:
5650 {
5651
5652
5653 pstXC_SET_FRC_WINDOW pXCArgs = (pstXC_SET_FRC_WINDOW) pArgs;
5654 psXCInstPri->fpXC_FRC_SetWindow(pInstance, pXCArgs->e3dInputMode, pXCArgs->e3dOutputMode, pXCArgs->e3dPanelType);
5655
5656
5657 u32Return = UTOPIA_STATUS_SUCCESS;
5658 break;
5659 }
5660
5661
5662 case E_XC_CMD_SET_2INITFACTOR_ENABLE:
5663 {
5664
5665
5666 pstXC_SET_2INITFACTOR_ENABLE pXCArgs = (pstXC_SET_2INITFACTOR_ENABLE) pArgs;
5667 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5668 USE_OTHER_SC_AS_SUB_WINDOW();
5669 #endif
5670 pXCArgs->bReturnValue = psXCInstPri->fpXC_Enable_TwoInitFactor(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5671
5672
5673 u32Return = UTOPIA_STATUS_SUCCESS;
5674 break;
5675 }
5676
5677
5678 case E_XC_CMD_CHECK_FIELDPACKINGMODE_SUPPORTED:
5679 {
5680
5681
5682 pstXC_CHECK_FIELDPACKINGMODE_SUPPORTED pXCArgs = (pstXC_CHECK_FIELDPACKINGMODE_SUPPORTED) pArgs;
5683 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsFieldPackingModeSupported(pInstance);
5684
5685
5686 u32Return = UTOPIA_STATUS_SUCCESS;
5687 break;
5688 }
5689
5690
5691 case E_XC_CMD_PREINIT:
5692 {
5693
5694
5695 pstXC_PREINIT pXCArgs = (pstXC_PREINIT) pArgs;
5696 pXCArgs->eReturnValue = psXCInstPri->fpXC_PreInit(pInstance, pXCArgs->eType, pXCArgs->para, pXCArgs->u32Length);
5697 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5698 CHECK_DEVICE1_INSTANCE();
5699 pXCArgs->eReturnValue = psXCInstPri->fpXC_PreInit(g_pDevice1Instance, pXCArgs->eType, pXCArgs->para, pXCArgs->u32Length);
5700 #endif
5701
5702 u32Return = UTOPIA_STATUS_SUCCESS;
5703 break;
5704 }
5705
5706
5707 case E_XC_CMD_GET_BUFFERDATA:
5708 {
5709
5710
5711 pstXC_GET_BUFFERDATA pXCArgs = (pstXC_GET_BUFFERDATA) pArgs;
5712 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5713 USE_OTHER_SC_AS_SUB_WINDOW();
5714 #endif
5715 psXCInstPri->fpXC_Get_BufferData(pInstance, pXCArgs->eBufType, pXCArgs->pRect, pXCArgs->pRectBuf, pXCArgs->eWindow);
5716
5717
5718 u32Return = UTOPIA_STATUS_SUCCESS;
5719 break;
5720 }
5721
5722
5723 case E_XC_CMD_SET_BUFFERDATA:
5724 {
5725
5726
5727 pstXC_SET_BUFFERDATA pXCArgs = (pstXC_SET_BUFFERDATA) pArgs;
5728 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5729 USE_OTHER_SC_AS_SUB_WINDOW();
5730 #endif
5731 psXCInstPri->fpXC_Set_BufferData(pInstance, pXCArgs->eBufType, pXCArgs->pDstRect, pXCArgs->pSrcBuf, pXCArgs->pSrcRect, pXCArgs->eWindow);
5732
5733
5734 u32Return = UTOPIA_STATUS_SUCCESS;
5735 break;
5736 }
5737
5738
5739 case E_XC_CMD_SET_MAINWINDOW_ENABLE:
5740 {
5741
5742
5743 pstXC_SET_MAINWINDOW_ENABLE pXCArgs = (pstXC_SET_MAINWINDOW_ENABLE) pArgs;
5744 psXCInstPri->fpXC_EnableMainWindow(pInstance, pXCArgs->bEnable);
5745
5746
5747 u32Return = UTOPIA_STATUS_SUCCESS;
5748 break;
5749 }
5750
5751
5752 case E_XC_CMD_SET_SUBWINDOW_ENABLE:
5753 {
5754
5755
5756 pstXC_SET_SUBWINDOW_ENABLE pXCArgs = (pstXC_SET_SUBWINDOW_ENABLE) pArgs;
5757 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0)
5758 psXCInstPri->fpXC_EnableSubWindow(pInstance, pXCArgs->pstDispWin);
5759 #else
5760 if(!MDrv_XC_GetMWEStatus(pInstance))
5761 {
5762 CHECK_DEVICE1_INSTANCE();
5763 psXCInstPri->fpXC_EnableSubWindow(g_pDevice1Instance, pXCArgs->pstDispWin);
5764 }
5765 else
5766 {
5767 psXCInstPri->fpXC_EnableSubWindow(pInstance, pXCArgs->pstDispWin);
5768 }
5769 #endif
5770
5771 u32Return = UTOPIA_STATUS_SUCCESS;
5772 break;
5773 }
5774
5775
5776 case E_XC_CMD_SET_SUBWINDOW_DISABLE:
5777 {
5778
5779
5780 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0)
5781 psXCInstPri->fpXC_DisableSubWindow(pInstance);
5782 #else
5783 if(!MDrv_XC_GetMWEStatus(pInstance))
5784 {
5785 CHECK_DEVICE1_INSTANCE();
5786 psXCInstPri->fpXC_DisableSubWindow(g_pDevice1Instance);
5787 }
5788 else
5789 {
5790 psXCInstPri->fpXC_DisableSubWindow(pInstance);
5791 }
5792 #endif
5793
5794 u32Return = UTOPIA_STATUS_SUCCESS;
5795 break;
5796 }
5797
5798
5799 case E_XC_CMD_SET_PIXEL_SHIFT:
5800 {
5801
5802
5803 pstXC_SET_PIXEL_SHIFT pXCArgs = (pstXC_SET_PIXEL_SHIFT) pArgs;
5804 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetPixelShift(pInstance, pXCArgs->s8H, pXCArgs->s8V);
5805
5806
5807 u32Return = UTOPIA_STATUS_SUCCESS;
5808 break;
5809 }
5810
5811
5812 case E_XC_CMD_SET_VIDEO_ON_OSD:
5813 {
5814 pstXC_SET_VIDEO_ON_OSD pXCArgs = (pstXC_SET_VIDEO_ON_OSD) pArgs;
5815 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetVideoOnOSD(pInstance, pXCArgs->enlayer, pXCArgs->eWindow);
5816
5817 u32Return = UTOPIA_STATUS_SUCCESS;
5818 break;
5819 }
5820 case E_XC_CMD_SET_OSD_LAYER_BLEANDING:
5821 {
5822 pstXC_SET_OSD_LAYER_BLENDING pXCArgs = (pstXC_SET_OSD_LAYER_BLENDING) pArgs;
5823 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOSDLayerBlending(pInstance, pXCArgs->u8Layer, pXCArgs->bEnable, pXCArgs->eWindow);
5824
5825 u32Return = UTOPIA_STATUS_SUCCESS;
5826 break;
5827 }
5828 case E_XC_CMD_SET_OSD_LAYER_ALPHA:
5829 {
5830 pstXC_SET_OSD_LAYER_ALPHA pXCArgs = (pstXC_SET_OSD_LAYER_ALPHA) pArgs;
5831 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOSDLayerAlpha(pInstance, pXCArgs->u8Layer, pXCArgs->u8Alpha);
5832
5833 u32Return = UTOPIA_STATUS_SUCCESS;
5834 break;
5835 }
5836 case E_XC_CMD_SET_OSD_BLENDING_FORMULA:
5837 {
5838 pstXC_SET_OSD_BLENDING_FORMULA pXCArgs = (pstXC_SET_OSD_BLENDING_FORMULA) pArgs;
5839 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOSDBlendingFormula(pInstance, pXCArgs->enOsdIndex, pXCArgs->enType, pXCArgs->eWindow);
5840
5841 u32Return = UTOPIA_STATUS_SUCCESS;
5842 break;
5843 }
5844
5845
5846 case E_XC_CMD_GET_REPORT_PIXEL_INFO:
5847 {
5848
5849
5850 pstXC_GET_REPORT_PIXEL_INFO pXCArgs = (pstXC_GET_REPORT_PIXEL_INFO) pArgs;
5851 pXCArgs->bReturnValue = psXCInstPri->fpXC_ReportPixelInfo(pInstance, pXCArgs->pstRepPixInfo);
5852
5853 u32Return = UTOPIA_STATUS_SUCCESS;
5854 break;
5855 }
5856
5857
5858 case E_XC_CMD_SET_SCALING:
5859 {
5860
5861
5862 pstXC_SET_SCALING pXCArgs = (pstXC_SET_SCALING) pArgs;
5863 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5864 USE_OTHER_SC_AS_SUB_WINDOW();
5865 #endif
5866 psXCInstPri->fpXC_SetScaling(pInstance, pXCArgs->bEnable, pXCArgs->eScaling_type, pXCArgs->eVector_type, pXCArgs->eWindow);
5867
5868
5869 u32Return = UTOPIA_STATUS_SUCCESS;
5870 break;
5871 }
5872
5873
5874 case E_XC_CMD_SET_MCDI_BUFFERADDRESS:
5875 {
5876
5877
5878 pstXC_SET_MCDI_BUFFERADDRESS pXCArgs = (pstXC_SET_MCDI_BUFFERADDRESS) pArgs;
5879 psXCInstPri->fpXC_SetMCDIBufferAddress(pInstance, pXCArgs->u32FBAddress, pXCArgs->u32FBSize, pXCArgs->eType);
5880 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5881 CHECK_DEVICE1_INSTANCE();
5882 psXCInstPri->fpXC_SetMCDIBufferAddress(g_pDevice1Instance, pXCArgs->u32FBAddress, pXCArgs->u32FBSize, pXCArgs->eType);
5883 #endif
5884
5885 u32Return = UTOPIA_STATUS_SUCCESS;
5886 break;
5887 }
5888
5889
5890 case E_XC_CMD_SET_MCDI_ENABLE:
5891 {
5892
5893
5894 pstXC_SET_MCDI_ENABLE pXCArgs = (pstXC_SET_MCDI_ENABLE) pArgs;
5895 psXCInstPri->fpXC_EnableMCDI(pInstance, pXCArgs->bEnable, pXCArgs->eType);
5896 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5897 CHECK_DEVICE1_INSTANCE();
5898 psXCInstPri->fpXC_EnableMCDI(g_pDevice1Instance, pXCArgs->bEnable, pXCArgs->eType);
5899 #endif
5900
5901
5902 u32Return = UTOPIA_STATUS_SUCCESS;
5903 break;
5904 }
5905
5906
5907 case E_XC_CMD_SEND_CMD2FRC:
5908 {
5909
5910
5911 pstXC_SEND_CMD2FRC pXCArgs = (pstXC_SEND_CMD2FRC) pArgs;
5912 pXCArgs->bReturnValue = psXCInstPri->fpXC_SendCmdToFRC(pInstance, pXCArgs->u8Cmd, pXCArgs->count, pXCArgs->pFRC_R2_Para);
5913
5914
5915 u32Return = UTOPIA_STATUS_SUCCESS;
5916 break;
5917 }
5918
5919
5920 case E_XC_CMD_GET_MSG_FROM_FRC:
5921 {
5922
5923
5924 pstXC_GET_MSG_FROM_FRC pXCArgs = (pstXC_GET_MSG_FROM_FRC) pArgs;
5925 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetMsgFromFRC(pInstance, pXCArgs->pu8Cmd, pXCArgs->pu8ParaCount, pXCArgs->pu8Para);
5926
5927
5928 u32Return = UTOPIA_STATUS_SUCCESS;
5929 break;
5930 }
5931
5932
5933 case E_XC_CMD_SET_AUTO_RWBANK_ENABLE:
5934 {
5935
5936
5937 pstXC_SET_AUTO_RWBANK_ENABLE pXCArgs = (pstXC_SET_AUTO_RWBANK_ENABLE) pArgs;
5938 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5939 USE_OTHER_SC_AS_SUB_WINDOW();
5940 #endif
5941 psXCInstPri->fpXC_EnableRWBankAuto(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5942
5943
5944 u32Return = UTOPIA_STATUS_SUCCESS;
5945 break;
5946 }
5947
5948
5949 case E_XC_CMD_SET_RWBANK_MAPPING_NUM:
5950 {
5951
5952
5953 pstXC_SET_RWBANK_MAPPING_NUM pXCArgs = (pstXC_SET_RWBANK_MAPPING_NUM) pArgs;
5954 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5955 USE_OTHER_SC_AS_SUB_WINDOW();
5956 #endif
5957 psXCInstPri->fpXC_SetWRBankMappingNum(pInstance, pXCArgs->u8Val, pXCArgs->eWindow);
5958
5959
5960 u32Return = UTOPIA_STATUS_SUCCESS;
5961 break;
5962 }
5963
5964
5965 case E_XC_CMD_GET_RWBANK_MAPPING_NUM:
5966 {
5967 pstXC_GET_RWBANK_MAPPING_NUM pXCArgs = (pstXC_GET_RWBANK_MAPPING_NUM) pArgs;
5968 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5969 USE_OTHER_SC_AS_SUB_WINDOW();
5970 #endif
5971 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_GetWRBankMappingNum(pInstance, pXCArgs->eWindow);
5972
5973 u32Return = UTOPIA_STATUS_SUCCESS;
5974 break;
5975 }
5976
5977 case E_XC_CMD_GET_RWBANK_MAPPING_NUM_FOR_ZAP:
5978 {
5979 pstXC_GET_RWBANK_MAPPING_NUM_FOR_ZAP pXCArgs = (pstXC_GET_RWBANK_MAPPING_NUM_FOR_ZAP) pArgs;
5980 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5981 USE_OTHER_SC_AS_SUB_WINDOW();
5982 #endif
5983 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_GetWRBankMappingNumForZap(pInstance, pXCArgs->eWindow);
5984
5985 u32Return = UTOPIA_STATUS_SUCCESS;
5986 break;
5987 }
5988
5989 case E_XC_CMD_SET_BOBMODE:
5990 {
5991 pstXC_SET_BOBMODE pXCArgs = (pstXC_SET_BOBMODE) pArgs;
5992 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5993 USE_OTHER_SC_AS_SUB_WINDOW();
5994 #endif
5995 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetBOBMode(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
5996
5997 u32Return = UTOPIA_STATUS_SUCCESS;
5998 break;
5999 }
6000
6001 case E_XC_CMD_SET_FORCE_READBANK:
6002 {
6003 pstXC_SET_FORCE_READBANK pXCArgs = (pstXC_SET_FORCE_READBANK) pArgs;
6004 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6005 USE_OTHER_SC_AS_SUB_WINDOW();
6006 #endif
6007 psXCInstPri->fpXC_SetForceReadBank(pInstance, pXCArgs->bEnable,pXCArgs->u8Bank, pXCArgs->eWindow);
6008
6009 u32Return = UTOPIA_STATUS_SUCCESS;
6010 break;
6011 }
6012
6013 case E_XC_CMD_SET_LOCK_POINT:
6014 {
6015 pstXC_SET_LOCK_POINT pXCArgs = (pstXC_SET_LOCK_POINT) pArgs;
6016 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6017 USE_OTHER_SC_AS_SUB_WINDOW();
6018 #endif
6019 psXCInstPri->fpXC_SetLockPoint(pInstance, pXCArgs->u16LockPoint, pXCArgs->eWindow);
6020
6021 u32Return = UTOPIA_STATUS_SUCCESS;
6022 break;
6023 }
6024
6025 case E_XC_CMD_LD_INIT:
6026 {
6027 pstXC_LD_INIT pXCArgs = (pstXC_LD_INIT) pArgs;
6028 pXCArgs->bReturnValue = psXCInstPri->fpXC_LD_Init(pInstance, pXCArgs->enLDPanelType);
6029
6030 u32Return = UTOPIA_STATUS_SUCCESS;
6031 break;
6032 }
6033
6034
6035 case E_XC_CMD_SET_LD_MEMORYADDRESS:
6036 {
6037 pstXC_SET_LD_MEMORYADDRESS pXCArgs = (pstXC_SET_LD_MEMORYADDRESS) pArgs;
6038 pXCArgs->bReturnValue = psXCInstPri->fpXC_LD_SetMemoryAddress(pInstance,
6039 pXCArgs->u8MIU,
6040 pXCArgs->u32LDFBase0,
6041 pXCArgs->u32LDFBase1,
6042 pXCArgs->u32LDBBase0,
6043 pXCArgs->u32LDBBase1,
6044 pXCArgs->u32EDGE2DBase,
6045 pXCArgs->u32LEDOffset);
6046
6047
6048 u32Return = UTOPIA_STATUS_SUCCESS;
6049 break;
6050 }
6051
6052 case E_XC_CMD_GET_LD_VALUE:
6053 {
6054 pstXC_GET_LD_VALUE pXCArgs = (pstXC_GET_LD_VALUE) pArgs;
6055 pXCArgs->bReturnValue = psXCInstPri->fpXC_LD_Get_Value(pInstance,
6056 pXCArgs->pu8LDValue,
6057 pXCArgs->u8WSize,
6058 pXCArgs->u8HSize);
6059
6060
6061 u32Return = UTOPIA_STATUS_SUCCESS;
6062 break;
6063 }
6064
6065 case E_XC_CMD_SET_LD_LEVEL:
6066 {
6067
6068
6069 pstXC_SET_LD_LEVEL pXCArgs = (pstXC_SET_LD_LEVEL) pArgs;
6070 pXCArgs->bReturnValue = psXCInstPri->fpXC_LD_SetLevel(pInstance, pXCArgs->enMode);
6071
6072
6073 u32Return = UTOPIA_STATUS_SUCCESS;
6074 break;
6075 }
6076
6077
6078 case E_XC_CMD_SET_LD_TURNOFF_LDBL:
6079 {
6080
6081
6082 pstXC_SET_LD_TURNOFF_LDBL pXCArgs = (pstXC_SET_LD_TURNOFF_LDBL) pArgs;
6083 pXCArgs->bReturnValue = psXCInstPri->fpSet_TurnoffLDBL(pInstance, pXCArgs->bTurnoffBL);
6084
6085
6086 u32Return = UTOPIA_STATUS_SUCCESS;
6087 break;
6088 }
6089
6090
6091 case E_XC_CMD_SET_NOTUPDATE_SPI_DATA_FLAGS:
6092 {
6093
6094
6095 pstXC_SET_NOTUPDATE_SPI_DATA_FLAGS pXCArgs = (pstXC_SET_NOTUPDATE_SPI_DATA_FLAGS) pArgs;
6096 pXCArgs->bReturnValue = psXCInstPri->fpSet_notUpdateSPIDataFlags(pInstance, pXCArgs->bRefreshSPIData);
6097
6098
6099 u32Return = UTOPIA_STATUS_SUCCESS;
6100 break;
6101 }
6102
6103
6104 case E_XC_CMD_SET_LD_USERMODEFLAGS:
6105 {
6106
6107
6108 pstXC_SET_LD_USERMODEFLAGS pXCArgs = (pstXC_SET_LD_USERMODEFLAGS) pArgs;
6109 pXCArgs->bReturnValue = psXCInstPri->fpSet_UsermodeLDFlags(pInstance, pXCArgs->bUserLDFlags);
6110
6111
6112 u32Return = UTOPIA_STATUS_SUCCESS;
6113 break;
6114 }
6115
6116
6117 case E_XC_CMD_SET_BL_LEVEL:
6118 {
6119
6120
6121 pstXC_SET_BL_LEVEL pXCArgs = (pstXC_SET_BL_LEVEL) pArgs;
6122 pXCArgs->bReturnValue = psXCInstPri->fpSet_BLLevel(pInstance, pXCArgs->u8BLLevel);
6123
6124
6125 u32Return = UTOPIA_STATUS_SUCCESS;
6126 break;
6127 }
6128
6129
6130 case E_XC_CMD_SET_BWS_MODE:
6131 {
6132
6133
6134 pstXC_SET_BWS_MODE pXCArgs = (pstXC_SET_BWS_MODE) pArgs;
6135 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6136 USE_OTHER_SC_AS_SUB_WINDOW();
6137 #endif
6138 psXCInstPri->fpXC_Set_BWS_Mode(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
6139
6140
6141 u32Return = UTOPIA_STATUS_SUCCESS;
6142 break;
6143 }
6144
6145
6146 case E_XC_CMD_SET_FRC_COLOR_PATH_CONTROL:
6147 {
6148
6149
6150 pstXC_SET_FRC_COLOR_PATH_CONTROL pXCArgs = (pstXC_SET_FRC_COLOR_PATH_CONTROL) pArgs;
6151 psXCInstPri->fpXC_FRC_ColorPathCtrl(pInstance, pXCArgs->u16Path_sel, pXCArgs->bEnable);
6152
6153
6154 u32Return = UTOPIA_STATUS_SUCCESS;
6155 break;
6156 }
6157
6158
6159 case E_XC_CMD_SET_FRC_OP2_RGBGAIN:
6160 {
6161
6162
6163 pstXC_SET_FRC_OP2_RGBGAIN pXCArgs = (pstXC_SET_FRC_OP2_RGBGAIN) pArgs;
6164 psXCInstPri->fpXC_FRC_OP2_SetRGBGain(pInstance, pXCArgs->u16RedGain, pXCArgs->u16GreenGain, pXCArgs->u16BlueGain);
6165
6166
6167 u32Return = UTOPIA_STATUS_SUCCESS;
6168 break;
6169 }
6170
6171
6172 case E_XC_CMD_SET_FRC_OP2_RGBOFFSET:
6173 {
6174
6175
6176 pstXC_SET_FRC_OP2_RGBOFFSET pXCArgs = (pstXC_SET_FRC_OP2_RGBOFFSET) pArgs;
6177 psXCInstPri->fpXC_FRC_OP2_SetRGBOffset(pInstance, pXCArgs->u16RedOffset, pXCArgs->u16GreenOffset, pXCArgs->u16BlueOffset);
6178
6179
6180 u32Return = UTOPIA_STATUS_SUCCESS;
6181 break;
6182 }
6183
6184
6185 case E_XC_CMD_SET_FRC_OP2_DITHER:
6186 {
6187
6188
6189 pstXC_SET_FRC_OP2_DITHER pXCArgs = (pstXC_SET_FRC_OP2_DITHER) pArgs;
6190 psXCInstPri->fpXC_FRC_OP2_SetDither(pInstance, pXCArgs->u16dither);
6191
6192
6193 u32Return = UTOPIA_STATUS_SUCCESS;
6194 break;
6195 }
6196
6197
6198 case E_XC_CMD_FRC_BYPASS:
6199 {
6200
6201
6202 pstXC_FRC_BYPASS pXCArgs = (pstXC_FRC_BYPASS) pArgs;
6203 pXCArgs->bReturnValue = psXCInstPri->fpXC_FRC_BypassMFC(pInstance, pXCArgs->bEnable);
6204
6205
6206 u32Return = UTOPIA_STATUS_SUCCESS;
6207 break;
6208 }
6209
6210 case E_XC_CMD_FRC_MUTE:
6211 {
6212
6213
6214 pstXC_FRC_MUTE pXCArgs = (pstXC_FRC_MUTE) pArgs;
6215 psXCInstPri->fpXC_FRC_Mute(pInstance, pXCArgs->bEnable);
6216
6217
6218 u32Return = UTOPIA_STATUS_SUCCESS;
6219 break;
6220 }
6221
6222 case E_XC_CMD_SET_FORCE_READ_FRAME:
6223 {
6224
6225
6226 pstXC_SET_FORCE_READ_FRAME pXCArgs = (pstXC_SET_FORCE_READ_FRAME) pArgs;
6227 pXCArgs->eReturnValue = psXCInstPri->fpXC_ForceReadFrame(pInstance, pXCArgs->bEnable, pXCArgs->u16FrameIndex);
6228 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6229 CHECK_DEVICE1_INSTANCE();
6230 pXCArgs->eReturnValue = psXCInstPri->fpXC_ForceReadFrame(g_pDevice1Instance, pXCArgs->bEnable, pXCArgs->u16FrameIndex);
6231 #endif
6232
6233 u32Return = UTOPIA_STATUS_SUCCESS;
6234 break;
6235 }
6236
6237
6238 case E_XC_CMD_SET_CSC:
6239 {
6240
6241
6242 pstXC_SET_CSC pXCArgs = (pstXC_SET_CSC) pArgs;
6243 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6244 USE_OTHER_SC_AS_SUB_WINDOW();
6245 #endif
6246 psXCInstPri->fpXC_SetCsc(pInstance, pXCArgs->bEnable, pXCArgs->eWindow);
6247
6248
6249 u32Return = UTOPIA_STATUS_SUCCESS;
6250 break;
6251 }
6252
6253
6254 case E_XC_CMD_SET_REGISTER_PQ_FPLL_THRESH_MODE:
6255 {
6256
6257
6258 pstXC_SET_REGISTER_PQ_FPLL_THRESH_MODE pXCArgs = (pstXC_SET_REGISTER_PQ_FPLL_THRESH_MODE) pArgs;
6259 psXCInstPri->fpXC_RegisterPQSetFPLLThreshMode(pInstance, pXCArgs->fpPQCB);
6260
6261
6262 u32Return = UTOPIA_STATUS_SUCCESS;
6263 break;
6264 }
6265
6266 case E_XC_CMD_GET_FREERUN_STATUS:
6267 {
6268 pstXC_GET_FREERUN_STATUS pXCArgs = (pstXC_GET_FREERUN_STATUS) pArgs;
6269 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetFreeRunStatus(pInstance);
6270
6271 u32Return = UTOPIA_STATUS_SUCCESS;
6272 break;
6273 }
6274
6275 case E_XC_CMD_SET_BYPASS_CSC:
6276 {
6277 pstXC_SET_BYPASS_CSC pXCArgs = (pstXC_SET_BYPASS_CSC) pArgs;
6278 psXCInstPri->fpXC_BYPASS_SetCSC(pInstance, pXCArgs->bEnable);
6279
6280 u32Return = UTOPIA_STATUS_SUCCESS;
6281 break;
6282 }
6283
6284 case E_XC_CMD_GET_DS_FORCE_INDEX_SUPPORTED:
6285 {
6286 pstXC_GET_DS_FORCE_INDEX_SUPPORTED pXCArgs = (pstXC_GET_DS_FORCE_INDEX_SUPPORTED) pArgs;
6287 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6288 USE_OTHER_SC_AS_SUB_WINDOW();
6289 #endif
6290 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_DSForceIndexSupported(pInstance, pXCArgs->eWindow);
6291
6292
6293 u32Return = UTOPIA_STATUS_SUCCESS;
6294 break;
6295 }
6296
6297
6298 case E_XC_CMD_SET_DS_FORCE_INDEX:
6299 {
6300
6301
6302 pstXC_SET_DS_FORCE_INDEX pXCArgs = (pstXC_SET_DS_FORCE_INDEX) pArgs;
6303 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6304 USE_OTHER_SC_AS_SUB_WINDOW();
6305 #endif
6306 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_DSForceIndex(pInstance, pXCArgs->bEnable, pXCArgs->u8Index, pXCArgs->eWindow);
6307
6308
6309 u32Return = UTOPIA_STATUS_SUCCESS;
6310 break;
6311 }
6312
6313
6314 case E_XC_CMD_SET_DS_INDEX_SOURCE_SELECT:
6315 {
6316 pstXC_SET_DS_INDEX_SOURCE_SELECT pXCArgs = (pstXC_SET_DS_INDEX_SOURCE_SELECT) pArgs;
6317 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6318 USE_OTHER_SC_AS_SUB_WINDOW();
6319 #endif
6320 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_DSIndexSourceSelect(pInstance, pXCArgs->eDSIdxSrc, pXCArgs->eWindow);
6321
6322 u32Return = UTOPIA_STATUS_SUCCESS;
6323 break;
6324 }
6325
6326 case E_XC_CMD_GET_DS_STATUS:
6327 {
6328 pstXC_GET_DS_STATUS pXCArgs = (pstXC_GET_DS_STATUS) pArgs;
6329 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetDynamicScalingStatus(pInstance);
6330
6331 u32Return = UTOPIA_STATUS_SUCCESS;
6332 break;
6333 }
6334
6335 case E_XC_CMD_OSDC_INITSETTING:
6336 {
6337 pstXC_OSDC_INITSETTING pXCArgs = (pstXC_OSDC_INITSETTING) pArgs;
6338 pXCArgs->eReturnValue = psXCInstPri->fpXC_OSDC_InitSetting(pInstance, pXCArgs->e_osdctgen_type, pXCArgs->pstOC_Tgen_Cus, pXCArgs->pstOC_Ctrl);
6339
6340 u32Return = UTOPIA_STATUS_SUCCESS;
6341 break;
6342 }
6343
6344 case E_XC_CMD_OSDC_SET_OUTPUTVFREQX10:
6345 {
6346 pstXC_OSDC_SET_OUTPUTVFREQX10 pXCArgs = (pstXC_OSDC_SET_OUTPUTVFREQX10) pArgs;
6347 psXCInstPri->fpXC_OSDC_SetOutVfreqx10(pInstance, pXCArgs->u16Vfreq);
6348
6349 u32Return = UTOPIA_STATUS_SUCCESS;
6350 break;
6351 }
6352
6353 case E_XC_CMD_OSDC_CONTROL:
6354 {
6355
6356
6357 pstXC_OSDC_CONTROL pXCArgs = (pstXC_OSDC_CONTROL) pArgs;
6358 pXCArgs->eReturnValue = psXCInstPri->fpXC_OSDC_Control(pInstance, pXCArgs->eCtrl_type);
6359
6360
6361 u32Return = UTOPIA_STATUS_SUCCESS;
6362 break;
6363 }
6364
6365
6366 case E_XC_CMD_OSDC_GET_DESTINATION_INFO:
6367 {
6368 pstXC_OSDC_GET_DESTINATION_INFO pXCArgs = (pstXC_OSDC_GET_DESTINATION_INFO) pArgs;
6369 pXCArgs->eReturnValue = psXCInstPri->fpXC_OSDC_GetDstInfo(pInstance, pXCArgs->pDstInfo, pXCArgs->u32SizeofDstInfo);
6370
6371 u32Return = UTOPIA_STATUS_SUCCESS;
6372 break;
6373 }
6374
6375 case E_XC_CMD_SET_POWERSTATE:
6376 {
6377 pstXC_SET_POWERSTATE pXCArgs = (pstXC_SET_POWERSTATE) pArgs;
6378 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_Set_PowerState(pInstance, pXCArgs->enPowerState);
6379
6380 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6381 CHECK_DEVICE1_INSTANCE();
6382 psXCInstPri->fpXC_Set_PowerState(g_pDevice1Instance, pXCArgs->enPowerState);
6383 #endif
6384
6385 u32Return = UTOPIA_STATUS_SUCCESS;
6386 break;
6387 }
6388
6389 case E_XC_CMD_SET_BYPASS_OSDVSYNC_POS:
6390 {
6391 pstXC_SET_BYPASS_OSDVSYNC_POS pXCArgs = (pstXC_SET_BYPASS_OSDVSYNC_POS) pArgs;
6392 psXCInstPri->fpXC_BYPASS_SetOSDVsyncPos(pInstance, pXCArgs->u16VsyncStart, pXCArgs->u16VsyncEnd);
6393
6394 u32Return = UTOPIA_STATUS_SUCCESS;
6395 break;
6396 }
6397
6398 case E_XC_CMD_SET_BYPASS_INPUTSRC:
6399 {
6400 pstXC_SET_BYPASS_INPUTSRC pXCArgs = (pstXC_SET_BYPASS_INPUTSRC) pArgs;
6401 psXCInstPri->fpXC_BYPASS_SetInputSrc(pInstance, pXCArgs->bEnable, pXCArgs->input);
6402
6403 u32Return = UTOPIA_STATUS_SUCCESS;
6404 break;
6405 }
6406
6407 case E_XC_CMD_SET_SEAMLESS_ZAPPING:
6408 {
6409 pstXC_SET_SEAMLESS_ZAPPING pXCArgs = (pstXC_SET_SEAMLESS_ZAPPING) pArgs;
6410 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6411 USE_OTHER_SC_AS_SUB_WINDOW();
6412 #endif
6413 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetSeamlessZapping(pInstance, pXCArgs->eWindow, pXCArgs->bEnable);
6414
6415 u32Return = UTOPIA_STATUS_SUCCESS;
6416 break;
6417 }
6418
6419 case E_XC_CMD_GET_SEAMLESS_ZAPPING_STATUS:
6420 {
6421 pstXC_GET_SEAMLESS_ZAPPING_STATUS pXCArgs = (pstXC_GET_SEAMLESS_ZAPPING_STATUS) pArgs;
6422 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6423 USE_OTHER_SC_AS_SUB_WINDOW();
6424 #endif
6425 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetSeamlessZappingStatus(pInstance, pXCArgs->eWindow, pXCArgs->pbEnable);
6426
6427 u32Return = UTOPIA_STATUS_SUCCESS;
6428 break;
6429 }
6430
6431 case E_XC_CMD_SET_VTRACK_PAYLOADDATA:
6432 {
6433 pstXC_SET_VTRACK_PAYLOADDATA pXCArgs = (pstXC_SET_VTRACK_PAYLOADDATA) pArgs;
6434 pXCArgs->eReturnValue = psXCInstPri->fpXC_Vtrack_SetPayloadData(pInstance, pXCArgs->u16Timecode, pXCArgs->u8OperatorID);
6435
6436 u32Return = UTOPIA_STATUS_SUCCESS;
6437 break;
6438 }
6439
6440 case E_XC_CMD_SET_VTRACK_USERDEFINED_SETTING:
6441 {
6442 pstXC_SET_VTRACK_USERDEFINED_SETTING pXCArgs = (pstXC_SET_VTRACK_USERDEFINED_SETTING) pArgs;
6443 pXCArgs->eReturnValue = psXCInstPri->fpXC_Vtrack_SetUserDefindedSetting(pInstance, pXCArgs->bUserDefinded, pXCArgs->pu8Setting);
6444
6445 u32Return = UTOPIA_STATUS_SUCCESS;
6446 break;
6447 }
6448
6449 case E_XC_CMD_SET_VTRACK_ENABLE:
6450 {
6451 pstXC_SET_VTRACK_ENABLE pXCArgs = (pstXC_SET_VTRACK_ENABLE) pArgs;
6452 pXCArgs->eReturnValue = psXCInstPri->fpXC_Vtrack_Enable(pInstance, pXCArgs->u8FrameRate, pXCArgs->bEnable);
6453
6454 u32Return = UTOPIA_STATUS_SUCCESS;
6455 break;
6456 }
6457
6458 case E_XC_CMD_PRESET_PQINFO:
6459 {
6460 pstXC_PRESET_PQINFO pXCArgs = (pstXC_PRESET_PQINFO) pArgs;
6461 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6462 USE_OTHER_SC_AS_SUB_WINDOW();
6463 #endif
6464 psXCInstPri->fpXC_PreSetPQInfo(pInstance, pXCArgs->pstXC_SetWin_Info, pXCArgs->eWindow);
6465
6466 u32Return = UTOPIA_STATUS_SUCCESS;
6467 break;
6468 }
6469
6470 case E_XC_GET_OP1_TESTPATTERN_ENABLED:
6471 {
6472 pstXC_GET_OP1_TESTPATTERN_ENABLED pXCArgs = (pstXC_GET_OP1_TESTPATTERN_ENABLED) pArgs;
6473 pXCArgs->bReturnValue= psXCInstPri->fpXC_Is_OP1_TestPattern_Enabled(pInstance);
6474
6475 u32Return = UTOPIA_STATUS_SUCCESS;
6476 break;
6477 }
6478
6479 case E_XC_SET_OP1_TESTPATTERN:
6480 {
6481 pstXC_SET_OP1_TESTPATTERN pXCArgs = (pstXC_SET_OP1_TESTPATTERN) pArgs;
6482 pXCArgs->eReturnValue= psXCInstPri->fpXC_Set_OP1_TestPattern(pInstance,pXCArgs->ePattern,pXCArgs->eMode);
6483
6484 u32Return = UTOPIA_STATUS_SUCCESS;
6485 break;
6486 }
6487
6488
6489 case E_XC_SET_OP2_TESTPATTERN:
6490 {
6491 pstXC_SET_OP2_TESTPATTERN pXCArgs = (pstXC_SET_OP2_TESTPATTERN) pArgs;
6492 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_OP2_TestPattern(pInstance
6493 ,pXCArgs->bEnable
6494 ,pXCArgs->u16R_Data
6495 ,pXCArgs->u16G_Data
6496 ,pXCArgs->u16B_Data);
6497
6498 u32Return = UTOPIA_STATUS_SUCCESS;
6499 break;
6500 }
6501 case E_XC_CHECK_WHITEBALANCE_PATTERN_MODE:
6502 {
6503 pstXC_CHECK_WB_TESTPATTERN pXCArgs = (pstXC_CHECK_WB_TESTPATTERN) pArgs;
6504 pXCArgs->eReturnValue = psXCInstPri->fpXC_Check_WhiteBalance_Pattern_Mode(pInstance
6505 ,pXCArgs->eWBPattern
6506 );
6507
6508 u32Return = UTOPIA_STATUS_SUCCESS;
6509 break;
6510 }
6511 case E_XC_SET_HLINEARSCALING:
6512 {
6513 pstXC_SET_HLINEARSCALING pXCArgs = (pstXC_SET_HLINEARSCALING) pArgs;
6514 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6515 USE_OTHER_SC_AS_SUB_WINDOW();
6516 #endif
6517 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_HLinearScaling(pInstance
6518 ,pXCArgs->bEnable
6519 ,pXCArgs->bSign
6520 ,pXCArgs->u16Delta
6521 ,pXCArgs->eWindow);
6522
6523 u32Return = UTOPIA_STATUS_SUCCESS;
6524 break;
6525 }
6526 case E_XC_SET_ENABLE_T3D:
6527 {
6528 pstXC_EnableT3D pXCArgs = (pstXC_EnableT3D) pArgs;
6529 pXCArgs->eReturnValue = psXCInstPri->fpXC_EnableT3D(pInstance
6530 ,pXCArgs->bEnable);
6531
6532 u32Return = UTOPIA_STATUS_SUCCESS;
6533 break;
6534 }
6535 case E_XC_SET_FRC_INPUTTIMING:
6536 {
6537 pstXC_Set_FRC_InputTiming pXCArgs = (pstXC_Set_FRC_InputTiming) pArgs;
6538 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_FRC_InputTiming(pInstance
6539 ,pXCArgs->enFRC_InputTiming);
6540
6541 u32Return = UTOPIA_STATUS_SUCCESS;
6542 break;
6543 }
6544 case E_XC_GET_FRC_INPUTTIMING:
6545 {
6546 pstXC_Get_FRC_InputTiming pXCArgs = (pstXC_Get_FRC_InputTiming) pArgs;
6547 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_FRC_InputTiming(pInstance, pXCArgs->penFRC_InputTiming);
6548
6549 u32Return = UTOPIA_STATUS_SUCCESS;
6550 break;
6551 }
6552 case E_XC_CMD_GET_VBOX_INFO:
6553 {
6554 pstXC_Get_VBOX_Info pXCArgs = (pstXC_Get_VBOX_Info) pArgs;
6555 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_VirtualBox_Info(pInstance, pXCArgs->pstXC_VboxInfo);
6556
6557 u32Return = UTOPIA_STATUS_SUCCESS;
6558 break;
6559 }
6560 case E_XC_SET_OSD_DETECT:
6561 {
6562 pstXC_Set_OSD_DETECT pXCArgs = (pstXC_Set_OSD_DETECT) pArgs;
6563 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_OSD_DETECT(pInstance, pXCArgs->bEnable,pXCArgs->Threhold);
6564 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6565 CHECK_DEVICE1_INSTANCE();
6566 pXCArgs->eReturnValue = psXCInstPri->fpXC_Set_OSD_DETECT(g_pDevice1Instance, pXCArgs->bEnable,pXCArgs->Threhold);
6567 #endif
6568 u32Return = UTOPIA_STATUS_SUCCESS;
6569 break;
6570 }
6571 case E_XC_GET_OSD_DETECT:
6572 {
6573 pstXC_Get_OSD_DETECT pXCArgs = (pstXC_Get_OSD_DETECT) pArgs;
6574 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_OSD_DETECT(pInstance, pXCArgs->pbOSD);
6575 /*
6576 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6577 CHECK_DEVICE1_INSTANCE();
6578 pXCArgs->eReturnValue = psXCInstPri->fpXC_Get_OSD_DETECT(g_pDevice1Instance, pXCArgs->pbOSD);
6579 #endif
6580 */
6581 u32Return = UTOPIA_STATUS_SUCCESS;
6582 break;
6583 }
6584 case E_XC_ENABLE_LOCKFREQONLY:
6585 {
6586 pstXC_Enable_LockFreqOnly pXCArgs = (pstXC_Enable_LockFreqOnly) pArgs;
6587 pXCArgs->eReturnValue = psXCInstPri->fpXC_Enable_LockFreqOnly(pInstance, pXCArgs->bEnable);
6588
6589 u32Return = UTOPIA_STATUS_SUCCESS;
6590 break;
6591 }
6592 case E_XC_IS2K2KTOFRCMODE:
6593 {
6594 pstXC_Is2K2KToFrcMode pXCArgs = (pstXC_Is2K2KToFrcMode) pArgs;
6595 pXCArgs->bReturnValue = psXCInstPri->fpXC_Is2K2KToFrcMode(pInstance);
6596
6597 u32Return = UTOPIA_STATUS_SUCCESS;
6598 break;
6599 }
6600 case E_XC_CMD_SET_XC_VOP:
6601 {
6602 pstXC_SetXC_VOP pXCArgs = (pstXC_SetXC_VOP) pArgs;
6603 pXCArgs->bReturn = psXCInstPri->fpXC_SetXCVOPdata(pInstance, pXCArgs->stXC_VOPData);
6604
6605 u32Return = UTOPIA_STATUS_SUCCESS;
6606 break;
6607 }
6608
6609 // OBSOLETE command **START**, please avoid using these
6610 case E_XC_CMD_GET_OUTPUT_VFREQ:
6611 {
6612
6613
6614 pstXC_SetXC_VOP pXCArgs = (pstXC_SetXC_VOP) pArgs;
6615 pXCArgs->bReturn = psXCInstPri->fpsc_get_output_vfreq(pInstance);
6616
6617
6618 u32Return = UTOPIA_STATUS_SUCCESS;
6619 break;
6620 }
6621
6622
6623 case E_XC_CMD_GET_CURRENT_OUTPUTVFREQX100:
6624 {
6625
6626
6627 pstXC_GET_CURRENT_OUTPUTVFREQX100 pXCArgs = (pstXC_GET_CURRENT_OUTPUTVFREQX100) pArgs;
6628 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_Get_Current_OutputVFreqX100(pInstance);
6629
6630
6631 u32Return = UTOPIA_STATUS_SUCCESS;
6632 break;
6633 }
6634
6635
6636 case E_XC_CMD_SET_MEMORY_WRITE_REQUEST:
6637 {
6638
6639
6640 pstXC_SET_MEMORY_WRITE_REQUEST pXCArgs = (pstXC_SET_MEMORY_WRITE_REQUEST) pArgs;
6641 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetMemoryWriteRequest(pInstance, pXCArgs->bEnable);
6642
6643
6644 u32Return = UTOPIA_STATUS_SUCCESS;
6645 break;
6646 }
6647
6648
6649 case E_XC_CMD_SET_MEMORY_FORMAT:
6650 {
6651
6652
6653 pstXC_SET_MEMORY_FORMAT pXCArgs = (pstXC_SET_MEMORY_FORMAT) pArgs;
6654 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_MemFmt(pInstance, pXCArgs->eMemFmt);
6655
6656
6657 u32Return = UTOPIA_STATUS_SUCCESS;
6658 break;
6659 }
6660
6661
6662 case E_XC_CMD_SET_OUTPUT_ADJUST_SETTING:
6663 {
6664
6665
6666 pstXC_SET_OUTPUT_ADJUST_SETTING pXCArgs = (pstXC_SET_OUTPUT_ADJUST_SETTING) pArgs;
6667 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetOutputAdjustSetting(pInstance, pXCArgs->stAdjSetting);
6668
6669
6670 u32Return = UTOPIA_STATUS_SUCCESS;
6671 break;
6672 }
6673
6674
6675 case E_XC_CMD_SET_FPLL_FSM:
6676 {
6677
6678
6679 pstXC_SET_FPLL_FSM pXCArgs = (pstXC_SET_FPLL_FSM) pArgs;
6680 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6681 USE_OTHER_SC_AS_SUB_WINDOW();
6682 #endif
6683 psXCInstPri->fsScaler_FPLL_FSM(pInstance, pXCArgs->eWindow);
6684
6685
6686 u32Return = UTOPIA_STATUS_SUCCESS;
6687 break;
6688 }
6689
6690
6691 case E_XC_CMD_SET_MIRROR_MODE_ENABLE:
6692 {
6693
6694
6695 pstXC_SET_MIRROR_MODE_ENABLE pXCArgs = (pstXC_SET_MIRROR_MODE_ENABLE) pArgs;
6696 psXCInstPri->fpXC_EnableMirrorMode(pInstance, pXCArgs->bEnable);
6697
6698
6699 u32Return = UTOPIA_STATUS_SUCCESS;
6700 break;
6701 }
6702
6703
6704 case E_XC_CMD_SET_MIRROR_MODE2_ENABLE:
6705 {
6706
6707
6708 pstXC_SET_MIRROR_MODE2_ENABLE pXCArgs = (pstXC_SET_MIRROR_MODE2_ENABLE) pArgs;
6709 psXCInstPri->fpXC_EnableMirrorMode2(pInstance, pXCArgs->eMirrorMode);
6710
6711
6712 u32Return = UTOPIA_STATUS_SUCCESS;
6713 break;
6714 }
6715
6716 case E_XC_CMD_GET_SWDSIndex:
6717 {
6718 pstXC_GET_SWDSIndex pXCArgs = (pstXC_GET_SWDSIndex) pArgs;
6719 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_GetSWDSIndex(pInstance);
6720
6721 u32Return = UTOPIA_STATUS_SUCCESS;
6722 break;
6723 }
6724
6725 case E_XC_CMD_GET_IS_SupportSWDS:
6726 {
6727 pstXC_GET_Is_SupportSWDS pXCArgs = (pstXC_GET_Is_SupportSWDS) pArgs;
6728 pXCArgs->bEnable = psXCInstPri->fpXC_Get_Is_SupportSWDS(pInstance);
6729
6730 u32Return = UTOPIA_STATUS_SUCCESS;
6731 break;
6732 }
6733 #ifdef UFO_XC_SET_DSINFO_V0
6734 case E_XC_CMD_SET_DSINFO:
6735 {
6736 pstXC_SET_DSINFO pXCArgs = (pstXC_SET_DSINFO) pArgs;
6737 psXCInstPri->fpXC_SetDSInfo(pInstance,pXCArgs->pstSetDSInfo, pXCArgs->u32DSInfoLen, pXCArgs->eWindow);
6738
6739 u32Return = UTOPIA_STATUS_SUCCESS;
6740 break;
6741 }
6742 #endif
6743 case E_XC_CMD_GET_FRCM_FRAMENUM:
6744 {
6745
6746 pstXC_GET_FRCM_FRAMENUM pXCArgs = (pstXC_GET_FRCM_FRAMENUM) pArgs;
6747 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6748 USE_OTHER_SC_AS_SUB_WINDOW();
6749 #endif
6750 pXCArgs->u8ReturnValue = psXCInstPri->fpXC_Get_FRCM_FrameNum(pInstance, pXCArgs->eWindow);
6751
6752 u32Return = UTOPIA_STATUS_SUCCESS;
6753 break;
6754 }
6755
6756 case E_XC_CMD_SET_PIXEL_SHIFT_FEATURES:
6757 {
6758 pstXC_SET_PIXELSHIFT_FEATURES pXCArgs = (pstXC_SET_PIXELSHIFT_FEATURES) pArgs;
6759 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetPixelShiftFeatures(pInstance,
6760 pXCArgs->u16HPixelShiftRange,
6761 pXCArgs->u16VPixelShiftRange,
6762 pXCArgs->ePixelShiftFeature);
6763
6764 u32Return = UTOPIA_STATUS_SUCCESS;
6765 break;
6766 }
6767 case E_XC_CMD_DUMP_SHM:
6768 {
6769 psXCInstPri->fpXC_dump_shm(pInstance);
6770 break;
6771 }
6772 case E_XC_CMD_SET_BWD_CONFIG:
6773 {
6774 pstXC_SetBwdConfig pXCArgs = (pstXC_SetBwdConfig)pArgs;
6775 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6776 USE_OTHER_SC_AS_SUB_WINDOW();
6777 #endif
6778 pXCArgs->bReturnValue = psXCInstPri->fpXC_SetBwdConfig(pInstance,pXCArgs->eType,pXCArgs->pstParam, pXCArgs->eWindow);
6779 u32Return = UTOPIA_STATUS_SUCCESS;
6780 break;
6781 }
6782 #ifdef UFO_XC_SUPPORT_DUAL_MIU
6783 case E_XC_CMD_ENABLE_DUAL_MODE:
6784 {
6785 pstXC_EnableDualMode pXCArgs = (pstXC_EnableDualMode)pArgs;
6786 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6787 USE_OTHER_SC_AS_SUB_WINDOW();
6788 #endif
6789 pXCArgs->bReturnValue = psXCInstPri->fpXC_enableDualMode(pInstance,pXCArgs->bEnable,pXCArgs->u32LeftFactor, pXCArgs->u32RightFactor,pXCArgs->eWindow);
6790 u32Return = UTOPIA_STATUS_SUCCESS;
6791 break;
6792 }
6793 #endif
6794
6795 case E_XC_CMD_IS_SUPPORT_2_STEP_SCALING:
6796 {
6797 pstXC_IsSupport2StepScaling pXCArgs = (pstXC_IsSupport2StepScaling)pArgs;
6798 pXCArgs->bReturnValue = psXCInstPri->fpXC_IsSupport2StepScaling(pInstance);
6799 u32Return = UTOPIA_STATUS_SUCCESS;
6800 break;
6801 }
6802
6803 case E_XC_CMD_SET_FORCE_WRITE:
6804 {
6805
6806
6807 pstXC_SET_FORCE_WRITE pXCArgs = (pstXC_SET_FORCE_WRITE) pArgs;
6808 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetForceWrite(pInstance, pXCArgs->enMuteType, pXCArgs->bIsForceWrite);
6809
6810
6811 u32Return = UTOPIA_STATUS_SUCCESS;
6812 break;
6813 }
6814
6815 case E_XC_CMD_GET_FORCE_WRITE:
6816 {
6817 pstXC_GET_FORCE_WRITE pXCArgs = (pstXC_GET_FORCE_WRITE) pArgs;
6818 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetForceWrite(pInstance, pXCArgs->enMuteType);
6819
6820 u32Return = UTOPIA_STATUS_SUCCESS;
6821 break;
6822 }
6823 case E_XC_CMD_VIDEO_PLAYBACK_CTRL:
6824 {
6825 pstXC_VIDEO_PLAYBACK_CTRL pXCArgs = (pstXC_VIDEO_PLAYBACK_CTRL) pArgs;
6826 pXCArgs->eReturnValue = psXCInstPri->fpXC_VideoPlaybackCtrl(pInstance,pXCArgs->u32Cmd,pXCArgs->pCmdArgs,pXCArgs->u32CmdArgsSize);
6827
6828 u32Return = UTOPIA_STATUS_SUCCESS;
6829 break;
6830 }
6831
6832 #ifdef UFO_XC_PQ_PATH
6833 case E_XC_CMD_GET_PQ_PATH:
6834 {
6835 pstXC_GetPqPathStatus pXCArgs = (pstXC_GetPqPathStatus)pArgs;
6836 pXCArgs->bReturnValue = psXCInstPri->fpXC_GetPQPathStatus(pInstance, pXCArgs->ePqPathType, pXCArgs->u16Width, pXCArgs->u16Height);
6837 u32Return = UTOPIA_STATUS_SUCCESS;
6838 break;
6839 }
6840 #endif
6841
6842 #ifdef UFO_XC_AUTO_DOWNLOAD
6843 case E_XC_CMD_AUTODOWNLOAD_CONFIG_CTRL:
6844 {
6845 pstXC_AUTODOWNLOAD_CONFIG_CTRL pXCArgs = (pstXC_AUTODOWNLOAD_CONFIG_CTRL) pArgs;
6846 pXCArgs->eReturnValue = psXCInstPri->fpXC_AutoDownloadConfig(pInstance,pXCArgs->pstConfigInfo);
6847
6848 u32Return = UTOPIA_STATUS_SUCCESS;
6849 break;
6850 }
6851 case E_XC_CMD_AUTODOWNLOAD_WRITE_CTRL:
6852 {
6853 pstXC_AUTODOWNLOAD_WRITE_CTRL pXCArgs = (pstXC_AUTODOWNLOAD_WRITE_CTRL) pArgs;
6854 pXCArgs->eReturnValue = psXCInstPri->fpXC_AutoDownloadWrite(pInstance,pXCArgs->pstDataInfo);
6855
6856 u32Return = UTOPIA_STATUS_SUCCESS;
6857 break;
6858 }
6859 case E_XC_CMD_AUTODOWNLOAD_FIRE_CTRL:
6860 {
6861 pstXC_AUTODOWNLOAD_FIRE_CTRL pXCArgs = (pstXC_AUTODOWNLOAD_FIRE_CTRL) pArgs;
6862 pXCArgs->eReturnValue = psXCInstPri->fpXC_AutoDownloadFire(pInstance,pXCArgs->enClient);
6863
6864 u32Return = UTOPIA_STATUS_SUCCESS;
6865 break;
6866 }
6867 #endif
6868 #ifdef UFO_XC_HDR
6869 #if (UFO_XC_HDR_VERSION == 2)
6870 case E_XC_CMD_HDR_CTRL:
6871 {
6872 pstXC_HDR_CTRL pXCArgs = (pstXC_HDR_CTRL) pArgs;
6873 pXCArgs->eReturnValue = psXCInstPri->fpXC_HDRControl(pInstance,pXCArgs->enCtrlType,pXCArgs->pParam);
6874
6875 u32Return = UTOPIA_STATUS_SUCCESS;
6876 break;
6877 }
6878 #endif
6879 #endif
6880 #ifdef UFO_XC_SETBLACKVIDEOBYMODE
6881 case E_XC_CMD_SET_BLACKVIDEO_BYMODE:
6882 {
6883 pstXC_SET_BLACKVIDEO_BYMODE pXCArgs = (pstXC_SET_BLACKVIDEO_BYMODE) pArgs;
6884 pXCArgs->eReturnValue = psXCInstPri->fpXC_GenerateBlackVideoByMode(pInstance, pXCArgs->bEnable, pXCArgs->eWindow, pXCArgs->eMode);
6885
6886 u32Return = UTOPIA_STATUS_SUCCESS;
6887 break;
6888 }
6889 #endif
6890
6891 case E_XC_CMD_SWDS_FIRE:
6892 {
6893 pstXC_SWDS_FIRE pXCArgs = (pstXC_SWDS_FIRE) pArgs;
6894 psXCInstPri->fpXC_swds_fire(pInstance, pXCArgs->eWindow);
6895
6896 u32Return = UTOPIA_STATUS_SUCCESS;
6897 break;
6898 }
6899 case E_XC_CMD_OPTEE_CTL:
6900 {
6901 pstXC_OPTEE_CTRL pXCArgs = (pstXC_OPTEE_CTRL) pArgs;
6902 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6903 if(pXCArgs->xc_handler->eWindow == SUB_WINDOW)
6904 {
6905 CHECK_DEVICE1_INSTANCE();
6906 pInstance = g_pDevice1Instance;
6907 pXCArgs->xc_handler->eWindow = MAIN_WINDOW;
6908 }
6909 #endif
6910 pXCArgs->bReturn = psXCInstPri->fpXC_OPTEE_Ctrl(pInstance,pXCArgs->action, pXCArgs->xc_handler);
6911 u32Return = UTOPIA_STATUS_SUCCESS;
6912 break;
6913 }
6914 case E_XC_CMD_OPTEE_CHECKRBASE:
6915 {
6916 pstXC_OPTEE_CheckRBase pXCArgs = (pstXC_OPTEE_CheckRBase) pArgs;
6917 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6918 if(pXCArgs->eWindow == SUB_WINDOW)
6919 {
6920 CHECK_DEVICE1_INSTANCE();
6921 pInstance = g_pDevice1Instance;
6922 pXCArgs->eWindow = MAIN_WINDOW;
6923 }
6924 #endif
6925 pXCArgs->bReturn = psXCInstPri->fpXC_OPTEE_CheckRBase(pInstance,pXCArgs->eWindow);
6926 u32Return = UTOPIA_STATUS_SUCCESS;
6927 break;
6928 }
6929 case E_XC_CMD_OPTEE_MUX:
6930 {
6931 pstXC_OPTEE_MUX pXCArgs = (pstXC_OPTEE_MUX) pArgs;
6932 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6933 if(pXCArgs->xc_mux_data.eWindow == SUB_WINDOW)
6934 {
6935 CHECK_DEVICE1_INSTANCE();
6936 pInstance = g_pDevice1Instance;
6937 pXCArgs->xc_mux_data.eWindow = MAIN_WINDOW;
6938 }
6939 #endif
6940 pXCArgs->bReturn = psXCInstPri->fpXC_OPTEE_Mux(pInstance,pXCArgs->action, pXCArgs->xc_mux_data);
6941 u32Return = UTOPIA_STATUS_SUCCESS;
6942 break;
6943 }
6944 case E_XC_CMD_GET_RES_BY_PIPE:
6945 {
6946 pstXC_GetResourceByPipeID pXCArgs = (pstXC_GetResourceByPipeID) pArgs;
6947 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6948 if(pXCArgs->u32PipeID == pipeID_SC1_main)
6949 {
6950 CHECK_DEVICE1_INSTANCE();
6951 pInstance = g_pDevice1Instance;
6952 }
6953 #endif
6954 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_GetResourceByPipeID(pInstance,pXCArgs->u32PipeID,pXCArgs->U32RetResNum,pXCArgs->pResource);
6955
6956 u32Return = UTOPIA_STATUS_SUCCESS;
6957 break;
6958 }
6959 case E_XC_CMD_CONFIG_PIPE:
6960 {
6961 pstXC_ConfigPipe pXCArgs = (pstXC_ConfigPipe) pArgs;
6962 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6963 if(pXCArgs->u32PipeID == pipeID_SC1_main)
6964 {
6965 CHECK_DEVICE1_INSTANCE();
6966 pInstance = g_pDevice1Instance;
6967 }
6968 #endif
6969 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_ConfigPipe(pInstance,pXCArgs->u32PipeID,pXCArgs->u32SecureDMA,pXCArgs->u32OperationMode);
6970
6971 u32Return = UTOPIA_STATUS_SUCCESS;
6972 break;
6973 }
6974 case E_XC_CMD_CHECK_PIPE:
6975 {
6976 pstXC_CheckPipe pXCArgs = (pstXC_CheckPipe) pArgs;
6977 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6978 if(pXCArgs->u32PipeID == pipeID_SC1_main)
6979 {
6980 CHECK_DEVICE1_INSTANCE();
6981 pInstance = g_pDevice1Instance;
6982 }
6983 #endif
6984 pXCArgs->u32ReturnValue = psXCInstPri->fpXC_CheckPipe(pInstance,pXCArgs->u32PipeID,pXCArgs->u32SecureDMA,pXCArgs->u32OperationMode);
6985
6986 u32Return = UTOPIA_STATUS_SUCCESS;
6987 break;
6988 }
6989 #ifdef UFO_XC_FB_LEVEL
6990 case E_XC_CMD_SET_FB_LEVEL:
6991 {
6992 pstXC_SET_FB_LEVEL pXCArgs = (pstXC_SET_FB_LEVEL) pArgs;
6993 pXCArgs->eReturnValue = psXCInstPri->fpXC_SetFBLevel(pInstance, pXCArgs->eFBLevel, pXCArgs->eWindow);
6994 u32Return = UTOPIA_STATUS_SUCCESS;
6995 break;
6996 }
6997 case E_XC_CMD_GET_FB_LEVEL:
6998 {
6999 pstXC_GET_FB_LEVEL pXCArgs = (pstXC_GET_FB_LEVEL) pArgs;
7000 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetFBLevel(pInstance, pXCArgs->eWindow);
7001
7002 u32Return = UTOPIA_STATUS_SUCCESS;
7003 break;
7004 }
7005 #endif
7006 case E_XC_CMD_GET_CONFIG:
7007 {
7008 pstXC_GET_CONFIG pXCArgs = (pstXC_GET_CONFIG) pArgs;
7009 pXCArgs->eReturnValue = psXCInstPri->fpXC_GetConfig(pInstance,pXCArgs->pXC_InitData);
7010 u32Return = UTOPIA_STATUS_SUCCESS;
7011 break;
7012 }
7013
7014
7015 case E_XC_CMD_GET_FDMASK_STATUS:
7016 {
7017
7018
7019 pstXC_GET_FDMASK_STATUS pXCArgs = (pstXC_GET_FDMASK_STATUS) pArgs;
7020 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
7021 USE_OTHER_SC_AS_SUB_WINDOW();
7022 #endif
7023 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_FD_Mask_Status(pInstance, pXCArgs->eWindow);
7024
7025
7026 u32Return = UTOPIA_STATUS_SUCCESS;
7027 break;
7028 }
7029
7030 case E_XC_CMD_SET_SWDR_INFO:
7031 {
7032 pstXC_SWDR_INFO pXCArgs = (pstXC_SWDR_INFO) pArgs;
7033 pXCArgs->bReturnValue = psXCInstPri->fpXC_Set_SWDR_Info(pInstance,pXCArgs->pSWDR_INFO);
7034 u32Return = UTOPIA_STATUS_SUCCESS;
7035 break;
7036 }
7037 case E_XC_CMD_GET_SWDR_INFO:
7038 {
7039 pstXC_SWDR_INFO pXCArgs = (pstXC_SWDR_INFO) pArgs;
7040 pXCArgs->bReturnValue = psXCInstPri->fpXC_Get_SWDR_Info(pInstance,pXCArgs->pSWDR_INFO);
7041 u32Return = UTOPIA_STATUS_SUCCESS;
7042 break;
7043 }
7044
7045 #ifdef UFO_XC_SUPPORT_HDMI_DOWNSCALE_OUTPUT_POLICY
7046 case E_XC_CMD_GET_HDMIPOLICY:
7047 {
7048
7049 pstXC_GET_HDMIPOLICY pXCArgs = (pstXC_GET_HDMIPOLICY) pArgs;
7050 pXCArgs-> u32HDMIPolicyInfo = psXCInstPri->fpXC_GetHDMIPolicy(pInstance);
7051 u32Return = UTOPIA_STATUS_SUCCESS;
7052 break;
7053 }
7054 #endif
7055 // OBSOLETE command **END**, please avoid using these
7056 case E_XC_CMD_NONE:
7057 case E_XC_CMD_MAX:
7058 default:
7059 {
7060 printf("Command %td is not existed\n",(ptrdiff_t)u32Cmd);
7061 u32Return = UTOPIA_STATUS_ERR_INVALID_HANDLE;
7062 break;
7063 }
7064 }
7065 return u32Return;
7066 }
7067
XCClose(void * pInstance)7068 MS_U32 XCClose(void* pInstance)
7069 {
7070 UtopiaInstanceDelete(pInstance);
7071
7072 return UTOPIA_STATUS_SUCCESS;
7073 }
7074
7075
7076 #undef _XC_C_
7077