1 2 #ifndef __RK_AIQ_TYPES_AE_HW_H__ 3 #define __RK_AIQ_TYPES_AE_HW_H__ 4 5 #define RAWAEBIG_SUBWIN_NUM 4 6 #define RAWAEBIG_WIN_NUM 225 7 #define RAWAELITE_WIN_NUM 25 8 #define YUVAE_SUBWIN_NUM 4 9 #define YUVAE_WIN_NUM 225 10 11 #define RAWHISTBIG_WIN_NUM 225 12 #define RAWHISTLITE_WIN_NUM 25 13 #define SIHIST_WINCFG_NUM 1 14 #define SIHIST_WIN_NUM 225 15 16 #define RAWHIST_BIN_N_MAX 256 17 #define RAWHIST_32LITE_BIN_N_MAX 64 18 #define SIHIST_BIN_N_MAX 32 19 20 #define MAX_AEC_EFFECT_FNUM 5 21 22 typedef enum _RAWAE_WND_NUM { 23 RAWAE_WND_1X1 = 0, 24 RAWAE_WND_5X5 = 1, 25 RAWAE_WND_15X15 = 2, 26 } RAWAE_WND_NUM; 27 28 typedef enum _RAWHIST_WND_NUM { 29 RAWHIST_WND_5X5 = 0, 30 RAWHIST_WND_15X15 = 2, 31 } RAWHISST_WND_NUM; 32 33 typedef enum _AE_MODE { 34 RAWAE_MODE_S_LITE = 0, 35 RAWAE_MODE_M_LITE = 1, 36 RAWAE_MODE_L_LITE = 2 37 } AE_MODE; 38 39 typedef enum WinSplitMode_s { 40 LEFT_AND_RIGHT_MODE = 0, 41 LEFT_MODE, 42 RIGHT_MODE, 43 } WinSplitMode; 44 45 /*****************************************************************************/ 46 /** 47 * @brief ISP2.0 AEC HW-Meas Config Params 48 */ 49 /*****************************************************************************/ 50 #pragma pack(1) 51 typedef struct window { 52 uint16_t h_offs; 53 uint16_t v_offs; 54 uint16_t h_size; 55 uint16_t v_size; 56 } window_t; 57 #pragma pack() 58 59 60 #pragma pack(1) 61 typedef struct rawaebig_meas_cfg { 62 unsigned char rawae_sel; 63 unsigned char wnd_num; 64 unsigned char subwin_en[RAWAEBIG_SUBWIN_NUM]; 65 window_t win; 66 window_t subwin[RAWAEBIG_SUBWIN_NUM]; 67 } rawaebig_meas_cfg_t; 68 #pragma pack() 69 70 #pragma pack(1) 71 typedef struct rawaelite_meas_cfg { 72 unsigned char rawae_sel; 73 unsigned char wnd_num; 74 window_t win; 75 } rawaelite_meas_cfg_t; 76 #pragma pack() 77 78 #pragma pack(1) 79 typedef struct yuvae_meas_cfg { 80 unsigned char ysel; 81 unsigned char wnd_num; 82 unsigned char subwin_en[YUVAE_SUBWIN_NUM]; 83 window_t win; 84 window_t subwin[YUVAE_SUBWIN_NUM]; 85 } yuvae_meas_cfg_t; 86 #pragma pack() 87 88 89 #pragma pack(1) 90 typedef struct rawhistbig_cfg { 91 unsigned char wnd_num; 92 unsigned char data_sel; 93 unsigned char waterline; 94 unsigned char mode; 95 unsigned char stepsize; 96 unsigned char off; 97 unsigned char bcc; 98 unsigned char gcc; 99 unsigned char rcc; 100 window_t win; 101 unsigned char weight[RAWHISTBIG_WIN_NUM]; 102 } rawhistbig_cfg_t; 103 #pragma pack() 104 105 #pragma pack(1) 106 typedef struct rawhistlite_cfg { 107 unsigned char data_sel; 108 unsigned char waterline; 109 unsigned char mode; 110 unsigned char stepsize; 111 unsigned char off; 112 unsigned char bcc; 113 unsigned char gcc; 114 unsigned char rcc; 115 window_t win; 116 unsigned char weight[RAWHISTLITE_WIN_NUM]; 117 } rawhistlite_cfg_t; 118 #pragma pack() 119 120 #pragma pack(1) 121 typedef struct sihst_win_cfg { 122 unsigned char data_sel; 123 unsigned char waterline; 124 unsigned char auto_stop; 125 unsigned char mode; 126 unsigned char stepsize; 127 window_t win; 128 } sihst_win_cfg_t; 129 #pragma pack() 130 131 #pragma pack(1) 132 typedef struct sihst_cfg { 133 unsigned char wnd_num; 134 sihst_win_cfg_t win_cfg[SIHIST_WINCFG_NUM]; 135 unsigned char hist_weight[SIHIST_WIN_NUM]; 136 } sihst_cfg_t; 137 #pragma pack() 138 139 /*NOTE: name of rawae/rawhist channel has been renamed! 140 RawAE0 = RawAE lite, addr=0x4500 <=> RawHIST0 141 RawAE1 = RawAE big2, addr=0x4600 <=> RawHIST1 142 RawAE2 = RawAE big3, addr=0x4700 <=> RawHIST2 143 RawAE3 = RawAE big1, addr=0x4400, extra aebig <=> RawHIST3 144 */ 145 typedef struct rk_aiq_ae_meas_params_s { 146 bool ae_meas_en; 147 bool ae_meas_update; 148 rawaelite_meas_cfg_t rawae0; 149 rawaebig_meas_cfg_t rawae1; 150 rawaebig_meas_cfg_t rawae2; 151 rawaebig_meas_cfg_t rawae3; 152 yuvae_meas_cfg_t yuvae; 153 } rk_aiq_ae_meas_params_t; 154 155 typedef struct rk_aiq_hist_meas_params_s { 156 bool hist_meas_en; 157 bool hist_meas_update; 158 unsigned char ae_swap; // used to choose LITE & BIG 159 unsigned char ae_sel; // used for rawae3 & rawhist3 160 rawhistlite_cfg_t rawhist0; 161 rawhistbig_cfg_t rawhist1; 162 rawhistbig_cfg_t rawhist2; 163 rawhistbig_cfg_t rawhist3; 164 sihst_cfg_t sihist; 165 } rk_aiq_hist_meas_params_t; 166 /*****************************************************************************/ 167 /** 168 * @brief ISP2.0 AEC AEC HW-Meas Res Params 169 */ 170 /*****************************************************************************/ 171 172 typedef struct rawhist_stat { 173 unsigned int bins[RAWHIST_BIN_N_MAX]; 174 } rawhist_stat_t; 175 176 typedef struct sihist_stat_t { 177 unsigned int bins[SIHIST_BIN_N_MAX]; 178 } sihist_stat_t; 179 180 typedef struct rawaebig_stat { 181 uint16_t channelr_xy[RAWAEBIG_WIN_NUM]; 182 uint16_t channelg_xy[RAWAEBIG_WIN_NUM]; 183 uint16_t channelb_xy[RAWAEBIG_WIN_NUM]; 184 uint16_t channely_xy[RAWAEBIG_WIN_NUM]; //not HW! 185 uint16_t wndx_channelr[RAWAEBIG_SUBWIN_NUM]; //not HW! 186 uint16_t wndx_channelg[RAWAEBIG_SUBWIN_NUM]; //not HW! 187 uint16_t wndx_channelb[RAWAEBIG_SUBWIN_NUM]; //not HW! 188 uint16_t wndx_channely[RAWAEBIG_SUBWIN_NUM]; //not HW! 189 uint64_t wndx_sumr[RAWAEBIG_SUBWIN_NUM]; 190 uint64_t wndx_sumg[RAWAEBIG_SUBWIN_NUM]; 191 uint64_t wndx_sumb[RAWAEBIG_SUBWIN_NUM]; 192 } rawaebig_stat_t; 193 194 typedef struct rawaelite_stat { 195 uint16_t channelr_xy[RAWAELITE_WIN_NUM]; 196 uint16_t channelg_xy[RAWAELITE_WIN_NUM]; 197 uint16_t channelb_xy[RAWAELITE_WIN_NUM]; 198 uint16_t channely_xy[RAWAELITE_WIN_NUM]; //not HW! 199 } rawaelite_stat_t; 200 201 typedef struct yuvae_stat { 202 unsigned char mean[YUVAE_WIN_NUM]; 203 uint64_t ro_yuvae_sumy[YUVAE_SUBWIN_NUM]; 204 } yuvae_stat_t; 205 206 typedef struct Aec_Stat_Res_s { 207 //rawae 208 rawaebig_stat_t rawae_big; 209 rawaelite_stat_t rawae_lite; 210 //rawhist 211 rawhist_stat_t rawhist_big; 212 rawhist_stat_t rawhist_lite; 213 } Aec_Stat_Res_t; 214 215 typedef struct RkAiqAecHwConfig_s { 216 rk_aiq_ae_meas_params_t ae_meas; 217 rk_aiq_hist_meas_params_t hist_meas; 218 int ae_swap; 219 int ae_sel; 220 } RkAiqAecHwConfig_t; 221 222 typedef struct RkAiqAecHwStatsRes_s { 223 Aec_Stat_Res_t chn[3]; 224 Aec_Stat_Res_t extra; 225 yuvae_stat_t yuvae; 226 sihist_stat_t sihist; 227 } RkAiqAecHwStatsRes_t; 228 229 230 /*****************************************************************************/ 231 /** 232 * @brief ISP2.0 AEC Exposure Params 233 */ 234 /*****************************************************************************/ 235 typedef struct CISFeature_s { 236 // M4_NUMBER_DESC("SNR", "u8", M4_RANGE(0,1), "0", M4_DIGIT(0),M4_HIDE(1)) 237 uint8_t SNR; 238 // M4_NUMBER_DESC("DR", "u8", M4_RANGE(0,1), "0", M4_DIGIT(0),M4_HIDE(1)) 239 uint8_t DR; 240 // M4_NUMBER_DESC("Sat", "u8", M4_RANGE(0,1), "0", M4_DIGIT(0),M4_HIDE(1)) 241 uint8_t Sat; 242 // M4_NUMBER_DESC("SEN", "u8", M4_RANGE(0,1), "0", M4_DIGIT(0),M4_HIDE(1)) 243 uint8_t SEN; 244 } CISFeature_t; 245 246 typedef struct RkAiqExpRealParam_s { 247 248 // M4_NUMBER_DESC("CISTime", "f32", M4_RANGE(0,1), "0", M4_DIGIT(6)) 249 float integration_time; 250 251 // M4_NUMBER_DESC("CISGain", "f32", M4_RANGE(0,4096), "0", M4_DIGIT(3)) 252 float analog_gain; 253 254 // M4_NUMBER_DESC("digital_gain", "f32", M4_RANGE(0,4096), "0", M4_DIGIT(3),M4_HIDE(1)) 255 float digital_gain; 256 257 // M4_NUMBER_DESC("isp_dgain", "f32", M4_RANGE(0,256), "0", M4_DIGIT(3),M4_HIDE(1)) 258 float isp_dgain; 259 260 // M4_NUMBER_DESC("iso", "s32", M4_RANGE(0,524288), "0", M4_DIGIT(0),M4_HIDE(1)) 261 int iso; 262 263 // M4_NUMBER_DESC("DcgMode", "s32", M4_RANGE(-1,1), "0", M4_DIGIT(0)) 264 int dcg_mode; 265 266 // M4_NUMBER_DESC("longfrm_mode", "s32", M4_RANGE(0,1), "0", M4_DIGIT(0),M4_HIDE(1)) 267 int longfrm_mode; 268 } RkAiqExpRealParam_t; 269 270 typedef struct RkAiqExpSensorParam_s { 271 272 // M4_NUMBER_DESC("fine_integration_time", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 273 unsigned int fine_integration_time; 274 275 // M4_NUMBER_DESC("coarse_integration_time", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 276 unsigned int coarse_integration_time; 277 278 // M4_NUMBER_DESC("analog_gain_code_global", "u32", M4_RANGE(0,524288), "0", M4_DIGIT(0),M4_HIDE(1)) 279 unsigned int analog_gain_code_global; 280 281 // M4_NUMBER_DESC("digital_gain_global", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 282 unsigned int digital_gain_global; 283 284 // M4_NUMBER_DESC("isp_digital_gain", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 285 unsigned int isp_digital_gain; 286 } RkAiqExpSensorParam_t; 287 288 #define MAX_I2CDATA_LEN 64 289 typedef struct RKAiqExpI2cParam_s { 290 // M4_BOOL_DESC("bValid", "0",M4_HIDE(1)) 291 bool bValid; 292 293 // M4_NUMBER_DESC("nNumRegs", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 294 unsigned int nNumRegs; 295 296 // M4_ARRAY_DESC("RegAddr", "u32", M4_SIZE(1,64), M4_RANGE(0,65535), "0", M4_DIGIT(0), M4_DYNAMIC(0),M4_HIDE(1)) 297 unsigned int RegAddr[MAX_I2CDATA_LEN]; 298 299 // M4_ARRAY_DESC("AddrByteNum", "u32", M4_SIZE(1,64), M4_RANGE(0,65535), "0", M4_DIGIT(0), M4_DYNAMIC(0),M4_HIDE(1)) 300 unsigned int AddrByteNum[MAX_I2CDATA_LEN]; 301 302 // M4_ARRAY_DESC("RegValue", "u32", M4_SIZE(1,64), M4_RANGE(0,65535), "0", M4_DIGIT(0), M4_DYNAMIC(0),M4_HIDE(1)) 303 unsigned int RegValue[MAX_I2CDATA_LEN]; 304 305 // M4_ARRAY_DESC("ValueByteNum", "u32", M4_SIZE(1,64), M4_RANGE(0,65535), "0", M4_DIGIT(0), M4_DYNAMIC(0),M4_HIDE(1)) 306 unsigned int ValueByteNum[MAX_I2CDATA_LEN]; 307 308 // M4_ARRAY_DESC("DelayFrames", "u32", M4_SIZE(1,64), M4_RANGE(0,65535), "0", M4_DIGIT(0), M4_DYNAMIC(0),M4_HIDE(1)) 309 unsigned int DelayFrames[MAX_I2CDATA_LEN]; 310 311 } RKAiqExpI2cParam_t; 312 313 typedef struct { 314 // M4_STRUCT_DESC("RealPara", "normal_ui_style") 315 RkAiqExpRealParam_t exp_real_params; //real value 316 317 // M4_STRUCT_DESC("RegPara", "normal_ui_style",M4_HIDE(1)) 318 RkAiqExpSensorParam_t exp_sensor_params;//reg value 319 } RkAiqExpParamComb_t; 320 321 typedef struct { 322 // M4_BOOL_DESC("update", "0",M4_HIDE(1)) 323 bool update; 324 // M4_NUMBER_DESC("step", "s32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 325 int step; 326 // M4_NUMBER_DESC("gain", "s32", M4_RANGE(0,65535), "0", M4_DIGIT(0),M4_HIDE(1)) 327 int gain; 328 } RkAiqPIrisParam_t; 329 330 typedef struct { 331 // M4_BOOL_DESC("update", "0",M4_HIDE(1)) 332 bool update; 333 // M4_NUMBER_DESC("pwmDuty", "s32", M4_RANGE(0,100), "0", M4_DIGIT(0),M4_HIDE(1)) 334 int pwmDuty; //percent value,range = 0-100 335 } RkAiqDCIrisParam_t; 336 337 typedef struct { 338 // M4_NUMBER_DESC("pwmDuty", "s32", M4_RANGE(0,1024), "0", M4_DIGIT(0),M4_HIDE(1)) 339 int target; 340 // M4_BOOL_DESC("update", "0",M4_HIDE(1)) 341 bool update; 342 // M4_NUMBER_DESC("adc", "s32", M4_RANGE(0,1024), "0", M4_DIGIT(0),M4_HIDE(1)) 343 int adc; 344 // M4_NUMBER_DESC("zoomPos", "s32", M4_RANGE(0,1024), "0", M4_DIGIT(0),M4_HIDE(1)) 345 int zoomPos; 346 } RkAiqHDCIrisParam_t; 347 348 typedef struct { 349 // M4_STRUCT_DESC("PIris", "normal_ui_style",M4_HIDE(1)) 350 RkAiqPIrisParam_t PIris; 351 // M4_STRUCT_DESC("DCIris", "normal_ui_style",M4_HIDE(1)) 352 RkAiqDCIrisParam_t DCIris; 353 // M4_STRUCT_DESC("HDCIris", "normal_ui_style",M4_HIDE(1)) 354 RkAiqHDCIrisParam_t HDCIris; 355 } RkAiqIrisParamComb_t; 356 357 typedef struct RKAiqAecExpInfo_s { 358 // M4_STRUCT_DESC("LinearExp", "normal_ui_style") 359 RkAiqExpParamComb_t LinearExp; 360 361 // M4_STRUCT_LIST_DESC("HdrExp", M4_SIZE(1,3), "normal_ui_style") 362 RkAiqExpParamComb_t HdrExp[3]; 363 364 // M4_STRUCT_DESC("Iris", "normal_ui_style",M4_HIDE(1)) 365 RkAiqIrisParamComb_t Iris; 366 367 // M4_NUMBER_DESC("LineLengthPixels(hts)", "u16", M4_RANGE(0,65535), "0", M4_DIGIT(0)) 368 uint16_t line_length_pixels; 369 370 // M4_NUMBER_DESC("FrameLengthLines(vts)", "u32", M4_RANGE(0,65535), "0", M4_DIGIT(0)) 371 uint32_t frame_length_lines; 372 373 // M4_NUMBER_DESC("PixelClockFreqMhz", "f32", M4_RANGE(0,65535), "0", M4_DIGIT(2)) 374 float pixel_clock_freq_mhz; 375 376 // M4_STRUCT_DESC("CISFeature_t", "normal_ui_style",M4_HIDE(1)) 377 CISFeature_t CISFeature; 378 } RKAiqAecExpInfo_t; 379 380 /** 381 * gcc-4.4.7 disallow typedef redefinition 382 * error: redefinition of typedef 'RKAiqAecExpInfo_t' with include/algos/rk_aiq_algo_des.h 383 */ 384 #ifndef RKAIQAECEXPINFO_T 385 #define RKAIQAECEXPINFO_T 386 #endif 387 388 /*****************************************************************************/ 389 /** 390 * @brief ISP2.0 AEC transfer Params(from demo to rkaiq) 391 */ 392 /*****************************************************************************/ 393 394 typedef struct RKAiqAecStats_s { 395 RkAiqAecHwStatsRes_t ae_data; //AeHwMeas_Res 396 RKAiqAecExpInfo_t ae_exp; //AeExp_Info 397 } RKAiqAecStats_t; 398 399 typedef RkAiqAecHwConfig_t html_aec_para_t; 400 401 #endif /*__RK_AIQ_TYPES_AE_HW_H__*/ 402