1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __VDPU34X_COM_H__ 18 #define __VDPU34X_COM_H__ 19 20 #include "mpp_device.h" 21 #include "mpp_buf_slot.h" 22 #include "vdpu34x.h" 23 24 #define OFFSET_COMMON_REGS (8 * sizeof(RK_U32)) 25 #define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(RK_U32)) 26 #define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) 27 #define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32)) 28 #define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(RK_U32)) 29 #define OFFSET_INTERRUPT_REGS (224 * sizeof(RK_U32)) 30 #define OFFSET_STATISTIC_REGS (256 * sizeof(RK_U32)) 31 32 #define RCB_ALLINE_SIZE (64) 33 34 #define MPP_RCB_BYTES(bits) MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE) 35 36 typedef enum Vdpu34x_RCB_TYPE_E { 37 RCB_DBLK_ROW, 38 RCB_INTRA_ROW, 39 RCB_TRANSD_ROW, 40 RCB_STRMD_ROW, 41 RCB_INTER_ROW, 42 RCB_SAO_ROW, 43 RCB_FBC_ROW, 44 RCB_TRANSD_COL, 45 RCB_INTER_COL, 46 RCB_FILT_COL, 47 48 RCB_BUF_COUNT, 49 } Vdpu34xRcbType_e; 50 51 typedef enum Vdpu34x_RCB_SET_MODE_E { 52 RCB_SET_BY_SIZE_SORT_MODE, 53 RCB_SET_BY_PRIORITY_MODE, 54 } Vdpu34xRcbSetMode_e; 55 56 /* base: OFFSET_COMMON_REGS */ 57 typedef struct Vdpu34xRegCommon_t { 58 struct SWREG8_IN_OUT { 59 RK_U32 in_endian : 1; 60 RK_U32 in_swap32_e : 1; 61 RK_U32 in_swap64_e : 1; 62 RK_U32 str_endian : 1; 63 RK_U32 str_swap32_e : 1; 64 RK_U32 str_swap64_e : 1; 65 RK_U32 out_endian : 1; 66 RK_U32 out_swap32_e : 1; 67 RK_U32 out_cbcr_swap : 1; 68 RK_U32 out_swap64_e : 1; 69 RK_U32 reserve : 22; 70 } reg008; 71 72 struct SWREG9_DEC_MODE { 73 RK_U32 dec_mode : 10; 74 RK_U32 reserve : 22; 75 } reg009; 76 77 struct SWREG10_DEC_E { 78 RK_U32 dec_e : 1; 79 RK_U32 reserve : 31; 80 } reg010; 81 82 struct SWREG11_IMPORTANT_EN { 83 RK_U32 reserver : 1; 84 RK_U32 dec_clkgate_e : 1; 85 RK_U32 dec_e_strmd_clkgate_dis : 1; 86 RK_U32 reserve0 : 1; 87 88 RK_U32 dec_irq_dis : 1; 89 RK_U32 dec_timeout_e : 1; 90 RK_U32 buf_empty_en : 1; 91 RK_U32 reserve1 : 3; 92 93 RK_U32 dec_e_rewrite_valid : 1; 94 RK_U32 reserve2 : 9; 95 RK_U32 softrst_en_p : 1; 96 RK_U32 force_softreset_valid : 1; 97 RK_U32 reserve3 : 2; 98 RK_U32 pix_range_detection_e : 1; 99 RK_U32 reserve4 : 7; 100 } reg011; 101 102 struct SWREG12_SENCODARY_EN { 103 RK_U32 wr_ddr_align_en : 1; 104 RK_U32 colmv_compress_en : 1; 105 RK_U32 fbc_e : 1; 106 RK_U32 reserve0 : 1; 107 108 RK_U32 buspr_slot_disable : 1; 109 RK_U32 error_info_en : 1; 110 RK_U32 info_collect_en : 1; 111 RK_U32 wait_reset_en : 1; 112 113 RK_U32 scanlist_addr_valid_en : 1; 114 RK_U32 scale_down_en : 1; 115 RK_U32 error_cfg_wr_disable : 1; 116 RK_U32 reserve1 : 21; 117 } reg012; 118 119 struct SWREG13_EN_MODE_SET { 120 RK_U32 timeout_mode : 1; 121 RK_U32 req_timeout_rst_sel : 1; 122 RK_U32 reserve0 : 1; 123 RK_U32 dec_commonirq_mode : 1; 124 RK_U32 reserve1 : 2; 125 RK_U32 stmerror_waitdecfifo_empty : 1; 126 RK_U32 reserve2 : 2; 127 RK_U32 h26x_streamd_error_mode : 1; 128 RK_U32 reserve3 : 2; 129 RK_U32 allow_not_wr_unref_bframe : 1; 130 RK_U32 fbc_output_wr_disable : 1; 131 RK_U32 reserve4 : 1; 132 RK_U32 colmv_error_mode : 1; 133 134 RK_U32 reserve5 : 2; 135 RK_U32 h26x_error_mode : 1; 136 RK_U32 reserve6 : 2; 137 RK_U32 ycacherd_prior : 1; 138 RK_U32 reserve7 : 2; 139 RK_U32 cur_pic_is_idr : 1; 140 RK_U32 reserve8 : 1; 141 RK_U32 right_auto_rst_disable : 1; 142 RK_U32 frame_end_err_rst_flag : 1; 143 RK_U32 rd_prior_mode : 1; 144 RK_U32 rd_ctrl_prior_mode : 1; 145 RK_U32 reserved9 : 1; 146 RK_U32 filter_outbuf_mode : 1; 147 } reg013; 148 149 struct SWREG14_FBC_PARAM_SET { 150 RK_U32 fbc_force_uncompress : 1; 151 152 RK_U32 reserve0 : 2; 153 RK_U32 allow_16x8_cp_flag : 1; 154 RK_U32 reserve1 : 2; 155 156 RK_U32 fbc_h264_exten_4or8_flag: 1; 157 RK_U32 reserve2 : 25; 158 } reg014; 159 160 struct SWREG15_STREAM_PARAM_SET { 161 RK_U32 rlc_mode_direct_write : 1; 162 RK_U32 rlc_mode : 1; 163 RK_U32 reserve0 : 3; 164 165 RK_U32 strm_start_bit : 7; 166 RK_U32 reserve1 : 20; 167 } reg015; 168 169 RK_U32 reg016_str_len; 170 171 struct SWREG17_SLICE_NUMBER { 172 RK_U32 slice_num : 25; 173 RK_U32 reserve : 7; 174 } reg017; 175 176 struct SWREG18_Y_HOR_STRIDE { 177 RK_U32 y_hor_virstride : 16; 178 RK_U32 reserve : 16; 179 } reg018; 180 181 struct SWREG19_UV_HOR_STRIDE { 182 RK_U32 uv_hor_virstride : 16; 183 RK_U32 reserve : 16; 184 } reg019; 185 186 union { 187 struct SWREG20_Y_STRIDE { 188 RK_U32 y_virstride : 28; 189 RK_U32 reserve : 4; 190 } reg020_y_virstride; 191 192 struct SWREG20_FBC_PAYLOAD_OFFSET { 193 RK_U32 reserve : 4; 194 RK_U32 payload_st_offset : 28; 195 } reg020_fbc_payload_off; 196 }; 197 198 199 struct SWREG21_ERROR_CTRL_SET { 200 RK_U32 inter_error_prc_mode : 1; 201 RK_U32 error_intra_mode : 1; 202 RK_U32 error_deb_en : 1; 203 RK_U32 picidx_replace : 5; 204 RK_U32 error_spread_e : 1; 205 RK_U32 : 3; 206 RK_U32 error_inter_pred_cross_slice : 1; 207 RK_U32 reserve0 : 11; 208 209 RK_U32 roi_error_ctu_cal_en : 1; 210 RK_U32 reserve1 : 7; 211 } reg021; 212 213 struct SWREG22_ERR_ROI_CTU_OFFSET_START { 214 RK_U32 roi_x_ctu_offset_st : 12; 215 RK_U32 reserve0 : 4; 216 RK_U32 roi_y_ctu_offset_st : 12; 217 RK_U32 reserve1 : 4; 218 } reg022; 219 220 struct SWREG23_ERR_ROI_CTU_OFFSET_END { 221 RK_U32 roi_x_ctu_offset_end : 12; 222 RK_U32 reserve0 : 4; 223 RK_U32 roi_y_ctu_offset_end : 12; 224 RK_U32 reserve1 : 4; 225 } reg023; 226 227 struct SWREG24_CABAC_ERROR_EN_LOWBITS { 228 RK_U32 cabac_err_en_lowbits : 32; 229 } reg024; 230 231 struct SWREG25_CABAC_ERROR_EN_HIGHBITS { 232 RK_U32 cabac_err_en_highbits : 30; 233 RK_U32 reserve : 2; 234 } reg025; 235 236 struct SWREG26_BLOCK_GATING_EN { 237 RK_U32 swreg_block_gating_e : 20; 238 RK_U32 reserve : 11; 239 RK_U32 reg_cfg_gating_en : 1; 240 } reg026; 241 242 /* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */ 243 struct SW027_CORE_SAFE_PIXELS { 244 // colmv and recon report coord x safe pixels 245 RK_U32 core_safe_x_pixels : 16; 246 // colmv and recon report coord y safe pixels 247 RK_U32 core_safe_y_pixels : 16; 248 } reg027; 249 250 struct SWREG28_MULTIPLY_CORE_CTRL { 251 RK_U32 swreg_vp9_wr_prob_idx : 3; 252 RK_U32 reserve0 : 1; 253 RK_U32 swreg_vp9_rd_prob_idx : 3; 254 RK_U32 reserve1 : 1; 255 256 RK_U32 swreg_ref_req_advance_flag : 1; 257 RK_U32 sw_colmv_req_advance_flag : 1; 258 RK_U32 sw_poc_only_highbit_flag : 1; 259 RK_U32 sw_poc_arb_flag : 1; 260 261 RK_U32 reserve2 : 4; 262 RK_U32 sw_film_idx : 10; 263 RK_U32 reserve3 : 2; 264 RK_U32 sw_pu_req_mismatch_dis : 1; 265 RK_U32 sw_colmv_req_mismatch_dis : 1; 266 RK_U32 reserve4 : 2; 267 } reg028; 268 269 struct SW029_SCALE_DOWN_CTRL { 270 RK_U32 scale_down_hor_ratio : 2; 271 RK_U32 : 6; 272 RK_U32 scale_down_vrz_ratio : 2; 273 RK_U32 : 22; 274 } reg029; 275 276 struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE { 277 RK_U32 y_scale_down_hor_stride : 20; 278 RK_U32 : 12; 279 } reg030; 280 281 struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE { 282 RK_U32 uv_scale_down_hor_stride : 20; 283 RK_U32 : 12; 284 } reg031; 285 286 /* NOTE: timeout must be config in vdpu38x */ 287 RK_U32 reg032_timeout_threshold; 288 } Vdpu34xRegCommon; 289 290 /* base: OFFSET_COMMON_ADDR_REGS */ 291 typedef struct Vdpu34xRegCommonAddr_t { 292 /* offset 128 */ 293 RK_U32 reg128_rlc_base; 294 295 RK_U32 reg129_rlcwrite_base; 296 297 RK_U32 reg130_decout_base; 298 299 RK_U32 reg131_colmv_cur_base; 300 301 RK_U32 reg132_error_ref_base; 302 303 RK_U32 reg133_rcb_intra_base; 304 305 RK_U32 reg134_rcb_transd_row_base; 306 307 RK_U32 reg135_rcb_transd_col_base; 308 309 RK_U32 reg136_rcb_streamd_row_base; 310 311 RK_U32 reg137_rcb_inter_row_base; 312 313 RK_U32 reg138_rcb_inter_col_base; 314 315 RK_U32 reg139_rcb_dblk_base; 316 317 RK_U32 reg140_rcb_sao_base; 318 319 RK_U32 reg141_rcb_fbc_base; 320 321 RK_U32 reg142_rcb_filter_col_base; 322 } Vdpu34xRegCommonAddr; 323 324 /* base: OFFSET_COMMON_ADDR_REGS */ 325 typedef struct Vdpu34xRegIrqStatus_t { 326 struct SWREG224_STA_INT { 327 RK_U32 dec_irq : 1; 328 RK_U32 dec_irq_raw : 1; 329 330 RK_U32 dec_rdy_sta : 1; 331 RK_U32 dec_bus_sta : 1; 332 RK_U32 dec_error_sta : 1; 333 RK_U32 dec_timeout_sta : 1; 334 RK_U32 buf_empty_sta : 1; 335 RK_U32 colmv_ref_error_sta : 1; 336 RK_U32 cabu_end_sta : 1; 337 338 RK_U32 softreset_rdy : 1; 339 340 RK_U32 reserve : 22; 341 } reg224; 342 343 struct SWREG225_STA_ERR_INFO { 344 RK_U32 all_frame_error_flag : 1; 345 RK_U32 strmd_detect_error_flag : 1; 346 RK_U32 reserve : 30; 347 } reg225; 348 349 struct SWREG226_STA_CABAC_ERROR_STATUS { 350 RK_U32 strmd_error_status : 28; 351 RK_U32 reserve : 4; 352 } reg226; 353 354 struct SWREG227_STA_COLMV_ERROR_REF_PICIDX { 355 RK_U32 colmv_error_ref_picidx : 4; 356 RK_U32 reserve : 28; 357 } reg227; 358 359 struct SWREG228_STA_CABAC_ERROR_CTU_OFFSET { 360 RK_U32 cabac_error_ctu_offset_x : 12; 361 RK_U32 : 4; 362 RK_U32 cabac_error_ctu_offset_y : 12; 363 RK_U32 : 4; 364 } reg228; 365 366 struct SWREG229_STA_SAOWR_CTU_OFFSET { 367 RK_U32 saowr_xoffset : 16; 368 RK_U32 saowr_yoffset : 16; 369 } reg229; 370 371 struct SWREG230_STA_SLICE_DEC_NUM { 372 RK_U32 slicedec_num : 25; 373 RK_U32 reserve : 7; 374 } reg230; 375 376 struct SWREG231_STA_FRAME_ERROR_CTU_NUM { 377 RK_U32 frame_ctu_err_num : 32; 378 } reg231; 379 380 struct SWREG232_STA_ERROR_PACKET_NUM { 381 RK_U32 packet_err_num : 16; 382 RK_U32 reserve : 16; 383 } reg232; 384 385 struct SWREG233_STA_ERR_CTU_NUM_IN_RO { 386 RK_U32 error_ctu_num_in_roi : 24; 387 RK_U32 reserve : 8; 388 } reg233; 389 390 RK_U32 reserve_reg234_237[4]; 391 } Vdpu34xRegIrqStatus; 392 393 typedef struct Vdpu34xRegStatistic_t { 394 struct SWREG256_DEBUG_PERF_LATENCY_CTRL0 { 395 RK_U32 axi_perf_work_e : 1; 396 RK_U32 axi_perf_clr_e : 1; 397 RK_U32 reserve0 : 1; 398 RK_U32 axi_cnt_type : 1; 399 RK_U32 rd_latency_id : 4; 400 RK_U32 rd_latency_thr : 12; 401 RK_U32 reserve1 : 12; 402 } reg256; 403 404 struct SWREG257_DEBUG_PERF_LATENCY_CTRL1 { 405 RK_U32 addr_align_type : 2; 406 RK_U32 ar_cnt_id_type : 1; 407 RK_U32 aw_cnt_id_type : 1; 408 RK_U32 ar_count_id : 4; 409 RK_U32 aw_count_id : 4; 410 RK_U32 rd_band_width_mode : 1; 411 RK_U32 reserve : 19; 412 } reg257; 413 414 struct SWREG258_DEBUG_PERF_RD_MAX_LATENCY_NUM { 415 RK_U32 rd_max_latency_num : 16; 416 RK_U32 reserve : 16; 417 } reg258; 418 419 RK_U32 reg259_rd_latency_thr_num_ch0; 420 RK_U32 reg260_rd_latency_acc_sum; 421 RK_U32 reg261_perf_rd_axi_total_byte; 422 RK_U32 reg262_perf_wr_axi_total_byte; 423 RK_U32 reg263_perf_working_cnt; 424 425 RK_U32 reserve_reg264; 426 427 struct SWREG265_DEBUG_PERF_SEL { 428 RK_U32 perf_cnt0_sel : 6; 429 RK_U32 reserve0 : 2; 430 RK_U32 perf_cnt1_sel : 6; 431 RK_U32 reserve1 : 2; 432 RK_U32 perf_cnt2_sel : 6; 433 RK_U32 reserve2 : 10; 434 } reg265; 435 436 RK_U32 reg266_perf_cnt0; 437 RK_U32 reg267_perf_cnt1; 438 RK_U32 reg268_perf_cnt2; 439 440 RK_U32 reserve_reg269; 441 442 struct SWREG270_DEBUG_QOS_CTRL { 443 RK_U32 bus2mc_buffer_qos_level : 8; 444 RK_U32 reserve0 : 8; 445 RK_U32 axi_rd_hurry_level : 2; 446 RK_U32 reserve1 : 2; 447 RK_U32 axi_wr_qos : 2; 448 RK_U32 reserve2 : 2; 449 RK_U32 axi_wr_hurry_level : 2; 450 RK_U32 reserve3 : 2; 451 RK_U32 axi_rd_qos : 2; 452 RK_U32 reserve4 : 2; 453 } reg270; 454 455 RK_U32 reg271_wr_wait_cycle_qos; 456 457 struct SWREG272_DEBUG_INT { 458 RK_U32 bu_rw_clean : 1; 459 RK_U32 saowr_frame_rdy : 1; 460 RK_U32 saobu_frame_rdy_valid : 1; 461 RK_U32 colmvwr_frame_rdy_real : 1; 462 RK_U32 cabu_rlcend_valid_real : 1; 463 RK_U32 stream_rdburst_cnteq0_towr : 1; 464 RK_U32 wr_tansfer_cnt : 6; 465 RK_U32 reserve0 : 4; 466 RK_U32 streamfifo_space2full : 7; 467 RK_U32 reserve1 : 9; 468 } reg272; 469 470 struct SWREG273 { 471 RK_U32 bus_status_flag : 19; 472 RK_U32 reserve0 : 12; 473 RK_U32 pps_no_ref_bframe_dec_r : 1; 474 } reg273; 475 476 RK_U16 reg274_y_min_value; 477 RK_U16 reg274_y_max_value; 478 RK_U16 reg275_u_min_value; 479 RK_U16 reg275_u_max_value; 480 RK_U16 reg276_v_min_value; 481 RK_U16 reg276_v_max_value; 482 483 struct SWREG277_ERROR_SPREAD_NUM { 484 RK_U32 err_spread_cnt_sum : 24; 485 RK_U32 : 8; 486 } reg277; 487 } Vdpu34xRegStatistic; 488 489 typedef struct vdpu34x_rcb_info_t { 490 RK_S32 reg; 491 RK_S32 size; 492 RK_S32 offset; 493 } Vdpu34xRcbInfo; 494 495 #ifdef __cplusplus 496 extern "C" { 497 #endif 498 499 RK_S32 vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height); 500 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info); 501 void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta); 502 void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand); 503 RK_S32 vdpu34x_set_rcbinfo(MppDev dev, Vdpu34xRcbInfo *rcb_info); 504 RK_U32 vdpu34x_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size, 505 RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress); 506 507 #ifdef __cplusplus 508 } 509 #endif 510 511 #endif /* __VDPU34X_COM_H__ */ 512