1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VOP_H_ 96 #define _REG_VOP_H_ 97 98 99 //------------------------------------------------------------------------------------------------- 100 // Hardware Capability 101 //------------------------------------------------------------------------------------------------- 102 103 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 108 109 //------------------------------------------------------------------------------ 110 // Base Address 111 //------------------------------------------------------------------------------ 112 #define MVOP_REG_BASE 0x1400 // 0x1400 - 0x14FF 113 #define MVOP_SUB_REG_BASE 0x1300 // 0x1300 - 0x13FF 114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 115 116 //------------------------------------------------------------------------------ 117 // MVOP Reg 118 //------------------------------------------------------------------------------ 119 #define VOP_FRAME_VCOUNT (MVOP_REG_BASE + 0x00) 120 #define VOP_FRAME_HCOUNT (MVOP_REG_BASE + 0x02) 121 #define VOP_VB0_STR (MVOP_REG_BASE + 0x04) 122 #define VOP_VB0_END (MVOP_REG_BASE + 0x06) 123 #define VOP_VB1_STR (MVOP_REG_BASE + 0x08) 124 #define VOP_VB1_END (MVOP_REG_BASE + 0x0A) 125 #define VOP_TF_STR (MVOP_REG_BASE + 0x0C) 126 #define VOP_BF_STR (MVOP_REG_BASE + 0x0E) 127 #define VOP_HACT_STR (MVOP_REG_BASE + 0x10) 128 #define VOP_IMG_HSTR (MVOP_REG_BASE + 0x12) 129 #define VOP_IMG_VSTR0 (MVOP_REG_BASE + 0x14) 130 #define VOP_IMG_VSTR1 (MVOP_REG_BASE + 0x16) 131 #define VOP_TF_VS (MVOP_REG_BASE + 0x18) 132 #define VOP_BF_VS (MVOP_REG_BASE + 0x1A) 133 134 135 ///TOP field Vsync start line number to MVD 136 #define VOP_TF_VS_MVD (MVOP_REG_BASE + 0x1C) //u3 new 137 ///Bottom field Vsync start line number to MVD 138 #define VOP_BF_VS_MVD (MVOP_REG_BASE + 0x1E) //u3 new 139 140 #define VOP_FSYNC_EN BIT4 //frame sync enable 141 #define VOP_CTRL0 (MVOP_REG_BASE + 0x22) 142 143 #define VOP_FLIP_UV BIT0 144 #define VOP_FLIP_YC BIT1 145 #define VOP_FLD_INV BIT2 146 #define VOP_OFLD_INV BIT4 147 #define VOP_CCIR_MD BIT5 148 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd) 149 #define VOP_MVD_VS_SEL BIT7 150 #define VOP_CTRL1 (MVOP_REG_BASE + 0x23) 151 152 #define VOP_TST_IMG (MVOP_REG_BASE + 0x24) 153 154 #define VOP_U_PAT (MVOP_REG_BASE + 0x26) 155 156 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4) 157 //DMA FIFO threshold 158 //= reg_dma_thd x 2 (reg_miu128b=1) 159 //= reg_dma_thd x 4 (reg_miu128b=0) 160 #define VOP_BURST_ST_SEL BIT7 161 //Timing to calculate burst length (only valid when reg_burst_ext = all) 162 //0: at mi2dc_rdy; 1: at dc2mi_rdy 163 #define VOP_DMA0 (MVOP_REG_BASE + 0x28) //t3 new 164 165 #define VOP_BURST_EXT (BIT0|BIT1|BIT2) 166 //DMA burst length 167 //0: 4 (reg_miu128b=1), 8 (reg_miu128b=0) 168 //1: 8 (reg_miu128b=1), 16 (reg_miu128b=0) 169 //2: 16 (reg_miu128b=1), 32 (reg_miu128b=0) 170 //3: 24 (reg_miu128b=1), 48 (reg_miu128b=0) 171 //4: 32 (reg_miu128b=1), 64 (reg_miu128b=0) 172 //5: 48 (reg_miu128b=1), 96 (reg_miu128b=0) 173 //6: 64 (reg_miu128b=1), 128 (reg_miu128b=0) 174 //7: all 175 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold 176 //(assert high priority if data count less then reg_hi_tsh x 8) 177 #define VOP_FORCE_HIGH BIT7 //Force DMA High priority 178 #define VOP_DMA1 (MVOP_REG_BASE + 0x29) //t3 new 179 180 #define VOP_BURST_CTRL0 (MVOP_REG_BASE + 0x2A) //monaco new 181 #define VOP_BURST_CTRL1 (MVOP_REG_BASE + 0x2B) //monaco new 182 183 #define VOP_DC_STRIP_H (MVOP_REG_BASE + 0x30) 184 185 #define VOP_INT_MASK (MVOP_REG_BASE + 0x3E) 186 #define VOP_MPG_JPG_SWITCH (MVOP_REG_BASE + 0x40) 187 #define VOP_DC_STRIP (MVOP_REG_BASE + 0x41) 188 #define VOP_JPG_YSTR0_L (MVOP_REG_BASE + 0x42) 189 #define VOP_JPG_YSTR0_H (MVOP_REG_BASE + 0x44) 190 #define VOP_JPG_UVSTR0_L (MVOP_REG_BASE + 0x46) 191 #define VOP_JPG_UVSTR0_H (MVOP_REG_BASE + 0x48) 192 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24) 193 194 #define VOP_JPG_HSIZE (MVOP_REG_BASE + 0x4A) 195 #define VOP_JPG_VSIZE (MVOP_REG_BASE + 0x4C) 196 197 #define VOP_LOAD_REG BIT0 //load new value into active registers 0x20-0x26 198 #define VOP_TILE_FORMAT BIT1 //0: 8x32, 1: 16x32 199 #define VOP_BUF_DUAL BIT2 200 #define VOP_FORCELOAD_REG BIT4 //force load registers 201 #define VOP_REG_WR (MVOP_REG_BASE + 0x4E) 202 203 #define VOP_MVD_EN BIT0 //t8 new 204 #define VOP_H264_PUREY BIT1 205 //#define VOP_RVD_EN BIT2 //a3: removed 206 #define VOP_HVD_EN BIT3 207 #define VOP_FORCE_SC_RDY BIT4 //u3 new: force sc2mvop_rdy = 1 208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select 209 #define VOP_INPUT_SWITCH0 (MVOP_REG_BASE + 0x50) 210 #define EVD_ENABLE BIT7 211 212 #define VOP_INPUT_SWITCH1 (MVOP_REG_BASE + 0x51) 213 214 #define VOP_RAMAP_LUMA_VAL 0x1f 215 #define VOP_RAMAP_LUMA_EN BIT7 216 #define VOP_RAMAP_LUMA (MVOP_REG_BASE + 0x52) 217 //u3 new: Luma range mapping for VC1 (value = 8~16) 218 219 #define VOP_RAMAP_CHROMA_VAL 0x1f 220 #define VOP_RAMAP_CHROMA_EN BIT7 221 #define VOP_RAMAP_CHROMA (MVOP_REG_BASE + 0x53) 222 //u3 new: Chroma range mapping for VC1 (value = 8~16) 223 224 // [T3 new 225 #define VOP_DEBUG_2A (MVOP_REG_BASE + 0x54) //2-byte 226 #define VOP_DEBUG_2B (MVOP_REG_BASE + 0x56) 227 #define VOP_DEBUG_2C (MVOP_REG_BASE + 0x58) 228 #define VOP_DEBUG_2D (MVOP_REG_BASE + 0x5A) 229 #define VOP_DEBUG_2E (MVOP_REG_BASE + 0x5C) 230 231 #define VOP_UF BIT0 //buf underflow 232 #define VOP_OF BIT1 //buf overflow 233 #define VOP_DEBUG_2F_L (MVOP_REG_BASE + 0x5E) 234 235 #define VOP_BIST_FAIL BIT0 //YUV fifo bist fail 236 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select 237 #define VOP_DEBUG_2F_H (MVOP_REG_BASE + 0x5F) 238 // ] 239 240 #define VOP_UV_SHIFT (MVOP_REG_BASE + 0x60) 241 242 #define VOP_GCLK_MIU_ON BIT2 //clk_miu use 0: free-run clock; 1: gated clock 243 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock 244 #define VOP_GCLK (MVOP_REG_BASE + 0x60) //u3 new 245 246 #define VOP_MIU_IF (MVOP_REG_BASE + 0x60) 247 #define VOP_MIU_128BIT BIT4 //MIU bus use 0: 64bit 1:128bit 248 #define VOP_MIU_128B_I64 BIT5 249 #define VOP_MIU_REQ_DIS BIT6 250 251 #define VOP_MIU_BUS (MVOP_REG_BASE + 0x60) //t3 new 252 253 #define VOP_MIU_SEL (MVOP_REG_BASE + 0x61) //kaiser new 254 #define VOP_BUF_MIU_SEL BIT0 255 256 #define VOP_JPG_YSTR1_L (MVOP_REG_BASE + 0x62) 257 #define VOP_JPG_YSTR1_H (MVOP_REG_BASE + 0x64) 258 #define VOP_JPG_UVSTR1_L (MVOP_REG_BASE + 0x66) 259 #define VOP_JPG_UVSTR1_H (MVOP_REG_BASE + 0x68) 260 261 #define VOP_SYNC_FRAME_V (MVOP_REG_BASE + 0x6A) 262 #define VOP_SYNC_FRAME_H (MVOP_REG_BASE + 0x6C) 263 264 #define VOP_INFO_FROM_CODEC_L (MVOP_REG_BASE + 0x70) 265 #define VOP_INFO_FROM_CODEC_BASE_ADDR (BIT0) //base address 266 #define VOP_INFO_FROM_CODEC_PITCH (BIT1) //pitch 267 #define VOP_INFO_FROM_CODEC_SIZE (BIT2) //size 268 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence 269 #define VOP_INFO_FROM_CODEC_FIELD (BIT4) //field 270 #define VOP_INFO_FROM_CODEC_RANGE_MAP (BIT5) //range map 271 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode 272 #define VOP_INFO_FROM_CODEC_422_FMT (BIT7) //422 format 273 274 #define VOP_INFO_FROM_CODEC_H (MVOP_REG_BASE + 0x71) 275 #define VOP_INFO_FROM_CODEC_DUAL_BUFF (BIT0) //dual buffer flag 276 #define VOP_INFO_FROM_CODEC_BPIC_REDUCT (BIT1) //bpic reduction 277 278 #define VOP_INT_TYPE (MVOP_REG_BASE + 0x73) 279 #define VOP_EVD_INT_SEP (BIT0) 280 #define VOP_EVD_10B_EN (MVOP_REG_BASE + 0x73) 281 #define VOP_EVD_10B_Y_EN (BIT1) //Enable EVD Y 10 bits mode 282 #define VOP_EVD_10B_UV_EN (BIT2) //Enable EVD UV 10 bits mode 283 284 #define VOP_MIRROR_CFG (MVOP_REG_BASE + 0x76) 285 #define VOP_MIRROR_CFG_VEN (BIT0) //vertical mirror enable 286 #define VOP_MIRROR_CFG_HEN (BIT1) //horizontal mirror enable 287 #define VOP_HW_FLD_BASE (BIT5) //Hardware calculate field jump base address 288 #define VOP_MASK_BASE_LSB (BIT7) //mask LSB of base address from Codec (always get top field base address) 289 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7) 290 291 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) 292 #define VOP_REF_SELF_FLD (BIT1) //source field flag set by internal timing generator 293 294 #define VOP_MULTI_WIN_CFG0 (MVOP_REG_BASE + 0x78) 295 #define VOP_LR_BUF_MODE (BIT0) //3D L/R dual buffer mode 296 #define VOP_P2I_MODE (BIT1) //progressive input, interlace output 297 //to SC vsync is twice of to MVD vsync 298 #define VOP_LR_LA_OUT (BIT2) //3D L/R dual buffer line alternative output 299 #define VOP_LR_LA2SBS_OUT (BIT3) //3D L/R dual buffer line alternative read, side-by-side output 300 #define VOP_LR_DIFF_SIZE (BIT7) //3D L/R dual buffer with difference size 301 302 #define VOP_RGB_FMT (MVOP_REG_BASE + 0x79) 303 #define VOP_RGB_FMT_565 (BIT0) //RGB 565 304 #define VOP_RGB_FMT_888 (BIT1) //RGB 888 305 #define VOP_RGB_FMT_SEL (BIT0 | BIT1) //RGB format selection 306 307 #define VOP_REG_DUMMY (MVOP_REG_BASE + 0x7B) 308 #define VOP_420_BW_SAVE (BIT7) //420 bw saving mode 309 310 #define VOP_REG_STRIP_ALIGN (MVOP_REG_BASE + 0x7E) 311 #define VOP_REG_WEIGHT_CTRL (MVOP_REG_BASE + 0x7E) 312 #define VOP_REG_FRAME_RST (MVOP_REG_BASE + 0x7E) //BIT15 313 314 #define VOP_REG_CROP_HSTART (MVOP_REG_BASE + 0x80) 315 #define VOP_REG_CROP_VSTART (MVOP_REG_BASE + 0x82) 316 #define VOP_REG_CROP_HSIZE (MVOP_REG_BASE + 0x84) 317 #define VOP_REG_CROP_VSIZE (MVOP_REG_BASE + 0x86) 318 319 //------------------------------------------------------------------------------ 320 // chip top 321 //------------------------------------------------------------------------------ 322 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98) 323 #define CKG_DC0_GATED BIT0 324 #define CKG_DC0_INVERT BIT1 325 #define CKG_DC0_MASK (BIT3 | BIT2) //select clk src 326 #define CKG_DC0_SYNCHRONOUS (0 << 2) 327 #define CKG_DC0_FREERUN (1 << 2) 328 #define CKG_DC0_160MHZ (2 << 2) 329 #define CKG_DC0_144MHZ (3 << 2) 330 331 // For check stc cw 332 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C) 333 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E) 334 335 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0x0A) 336 #define UPDATE_DC0_FREERUN_CW BIT3 337 #define UPDATE_DC0_SYNC_CW BIT4 338 339 //#define REG_UPDATE_DC0_SYNC_CW (CHIP_REG_BASE + 0x0A) 340 #define REG_DC0_NUM (CHIP_REG_BASE + 0x14) 341 #define REG_DC0_DEN (CHIP_REG_BASE + 0x16) 342 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0x10) 343 #define REG_DC0_FREERUN_CW_H (CHIP_REG_BASE + 0x12) 344 345 #endif // _REG_VOP_H_ 346 347