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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDAC.h 98 /// @author MStar Semiconductor Inc. 99 /// @brief DAC Driver Interface 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DAC_H_ 103 #define _DRV_DAC_H_ 104 105 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 #include "UFO.h" 111 //------------------------------------------------------------------------------------------------- 112 // Driver Capability 113 //------------------------------------------------------------------------------------------------- 114 115 116 //------------------------------------------------------------------------------------------------- 117 // Macro and Define 118 //------------------------------------------------------------------------------------------------- 119 120 //------------------------------------------------------------------------------------------------- 121 // Type and Structure 122 //------------------------------------------------------------------------------------------------- 123 typedef enum 124 { 125 RES_720x480I_60Hz = 0, 126 RES_720x480P_60Hz, 127 RES_720x576I_50Hz, 128 RES_720x576P_50Hz, 129 RES_1280x720P_50Hz, 130 RES_1280x720P_60Hz, 131 RES_1920x1080I_50Hz, 132 RES_1920x1080I_60Hz, 133 RES_1920x1080P_50Hz, 134 RES_1920x1080P_60Hz, 135 RES_1920x1080P_24Hz, 136 RES_1920x1080P_25Hz, 137 RES_1920x1080P_30Hz, 138 RES_640x480P_60Hz, 139 RES_1920x2205P_24Hz, 140 RES_1280x1470P_50Hz, 141 RES_1280x1470P_60Hz, 142 RES_VGA640x480P_60Hz, 143 RES_TTL480X272P_60Hz, 144 RES_3840x2160P_24Hz, 145 RES_3840x2160P_25Hz, 146 RES_3840x2160P_30Hz, 147 RES_3840x2160P_50Hz, 148 RES_3840x2160P_60Hz, 149 RES_4096x2160P_24Hz, 150 RES_4096x2160P_25Hz, 151 RES_4096x2160P_30Hz, 152 RES_4096x2160P_50Hz, 153 RES_4096x2160P_60Hz, 154 RES_3840x2160P420_30Hz, 155 RES_3840x2160P420_50Hz, 156 RES_3840x2160P420_60Hz, 157 RES_4096x2160P420_30Hz, 158 RES_4096x2160P420_50Hz, 159 RES_4096x2160P420_60Hz, 160 RES_1600x1200P_60Hz, 161 RES_1440x900P_60Hz, 162 RES_1280x1024P_60Hz, 163 RES_1024x768P_60Hz, 164 } EN_OUTPUT_VIDEO_TIMING_TYPE; 165 166 typedef enum 167 { 168 COLOR_8_BIT, 169 COLOR_10_BIT, 170 COLOR_12_BIT, 171 }EN_OUTPUT_BIT_TYPE; 172 173 typedef enum 174 { 175 DAC_CLK_FROM_DISP, 176 DAC_CLK_FROM_VEDAC, 177 DAC_CLK_FROM_DVBC_INN, 178 DAC_CLK_FROM_DVBC_EQ, 179 DAC_CLK_FROM_ADCD_D, 180 DAC_CLK_FROM_DFT, 181 } EN_DAC_CLK_TYPE; 182 183 typedef enum 184 { 185 DAC_TO_HDGEN = 0, //HD Gen output 186 DAC_TO_VE = 1, //VE output (CVBS + S-Video) 187 DAC_TO_VE_YPBPR =3 //VE output (Y/Pb/Pr) 188 } EN_DAC_OUTPUT_TYPE; 189 190 typedef enum 191 { 192 DAC_R_G_B = 0, 193 DAC_R_B_G = 1, 194 DAC_G_R_B = 2, 195 DAC_B_G_R = 4, 196 DAC_G_B_R = 5, 197 DAC_B_R_G = 6, 198 DAC_R_R_R = 7, 199 } EN_DAC_SWAP_SEL; 200 201 typedef enum 202 { 203 DAC_OUTPUT_LEVEL_HIGH = 0, //1.3V 204 DAC_OUTPUT_LEVEL_LOW = 1 //1V 205 } EN_DAC_MAX_OUTPUT_LEVEL; 206 207 typedef enum 208 { 209 DAC_SD_OFF =0, 210 DAC_SD_X = 1, 211 DAC_SD_Y = 2, 212 DAC_SD_XY = 3, 213 DAC_SD_C = 4, 214 DAC_SD_XC = 5, 215 DAC_SD_YC = 6, 216 DAC_SD_XYC = 7, 217 218 }EN_DAC_SD_ENABLE_CTRL; 219 220 typedef enum 221 { 222 DAC_HD_OFF =0, 223 DAC_HD_R = 1, 224 DAC_HD_G = 2, 225 DAC_HD_RG = 3, 226 DAC_HD_B = 4, 227 DAC_HD_RB = 5, 228 DAC_HD_GB = 6, 229 DAC_HD_RGB = 7, 230 231 }EN_DAC_HD_ENABLE_CTRL; 232 233 typedef enum 234 { 235 DAC_DETECT_PLUGIN, //Detect Plug_IN 236 DAC_DETECT_PLUGOUT, // Detect Plug_OUT 237 }EN_DAC_DETECT_TYPE; 238 239 typedef enum 240 { 241 DAC_DETECT_HD, //Detect HD_DAC 242 DAC_DETECT_SD, // Detect SD_DAC 243 }EN_DAC_DETECT; 244 245 typedef enum 246 { 247 DAC_VIDEO_VBI_WSS_START = 0x0000, 248 249 DAC_VIDEO_VBI_WSS_AS_4x3_FULL, 250 DAC_VIDEO_VBI_WSS_AS_14x9_LETTERBOX_CENTER, 251 DAC_VIDEO_VBI_WSS_AS_14x9_LETTERBOX_TOP, 252 DAC_VIDEO_VBI_WSS_AS_16x9_LETTERBOX_CENTER, 253 DAC_VIDEO_VBI_WSS_AS_16x9_LETTERBOX_TOP, 254 DAC_VIDEO_VBI_WSS_AS_ABOVE16x9_LETTERBOX_CENTER, 255 DAC_VIDEO_VBI_WSS_AS_14x9_FULL_CENTER, 256 DAC_VIDEO_VBI_WSS_AS_16x9_ANAMORPHIC, 257 258 DAC_VIDEO_VBI_WSS_CGMS_COPYRIGHT, 259 DAC_VIDEO_VBI_WSS_CGMS_COPY_PROTECTION, 260 261 DAC_VIDEO_VBI_WSS_CGMS_COPY_FREELY, //No Copyright Issue 262 DAC_VIDEO_VBI_WSS_CGMS_COPY_ONCE, //VBI_WSS_COPYRIGHT 263 DAC_VIDEO_VBI_WSS_CGMS_COPY_NO_MORE, //VBI_WSS_COPY_PROTECTION 264 DAC_VIDEO_VBI_WSS_CGMS_COPY_NEVER, //VBI_WSS_COPYRIGHT | VBI_WSS_COPY_PROTECTION 265 266 DAC_VIDEO_VBI_WSS525_A_START = 0x0100, 267 268 DAC_VIDEO_VBI_WSS525_A_AS_4x3_NORMAL, 269 DAC_VIDEO_VBI_WSS525_A_AS_4x3_LETTERBOX, 270 DAC_VIDEO_VBI_WSS525_A_AS_16x9_ANAMORPHIC, //Using in CVBS 271 DAC_VIDEO_VBI_WSS525_A_AS_16x9_NORMAL = DAC_VIDEO_VBI_WSS525_A_AS_16x9_ANAMORPHIC, //Using in YPbPr 272 DAC_VIDEO_VBI_WSS525_A_AS_RESERVED, 273 274 DAC_VIDEO_VBI_WSS525_A_CGMS_COPY_FREELY, 275 DAC_VIDEO_VBI_WSS525_A_CGMS_COPY_ONCE, 276 DAC_VIDEO_VBI_WSS525_A_CGMS_COPY_NO_MORE, 277 DAC_VIDEO_VBI_WSS525_A_CGMS_COPY_NEVER, 278 279 DAC_VIDEO_VBI_WSS525_A_APS_NO_APS, 280 DAC_VIDEO_VBI_WSS525_A_APS_PSP_CS_OFF, 281 DAC_VIDEO_VBI_WSS525_A_APS_PSP_2_LINE_CS, 282 DAC_VIDEO_VBI_WSS525_A_APS_PSP_4_LINE_CS, 283 } EN_DAC_VIDEO_VBI_WSS_TYPE; 284 285 typedef enum 286 { 287 VIDEO_VBI_WSS525_A_AS_4x3_NORMAL = 0x0, 288 VIDEO_VBI_WSS525_A_AS_4x3_LETTERBOX = 0x2, 289 VIDEO_VBI_WSS525_A_AS_16x9_ANAMORPHIC = 0x1, 290 VIDEO_VBI_WSS525_A_AS_16x9_NORMAL = VIDEO_VBI_WSS525_A_AS_16x9_ANAMORPHIC, 291 VIDEO_VBI_WSS525_A_AS_RESERVED = 0x3, 292 }EN_VIDEO_VBI_WSS525_A_AS_TYPE; 293 294 typedef enum 295 { 296 VIDEO_VBI_WSS_AS_4x3_FULL = 0x8, 297 VIDEO_VBI_WSS_AS_14x9_LETTERBOX_CENTER = 0x1, 298 VIDEO_VBI_WSS_AS_14x9_LETTERBOX_TOP = 0x2, 299 VIDEO_VBI_WSS_AS_16x9_LETTERBOX_CENTER = 0xB, 300 VIDEO_VBI_WSS_AS_16x9_LETTERBOX_TOP = 0x4, 301 VIDEO_VBI_WSS_AS_ABOVE16x9_LETTERBOX_CENTER = 0xD, 302 VIDEO_VBI_WSS_AS_14x9_FULL_CENTER = 0xE, 303 VIDEO_VBI_WSS_AS_16x9_ANAMORPHIC = 0x7, 304 }EN_VIDEO_VBI_WSS_AS_TYPE; 305 306 typedef enum 307 { 308 VIDEO_VBI_WSS525_A_CGMS_COPY_FREELY = 0x0, 309 VIDEO_VBI_WSS525_A_CGMS_COPY_ONCE = 0x1, //COPYRIGHT 310 VIDEO_VBI_WSS525_A_CGMS_COPY_NO_MORE = 0x2, //COPY_PROTECTION 311 VIDEO_VBI_WSS525_A_CGMS_COPY_NEVER = (VIDEO_VBI_WSS525_A_CGMS_COPY_ONCE|VIDEO_VBI_WSS525_A_CGMS_COPY_NO_MORE), 312 }EN_VIDEO_VBI_WSS525_A_CGMS_TYPE; 313 314 typedef enum 315 { 316 VIDEO_VBI_WSS_CGMS_COPYRIGHT = 0x1, 317 VIDEO_VBI_WSS_CGMS_COPY_PROTECTION = 0x2, 318 319 VIDEO_VBI_WSS_CGMS_COPY_FREELY = 0x0, 320 VIDEO_VBI_WSS_CGMS_COPY_ONCE = VIDEO_VBI_WSS_CGMS_COPYRIGHT, 321 VIDEO_VBI_WSS_CGMS_COPY_NO_MORE = VIDEO_VBI_WSS_CGMS_COPY_PROTECTION, 322 VIDEO_VBI_WSS_CGMS_COPY_NEVER = (VIDEO_VBI_WSS_CGMS_COPYRIGHT|VIDEO_VBI_WSS_CGMS_COPY_PROTECTION), 323 }EN_VIDEO_VBI_WSS_CGMS_TYPE; 324 325 typedef enum 326 { 327 VIDEO_VBI_WSS525_A_APS_NO_APS = 0x0, 328 VIDEO_VBI_WSS525_A_APS_PSP_CS_OFF = 0x2, 329 VIDEO_VBI_WSS525_A_APS_PSP_2_LINE_CS = 0x1, 330 VIDEO_VBI_WSS525_A_APS_PSP_4_LINE_CS = 0x3, 331 }EN_VIDEO_VBI_WSS525_A_APS_TYPE; 332 333 //------------------------------------------------------------------------------------------------- 334 // Function Prototype 335 //------------------------------------------------------------------------------------------------- 336 #ifdef MDRV_DAC_C 337 #define MDRV_INTERFACE 338 #else 339 #define MDRV_INTERFACE extern 340 #endif 341 342 MDRV_INTERFACE void MDrv_DAC_SetIOMapBase(MS_VIRT virtNPMBase, MS_VIRT virtPMBase); 343 MDRV_INTERFACE void MDrv_DAC_Init(void); 344 MDRV_INTERFACE void MDrv_DAC_Enable(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 345 MDRV_INTERFACE void MDrv_DAC_SetClkInv(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 346 MDRV_INTERFACE void MDrv_DAC_SetOutputSource(EN_DAC_OUTPUT_TYPE enOutputType, MS_BOOL bIsYPbPr); 347 MDRV_INTERFACE void MDrv_DAC_SetOutputLevel(EN_DAC_MAX_OUTPUT_LEVEL enLevel, MS_BOOL bIsYPbPr); 348 MDRV_INTERFACE void MDrv_DAC_SetOutputSwapSel(EN_DAC_SWAP_SEL enSwap,MS_BOOL bIsYPbPr); 349 MDRV_INTERFACE void MDrv_DAC_SetOutputTiming(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming); 350 MDRV_INTERFACE void MDrv_ClkSel_Set(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming, EN_OUTPUT_BIT_TYPE enBits); 351 MDRV_INTERFACE void MDrv_DAC_OnOffSD(EN_DAC_SD_ENABLE_CTRL enBit); 352 MDRV_INTERFACE EN_DAC_SD_ENABLE_CTRL MDrv_DAC_GetSDStatus(void); 353 MDRV_INTERFACE void MDrv_DAC_OnOffHD(EN_DAC_HD_ENABLE_CTRL enBit); 354 MDRV_INTERFACE EN_DAC_HD_ENABLE_CTRL MDrv_DAC_GetHDStatus(void); 355 MDRV_INTERFACE void MDrv_DAC_Exit(void); 356 MDRV_INTERFACE void MDrv_DAC_DumpTable(MS_U8 * pTCONTable, MS_U8 u8Tcontype); 357 MDRV_INTERFACE void MDrv_DAC_SetWSSOnOff(MS_BOOL bEnable); 358 MDRV_INTERFACE MS_BOOL MDrv_DAC_GetWSSStatus(void); 359 MDRV_INTERFACE void MDrv_DAC_ResetWSSData(void); 360 MDRV_INTERFACE MS_BOOL MDrv_DAC_WSS_SetAS(MS_BOOL bEnable, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, EN_DAC_VIDEO_VBI_WSS_TYPE eWSS_TYPE); 361 MDRV_INTERFACE MS_BOOL MDrv_DAC_WSS_SetCGMS(MS_BOOL bEnable, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, EN_DAC_VIDEO_VBI_WSS_TYPE eWSS_TYPE); 362 MDRV_INTERFACE MS_BOOL MDrv_DAC_WSS_SetAPS(MS_BOOL bEnable, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, EN_DAC_VIDEO_VBI_WSS_TYPE eWSS_TYPE); 363 364 #ifdef UFO_XC_GETOUTPUTINTELACETIMING 365 //---------------------------------------------------------------- 366 // MDrv_DAC_GetOutputInterlaceTiming - Get InterlaceTiming 367 // @return: TRUE is InterlaceTiming 368 //---------------------------------------------------------------- 369 MDRV_INTERFACE MS_BOOL MDrv_DAC_GetOutputInterlaceTiming(void); 370 #endif 371 //---------------------------------------------------------------- 372 // DAC - set half output current 373 // @return none 374 //---------------------------------------------------------------- 375 MDRV_INTERFACE void MDrv_DAC_SetIHalfOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 376 377 //---------------------------------------------------------------- 378 // DAC - set half output current 379 // @return none 380 //---------------------------------------------------------------- 381 MDRV_INTERFACE void MDrv_DAC_SetQuartOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 382 383 //---------------------------------------------------------------- 384 // MDrv_DAC_SetDACState - Set DAC init state 385 // @param: bEnable: TRUE for DAC is initialized, FALSE for not initialized 386 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS 387 // @return none 388 //---------------------------------------------------------------- 389 MDRV_INTERFACE void MDrv_DAC_SetDACState(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 390 391 //---------------------------------------------------------------- 392 // MDrv_DAC_GetDACState - Get DAC init state 393 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS 394 // @return: TRUE is DAC is initialized 395 //---------------------------------------------------------------- 396 MDRV_INTERFACE MS_BOOL MDrv_DAC_GetDACState(MS_BOOL bIsYPbPr); 397 398 //---------------------------------------------------------------- 399 // MDrv_DAC_HotPlugDetect - Get DAC HotPlug state 400 // @param: SelDAC: DAC_DETECT_HD, DAC_DETECT_SD 401 // @param: DetectType: DAC_DETECT_PLUGIN, DAC_DETECT_PLUGOUT 402 // @param: bIsSignIn: Report signal is in/out 403 // @return: TRUE is working successful 404 //---------------------------------------------------------------- 405 MDRV_INTERFACE MS_BOOL MDrv_DAC_HotPlugDetect(EN_DAC_DETECT SelDAC, EN_DAC_DETECT_TYPE DetectType, MS_BOOL *State); 406 407 //---------------------------------------------------------------- 408 // MDrv_DAC_EnableICT - Enable ICT (Image Constraint Token) function 409 // @bEnable: TRUE: enable, FALSE: disable 410 // @return: TRUE is working successful 411 //---------------------------------------------------------------- 412 MDRV_INTERFACE MS_BOOL MDrv_DAC_EnableICT(MS_BOOL bEnable); 413 414 //---------------------------------------------------------------- 415 // DAC - set VGA Hsync Vsync 416 // @return none 417 //---------------------------------------------------------------- 418 MDRV_INTERFACE void MDrv_DAC_SetVGAHsyncVsync(MS_BOOL bEnable); 419 420 421 #ifdef __cplusplus 422 } 423 #endif 424 425 #endif // _DRV_HDMITX_H_ 426 427