1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Shunqing Chen <csq@rock-chips.com> 6 */ 7 8 #ifndef __RK628_HDMIRX_H 9 #define __RK628_HDMIRX_H 10 11 #include "rk628.h" 12 13 /* --------- EDID and HDCP KEY ------- */ 14 #define EDID_BASE 0x000a0000 15 #define HDCP_KEY_BASE 0x000a8000 16 #define HDCP_KEY_KSV0 (HDCP_KEY_BASE + 4) 17 #define HDCP_KEY_DPK0 (HDCP_KEY_BASE + 36) 18 19 #define KEY_MAX_REGISTER 0x000a8490 20 21 /* --------- GPIO0 REG --------------- */ 22 #define GPIO0_SWPORT_DDR_L 0xd0008 23 #define GPIO1_SWPORT_DR_L 0xe0000 24 #define GPIO1_SWPORT_DDR_L 0xe0008 25 #define GPIO1_VER_ID 0xe0078 26 27 /* --------- HDMI RX REG ------------- */ 28 #define HDMI_RX_BASE 0x00030000 29 #define HDMI_RX_HDMI_SETUP_CTRL (HDMI_RX_BASE + 0x0000) 30 #define HOT_PLUG_DETECT_INPUT_A_MASK BIT(24) 31 #define HOT_PLUG_DETECT_INPUT_A(x) UPDATE(x, 24, 24) 32 #define HOT_PLUG_DETECT_MASK BIT(0) 33 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0) 34 #define HDMI_RX_HDMI_TIMER_CTRL (HDMI_RX_BASE + 0x0008) 35 #define HDMI_RX_HDMI_RES_OVR (HDMI_RX_BASE + 0x0010) 36 #define HDMI_RX_HDMI_PLL_FRQSET2 (HDMI_RX_BASE + 0x0020) 37 #define HDMI_RX_HDMI_PCB_CTRL (HDMI_RX_BASE + 0x0038) 38 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18) 39 #define INPUT_SELECT_MASK BIT(16) 40 #define INPUT_SELECT(x) UPDATE(x, 16, 16) 41 #define HDMI_RX_HDMI_PHS_CTR (HDMI_RX_BASE + 0x0040) 42 #define HDMI_RX_HDMI_EQ_MEAS_CTRL (HDMI_RX_BASE + 0x005c) 43 #define HDMI_RX_HDMI_CTRL (HDMI_RX_BASE + 0x0064) 44 #define HDMI_RX_HDMI_MODE_RECOVER (HDMI_RX_BASE + 0x0080) 45 #define SPIKE_FILTER_EN_MASK BIT(18) 46 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18) 47 #define DVI_MODE_HYST_MASK GENMASK(17, 13) 48 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13) 49 #define HDMI_MODE_HYST_MASK GENMASK(12, 8) 50 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8) 51 #define HDMI_MODE_MASK GENMASK(7, 6) 52 #define HDMI_MODE(x) UPDATE(x, 7, 6) 53 #define GB_DET_MASK GENMASK(5, 4) 54 #define GB_DET(x) UPDATE(x, 5, 4) 55 #define EESS_OESS_MASK GENMASK(3, 2) 56 #define EESS_OESS(x) UPDATE(x, 3, 2) 57 #define SEL_CTL01_MASK GENMASK(1, 0) 58 #define SEL_CTL01(x) UPDATE(x, 1, 0) 59 #define HDMI_RX_HDMI_ERROR_PROTECT (HDMI_RX_BASE + 0x0084) 60 #define RG_BLOCK_OFF(x) UPDATE(x, 20, 20) 61 #define BLOCK_OFF(x) UPDATE(x, 19, 19) 62 #define VALID_MODE(x) UPDATE(x, 18, 16) 63 #define CTRL_FILT_SENS(x) UPDATE(x, 13, 12) 64 #define VS_FILT_SENS(x) UPDATE(x, 11, 10) 65 #define HS_FILT_SENS(x) UPDATE(x, 9, 8) 66 #define DE_MEASURE_MODE(x) UPDATE(x, 7, 6) 67 #define DE_REGEN(x) UPDATE(x, 5, 5) 68 #define DE_FILTER_SENS(x) UPDATE(x, 4, 3) 69 #define HDMI_RX_HDMI_ERD_STS (HDMI_RX_BASE + 0x0088) 70 #define HDMI_RX_HDMI_SYNC_CTRL (HDMI_RX_BASE + 0x0090) 71 #define VS_POL_ADJ_MODE_MASK GENMASK(4, 3) 72 #define VS_POL_ADJ_MODE(x) UPDATE(x, 4, 3) 73 #define HS_POL_ADJ_MODE_MASK GENMASK(2, 1) 74 #define HS_POL_ADJ_MODE(x) UPDATE(x, 2, 1) 75 #define HDMI_RX_HDMI_CKM_EVLTM (HDMI_RX_BASE + 0x0094) 76 #define HDMI_RX_HDMI_CKM_F (HDMI_RX_BASE + 0x0098) 77 #define HDMI_RX_HDMI_CKM_RESULT (HDMI_RX_BASE + 0x009c) 78 #define HDMI_RX_HDMI_RESMPL_CTRL (HDMI_RX_BASE + 0x00a4) 79 #define HDMI_RX_HDMI_DCM_CTRL (HDMI_RX_BASE + 0x00a8) 80 #define DCM_DEFAULT_PHASE(x) UPDATE(x, 18, 18) 81 #define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12) 82 #define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8) 83 #define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2) 84 #define HDMI_VM_CFG_CH2 (HDMI_RX_BASE + 0x00b4) 85 #define HDMI_RX_HDCP_CTRL (HDMI_RX_BASE + 0x00c0) 86 #define HDCP_ENABLE_MASK BIT(24) 87 #define HDCP_ENABLE(x) UPDATE(x, 24, 24) 88 #define FREEZE_HDCP_FSM_MASK BIT(21) 89 #define FREEZE_HDCP_FSM(x) UPDATE(x, 21, 21) 90 #define FREEZE_HDCP_STATE_MASK GENMASK(20, 15) 91 #define FREEZE_HDCP_STATE(x) UPDATE(x, 20, 15) 92 #define HDCP_CTL_MASK GENMASK(9, 8) 93 #define HDCP_CTL(x) UPDATE(x, 9, 8) 94 #define HDCP_RI_RATE_MASK GENMASK(7, 6) 95 #define HDCP_RI_RATE(x) UPDATE(x, 7, 6) 96 #define HDMI_MODE_ENABLE_MASK BIT(2) 97 #define HDMI_MODE_ENABLE(x) UPDATE(x, 2, 2) 98 #define KEY_DECRIPT_ENABLE_MASK BIT(1) 99 #define KEY_DECRIPT_ENABLE(x) UPDATE(x, 1, 1) 100 #define HDCP_ENC_EN_MASK BIT(0) 101 #define HDCP_ENC_EN(x) UPDATE(x, 0, 0) 102 #define HDMI_RX_HDCP_SETTINGS (HDMI_RX_BASE + 0x00c4) 103 #define HDMI_RESERVED(x) UPDATE(x, 13, 13) 104 #define HDMI_RESERVED_MASK BIT(13) 105 #define FAST_I2C(x) UPDATE(x, 12, 12) 106 #define FAST_I2C_MASK BIT(12) 107 #define ONE_DOT_ONE(x) UPDATE(x, 9, 9) 108 #define ONE_DOT_ONE_MASK BIT(9) 109 #define FAST_REAUTH(x) UPDATE(x, 8, 8) 110 #define FAST_REAUTH_MASK BIT(8) 111 #define HDMI_RX_HDCP_SEED (HDMI_RX_BASE + 0x00c8) 112 #define HDMI_RX_HDCP_KIDX (HDMI_RX_BASE + 0x00d4) 113 #define HDMI_RX_HDCP_DBG (HDMI_RX_BASE + 0x00e0) 114 #define HDMI_RX_HDCP_AN0 (HDMI_RX_BASE + 0x00f0) 115 #define HDMI_RX_HDCP_STS (HDMI_RX_BASE + 0x00fc) 116 #define HDMI_RX_MD_HCTRL1 (HDMI_RX_BASE + 0x0140) 117 #define HACT_PIX_ITH(x) UPDATE(x, 10, 8) 118 #define HACT_PIX_SRC(x) UPDATE(x, 5, 5) 119 #define HTOT_PIX_SRC(x) UPDATE(x, 4, 4) 120 #define HDMI_RX_MD_HCTRL2 (HDMI_RX_BASE + 0x0144) 121 #define HS_CLK_ITH(x) UPDATE(x, 14, 12) 122 #define HTOT32_CLK_ITH(x) UPDATE(x, 9, 8) 123 #define VS_ACT_TIME(x) UPDATE(x, 5, 5) 124 #define HS_ACT_TIME(x) UPDATE(x, 4, 3) 125 #define H_START_POS(x) UPDATE(x, 1, 0) 126 #define HDMI_RX_MD_HT0 (HDMI_RX_BASE + 0x0148) 127 #define HDMI_RX_MD_HT1 (HDMI_RX_BASE + 0x014c) 128 #define HDMI_RX_MD_HACT_PX (HDMI_RX_BASE + 0x0150) 129 #define HDMI_RX_MD_VCTRL (HDMI_RX_BASE + 0x0158) 130 #define V_OFFS_LIN_MODE(x) UPDATE(x, 4, 4) 131 #define V_EDGE(x) UPDATE(x, 1, 1) 132 #define V_MODE(x) UPDATE(x, 0, 0) 133 #define HDMI_RX_MD_VSC (HDMI_RX_BASE + 0x015c) 134 #define HDMI_RX_MD_VOL (HDMI_RX_BASE + 0x0164) 135 #define HDMI_RX_MD_VAL (HDMI_RX_BASE + 0x0168) 136 #define HDMI_RX_MD_VTH (HDMI_RX_BASE + 0x016c) 137 #define VOFS_LIN_ITH(x) UPDATE(x, 11, 10) 138 #define VACT_LIN_ITH(x) UPDATE(x, 9, 8) 139 #define VTOT_LIN_ITH(x) UPDATE(x, 7, 6) 140 #define VS_CLK_ITH(x) UPDATE(x, 5, 3) 141 #define VTOT_CLK_ITH(x) UPDATE(x, 2, 0) 142 #define HDMI_RX_MD_VTL (HDMI_RX_BASE + 0x0170) 143 #define HDMI_RX_MD_IL_POL (HDMI_RX_BASE + 0x017c) 144 #define FAFIELDDET_EN(x) UPDATE(x, 2, 2) 145 #define FIELD_POL_MODE(x) UPDATE(x, 1, 0) 146 #define HDMI_RX_MD_STS (HDMI_RX_BASE + 0x0180) 147 #define ILACE_STS BIT(3) 148 #define HDMI_RX_AUD_CTRL (HDMI_RX_BASE + 0x0200) 149 #define HDMI_RX_AUD_PLL_CTRL (HDMI_RX_BASE + 0x0208) 150 #define PLL_LOCK_TOGGLE_DIV_MASK GENMASK(27, 24) 151 #define PLL_LOCK_TOGGLE_DIV(x) UPDATE(x, 27, 24) 152 #define HDMI_RX_AUD_CLK_CTRL (HDMI_RX_BASE + 0x0214) 153 #define CTS_N_REF_MASK BIT(4) 154 #define CTS_N_REF(x) UPDATE(x, 4, 4) 155 #define HDMI_RX_AUD_FIFO_CTRL (HDMI_RX_BASE + 0x0240) 156 #define AFIF_SUBPACKET_DESEL_MASK GENMASK(27, 24) 157 #define AFIF_SUBPACKET_DESEL(x) UPDATE(x, 27, 24) 158 #define AFIF_SUBPACKETS_MASK BIT(16) 159 #define AFIF_SUBPACKETS(x) UPDATE(x, 16, 16) 160 #define HDMI_RX_AUD_FIFO_TH (HDMI_RX_BASE + 0x0244) 161 #define AFIF_TH_START_MASK GENMASK(26, 18) 162 #define AFIF_TH_START(x) UPDATE(x, 26, 18) 163 #define AFIF_TH_MAX_MASK GENMASK(17, 9) 164 #define AFIF_TH_MAX(x) UPDATE(x, 17, 9) 165 #define AFIF_TH_MIN_MASK GENMASK(8, 0) 166 #define AFIF_TH_MIN(x) UPDATE(x, 8, 0) 167 #define HDMI_RX_AUD_CHEXTR_CTRL (HDMI_RX_BASE + 0x0254) 168 #define AUD_LAYOUT_CTRL(x) UPDATE(x, 1, 0) 169 #define HDMI_RX_AUD_MUTE_CTRL (HDMI_RX_BASE + 0x0258) 170 #define APPLY_INT_MUTE(x) UPDATE(x, 31, 31) 171 #define APORT_SHDW_CTRL(x) UPDATE(x, 22, 21) 172 #define AUTO_ACLK_MUTE(x) UPDATE(x, 20, 19) 173 #define AUD_MUTE_SPEED(x) UPDATE(x, 16, 10) 174 #define AUD_AVMUTE_EN(x) UPDATE(x, 7, 7) 175 #define AUD_MUTE_SEL(x) UPDATE(x, 6, 5) 176 #define AUD_MUTE_MODE(x) UPDATE(x, 4, 3) 177 #define HDMI_RX_AUD_FIFO_FILLSTS1 (HDMI_RX_BASE + 0x025c) 178 #define HDMI_RX_AUD_SAO_CTRL (HDMI_RX_BASE + 0x0260) 179 #define I2S_ENABLE_BITS_MASK GENMASK(10, 5) 180 #define I2S_ENABLE_BITS(x) UPDATE(x, 10, 5) 181 #define I2S_LPCM_BPCUV_MASK BIT(11) 182 #define I2S_LPCM_BPCUV(x) UPDATE(x, 11, 11) 183 #define I2S_32_16_MASK BIT(0) 184 #define I2S_32_16(x) UPDATE(x, 0, 0) 185 #define HDMI_RX_AUD_PAO_CTRL (HDMI_RX_BASE + 0x0264) 186 #define PAO_RATE(x) UPDATE(x, 17, 16) 187 #define HDMI_RX_AUD_FIFO_STS (HDMI_RX_BASE + 0x027c) 188 #define HDMI_RX_AUDPLL_GEN_CTS (HDMI_RX_BASE + 0x0280) 189 #define HDMI_RX_AUDPLL_GEN_N (HDMI_RX_BASE + 0x0284) 190 #define HDMI_RX_SNPS_PHYG3_CTRL (HDMI_RX_BASE + 0x02c0) 191 #define PORTSELECT(x) UPDATE(x, 3, 2) 192 #define HDMI_RX_PDEC_CTRL (HDMI_RX_BASE + 0x0300) 193 #define PFIFO_STORE_FILTER_EN_MASK BIT(31) 194 #define PFIFO_STORE_FILTER_EN(x) UPDATE(x, 31, 31) 195 #define PFIFO_STORE_DRM_IF_MASK BIT(29) 196 #define PFIFO_STORE_DRM_IF(x) UPDATE(x, 29, 29) 197 #define PFIFO_STORE_AMP_MASK BIT(28) 198 #define PFIFO_STORE_AMP(x) UPDATE(x, 28, 28) 199 #define PFIFO_STORE_NTSCVBI_IF_MASK BIT(27) 200 #define PFIFO_STORE_NTSCVBI_IF(x) UPDATE(x, 27, 27) 201 #define PFIFO_STORE_MPEGS_IF_MASK BIT(26) 202 #define PFIFO_STORE_MPEGS_IF(x) UPDATE(x, 26, 26) 203 #define PFIFO_STORE_AUD_IF_MASK BIT(25) 204 #define PFIFO_STORE_AUD_IF(x) UPDATE(x, 25, 25) 205 #define PFIFO_STORE_SPD_IF_MASK BIT(24) 206 #define PFIFO_STORE_SPD_IF(x) UPDATE(x, 24, 24) 207 #define PFIFO_STORE_AVI_IF_MASK BIT(23) 208 #define PFIFO_STORE_AVI_IF(x) UPDATE(x, 23, 23) 209 #define PFIFO_STORE_VS_IF_MASK BIT(22) 210 #define PFIFO_STORE_VS_IF(x) UPDATE(x, 22, 22) 211 #define PFIFO_STORE_GMTP_MASK BIT(21) 212 #define PFIFO_STORE_GMTP(x) UPDATE(x, 21, 21) 213 #define PFIFO_STORE_ISRC2_MASK BIT(20) 214 #define PFIFO_STORE_ISRC2(x) UPDATE(x, 20, 20) 215 #define PFIFO_STORE_ISRC1_MASK BIT(19) 216 #define PFIFO_STORE_ISRC1(x) UPDATE(x, 19, 19) 217 #define PFIFO_STORE_ACP_MASK BIT(18) 218 #define PFIFO_STORE_ACP(x) UPDATE(x, 18, 18) 219 #define PFIFO_STORE_GCP_MASK BIT(17) 220 #define PFIFO_STORE_GCP(x) UPDATE(x, 17, 17) 221 #define PFIFO_STORE_ACR_MASK BIT(16) 222 #define PFIFO_STORE_ACR(x) UPDATE(x, 16, 16) 223 #define GCPFORCE_SETAVMUTE_MASK BIT(13) 224 #define GCPFORCE_SETAVMUTE(x) UPDATE(x, 13, 13) 225 #define PDEC_BCH_EN_MASK BIT(0) 226 #define PDEC_BCH_EN(x) UPDATE(x, 0, 0) 227 #define HDMI_RX_PDEC_FIFO_CFG (HDMI_RX_BASE + 0x0304) 228 #define HDMI_RX_PDEC_AUDIODET_CTRL (HDMI_RX_BASE + 0x0310) 229 #define AUDIODET_THRESHOLD(x) UPDATE(x, 13, 9) 230 #define HDMI_RX_PDEC_ACRM_CTRL (HDMI_RX_BASE + 0x0330) 231 #define DELTACTS_IRQTRIG(x) UPDATE(x, 4, 2) 232 #define HDMI_RX_PDEC_ERR_FILTER (HDMI_RX_BASE + 0x033c) 233 #define HDMI_RX_PDEC_ASP_CTRL (HDMI_RX_BASE + 0x0340) 234 #define HDMI_RX_PDEC_STS (HDMI_RX_BASE + 0x0360) 235 #define DVI_DET BIT(28) 236 #define HDMI_RX_PDEC_GCP_AVMUTE (HDMI_RX_BASE + 0x0380) 237 #define HDMI_RX_PDEC_AVI_PB (HDMI_RX_BASE + 0x03a4) 238 #define VIDEO_FORMAT_MASK GENMASK(6, 5) 239 #define VIDEO_FORMAT(x) UPDATE(x, 6, 5) 240 #define ACT_INFO_PRESENT_MASK BIT(4) 241 #define HDMI_RX_PDEC_ACR_CTS (HDMI_RX_BASE + 0x0390) 242 #define HDMI_RX_PDEC_ACR_N (HDMI_RX_BASE + 0x0394) 243 #define HDMI_RX_PDEC_AIF_CTRL (HDMI_RX_BASE + 0x03c0) 244 #define FC_LFE_EXCHG(x) UPDATE(x, 18, 18) 245 #define HDMI_RX_PDEC_AIF_PB0 (HDMI_RX_BASE + 0x03c8) 246 247 #define HDMI_RX_HDMI20_CONTROL (HDMI_RX_BASE + 0x0800) 248 #define PVO1UNMUTE(x) UPDATE(x, 29, 29) 249 #define PIXELMODE(x) UPDATE(x, 28, 28) 250 #define CTRLCHECKEN(x) UPDATE(x, 8, 8) 251 #define SCDC_ENABLE(x) UPDATE(x, 4, 4) 252 #define SCRAMBEN_SEL(x) UPDATE(x, 1, 0) 253 #define HDMI_RX_SCDC_I2CCONFIG (HDMI_RX_BASE + 0x0804) 254 #define I2CSPIKESUPPR(x) UPDATE(x, 25, 24) 255 #define HDMI_RX_SCDC_CONFIG (HDMI_RX_BASE + 0x0808) 256 #define POWERPROVIDED_MASK BIT(0) 257 #define HDMI_RX_CHLOCK_CONFIG (HDMI_RX_BASE + 0x080c) 258 #define CHLOCKMAXER(x) UPDATE(x, 29, 20) 259 #define MILISECTIMERLIMIT(x) UPDATE(x, 15, 0) 260 #define HDMI_RX_HDCP22_CONTROL (HDMI_RX_BASE + 0x081c) 261 #define HDMI_RX_SCDC_REGS0 (HDMI_RX_BASE + 0x0820) 262 #define HDMI_RX_SCDC_REGS1 (HDMI_RX_BASE + 0x0824) 263 #define HDMI_RX_SCDC_REGS2 (HDMI_RX_BASE + 0x0828) 264 #define HDMI_RX_SCDC_REGS3 (HDMI_RX_BASE + 0x082c) 265 #define HDMI_RX_SCDC_WRDATA0 (HDMI_RX_BASE + 0x0860) 266 #define MANUFACTUREROUI(x) UPDATE(x, 31, 8) 267 #define SINKVERSION(x) UPDATE(x, 7, 0) 268 269 #define HDMI_RX_HDMI2_IEN_CLR (HDMI_RX_BASE + 0x0f60) 270 #define HDMI_RX_HDMI2_ISTS (HDMI_RX_BASE + 0x0f68) 271 #define HDMI_RX_PDEC_IEN_CLR (HDMI_RX_BASE + 0x0f78) 272 #define ACR_N_CHG_ICLR BIT(23) 273 #define ACR_CTS_CHG_ICLR BIT(22) 274 #define GCP_AV_MUTE_CHG_ENCLR BIT(21) 275 #define AIF_RCV_ENCLR BIT(19) 276 #define AVI_RCV_ENCLR BIT(18) 277 #define GCP_RCV_ENCLR BIT(16) 278 #define HDMI_RX_PDEC_IEN_SET (HDMI_RX_BASE + 0x0f7c) 279 #define ACR_N_CHG_IEN BIT(23) 280 #define ACR_CTS_CHG_IEN BIT(22) 281 #define GCP_AV_MUTE_CHG_ENSET BIT(21) 282 #define AIF_RCV_ENSET BIT(19) 283 #define AVI_RCV_ENSET BIT(18) 284 #define GCP_RCV_ENSET BIT(16) 285 #define AMP_RCV_ENSET BIT(14) 286 #define HDMI_RX_PDEC_ISTS (HDMI_RX_BASE + 0x0f80) 287 #define GCP_AV_MUTE_CHG_ISTS BIT(21) 288 #define AIF_RCV_ISTS BIT(19) 289 #define AVI_RCV_ISTS BIT(18) 290 #define GCP_RCV_ISTS BIT(16) 291 #define AMP_RCV_ISTS BIT(14) 292 #define HDMI_RX_PDEC_IEN (HDMI_RX_BASE + 0x0f84) 293 #define HDMI_RX_PDEC_ICLR (HDMI_RX_BASE + 0x0f88) 294 #define HDMI_RX_PDEC_ISET (HDMI_RX_BASE + 0x0f8c) 295 #define HDMI_RX_AUD_CEC_IEN_CLR (HDMI_RX_BASE + 0x0f90) 296 #define HDMI_RX_AUD_CEC_IEN (HDMI_RX_BASE + 0x0f9c) 297 #define HDMI_RX_AUD_FIFO_IEN_CLR (HDMI_RX_BASE + 0x0fa8) 298 #define HDMI_RX_AUD_FIFO_IEN_SET (HDMI_RX_BASE + 0x0fac) 299 #define AFIF_OVERFL_ENSET BIT(4) 300 #define AFIF_UNDERFL_ENSET BIT(3) 301 #define AFIF_THS_PASS_ENSET BIT(2) 302 #define AFIF_TH_MAX_ENSET BIT(1) 303 #define AFIF_TH_MIN_ENSET BIT(0) 304 #define HDMI_RX_AUD_FIFO_ISTS (HDMI_RX_BASE + 0x0fb0) 305 #define AFIF_OVERFL_ISTS BIT(4) 306 #define AFIF_UNDERFL_ISTS BIT(3) 307 #define AFIF_THS_PASS_ISTS BIT(2) 308 #define AFIF_TH_MAX_ISTS BIT(1) 309 #define AFIF_TH_MIN_ISTS BIT(0) 310 #define HDMI_RX_AUD_FIFO_IEN (HDMI_RX_BASE + 0x0fb4) 311 #define HDMI_RX_AUD_FIFO_ICLR (HDMI_RX_BASE + 0x0fb8) 312 #define HDMI_RX_MD_IEN_CLR (HDMI_RX_BASE + 0x0fc0) 313 #define HDMI_RX_MD_IEN_SET (HDMI_RX_BASE + 0x0fc4) 314 #define VACT_LIN_ENSET BIT(9) 315 #define HACT_PIX_ENSET BIT(6) 316 #define HS_CLK_ENSET BIT(5) 317 #define DE_ACTIVITY_ENSET BIT(2) 318 #define VS_ACT_ENSET BIT(1) 319 #define HS_ACT_ENSET BIT(0) 320 #define HDMI_RX_MD_ISTS (HDMI_RX_BASE + 0x0fc8) 321 #define VACT_LIN_ISTS BIT(9) 322 #define HACT_PIX_ISTS BIT(6) 323 #define HS_CLK_ISTS BIT(5) 324 #define DE_ACTIVITY_ISTS BIT(2) 325 #define VS_ACT_ISTS BIT(1) 326 #define HS_ACT_ISTS BIT(0) 327 #define HDMI_RX_MD_IEN (HDMI_RX_BASE + 0x0fcc) 328 #define HDMI_RX_MD_ICLR (HDMI_RX_BASE + 0x0fd0) 329 #define HDMI_RX_MD_ISET (HDMI_RX_BASE + 0x0fd4) 330 #define HDMI_RX_HDMI_IEN_CLR (HDMI_RX_BASE + 0x0fd8) 331 #define CLK_CHANGE_ENCLR BIT(6) 332 #define HDMI_RX_HDMI_IEN_SET (HDMI_RX_BASE + 0x0fdc) 333 #define CLK_CHANGE_ENSET BIT(6) 334 #define HDMI_RX_HDMI_ISTS (HDMI_RX_BASE + 0x0fe0) 335 #define CLK_CHANGE_ISTS BIT(6) 336 #define HDMI_RX_HDMI_IEN (HDMI_RX_BASE + 0x0fe4) 337 #define HDMI_RX_HDMI_ICLR (HDMI_RX_BASE + 0x0fe8) 338 #define HDMI_RX_HDMI_ISET (HDMI_RX_BASE + 0x0fec) 339 #define CLK_CHANGE_CLR BIT(6) 340 #define HDCP_DKSET_DONE_ISTS_MASK BIT(31) 341 #define HDMI_RX_DMI_SW_RST (HDMI_RX_BASE + 0x0ff0) 342 #define HDMI_RX_DMI_DISABLE_IF (HDMI_RX_BASE + 0x0ff4) 343 #define VID_ENABLE(x) UPDATE(x, 7, 7) 344 #define VID_ENABLE_MASK BIT(7) 345 #define AUD_ENABLE(x) UPDATE(x, 4, 4) 346 #define AUD_ENABLE_MASK BIT(4) 347 #define HDMI_ENABLE(x) UPDATE(x, 2, 2) 348 #define HDMI_ENABLE_MASK BIT(2) 349 350 #define HDMI_RX_IVECTOR_INDEX_CB (HDMI_RX_BASE + 0x32e4) 351 #define HDMI_RX_MAX_REGISTER HDMI_RX_IVECTOR_INDEX_CB 352 353 #define HDCP_KEY_KSV_SIZE 8 354 #define HDCP_PRIVATE_KEY_SIZE 280 355 #define HDCP_KEY_SHA_SIZE 20 356 #define HDCP_KEY_SIZE 308 357 #define HDCP_KEY_SEED_SIZE 2 358 #define KSV_LEN 5 359 360 #define HDMIRX_HDCP1X_ID 13 361 362 struct hdcp_keys { 363 u8 KSV[HDCP_KEY_KSV_SIZE]; 364 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 365 u8 sha[HDCP_KEY_SHA_SIZE]; 366 }; 367 368 struct rk628_hdcp { 369 char *seeds; 370 struct hdcp_keys *keys; 371 }; 372 373 void rk628_hdmirx_set_hdcp(struct rk628 *rk628, struct rk628_hdcp *hdcp, bool en); 374 void rk628_hdmirx_controller_setup(struct rk628 *rk628); 375 376 typedef void *HAUDINFO; 377 HAUDINFO rk628_hdmirx_audioinfo_alloc(struct device *dev, 378 struct mutex *confctl_mutex, 379 struct rk628 *rk628, 380 bool en); 381 void rk628_hdmirx_audio_destroy(HAUDINFO info); 382 void rk628_hdmirx_audio_setup(HAUDINFO info); 383 void rk628_hdmirx_audio_cancel_work_audio(HAUDINFO info, bool sync); 384 void rk628_hdmirx_audio_cancel_work_rate_change(HAUDINFO info, bool sync); 385 bool rk628_hdmirx_audio_present(HAUDINFO info); 386 int rk628_hdmirx_audio_fs(HAUDINFO info); 387 void rk628_hdmirx_audio_i2s_ctrl(HAUDINFO info, bool enable); 388 389 /* for audio isr process */ 390 bool rk628_audio_fifoints_enabled(HAUDINFO info); 391 bool rk628_audio_ctsnints_enabled(HAUDINFO info); 392 void rk628_csi_isr_ctsn(HAUDINFO info, u32 pdec_ints); 393 void rk628_csi_isr_fifoints(HAUDINFO info, u32 fifo_ints); 394 int rk628_is_avi_ready(struct rk628 *rk628, bool avi_rcv_rdy); 395 396 #endif 397