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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef MHAL_XC_CONFIG_H 95 #define MHAL_XC_CONFIG_H 96 97 //------------------------------------------------------------------------------------------------- 98 // Monaco 99 //------------------------------------------------------------------------------------------------- 100 //------------------------------------------------------------------------------------------------- 101 // Chip Configuration 102 //------------------------------------------------------------------------------------------------- 103 #define MAX_XC_DEVICE_NUM (2) 104 #define MAX_XC_DEVICE0_OFFSET (0) 105 #define MAX_XC_DEVICE1_OFFSET (128) 106 107 #define MAX_WINDOW_NUM (2) 108 #define MAX_FRAME_NUM_IN_MEM (4) // Progressive 109 #define MAX_FIELD_NUM_IN_MEM (16) // Interlace 110 #define NUM_OF_DIGITAL_DDCRAM (1) 111 112 #define SCALER_LINE_BUFFER_MAX (4096UL) 113 #define MST_LINE_BFF_MAX MAX(4096, SCALER_LINE_BUFFER_MAX) 114 115 #define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 116 #define SUB_SCALER_LINE_BUFFER_MAX 2048UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 117 #define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 118 119 #define MS_3D_LINE_BFF_MAX (2048UL) 120 #define PHASE_OFFSET_LIMIT (0x400UL) 121 #define PHASE_OFFSET_LIMIT_FREQ_ONLY (0x2000UL) //0x03DFUL // 0x8000UL 122 123 // MIU Word (Bytes) 124 #define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W 125 #define OFFSET_PIXEL_ALIGNMENT (64) 126 #define LPLL_LOOPGAIN (32) //due to bound cale. 127 #define LVDS_MPLL_CLOCK_MHZ (432) 128 #define FRC_OFFSET_PIXEL_ALIGNMENT (128) 129 130 #define FRC_BYTE_PER_WORD 32 131 #define MCDI_BYTE_PER_WORD 32 132 133 //value for pipe vcnt and hcnt delay 134 #define FRC_PIPE_DELAY_VCNT_FRC 0x10 135 #define FRC_PIPE_DELAY_HCNT_FRC 0x140 136 #define FRC_PIPE_DELAY_VCNT_FRC_FHD_OUT 0x06 137 #define FRC_PIPE_DELAY_HCNT_FRC_FHD_OUT 0x140 138 #define FRC_PIPE_DELAY_VCNT_FSC_FHD 0x1D 139 #define FRC_PIPE_DELAY_HCNT_FSC_FHD 0x140 140 #define FRC_PIPE_DELAY_VCNT_FSC_4K 0x0B 141 #define FRC_PIPE_DELAY_HCNT_FSC_4K 0x140 142 #define FRC_PIPE_DELAY_VCNT_FSC_4K_120Hz 0x0A 143 #define FRC_PIPE_DELAY_HCNT_FSC_4K_120Hz 0x140 144 145 #define FRC_PIPE_DELAY_VCNT_FRC_DTV 0x08 146 #define FRC_PIPE_DELAY_HCNT_FRC_DTV 0x140 147 148 #define DEFAULT_STEP_P 4 //conservative step value 149 #define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 150 #define STEP_P 2 //recommended step value -> more faster fpll(T3) 151 #define STEP_I ((STEP_P*STEP_P)/2) 152 #define IPGAIN_REFACTOR 5 153 154 #define F2_WRITE_LIMIT_EN BIT(31) //BK12_1b[15] 155 #define F2_WRITE_LIMIT_MIN BIT(30) //BK12_1b[14] 156 157 #define F1_WRITE_LIMIT_EN BIT(31) //BK12_5b[15] 158 #define F1_WRITE_LIMIT_MIN BIT(30) //BK12_5b[14] 159 160 #define F2_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_1b[15] 161 #define F1_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_5b[15] 162 163 #define F2_V_WRITE_LIMIT_EN BIT(15) //BK12_18[12] 164 #define F1_V_WRITE_LIMIT_EN BIT(15) //BK12_58[12] 165 166 #define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 167 #define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 168 169 #define ADC_MAX_CLK (3500) 170 171 #define SUPPORTED_XC_INT ((1UL << SC_INT_DIPW) | \ 172 (1UL << SC_INT_VSINT) | \ 173 (1UL << SC_INT_F2_VTT_CHG) | \ 174 (1UL << SC_INT_F1_VTT_CHG) | \ 175 (1UL << SC_INT_F2_VS_LOSE) | \ 176 (1UL << SC_INT_F1_VS_LOSE) | \ 177 (1UL << SC_INT_F2_JITTER) | \ 178 (1UL << SC_INT_F1_JITTER) | \ 179 (1UL << SC_INT_F2_IPVS_SB) | \ 180 (1UL << SC_INT_F1_IPVS_SB) | \ 181 (1UL << SC_INT_F2_IPHCS_DET) | \ 182 (1UL << SC_INT_F1_IPHCS_DET) | \ 183 (1UL << SC_INT_F2_HTT_CHG) | \ 184 (1UL << SC_INT_F1_HTT_CHG) | \ 185 (1UL << SC_INT_F2_HS_LOSE) | \ 186 (1UL << SC_INT_F1_HS_LOSE) | \ 187 (1UL << SC_INT_F2_CSOG) | \ 188 (1UL << SC_INT_F1_CSOG) | \ 189 (1UL << SC_INT_F2_ATP_READY) | \ 190 (1UL << SC_INT_F1_ATP_READY)) 191 192 #define SUPPORTED_KERNEL_INT ((1UL << SC_INT_VSINT)) 193 194 //These table definition is from SC_BK0 spec. 195 //Because some chip development is different, it need to check and remap when INT function is used 196 #define IRQ_CLEAN_INKERNEL 1 197 198 #define IRQ_INT_DIPW 0 199 #define IRQ_INT_START 3 200 #define IRQ_INT_RESERVED1 IRQ_INT_START 201 202 #define IRQ_INT_VSINT 4 203 #define IRQ_INT_F2_VTT_CHG 5 204 #define IRQ_INT_F1_VTT_CHG 6 205 #define IRQ_INT_F2_VS_LOSE 7 206 #define IRQ_INT_F1_VS_LOSE 8 207 #define IRQ_INT_F2_JITTER 9 208 #define IRQ_INT_F1_JITTER 10 209 #define IRQ_INT_F2_IPVS_SB 11 210 #define IRQ_INT_F1_IPVS_SB 12 211 #define IRQ_INT_F2_IPHCS_DET 13 212 #define IRQ_INT_F1_IPHCS_DET 14 213 214 #define IRQ_INT_PWM_RP_L_INT 15 215 #define IRQ_INT_PWM_FP_L_INT 16 216 #define IRQ_INT_F2_HTT_CHG 17 217 #define IRQ_INT_F1_HTT_CHG 18 218 #define IRQ_INT_F2_HS_LOSE 19 219 #define IRQ_INT_F1_HS_LOSE 20 220 #define IRQ_INT_PWM_RP_R_INT 21 221 #define IRQ_INT_PWM_FP_R_INT 22 222 #define IRQ_INT_F2_CSOG 23 223 #define IRQ_INT_F1_CSOG 24 224 #define IRQ_INT_F2_RESERVED2 25 225 #define IRQ_INT_F1_RESERVED2 26 226 #define IRQ_INT_F2_ATP_READY 27 227 #define IRQ_INT_F1_ATP_READY 28 228 #define IRQ_INT_F2_RESERVED3 29 229 #define IRQ_INT_F1_RESERVED3 30 230 231 //------------------------------------------------------------------------------------------------- 232 // Chip Feature 233 //------------------------------------------------------------------------------------------------- 234 /* 12 frame mode for progessive */ 235 #define _12FRAME_BUFFER_PMODE_SUPPORTED 1 236 /* 8 frame mode for progessive */ 237 #define _8FRAME_BUFFER_PMODE_SUPPORTED 1 238 /* 6 frame mode for progessive */ 239 #define _6FRAME_BUFFER_PMODE_SUPPORTED 1 240 /* 4 frame mode for progessive */ 241 #define _4FRAME_BUFFER_PMODE_SUPPORTED 1 242 /* 3 frame mode for progessive */ 243 #define _3FRAME_BUFFER_PMODE_SUPPORTED 1 244 /* change Vtt BK68 replace BK10 */ 245 #define PATCH_HW_VTT_LIMITATION 1 246 /* Vtt BK10 not be replaced, CHIP number after U3 */ 247 #define HW_VTT_LIMITATION_CHIPREV 2 248 249 /* 250 Field-packing ( Customized name ) 251 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 252 IPM buffer address). We show one of memory format for example at below. 253 254 Block : Y0 C0 L M Y1 C1 255 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 256 Y0 has 64 * 4 bits ( 8 pixel for each field ). 257 Y1 has 64 * 4 bits ( 8 pixel for each field ). 258 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 259 For cropping, OPM address offset have to multiple 4. 260 */ 261 #define _FIELD_PACKING_MODE_SUPPORTED 1 262 263 #if (_FIELD_PACKING_MODE_SUPPORTED) 264 265 /* Linear mode */ 266 #define _LINEAR_ADDRESS_MODE_SUPPORTED 0 267 268 #else 269 /* Linear mode */ 270 #define _LINEAR_ADDRESS_MODE_SUPPORTED 1 271 272 #endif 273 274 #define SUPPORT_2_FRAME_MIRROR 0 275 276 /* Because fix loop_div, lpll initial set is different between singal port and dual port */ 277 #define _FIX_LOOP_DIV_SUPPORTED 1 278 279 // You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 280 // 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 281 #define ENABLE_8_FIELD_SUPPORTED 0 282 #define ENABLE_16_FIELD_SUPPORTED 1 283 #define ENABLE_OPM_WRITE_SUPPORTED 1 284 #define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 285 #define ENABLE_VD_PRESCALING_TO_DOT75 0 286 #define ENABLE_NONSTD_INPUT_MCNR 0 287 #define ENABLE_REGISTER_SPREAD 1 288 289 #define ENABLE_REQUEST_FBL 1 290 #define DELAY_LINE_SC_UP 7 291 #define DELAY_LINE_SC_DOWN 8 292 293 #define CHANGE_VTT_STEPS 1 294 #define CHANGE_VTT_DELAY 1 295 296 #define SUPPORT_IMMESWITCH 1 297 #define SUPPORT_DVI_AUTO_EQ 1 298 #define SUPPORT_MHL 0 299 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 300 #define SUPPORT_DEVICE1 0 301 #define SUPPORT_SEAMLESS_ZAPPING 0 302 #define SUPPORT_OP2_TEST_PATTERN 1 303 #define SUPPORT_FRCM_MODE 0 304 #define SUPPORT_4K2K_PIP 1 305 #define SUPPORT_KERNEL_MLOAD 1 306 #define SUPPORT_KERNEL_DS 1 307 308 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 309 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 310 311 #define LD_ENABLE 0 // 1 312 #define FRC_INSIDE TRUE //FALSE 313 #define FRC_IP_NUM_Passive 17 //FRC__NUM_FRC_Mapping_mode 314 315 #define ENABLE_SPREADMODE 316 317 #define SUPPORT_FHD_MEMC 318 //#define HW_SUPPORT_FRC_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 319 320 // 480p and 576p have FPLL problem in HV mode. 321 // So only allow HV mode for 720P 322 #define ONLY_ALLOW_HV_MODE_FOR_720P 0 323 324 //For Manhattan U01 GOP HW bug //U02 Fix 325 #define MANHATTAN_GOP_HW_BUG_PATCH 0 326 327 #define _ENABLE_SW_DS 0 328 #define DS_BUFFER_NUM_EX 6 329 #define DS_MAX_INDEX 6 330 331 #define ENABLE_64BITS_COMMAND 1 332 #define ENABLE_64BITS_SPREAD_MODE 1 //need enable ENABLE_64BITS_COMMAND first 333 //------------------------------------------------------------------------------------------------- 334 /// enable ENABLE_MLOAD_SAME_REG_COMBINE you can do: 335 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(N), BIT(N)); 336 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(M), BIT(M)); 337 /// MApi_XC_MLoad_Fire(); 338 //------------------------------------------------------------------------------------------------- 339 #define ENABLE_MLOAD_SAME_REG_COMBINE 1 340 //#define SRAMPD_XC_CLOSE_TEMP 1 341 342 #define IS_SUPPORT_64BITS_COMMAND(bEnable64bitsCmd, u32DeviceID) ((bEnable64bitsCmd == 1) && (u32DeviceID == 0)) 343 #define ENABLE_DS_4_BASEADDR_MODE 1 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 344 #define DS_CMD_LEN_64BITS 8 345 346 #define IS_SUPPORT_DS_SR(fps) 0//((fps >= 230) && (fps <= 600)) 347 // T12, T13 cannot use IP_HDMI for HV mode 348 // We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 349 //Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 350 // and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 351 // Thus, chip could use this flag to determine whether could do HV mode or not. 352 #define SUPPORT_IP_HDMI_FOR_HV_MODE 0 353 354 // version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 355 // version2: nike: 356 // version3: napoli: frc: double frc and width 357 // version4: monaco: frcm and 2p 358 // version5: clippers: 4k2k@60 MVOP directly output to HVSP 359 // version6: Monet/Maya/Manhattan: 360 // for Manhattan pip:1.SC1(1P) Htt = SC0(2P) Htt/2 361 // 2.if xc mute SC1 main, please mute SC0 sub. The same to mute color. 362 // 3.SC1 DE(bank 0x90) HStart = SC0 DE HStart/2, SC1 DE(bank 0x90) Width = SC0 DE Width/2 363 // 4.temp solution:SC0 DE VStart/Vend should add 6, so is SC1 DE Vstart/Vend 364 #define HW_DESIGN_4K2K_VER (6) 365 366 // version0: Not support TV chip as HDMITx 367 // version1: Maserati + Raptor 368 // version2: Maxim + inside HDMITx 369 #define HW_DESIGN_HDMITX_VER (1) 370 371 #define HW_DESIGN_3D_VER (3) 372 #define HW_2DTO3D_SUPPORT TRUE 373 #define HW_2DTO3D_VER (4) 374 #define HW_2DTO3D_BYTE_PER_WORD (32) 375 #define HW_2DTO3D_PATCH FALSE //a1 u01:2d to 3d hw bug 376 #define HW_2DTO3D_BLOCK_DR_BUF_SIZE (0x2200) 377 #define HW_2DTO3D_DD_BUF_SIZE (0xFF00) 378 //HW support check board and pixel alternative 379 #define HW_SUPPORT_3D_CB_AND_PA TRUE 380 #define ENABLE_GOP_T3DPATCH 381 #define VALUE_AUTO_TUNE_AREA_TRIG_4K540P (0x0A) //4k0.5k 3D 382 #define VALUE_DISP_AREA_TRIG_4K540P (0x0D) //4k0.5k 3D 383 // maserati use 4 tap scaling in 3D mode. PQ is 6 tap mode. Line buffer is not enough because 12 line mode is disabled in 3D mode. 384 #define HW_6TAP_MODE_SUPPORT FALSE 385 386 //hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 387 #define HW_3D_SUPPORT_FBL TRUE 388 //M10, A2, J2 ,A5,A6,A3,Agate HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 389 //and for mirror cbcr swap, need check IPM fetch to decide if need swap 390 #define HW_IPM_FETCH_ALIGNMENT TRUE 391 //hw support 2 line mode deinterlace for interlace or not 392 #define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 393 #define HW_CLK_CTRL TRUE 394 #define SUPPORT_OSD_HSLVDS_PATH 1 395 #define MLG_1024 396 397 #define OSD_LAYER_NUM (5) 398 #define VIDEO_OSD_SWITCH_VER (2) 399 400 //#define FA_1920X540_OUTPUT 401 #define XC_SUPPORT_4K2K 1 402 403 // if H/W support 2p mode to achieve 600M HZ 404 #define XC_SUPPORT_2P_MODE TRUE 405 406 //device 1 is interlace out 407 #define XC_DEVICE1_IS_INTERLACE_OUT 0 408 409 //if H/W support force post-Vscalin-down in DS mode 410 #define HW_SUPPORT_FORCE_VSP_IN_DS_MODE TRUE 411 412 //if H/W support LPLL lock freqence not lock phase mode 413 #define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE TRUE 414 415 // if H/W support interlace output timing 416 #define HW_SUPPORT_INTERLACE_OUTPUT TRUE 417 418 // if H/W support 4k2k_60p output timing 419 #define HW_SUPPORT_4K2K_60P_OUTPUT TRUE 420 421 #define SUPPORT_MOD_ADBANK_SEPARATE 422 423 //#define SUPPORT_FPLL_REFER_24MXTAL 424 425 #define SUPPORT_FPLL_REFER_24MXTAL_4P /// 24MXTAL_4P>>24MXTAL 426 427 // for 4K 0.5K 240Hz case, if input only 25fps, ivs:ovs = 5:48 case 428 #define SUPPORT_FPLL_DOUBLE_OVS 429 430 #define SUPPORT_HDMI20 1 431 432 #define LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 1 433 434 /// for Chip bringup 435 #define ENABLE_CHIP_BRINGUP 436 #define PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 1 // support pip&pop by multi sc ,such as sc1 support pip&pop 437 438 #define HW_4K2K_VIP_PEAKING_LIMITATION 0 439 #define HW_SCALING_LIMITATION 0 //NO LIMITATION 440 441 #define HW_FRC_PIPE_DELAY_DTV_4K2K_LIMITATION 442 443 // support 3D DS 444 #define SUPPORT_3D_DS 0 445 446 // support OPTEE memory check 447 #define SUPPORT_READLIMIT_1BIT_NS_SW 448 449 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0) 450 //#define ENABLE_TV_SC2_PQ 451 #endif 452 //#define MONACO_SC2_PATCH 453 454 455 //4K_I_MODE_PATCH 456 #define VIDEO_4K_I_PATCH 1 457 #define VIDEO_4K_I_HEIGHT 2000 458 #define VIDEO_4K_I_BIG_HEIGHT 2200 459 460 #define XC_SUPPORT_CMA TRUE 461 462 #define XC_CMA_8MB 0x0800000 463 #define XC_CMA_10MB 0x0A00000 464 #define XC_CMA_12MB 0x0C00000 465 #define XC_CMA_15MB 0x0F00000 466 #define XC_CMA_16MB 0x1000000 467 #define XC_CMA_18MB 0x1200000 468 #define XC_CMA_19MB 0x1300000 469 #define XC_CMA_20MB 0x1400000 470 #define XC_CMA_22MB 0x1600000 471 #define XC_CMA_24MB 0x1800000 472 #define XC_CMA_32MB 0x2000000 473 #define XC_CMA_36MB 0x2400000 474 #define XC_CMA_30MB 0x1E00000 475 #define XC_CMA_40MB 0x2800000 476 #define XC_CMA_48MB 0x3000000 477 #define XC_CMA_64MB 0x4000000 478 #define XC_CMA_72MB 0x4800000 479 #define XC_CMA_96MB 0x6000000 480 481 #define XC_4K2K_WIDTH_MAX 4500 482 #define XC_4K2K_WIDTH_MIN 3000 483 #define XC_4K2K_HIGH_MAX 2500 484 #define XC_4K2K_HIGH_MIN 1900 485 486 #define XC_4K1K_WIDTH_MAX 4500 487 #define XC_4K1K_WIDTH_MIN 3000 488 #define XC_4K1K_HIGH_MAX 1300 489 #define XC_4K1K_HIGH_MIN 900 490 491 #define XC_4K_HALFK_WIDTH_MAX 4500 // 4K 0.5K 492 #define XC_4K_HALFK_WIDTH_MIN 3000 // 4K 0.5K 493 #define XC_4K_HALFK_HIGH_MAX 600 // 4K 0.5K 494 #define XC_4K_HALFK_HIGH_MIN 500 // 4K 0.5K 495 496 #define XC_2K2K_WIDTH_MAX 2300 497 #define XC_2K2K_WIDTH_MIN 1500 498 #define XC_2K2K_HIGH_MAX 2500 499 #define XC_2K2K_HIGH_MIN 1900 500 501 #define XC_FHD_WIDTH_MAX 2300 502 #define XC_FHD_WIDTH_MIN 1500 503 #define XC_FHD_HIGH_MAX 1300 504 #define XC_FHD_HIGH_MIN 900 505 506 #define XC_720_WIDTH_MAX 1500 507 #define XC_720_WIDTH_MIN 800 508 #define XC_720_HIGH_MAX 800 509 #define XC_720_HIGH_MIN 700 510 511 #define XC_576_WIDTH_MAX 800 512 #define XC_576_WIDTH_MIN 500 513 #define XC_576_HIGH_MAX 700 514 #define XC_576_HIGH_MIN 500 515 516 #define XC_480_WIDTH_MAX 800 517 #define XC_480_WIDTH_MIN 500 518 #define XC_480_HIGH_MAX 500 519 #define XC_480_HIGH_MIN 300 520 521 #define XC_FP1080P_H_SIZE 1920 522 #define XC_FP1080P_V_SIZE 2205 523 524 #define FRC_MEMORY_PROTECT 525 526 #define XC_FRC_IPM_L 0x3F48000 // 4096x2160x1.5x10/2 527 #define XC_FRC_IPM_R 0x3F48000 // 4096x2160x1.5x10/2 528 #define XC_FRC_MEDS_L 0x0BDD800 // 2048x1080x1.125x10/2 529 #define XC_FRC_MEDS_R 0x0BDD800 // 2048x1080x1.125x10/2 530 #define XC_FRC_ME1_X1_READ 0x0002800 // ME1_X1 pre-fetch size 531 #define XC_FRC_ME1_X1 0x0061C00 // 8x136x32x11.5 532 #define XC_FRC_ME1_S1 0x0030E00 // 2x136x32x23 533 #define XC_FRC_ME2_X2 0x02DD200 // 30x272x32x11.5 534 #define XC_FRC_ME2_Y2 0x00C3800 // 8x272x32x11.5 535 #define XC_FRC_ME2_F2 0x01B7E00 // 18x272x32x11.5 536 #define XC_FRC_ME2_LOGO 0x00C3800 // 8x272x32x11.5 537 #define XC_FRC_ME2_S2 0x00C3800 // 8x272x32x11.5 538 #define XC_FRC_HR 0x03FC000 // 40x272x32x12 539 #define XC_FRC_HR_BUF23 0x02FD000 // 30x272x32x12 540 541 542 543 //------------------------------------------------------------------------------------------------- 544 // Register base 545 //------------------------------------------------------------------------------------------------- 546 547 // PM 548 #define REG_DDC_BASE 0x000400UL 549 #define REG_PM_SLP_BASE 0x000E00UL 550 #define REG_PM_GPIO_BASE 0x000F00UL 551 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 552 #define REG_PAD_SAR_BASE 0x001400UL 553 #define REG_SCDC0_BASE 0x010200UL 554 #define REG_SCDC1_BASE 0x010300UL 555 #define REG_SCDC2_BASE 0x010400UL 556 #define REG_SCDC3_BASE 0x010500UL 557 #define REG_PM_TOP_BASE 0x001E00UL 558 #define REG_MHL_CBUS_BANK 0x001F00UL 559 #define REG_EFUSE_BASE 0x002000UL 560 #define REG_PM_MHL_CBUS_BANK 0x002F00UL 561 562 // NONPM 563 #define REG_MIU0_BASE 0x101200UL 564 #define REG_MIU0_EX_BASE 0x161500UL 565 #define REG_MIU0_ARBB_BASE 0x152000UL 566 #define REG_MIU1_BASE 0x100600UL 567 #define REG_MIU1_EX_BASE 0x162200UL 568 #define REG_MIU1_ARBB_BASE 0x152100UL 569 #define REG_MIU2_BASE 0x162000UL 570 #define REG_MIU2_EX_BASE 0x162300UL 571 #define REG_MIU2_ARBB_BASE 0x152200UL 572 573 #define REG_CLKGEN2_BASE 0x100A00UL 574 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF 575 #define REG_CHIP_BASE 0x101E00UL 576 #define REG_UHC0_BASE 0x102400UL 577 #define REG_UHC1_BASE 0x100D00UL 578 #define REG_ADC_ATOP_BASE 0x102500UL // 0x2500 - 0x25FF 579 #define REG_ADC_DTOP_BASE 0x102600UL // 0x2600 - 0x26EF 580 #define REG_ADC_CHIPTOP_BASE 0x101E00UL // 0x1E00 - 0x1EFF 581 #define REG_HDMI_BASE 0x102700UL // 0x2700 - 0x27FF 582 #define REG_CHIP_GPIO_BASE 0x102B00UL 583 #define REG_ADC_ATOPB_BASE 0x103D00UL // 0x3D00 - 0x3DFF 584 585 #define REG_HDMI2_BASE 0x101A00UL 586 #define REG_IPMUX_BASE 0x102E00UL 587 #define REG_MVOP_BASE 0x101400UL 588 #define REG_SUBMVOP_BASE 0x101300UL 589 #if ENABLE_REGISTER_SPREAD 590 #define REG_SCALER_BASE 0x130000UL 591 #else 592 #define REG_SCALER_BASE 0x102F00UL 593 #endif 594 #define REG_LPLL_BASE 0x103100UL 595 #define REG_MOD_BASE 0x103200UL 596 #define REG_PWM_BASE 0x13F400UL 597 #define REG_MOD_A_BASE 0x111E00UL 598 #define REG_AFEC_BASE 0x103500UL 599 #define REG_COMB_BASE 0x103600UL 600 601 #define REG_HDCPKEY_BASE 0x173800UL 602 #define REG_DVI_ATOP_BASE 0x110900UL 603 #define REG_DVI_DTOP_BASE 0x110A00UL 604 #define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 605 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 606 #define REG_ADC_DTOPB_BASE 0x111200UL // ADC DTOPB 607 #define REG_DVI_ATOP1_BASE 0x113200UL 608 #define REG_DVI_DTOP1_BASE 0x113300UL 609 #define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 610 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 611 #define REG_DVI_ATOP2_BASE 0x113400UL 612 #define REG_DVI_ATOP3_BASE 0x162F00UL 613 #define REG_DVI_DTOP2_BASE 0x113500UL 614 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 615 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 616 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving 617 #define REG_DVI_PS1_BASE 0x113640UL // DVI power saving1 618 #define REG_DVI_PS2_BASE 0x113680UL // DVI power saving2 619 #define REG_DVI_PS3_BASE 0x1136C0UL // DVI power saving3 620 #define REG_DVI_DTOP3_BASE 0x113700UL 621 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 622 #define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 623 624 #define REG_CHIP_ID_MAJOR 0x1ECC 625 #define REG_CHIP_ID_MINOR 0x1ECD 626 #define REG_CHIP_VERSION 0x1ECE 627 #define REG_CHIP_REVISION 0x1ECFUL 628 #define REG_CHIP_GPIO1_BASE 0x110300UL 629 630 #define REG_COMBO_PHY0_P0_BASE 0x170200UL 631 #define REG_COMBO_PHY1_P0_BASE 0x170300UL 632 #define REG_COMBO_PHY0_P1_BASE 0x170400UL 633 #define REG_COMBO_PHY1_P1_BASE 0x170500UL 634 #define REG_COMBO_PHY0_P2_BASE 0x170600UL 635 #define REG_COMBO_PHY1_P2_BASE 0x170700UL 636 #define REG_COMBO_PHY0_P3_BASE 0x170800UL 637 #define REG_COMBO_PHY1_P3_BASE 0x170900UL 638 639 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL 640 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL 641 #define REG_HDCP_DUAL_P0_BASE 0x171200UL 642 #define REG_DVI_DTOP_DUAL_P1_BASE 0x171300UL 643 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL 644 #define REG_HDCP_DUAL_P1_BASE 0x171500UL 645 #define REG_DVI_DTOP_DUAL_P2_BASE 0x171600UL 646 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL 647 #define REG_HDCP_DUAL_P2_BASE 0x171800UL 648 #define REG_DVI_DTOP_DUAL_P3_BASE 0x171900UL 649 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL 650 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL 651 652 #define REG_HDMI_DUAL_0_BASE 0x173000UL 653 #define REG_HDMI2_DUAL_0_BASE 0x173100UL 654 #define REG_HDMI3_DUAL_0_BASE 0x173400UL 655 #define REG_HDMI_DUAL_1_BASE 0x173200UL 656 #define REG_HDMI2_DUAL_1_BASE 0x173300UL 657 #define REG_HDMI3_DUAL_1_BASE 0x173600UL 658 659 #define REG_COMBO_GP_TOP_BASE 0x173900UL 660 #define REG_SECURE_TZPC_BASE 0x173A00UL 661 662 ////////////////////////// FRC using //////////////////////////////// 663 #define REG_CLKGEN0_BASE 0x100B00UL 664 #define REG_CLKGEN1_BASE 0x103300UL 665 666 ///FRC Area 667 #define REG_FSC_BANK_BASE 0x140000UL // FSC 0x102C bank, direct bank is 0x1400 668 #define REG_FRC_BANK_BASE 0x400000UL 669 670 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 671 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 672 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 673 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 674 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) 675 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x) 676 677 /////////////////////////////////////////////////////////////////// 678 679 // store bank 680 #define LPLL_BK_STORE \ 681 MS_U8 u8Bank; \ 682 u8Bank = MDrv_ReadByte(REG_LPLL_BASE) 683 684 // restore bank 685 #define LPLL_BK_RESTORE MDrv_WriteByte(REG_LPLL_BASE, u8Bank) 686 687 // switch bank 688 #define LPLL_BK_SWITCH(_x_) MDrv_WriteByte(REG_LPLL_BASE, _x_) 689 690 691 //------------------------------------------------------------------------------ 692 // Register configure 693 //------------------------------------------------------------------------------ 694 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out 695 #define CKG_DACA2_GATED BIT(0) 696 #define CKG_DACA2_INVERT BIT(1) 697 #define CKG_DACA2_MASK BMASK(3:2) 698 #define CKG_DACA2_VIF_CLK (0 << 2) 699 #define CKG_DACA2_VD_CLK (1 << 2) 700 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 701 #define CKG_DACA2_XTAL (3 << 2) 702 703 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out 704 #define CKG_DACB2_GATED BIT(0) 705 #define CKG_DACB2_INVERT BIT(1) 706 #define CKG_DACB2_MASK BMASK(3:2) 707 #define CKG_DACB2_VIF_CLK (0 << 2) 708 #define CKG_DACB2_VD_CLK (1 << 2) 709 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 710 #define CKG_DACB2_XTAL (3 << 2) 711 712 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L 713 #define CKG_EDCLK_F1_GATED BIT(0) 714 #define CKG_EDCLK_F1_INVERT BIT(1) 715 #define CKG_EDCLK_F1_MASK BMASK(4:2) 716 #define CKG_EDCLK_F1_ADC (0 << 2) 717 #define CKG_EDCLK_F1_DVI (1 << 2) 718 #define CKG_EDCLK_F1_345MHZ (2 << 2) 719 #define CKG_EDCLK_F1_216MHZ (3 << 2) 720 #define CKG_EDCLK_F1_192MHZ (4 << 2) 721 #define CKG_EDCLK_F1_240MHZ (5 << 2) 722 #define CKG_EDCLK_F1_320MHZ (6 << 2) 723 #define CKG_EDCLK_F1_XTAL (7 << 2) 724 725 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L 726 #define CKG_EDCLK_F2_GATED BIT(0) 727 #define CKG_EDCLK_F2_INVERT BIT(1) 728 #define CKG_EDCLK_F2_MASK BMASK(4:2) 729 #define CKG_EDCLK_F2_ADC (0 << 2) 730 #define CKG_EDCLK_F2_DVI (1 << 2) 731 #define CKG_EDCLK_F2_345MHZ (2 << 2) 732 #define CKG_EDCLK_F2_216MHZ (3 << 2) 733 #define CKG_EDCLK_F2_192MHZ (4 << 2) 734 #define CKG_EDCLK_F2_240MHZ (5 << 2) 735 #define CKG_EDCLK_F2_320MHZ (6 << 2) 736 #define CKG_EDCLK_F2_XTAL (7 << 2) 737 738 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) 739 #define CKG_FMCLK_GATED BIT(0) 740 #define CKG_FMCLK_INVERT BIT(1) 741 #define CKG_FMCLK_MASK BMASK(3:2) 742 #define CKG_FMCLK_FCLK (0 << 2) 743 #define CKG_FMCLK_MIU_256 (1 << 2) 744 #define CKG_FMCLK_MIU_128 (2 << 2) 745 746 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) 747 #define CKG_SC_ROT_GATED BIT(0) 748 #define CKG_SC_ROT_INVERT BIT(1) 749 #define CKG_SC_ROT_MASK BMASK(3:2) 750 #define CKG_SC_ROT_MIU_256 (0 << 2) 751 #define CKG_SC_ROT_MIU_128 (1 << 2) 752 753 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 754 #define CKG_FICLK_F1_GATED BIT(0) 755 #define CKG_FICLK_F1_INVERT BIT(1) 756 #define CKG_FICLK_F1_MASK BMASK(3:2) 757 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 758 #define CKG_FICLK_F1_FLK (1 << 2) 759 //#define CKG_FICLK_F1_XTAL (3 << 2) 760 761 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using, not for FLCIK, and should set 0x00 for VE 762 #define CKG_FICLK_F2_GATED BIT(0) 763 #define CKG_FICLK_F2_INVERT BIT(1) 764 #define CKG_FICLK_F2_MASK BMASK(3:2) 765 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 766 #define CKG_FICLK_F2_FLK (0 << 2) 767 //#define CKG_FICLK_F2_XTAL (3 << 2) 768 769 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 770 #define CKG_FICLK2_F2_GATED BIT(4) 771 #define CKG_FICLK2_F2_INVERT BIT(5) 772 #define CKG_FICLK2_F2_MASK BMASK(7:6) 773 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 774 #define CKG_FICLK2_F2_FCLK (1 << 6) 775 776 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk 777 #define CKG_FCLK_GATED BIT(0) 778 #define CKG_FCLK_INVERT BIT(1) 779 #define CKG_FCLK_MASK BMASK(4:2) 780 #define CKG_FCLK_170MHZ (0 << 2) 781 #define CKG_FCLK_CLK_MIU (1 << 2) 782 #define CKG_FCLK_345MHZ (2 << 2) 783 #define CKG_FCLK_216MHZ (3 << 2) 784 #define CKG_FCLK_192MHZ (4 << 2) 785 #define CKG_FCLK_240MHZ (5 << 2) 786 #define CKG_FCLK_320MHZ (6 << 2) 787 #define CKG_FCLK_XTAL (7 << 2) 788 #define CKG_FCLK_XTAL_ CKG_FCLK_XTAL//(8 << 2) for A5 no XTAL 789 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ 790 791 #define REG_CKG_ODCLK (REG_CLKGEN0_BASE + 0xA6 ) // output dot clock, usually select LPLL, select XTAL when debug 792 #define CKG_ODCLK_GATED BIT(0) 793 #define CKG_ODCLK_INVERT BIT(1) 794 #define CKG_ODCLK_MASK BMASK(5:2) 795 #define CKG_ODCLK_SC_PLL (0 << 2) 796 #define CKG_ODCLK_LPLL_DIV2 (1 << 2) 797 #define CKG_ODCLK_27M (2 << 2) 798 #define CKG_ODCLK_CLK_LPLL (3 << 2) 799 //#define CKG_ODCLK_XTAL (8 << 2) 800 801 #define REG_CKG_IDCLK0 (REG_CLKGEN0_BASE + 0xA8 ) // off-line detect idclk 802 #define CKG_IDCLK0_GATED BIT(0) 803 #define CKG_IDCLK0_INVERT BIT(1) 804 #define CKG_IDCLK0_MASK BMASK(5:2) 805 #define CKG_IDCLK0_CLK_ADC (0 << 2) 806 #define CKG_IDCLK0_CLK_DVI (1 << 2) 807 #define CKG_IDCLK0_CLK_VD (2 << 2) 808 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 809 #define CKG_IDCLK0_ODCLK (4 << 2) 810 #define CKG_IDCLK0_0 (5 << 2) 811 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 812 #define CKG_IDCLK0_00 (7 << 2) // same as 5 --> also is 0 813 #define CKG_IDCLK0_XTAL CKG_IDCLK0_ODCLK//(8 << 2) for A5 no XTAL, select as OD 814 815 #define REG_CKG_IDCLK1 (REG_CLKGEN0_BASE + 0xA9 ) // sub main window idclk 816 #define CKG_IDCLK1_GATED BIT(0) 817 #define CKG_IDCLK1_INVERT BIT(1) 818 #define CKG_IDCLK1_MASK BMASK(5:2) 819 #define CKG_IDCLK1_CLK_ADC (0 << 2) 820 #define CKG_IDCLK1_CLK_DVI (1 << 2) 821 #define CKG_IDCLK1_CLK_VD (2 << 2) 822 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 823 #define CKG_IDCLK1_ODCLK (4 << 2) 824 #define CKG_IDCLK1_0 (5 << 2) 825 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 826 #define CKG_IDCLK1_00 (7 << 2) // same as 5 --> also is 0 827 #define CKG_IDCLK1_XTAL CKG_IDCLK1_ODCLK//(8 << 2) for A5 no XTAL,select as OD 828 829 #define REG_CKG_PRE_IDCLK1 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 830 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 831 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 832 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 833 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 834 835 #define REG_CKG_IDCLK2 (REG_CLKGEN0_BASE + 0xAA ) // main window idclk 836 #define CKG_IDCLK2_GATED BIT(0) 837 #define CKG_IDCLK2_INVERT BIT(1) 838 #define CKG_IDCLK2_MASK BMASK(5:2) 839 #define CKG_IDCLK2_CLK_ADC (0 << 2) 840 #define CKG_IDCLK2_CLK_DVI (1 << 2) 841 #define CKG_IDCLK2_CLK_VD (2 << 2) 842 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 843 #define CKG_IDCLK2_CLK_ADC2 (4 << 2) 844 #define CKG_IDCLK2_0 (5 << 2) 845 #define CKG_IDCLK2_00 (6 << 2) 846 #define CKG_IDCLK2_ODCLK (7 << 2) // same as 5 --> also is 0 847 #define CKG_IDCLK2_CLK_SUB_DC0 (8 << 2) 848 #define CKG_IDCLK2_CLK_ADC3 (9 << 2) 849 #define CKG_IDCLK2_ODCLK2 (10 << 2) 850 #define CKG_IDCLK2_CLKMHL (11 << 2) 851 #define CKG_IDCLK2_XTAL CKG_IDCLK2_ODCLK//(8 << 2)no XTAL select as OD 852 853 #define REG_CKG_PRE_IDCLK2 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 854 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 855 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 856 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 857 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 858 859 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + 0xB2 ) 860 #define CKG_IDCLK3_GATED BIT(0) 861 #define CKG_IDCLK3_INVERT BIT(1) 862 #define CKG_IDCLK3_MASK BMASK(5:2) 863 #define CKG_IDCLK3_CLK_ADC (0 << 2) 864 #define CKG_IDCLK3_CLK_DVI (1 << 2) 865 #define CKG_IDCLK3_CLK_VD (2 << 2) 866 #define CKG_IDCLK3_CLK_DC0 (3 << 2) 867 #define CKG_IDCLK3_ODCLK (4 << 2) 868 #define CKG_IDCLK3_0 (5 << 2) 869 #define CKG_IDCLK3_CLK_VD_ADC (6 << 2) 870 #define CKG_IDCLK3_00 (7 << 2) // same as 5 --> also is 0 871 #define CKG_IDCLK3_XTAL (8 << 2) 872 873 #define REG_CKG_IDCLK_USR_ENA (REG_CLKGEN0_BASE + 0xB4 ) // idclk user enable 874 #define CKG_IDCLK3_USR_ENA BIT(3) 875 876 #define REG_CKG_PRE_IDCLK3 (REG_CLKGEN0_BASE + 0xBC ) 877 #define CKG_PRE_IDCLK3_MASK BMASK(11:9) 878 #define CKG_PRE_IDCLK3_CLK_ADC (0 << 9) 879 #define CKG_PRE_IDCLK3_CLK_DVI (1 << 9) 880 #define CKG_PRE_IDCLK3_CLK_MHL (2 << 9) 881 882 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) 883 #define CKG_PDW0_GATED BIT(0) 884 #define CKG_PDW0_INVERT BIT(1) 885 #define CKG_PDW0_MASK BMASK(4:2) 886 #define CKG_PDW0_CLK_ADC (0 << 2) 887 #define CKG_PDW0_CLK_DVI (1 << 2) 888 #define CKG_PDW0_CLK_VD (2 << 2) 889 #define CKG_PDW0_CLK_DC0 (3 << 2) 890 #define CKG_PDW0_ODCLK (4 << 2) 891 #define CKG_PDW0_0 (5 << 2) 892 #define CKG_PDW0_CLK_VD_ADC (6 << 2) 893 #define CKG_PDW0_00 (7 << 2) // same as 5 --> also is 0 894 #define CKG_PDW0_XTAL (8 << 2) 895 896 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) 897 #define CKG_PDW1_GATED BIT(0) 898 #define CKG_PDW1_INVERT BIT(1) 899 #define CKG_PDW1_MASK BMASK(4:2) 900 #define CKG_PDW1_CLK_ADC (0 << 2) 901 #define CKG_PDW1_CLK_DVI (1 << 2) 902 #define CKG_PDW1_CLK_VD (2 << 2) 903 #define CKG_PDW1_CLK_DC0 (3 << 2) 904 #define CKG_PDW1_ODCLK (4 << 2) 905 #define CKG_PDW1_0 (5 << 2) 906 #define CKG_PDW1_CLK_VD_ADC (6 << 2) 907 #define CKG_PDW1_00 (7 << 2) // same as 5 --> also is 0 908 #define CKG_PDW1_XTAL (8 << 2) 909 910 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) 911 #define CKG_OSDC_GATED BIT(0) 912 #define CKG_OSDC_INVERT BIT(1) 913 #define CKG_OSDC_MASK BMASK(3:2) 914 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 915 916 #define REG_DE_ONLY_F3 (REG_CLKGEN0_BASE + 0xA0 ) 917 #define DE_ONLY_F3_MASK BIT(3) 918 919 #define REG_DE_ONLY_F2 (REG_CLKGEN0_BASE + 0xA0 ) 920 #define DE_ONLY_F2_MASK BIT(2) 921 922 #define REG_DE_ONLY_F1 (REG_CLKGEN0_BASE + 0xA0 ) 923 #define DE_ONLY_F1_MASK BIT(1) 924 925 #define REG_DE_ONLY_F0 (REG_CLKGEN0_BASE + 0xA0 ) 926 #define DE_ONLY_F0_MASK BIT(0) 927 928 929 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 930 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 931 932 #define REG_CLKGEN0_50_L (REG_CLKGEN0_BASE + 0xA0) 933 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) 934 #define REG_CLKGEN0_57_L (REG_CLKGEN0_BASE + 0xAE) 935 936 //MVOP 8bit address 937 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 938 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80) 939 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82) 940 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84) 941 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86) 942 #define REG_SUBMVOP_MIRROR (REG_SUBMVOP_BASE + 0x76) 943 #define REG_SUBMVOP_CROP_H_START (REG_SUBMVOP_BASE + 0x80) 944 #define REG_SUBMVOP_CROP_V_START (REG_SUBMVOP_BASE + 0x82) 945 #define REG_SUBMVOP_CROP_H_SIZE (REG_SUBMVOP_BASE + 0x84) 946 #define REG_SUBMVOP_CROP_V_SIZE (REG_SUBMVOP_BASE + 0x86) 947 948 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 ) 949 #define CKG_S2_MECLK_GATED BIT(0) 950 #define CKG_S2_MECLK_INVERT BIT(1) 951 #define CKG_S2_MECLK_MASK BMASK(5:2) 952 953 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 ) 954 #define CKG_S2_MGCLK_GATED BIT(0) 955 #define CKG_S2_MGCLK_INVERT BIT(1) 956 #define CKG_S2_MGCLK_MASK BMASK(5:2) 957 958 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) 959 #define CKG_S2_GOP_HDR_GATED BIT(0) 960 #define CKG_S2_GOP_HDR_INVERT BIT(1) 961 #define CKG_S2_GOP_HDR_MASK BMASK(5:2) 962 #define CKG_S2_GOP_HDR_ODCLK (0 << 2) 963 #define CKG_S2_GOP_HDR_EDCLK (1 << 2) 964 965 //// for SC2, at REG_CLKGEN2_BASE 966 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 ) 967 #define CKG_S2_FICLK_F1_GATED BIT(0) 968 #define CKG_S2_FICLK_F1_INVERT BIT(1) 969 #define CKG_S2_FICLK_F1_MASK BMASK(3:2) 970 #define CKG_S2_FICLK_F1_IDCLK1 (0 << 2) 971 #define CKG_S2_FICLK_F1_FLK (1 << 2) 972 973 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 ) 974 #define CKG_S2_FICLK_F2_GATED BIT(0) 975 #define CKG_S2_FICLK_F2_INVERT BIT(1) 976 #define CKG_S2_FICLK_F2_MASK BMASK(3:2) 977 #define CKG_S2_FICLK_F2_IDCLK2 (0 << 2) 978 #define CKG_S2_FICLK_F2_FLK (1 << 2) 979 980 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) 981 #define CKG_S2_FICLK2_F2_GATED BIT(0) 982 #define CKG_S2_FICLK2_F2_INVERT BIT(1) 983 #define CKG_S2_FICLK2_F2_MASK BMASK(3:2) 984 #define CKG_S2_FICLK2_F2_IDCLK2 (0 << 2) // v prescaling 985 #define CKG_S2_FICLK2_F2_FCLK (1 << 2) // normal 986 #define CKG_S2_FICLK2_F2_MIUCLK (2 << 2) // DIP case 987 988 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk 989 #define CKG_S2_FCLK_GATED BIT(0) 990 #define CKG_S2_FCLK_INVERT BIT(1) 991 #define CKG_S2_FCLK_MASK BMASK(4:2) 992 #define CKG_S2_FCLK_172MHZ (0 << 2) 993 #define CKG_S2_FCLK_CLK_MIU (1 << 2) 994 #define CKG_S2_FCLK_345MHZ (2 << 2) 995 #define CKG_S2_FCLK_216MHZ (3 << 2) 996 #define CKG_S2_FCLK_192MHZ (4 << 2) 997 #define CKG_S2_FCLK_240MHZ (5 << 2) 998 #define CKG_S2_FCLK_320MHZ (6 << 2) 999 #define CKG_S2_FCLK_XTAL (7 << 2) 1000 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ 1001 1002 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 ) 1003 #define CKG_S2_FODCLK_GATED BIT(0) 1004 #define CKG_S2_FODCLK_INVERT BIT(1) 1005 #define CKG_S2_FODCLK_CLK_ODCLK (0 << 2) 1006 #define CKG_S2_FODCLK_CLK_MIU (1 << 2) 1007 1008 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 ) 1009 #define CKG_S2_ODCLK_GATED BIT(0) 1010 #define CKG_S2_ODCLK_INVERT BIT(1) 1011 #define CKG_S2_ODCLK_MASK BMASK(3:2) 1012 #define CKG_S2_ODCLK_SYN_CLK (0 << 2) 1013 #define CKG_S2_ODCLK_LPLL_DIV2 (1 << 2) 1014 #define CKG_S2_ODCLK_27M (2 << 2) 1015 #define CKG_S2_ODCLK_CLK_LPLL (3 << 2) 1016 1017 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk 1018 #define CKG_S2_IDCLK0_GATED BIT(0) 1019 #define CKG_S2_IDCLK0_INVERT BIT(1) 1020 #define CKG_S2_IDCLK0_MASK BMASK(5:2) 1021 #define CKG_S2_IDCLK0_CLK_ADC (0 << 2) 1022 #define CKG_S2_IDCLK0_CLK_DVI (1 << 2) 1023 #define CKG_S2_IDCLK0_CLK_VD (2 << 2) 1024 #define CKG_S2_IDCLK0_CLK_DC0 (3 << 2) 1025 #define CKG_S2_IDCLK0_CLK_ADC2 (4 << 2) 1026 #define CKG_S2_IDCLK0_0 (5 << 2) 1027 #define CKG_S2_IDCLK0_00 (6 << 2) 1028 #define CKG_S2_IDCLK0_ODCLK (7 << 2) 1029 #define CKG_S2_IDCLK0_CLK_SUB_DC0 (8 << 2) 1030 #define CKG_S2_IDCLK0_CLK_ADC3 (9 << 2) 1031 #define CKG_S2_IDCLK0_ODCLK2 (10<< 2) 1032 #define CKG_S2_IDCLK0_MHL (13<< 2) 1033 #define CKG_S2_IDCLK0_XTAL CKG_S2_IDCLK0_ODCLK 1034 1035 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk 1036 #define CKG_S2_IDCLK1_GATED BIT(0) 1037 #define CKG_S2_IDCLK1_INVERT BIT(1) 1038 #define CKG_S2_IDCLK1_MASK BMASK(5:2) 1039 #define CKG_S2_IDCLK1_CLK_ADC (0 << 2) 1040 #define CKG_S2_IDCLK1_CLK_DVI (1 << 2) 1041 #define CKG_S2_IDCLK1_CLK_VD (2 << 2) 1042 #define CKG_S2_IDCLK1_CLK_DC0 (3 << 2) 1043 #define CKG_S2_IDCLK1_CLK_ADC2 (4 << 2) 1044 #define CKG_S2_IDCLK1_0 (5 << 2) 1045 #define CKG_S2_IDCLK1_00 (6 << 2) 1046 #define CKG_S2_IDCLK1_ODCLK (7 << 2) 1047 #define CKG_S2_IDCLK1_CLK_SUB_DC0 (8 << 2) 1048 #define CKG_S2_IDCLK1_CLK_ADC3 (9 << 2) 1049 #define CKG_S2_IDCLK1_ODCLK2 (10<< 2) 1050 #define CKG_S2_IDCLK1_MHL (13<< 2) 1051 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK 1052 1053 #define REG_CKG_S2_IDCLK2 (REG_CLKGEN2_BASE + 0xCA ) // off-line detect idclk 1054 #define CKG_S2_IDCLK2_GATED BIT(0) 1055 #define CKG_S2_IDCLK2_INVERT BIT(1) 1056 #define CKG_S2_IDCLK2_MASK BMASK(5:2) 1057 #define CKG_S2_IDCLK2_CLK_ADC (0 << 2) 1058 #define CKG_S2_IDCLK2_CLK_DVI (1 << 2) 1059 #define CKG_S2_IDCLK2_CLK_VD (2 << 2) 1060 #define CKG_S2_IDCLK2_CLK_DC0 (3 << 2) 1061 #define CKG_S2_IDCLK2_CLK_ADC2 (4 << 2) 1062 #define CKG_S2_IDCLK2_0 (5 << 2) 1063 #define CKG_S2_IDCLK2_00 (6 << 2) 1064 #define CKG_S2_IDCLK2_ODCLK (7 << 2) 1065 #define CKG_S2_IDCLK2_CLK_SUB_DC0 (8 << 2) 1066 #define CKG_S2_IDCLK2_CLK_ADC3 (9 << 2) 1067 #define CKG_S2_IDCLK2_ODCLK2 (10<< 2) 1068 #define CKG_S2_IDCLK2_MHL (13<< 2) 1069 #define CKG_S2_IDCLK2_XTAL CKG_S2_IDCLK2_ODCLK 1070 1071 #define REG_CKG_S2_IDCLK3 (REG_CLKGEN2_BASE + 0xD2 ) // off-line detect idclk 1072 #define CKG_S2_IDCLK3_ATED BIT(0) 1073 #define CKG_S2_IDCLK3_INVERT BIT(1) 1074 #define CKG_S2_IDCLK3_MASK BMASK(5:2) 1075 #define CKG_S2_IDCLK3_CLK_ADC (0 << 2) 1076 #define CKG_S2_IDCLK3_CLK_DVI (1 << 2) 1077 #define CKG_S2_IDCLK3_CLK_VD (2 << 2) 1078 #define CKG_S2_IDCLK3_CLK_DC0 (3 << 2) 1079 #define CKG_S2_IDCLK3_CLK_ADC2 (4 << 2) 1080 #define CKG_S2_IDCLK3_0 (5 << 2) 1081 #define CKG_S2_IDCLK3_00 (6 << 2) 1082 #define CKG_S2_IDCLK3_ODCLK (7 << 2) 1083 #define CKG_S2_IDCLK3_CLK_SUB_DC0 (8 << 2) 1084 #define CKG_S2_IDCLK3_CLK_ADC3 (9 << 2) 1085 #define CKG_S2_IDCLK3_ODCLK2 (10<< 2) 1086 #define CKG_S2_IDCLK3_MHL (13<< 2) 1087 #define CKG_S2_IDCLK3_XTAL CKG_S2_IDCLK3_ODCLK 1088 1089 1090 #define REG_S2_DE_ONLY_F3 (REG_CLKGEN2_BASE + 0xC0 ) 1091 #define S2_DE_ONLY_F3_MASK BIT(3) 1092 1093 #define REG_S2_DE_ONLY_F2 (REG_CLKGEN2_BASE + 0xC0 ) 1094 #define S2_DE_ONLY_F2_MASK BIT(2) 1095 1096 #define REG_S2_DE_ONLY_F1 (REG_CLKGEN2_BASE + 0xC0 ) 1097 #define S2_DE_ONLY_F1_MASK BIT(1) 1098 1099 #define REG_S2_DE_ONLY_F0 (REG_CLKGEN2_BASE + 0xC0 ) 1100 #define S2_DE_ONLY_F0_MASK BIT(0) 1101 1102 //// 1103 #define CLK_SRC_IDCLK2 0 1104 #define CLK_SRC_FCLK 1 1105 #define CLK_SRC_XTAL 3 1106 1107 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 1108 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 1109 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 1110 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 1111 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06) 1112 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26) 1113 #define MIU0_G6_REQUEST_MASK (REG_MIU0_ARBB_BASE + 0x06) 1114 1115 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 1116 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 1117 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 1118 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 1119 #define MIU1_G4_REQUEST_MASK (REG_MIU1_EX_BASE + 0x06) 1120 #define MIU1_G5_REQUEST_MASK (REG_MIU1_EX_BASE + 0x26) 1121 #define MIU1_G6_REQUEST_MASK (REG_MIU1_ARBB_BASE + 0x06) 1122 1123 #define MIU2_G0_REQUEST_MASK (REG_MIU2_BASE + 0x46) 1124 #define MIU2_G1_REQUEST_MASK (REG_MIU2_BASE + 0x66) 1125 #define MIU2_G2_REQUEST_MASK (REG_MIU2_BASE + 0x86) 1126 #define MIU2_G3_REQUEST_MASK (REG_MIU2_BASE + 0xA6) 1127 #define MIU2_G4_REQUEST_MASK (REG_MIU2_EX_BASE + 0x06) 1128 #define MIU2_G5_REQUEST_MASK (REG_MIU2_EX_BASE + 0x26) 1129 #define MIU2_G6_REQUEST_MASK (REG_MIU2_ARBB_BASE + 0x06) 1130 1131 #define MIU_SC_G0REQUEST_MASK (0x0000) 1132 #define MIU_SC_G1REQUEST_MASK (0x0000) 1133 #define MIU_SC_G2REQUEST_MASK (0x0000) 1134 #define MIU_SC_G3REQUEST_MASK (0x0000) 1135 #define MIU_SC_G4REQUEST_MASK (0x0000) 1136 #define MIU_SC_G5REQUEST_MASK (0x0000) 1137 #define MIU_SC_G6REQUEST_MASK (0xF603) 1138 1139 ////////////////////////// FRC using //////////////////////////////// 1140 1141 #define MIU_FRC_G0REQUEST_MASK (0x0000) 1142 #define MIU_FRC_G1REQUEST_MASK (0x0000) 1143 #define MIU_FRC_G2REQUEST_MASK (0x0000) 1144 #define MIU_FRC_G3REQUEST_MASK (0x0000) 1145 #define MIU_FRC_G4REQUEST_MASK (0x0000) 1146 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) 1147 #define MIU_FRC_G6REQUEST_MASK (0x0000) 1148 1149 1150 1151 /////////////////////////////////////////////////////////////////// 1152 1153 #define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 1154 #define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 1155 #define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 1156 #define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 1157 1158 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 1159 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 1160 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 1161 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 1162 1163 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 1164 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 1165 1166 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 1167 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 1168 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 1169 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 1170 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 1171 1172 1173 #define HW_DESIGN_LD_VER (2) 1174 1175 #define FPLL_THRESH_MODE_SUPPORT 0 1176 1177 #define ADC_EFUSE_IN_MBOOT 1178 1179 #define ADC_CENTER_GAIN 0x1000 1180 #define ADC_CENTER_OFFSET 0x0800 1181 #define ADC_GAIN_BIT_CNT 14 1182 #define ADC_OFFSET_BIT_CNT 13 1183 1184 #define ADC_VGA_DEFAULT_GAIN_R 0x1000 1185 #define ADC_VGA_DEFAULT_GAIN_G 0x1000 1186 #define ADC_VGA_DEFAULT_GAIN_B 0x1000 1187 #define ADC_VGA_DEFAULT_OFFSET_R 0x0000 1188 #define ADC_VGA_DEFAULT_OFFSET_G 0x0000 1189 #define ADC_VGA_DEFAULT_OFFSET_B 0x0000 1190 #define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 1191 #define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 1192 #define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 1193 #define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 1194 #define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 1195 #define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 1196 #define ADC_SCART_DEFAULT_GAIN_R 0x1000 1197 #define ADC_SCART_DEFAULT_GAIN_G 0x1000 1198 #define ADC_SCART_DEFAULT_GAIN_B 0x1000 1199 #define ADC_SCART_DEFAULT_OFFSET_R 0x0100 1200 #define ADC_SCART_DEFAULT_OFFSET_G 0x0100 1201 #define ADC_SCART_DEFAULT_OFFSET_B 0x0100 1202 1203 /////////////////////////////////////////////// 1204 // Enable Hardware auto gain/offset 1205 #define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 1206 #define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 1207 #define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 1208 #define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 1209 #define ADC_VGA_FIXED_GAIN_R 0x1796 1210 #define ADC_VGA_FIXED_GAIN_G 0x1796 1211 #define ADC_VGA_FIXED_GAIN_B 0x1796 1212 #define ADC_VGA_FIXED_OFFSET_R 0x0000 1213 #define ADC_VGA_FIXED_OFFSET_G 0x0000 1214 #define ADC_VGA_FIXED_OFFSET_B 0x0000 1215 #define ADC_YPBPR_FIXED_GAIN_R 0x14B7 1216 #define ADC_YPBPR_FIXED_GAIN_G 0x1441 1217 #define ADC_YPBPR_FIXED_GAIN_B 0x14B7 1218 #define ADC_YPBPR_FIXED_OFFSET_R 0x0800 1219 #define ADC_YPBPR_FIXED_OFFSET_G 0x0100 1220 #define ADC_YPBPR_FIXED_OFFSET_B 0x0800 1221 #define ADC_SCART_FIXED_GAIN_R 0x1796 1222 #define ADC_SCART_FIXED_GAIN_G 0x1796 1223 #define ADC_SCART_FIXED_GAIN_B 0x1796 1224 #define ADC_SCART_FIXED_OFFSET_R 0x0000 1225 #define ADC_SCART_FIXED_OFFSET_G 0x0000 1226 #define ADC_SCART_FIXED_OFFSET_B 0x0000 1227 1228 // patch for china player 1229 // there are some undefined signal between sync and DE in YPbPr fullHD 1230 // so we ignore this signal with coast window 1231 //#define ADC_BYPASS_YPBPR_MACRO_VISION_PATCH 1232 1233 #define SUPPORT_SC0_SUB_WIN FALSE 1234 #define SUPPORT_DUAL_MIU_MIRROR_SWAP_IPM TRUE 1235 1236 1237 // GOP need this define, MI system would call MDrv_SC_SetOSDBlendingFormula before XC init 1238 // determinated dual op by panel type would be failed. 1239 #define GOP_SUPPORT_DUALRATE 1240 1241 1242 // IP Authorization number for dolby 1243 #define IPAUTH_DOLBY_HDR_PIN 118 1244 1245 //#define PATCH_ENABLE_MVOP_HANDSHAKE_MODE_WHEN_BW_NOT_ENOUGH_IN_120HZ_PANEL TRUE 1246 //#define XC_DUAL_MIU_SUPPORT_SUB_WINDOW 1247 //#define XC_DUAL_MIU_SUPPORT_DS 1248 #endif /* MHAL_XC_CONFIG_H */ 1249 1250