1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H264E_VEPU2_REG_TBL_H__ 18 #define __HAL_H264E_VEPU2_REG_TBL_H__ 19 20 #include "rk_type.h" 21 22 #define BIT(n) (1<<(n)) 23 24 /* RK3228 Encoder registers. */ 25 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24)) 26 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) 27 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) 28 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24)) 29 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) 30 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) 31 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24)) 32 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) 33 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) 34 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24)) 35 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) 36 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) 37 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) 38 #define VEPU_REG_VP8_QUT_5TH(i) (0x010 + ((i) * 0x24)) 39 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) 40 #define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) 41 #define VEPU_REG_VP8_QUT_ZB_AC_Y1(x) (((x) & 0x1ff) << 0) 42 #define VEPU_REG_VP8_QUT_6TH(i) (0x014 + ((i) * 0x24)) 43 #define VEPU_REG_VP8_QUT_RND_DC_CHR(x) (((x) & 0xff) << 16) 44 #define VEPU_REG_VP8_QUT_RND_DC_Y2(x) (((x) & 0xff) << 8) 45 #define VEPU_REG_VP8_QUT_RND_DC_Y1(x) (((x) & 0xff) << 0) 46 #define VEPU_REG_VP8_QUT_7TH(i) (0x018 + ((i) * 0x24)) 47 #define VEPU_REG_VP8_QUT_RND_AC_CHR(x) (((x) & 0xff) << 16) 48 #define VEPU_REG_VP8_QUT_RND_AC_Y2(x) (((x) & 0xff) << 8) 49 #define VEPU_REG_VP8_QUT_RND_AC_Y1(x) (((x) & 0xff) << 0) 50 #define VEPU_REG_VP8_QUT_8TH(i) (0x01c + ((i) * 0x24)) 51 #define VEPU_REG_VP8_SEG_FILTER_LEVEL(x) (((x) & 0x3f) << 25) 52 #define VEPU_REG_VP8_DEQUT_DC_CHR(x) (((x) & 0xff) << 17) 53 #define VEPU_REG_VP8_DEQUT_DC_Y2(x) (((x) & 0x1ff) << 8) 54 #define VEPU_REG_VP8_DEQUT_DC_Y1(x) (((x) & 0xff) << 0) 55 #define VEPU_REG_VP8_QUT_9TH(i) (0x020 + ((i) * 0x24)) 56 #define VEPU_REG_VP8_DEQUT_AC_CHR(x) (((x) & 0x1ff) << 18) 57 #define VEPU_REG_VP8_DEQUT_AC_Y2(x) (((x) & 0x1ff) << 9) 58 #define VEPU_REG_VP8_DEQUT_AC_Y1(x) (((x) & 0x1ff) << 0) 59 #define VEPU_REG_ADDR_VP8_SEG_MAP 0x06c 60 #define VEPU_REG_VP8_INTRA_4X4_PENALTY(i) (0x070 + ((i) * 0x4)) 61 #define VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x) (((x) & 0xfff) << 0) 62 #define VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x) (((x) & 0xfff) << 16) 63 #define VEPU_REG_VP8_INTRA_16X16_PENALTY(i) (0x084 + ((i) * 0x4)) 64 #define VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x) (((x) & 0xfff) << 0) 65 #define VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x) (((x) & 0xfff) << 16) 66 #define VEPU_REG_VP8_CONTROL 0x0a0 67 #define VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x) (((x) & 0x1f) << 24) 68 #define VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x) (((x) & 0x7f) << 16) 69 #define VEPU_REG_VP8_INTER_TYPE_BIT_COST(x) (((x) & 0xfff) << 0) 70 #define VEPU_REG_VP8_REF_FRAME_VAL 0x0a4 71 #define VEPU_REG_VP8_COEF_DMV_PENALTY(x) (((x) & 0xfff) << 16) 72 #define VEPU_REG_VP8_REF_FRAME(x) (((x) & 0xfff) << 0) 73 #define VEPU_REG_VP8_LOOP_FILTER_REF_DELTA 0x0a8 74 #define VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x) (((x) & 0x7f) << 16) 75 #define VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x) (((x) & 0x7f) << 8) 76 #define VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x) (((x) & 0x7f) << 0) 77 #define VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA 0x0ac 78 #define VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x) (((x) & 0x7f) << 16) 79 #define VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x) (((x) & 0x7f) << 8) 80 #define VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x) (((x) & 0x7f) << 0) 81 #define VEPU_REG_INTRA_SLICE_BITMAP(i) (0x0b0 + ((i) * 0x4)) 82 #define VEPU_REG_ADDR_VP8_DCT_PART(i) (0x0b0 + ((i) * 0x4)) 83 #define VEPU_REG_INTRA_AREA_CTRL 0x0b8 84 #define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 24) 85 #define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 16) 86 #define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 8) 87 #define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 0) 88 #define VEPU_REG_CIR_INTRA_CTRL 0x0bc 89 #define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16) 90 #define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0) 91 #define VEPU_REG_ADDR_IN_LUMA 0x0c0 92 #define VEPU_REG_ADDR_IN_CB 0x0c4 93 #define VEPU_REG_ADDR_IN_CR 0x0c8 94 #define VEPU_REG_STR_HDR_REM_MSB 0x0cc 95 #define VEPU_REG_STR_HDR_REM_LSB 0x0d0 96 #define VEPU_REG_STR_BUF_LIMIT 0x0d4 97 #define VEPU_REG_AXI_CTRL 0x0d8 98 #define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 24) 99 #define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 16) 100 #define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8) 101 #define VEPU_REG_AXI_CTRL_INCREMENT_MODE(x) (((x) & 0x01) << 2) 102 #define VEPU_REG_AXI_CTRL_BIRST_DISCARD(x) (((x) & 0x01) << 1) 103 #define VEPU_REG_AXI_CTRL_BIRST_DISABLE BIT(0) 104 #define VEPU_QP_ADJUST_MAD_DELTA_ROI 0x0dc 105 #define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 12) 106 #define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 8) 107 #define VEPU_REG_MAD_QP_ADJUSTMENT (((x) & 0xf) << 0) 108 #define VEPU_REG_ADDR_REF_LUMA 0x0e0 109 #define VEPU_REG_ADDR_REF_CHROMA 0x0e4 110 #define VEPU_REG_QP_SUM_DIV2 0x0e8 111 #define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2) 112 #define VEPU_REG_ENC_CTRL0 0x0ec 113 #define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(28) 114 #define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 24) 115 #define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 21) 116 #define VEPU_REG_ENTROPY_CODING_MODE BIT(20) 117 #define VEPU_REG_H264_TRANS8X8_MODE BIT(17) 118 #define VEPU_REG_H264_INTER4X4_MODE BIT(16) 119 #define VEPU_REG_H264_STREAM_MODE BIT(15) 120 #define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 8) 121 #define VEPU_REG_ENC_OVER_FILL_STRM_OFFSET 0x0f0 122 #define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 16) 123 #define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 8) 124 #define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 4) 125 #define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 0) 126 #define VEPU_REG_INPUT_LUMA_INFO 0x0f4 127 #define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 20) 128 #define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 16) 129 #define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 0) 130 #define VEPU_REG_RLC_SUM 0x0f8 131 #define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4) 132 #define VEPU_REG_SPLIT_PENALTY_4X4 0x0f8 133 #define VEPU_REG_VP8_SPLIT_PENALTY_4X4 (((x) & 0x1ff) << 19) 134 #define VEPU_REG_ADDR_REC_LUMA 0x0fc 135 #define VEPU_REG_ADDR_REC_CHROMA 0x100 136 #define VEPU_REG_CHECKPOINT(i) (0x104 + ((i) * 0x4)) 137 #define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) 138 #define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) 139 #define VEPU_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \ 140 * (i & 1))) & 0xffff) \ 141 * 32) 142 #define VEPU_REG_VP8_SEG0_QUANT_AC_Y1 0x104 143 #define VEPU_REG_VP8_SEG0_RND_AC_Y1(x) (((x) & 0xff) << 23) 144 #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y1(x) (((x) & 0x1ff) << 14) 145 #define VEPU_REG_VP8_SEG0_QUT_AC_Y1(x) (((x) & 0x3fff) << 0) 146 #define VEPU_REG_VP8_SEG0_QUANT_DC_Y2 0x108 147 #define VEPU_REG_VP8_SEG0_RND_DC_Y2(x) (((x) & 0xff) << 23) 148 #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y2(x) (((x) & 0x1ff) << 14) 149 #define VEPU_REG_VP8_SEG0_QUT_DC_Y2(x) (((x) & 0x3fff) << 0) 150 #define VEPU_REG_VP8_SEG0_QUANT_AC_Y2 0x10c 151 #define VEPU_REG_VP8_SEG0_RND_AC_Y2(x) (((x) & 0xff) << 23) 152 #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y2(x) (((x) & 0x1ff) << 14) 153 #define VEPU_REG_VP8_SEG0_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) 154 #define VEPU_REG_VP8_SEG0_QUANT_DC_CHR 0x110 155 #define VEPU_REG_VP8_SEG0_RND_DC_CHR(x) (((x) & 0xff) << 23) 156 #define VEPU_REG_VP8_SEG0_ZBIN_DC_CHR(x) (((x) & 0x1ff) << 14) 157 #define VEPU_REG_VP8_SEG0_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) 158 #define VEPU_REG_VP8_SEG0_QUANT_AC_CHR 0x114 159 #define VEPU_REG_VP8_SEG0_RND_AC_CHR(x) (((x) & 0xff) << 23) 160 #define VEPU_REG_VP8_SEG0_ZBIN_AC_CHR(x) (((x) & 0x1ff) << 14) 161 #define VEPU_REG_VP8_SEG0_QUT_AC_CHR(x) (((x) & 0x3fff) << 0) 162 #define VEPU_REG_VP8_SEG0_QUANT_DQUT 0x118 163 #define VEPU_REG_VP8_MV_REF_IDX1(x) (((x) & 0x03) << 26) 164 #define VEPU_REG_VP8_SEG0_DQUT_DC_Y2(x) (((x) & 0x1ff) << 17) 165 #define VEPU_REG_VP8_SEG0_DQUT_AC_Y1(x) (((x) & 0x1ff) << 8) 166 #define VEPU_REG_VP8_SEG0_DQUT_DC_Y1(x) (((x) & 0xff) << 0) 167 #define VEPU_REG_CHKPT_WORD_ERR(i) (0x118 + ((i) * 0x4)) 168 #define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) 169 #define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) 170 #define VEPU_REG_VP8_SEG0_QUANT_DQUT_1 0x11c 171 #define VEPU_REG_VP8_SEGMENT_MAP_UPDATE BIT(30) 172 #define VEPU_REG_VP8_SEGMENT_EN BIT(29) 173 #define VEPU_REG_VP8_MV_REF_IDX2_EN BIT(28) 174 #define VEPU_REG_VP8_MV_REF_IDX2(x) (((x) & 0x03) << 26) 175 #define VEPU_REG_VP8_SEG0_DQUT_AC_CHR(x) (((x) & 0x1ff) << 17) 176 #define VEPU_REG_VP8_SEG0_DQUT_DC_CHR(x) (((x) & 0xff) << 9) 177 #define VEPU_REG_VP8_SEG0_DQUT_AC_Y2(x) (((x) & 0x1ff) << 0) 178 #define VEPU_REG_VP8_BOOL_ENC_VALUE 0x120 179 #define VEPU_REG_CHKPT_DELTA_QP 0x124 180 #define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) 181 #define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) 182 #define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) 183 #define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) 184 #define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) 185 #define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) 186 #define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) 187 #define VEPU_REG_VP8_ENC_CTRL2 0x124 188 #define VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2(x) (((x) & 0xff) << 24) 189 #define VEPU_REG_VP8_FILTER_SHARPNESS(x) (((x) & 0x07) << 21) 190 #define VEPU_REG_VP8_FILTER_LEVEL(x) (((x) & 0x3f) << 15) 191 #define VEPU_REG_VP8_DCT_PARTITION_CNT(x) (((x) & 0x03) << 13) 192 #define VEPU_REG_VP8_BOOL_ENC_VALUE_BITS(x) (((x) & 0x1f) << 8) 193 #define VEPU_REG_VP8_BOOL_ENC_RANGE(x) (((x) & 0xff) << 0) 194 #define VEPU_REG_ENC_CTRL1 0x128 195 #define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 24) 196 #define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16) 197 #define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 4) 198 #define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 2) 199 #define VEPU_REG_SIZE_TABLE_PRESENT BIT(0) 200 #define VEPU_REG_INTRA_INTER_MODE 0x12c 201 #define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 16) 202 #define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0) 203 #define VEPU_REG_ENC_CTRL2 0x130 204 #define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26) 205 #define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22) 206 #define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18) 207 #define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13) 208 #define VEPU_REG_FILTER_DISABLE BIT(5) 209 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) 210 #define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0) 211 #define VEPU_REG_ADDR_OUTPUT_STREAM 0x134 212 #define VEPU_REG_ADDR_OUTPUT_CTRL 0x138 213 #define VEPU_REG_ADDR_NEXT_PIC 0x13c 214 #define VEPU_REG_ADDR_MV_OUT 0x140 215 #define VEPU_REG_ADDR_CABAC_TBL 0x144 216 #define VEPU_REG_ROI1 0x148 217 #define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 24) 218 #define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 16) 219 #define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 8) 220 #define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 0) 221 #define VEPU_REG_ROI2 0x14c 222 #define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 24) 223 #define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 16) 224 #define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 8) 225 #define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 0) 226 #define VEPU_REG_STABLE_MATRIX(i) (0x150 + ((i) * 0x4)) 227 #define VEPU_REG_STABLE_MOTION_SUM 0x174 228 #define VEPU_REG_STABLILIZATION_OUTPUT 0x178 229 #define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 8) 230 #define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 6) 231 #define VEPU_REG_STABLE_HOR_GMV(x) (((x) & 0x3f) << 0) 232 #define VEPU_REG_RGB2YUV_CONVERSION_COEF1 0x17c 233 #define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16) 234 #define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0) 235 #define VEPU_REG_RGB2YUV_CONVERSION_COEF2 0x180 236 #define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16) 237 #define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0) 238 #define VEPU_REG_RGB2YUV_CONVERSION_COEF3 0x184 239 #define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0) 240 #define VEPU_REG_RGB_MASK_MSB 0x188 241 #define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 16) 242 #define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 8) 243 #define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 0) 244 #define VEPU_REG_MV_PENALTY 0x18c 245 #define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 21) 246 #define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 11) 247 #define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 1) 248 #define VEPU_REG_SPLIT_MV_MODE_EN BIT(0) 249 #define VEPU_REG_QP_VAL 0x190 250 #define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26) 251 #define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20) 252 #define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14) 253 #define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0) 254 #define VEPU_REG_VP8_SEG0_QUANT_DC_Y1 0x190 255 #define VEPU_REG_VP8_SEG0_RND_DC_Y1(x) (((x) & 0xff) << 23) 256 #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y1(x) (((x) & 0x1ff) << 14) 257 #define VEPU_REG_VP8_SEG0_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) 258 #define VEPU_REG_MVC_RELATE 0x198 259 #define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 20) 260 #define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 11) 261 #define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 8) 262 #define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(7) 263 #define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 4) 264 #define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 1) 265 #define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(0) 266 #define VEPU_REG_ENCODE_START 0x19c 267 #define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 20) 268 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) 269 #define VEPU_REG_PIC_TYPE(x) (((x) & 0x3) << 6) 270 #define VEPU_REG_ENCODE_FORMAT(x) (((x) & 0x3) << 4) 271 #define VEPU_REG_ENCODE_ENABLE BIT(0) 272 #define VEPU_REG_MB_CTRL 0x1a0 273 #define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 16) 274 #define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 0) 275 #define VEPU_REG_DATA_ENDIAN 0x1a4 276 #define VEPU_REG_INPUT_SWAP8 BIT(31) 277 #define VEPU_REG_INPUT_SWAP8_(x) (((x) & 1) << 31) 278 #define VEPU_REG_INPUT_SWAP16 BIT(30) 279 #define VEPU_REG_INPUT_SWAP16_(x) (((x) & 1) << 30) 280 #define VEPU_REG_INPUT_SWAP32 BIT(29) 281 #define VEPU_REG_INPUT_SWAP32_(x) (((x) & 1) << 29) 282 #define VEPU_REG_OUTPUT_SWAP8 BIT(28) 283 #define VEPU_REG_OUTPUT_SWAP16 BIT(27) 284 #define VEPU_REG_OUTPUT_SWAP32 BIT(26) 285 #define VEPU_REG_TEST_IRQ BIT(24) 286 #define VEPU_REG_TEST_COUNTER(x) (((x) & 0xf) << 20) 287 #define VEPU_REG_TEST_REG BIT(19) 288 #define VEPU_REG_TEST_MEMORY BIT(18) 289 #define VEPU_REG_TEST_LEN(x) (((x) & 0x3ffff) << 0) 290 #define VEPU_REG_ENC_CTRL3 0x1a8 291 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) 292 #define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16) 293 #define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0) 294 #define VEPU_REG_ENC_CTRL4 0x1ac 295 #define VEPU_REG_MV_PENALTY_16X8_8X16(x) (((x) & 0x3ff) << 20) 296 #define VEPU_REG_MV_PENALTY_8X8(x) (((x) & 0x3ff) << 10) 297 #define VEPU_REG_MV_PENALTY_8X4_4X8(x) (((x) & 0x3ff) << 0) 298 #define VEPU_REG_ADDR_VP8_PROB_CNT 0x1b0 299 #define VEPU_REG_INTERRUPT 0x1b4 300 #define VEPU_REG_INTERRUPT_NON BIT(28) 301 #define VEPU_REG_MV_WRITE_EN BIT(24) 302 #define VEPU_REG_RECON_WRITE_DIS BIT(20) 303 #define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(16) 304 #define VEPU_REG_CLK_GATING_EN BIT(12) 305 #define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(10) 306 #define VEPU_REG_INTERRUPT_RESET BIT(9) 307 #define VEPU_REG_INTERRUPT_DIS_BIT BIT(8) 308 #define VEPU_REG_INTERRUPT_TIMEOUT BIT(6) 309 #define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5) 310 #define VEPU_REG_INTERRUPT_BUS_ERROR BIT(4) 311 #define VEPU_REG_INTERRUPT_FUSE BIT(3) 312 #define VEPU_REG_INTERRUPT_SLICE_READY BIT(2) 313 #define VEPU_REG_INTERRUPT_FRAME_READY BIT(1) 314 #define VEPU_REG_INTERRUPT_BIT BIT(0) 315 #define VEPU_REG_DMV_PENALTY_TBL(i) (0x1E0 + ((i) * 0x4)) 316 #define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) (x << i * 8) 317 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i) (0x260 + ((i) * 0x4)) 318 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) (x << i * 8) 319 320 /* vpu decoder register */ 321 #define VDPU_REG_DEC_CTRL0 0x0c8 322 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 25) 323 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 13) 324 #define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(12) 325 #define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(11) 326 #define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(10) 327 #define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(9) 328 #define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(8) 329 #define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(7) 330 #define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 1) 331 #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) 332 #define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(0) 333 #define VDPU_REG_STREAM_LEN 0x0cc 334 #define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) 335 #define VDPU_REG_DEC_STREAM_LEN_HI BIT(24) 336 #define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) 337 #define VDPU_REG_ERROR_CONCEALMENT 0x0d0 338 #define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 17) 339 #define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 8) 340 #define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 0) 341 #define VDPU_REG_DEC_FORMAT 0x0d4 342 #define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 0) 343 #define VDPU_REG_DATA_ENDIAN 0x0d8 344 #define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(5) 345 #define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(4) 346 #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(3) 347 #define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(2) 348 #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(1) 349 #define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(0) 350 #define VDPU_REG_INTERRUPT 0x0dc 351 #define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(13) 352 #define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(12) 353 #define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(10) 354 #define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(9) 355 #define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(8) 356 #define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(6) 357 #define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(5) 358 #define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(4) 359 #define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(1) 360 #define VDPU_REG_INTERRUPT_DEC_IRQ BIT(0) 361 #define VDPU_REG_AXI_CTRL 0x0e0 362 #define VDPU_REG_AXI_DEC_SEL BIT(23) 363 #define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(22) 364 #define VDPU_REG_PARAL_BUS_E(x) BIT(21) 365 #define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 16) 366 #define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 8) 367 #define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 0) 368 #define VDPU_REG_EN_FLAGS 0x0e4 369 #define VDPU_REG_AHB_HLOCK_E BIT(31) 370 #define VDPU_REG_CACHE_E BIT(29) 371 #define VDPU_REG_PREFETCH_SINGLE_CHANNEL_E BIT(28) 372 #define VDPU_REG_INTRA_3_CYCLE_ENHANCE BIT(27) 373 #define VDPU_REG_INTRA_DOUBLE_SPEED BIT(26) 374 #define VDPU_REG_INTER_DOUBLE_SPEED BIT(25) 375 #define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(22) 376 #define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(21) 377 #define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(20) 378 #define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(19) 379 #define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(18) 380 #define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(17) 381 #define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(16) 382 #define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(15) 383 #define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(14) 384 #define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(13) 385 #define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(12) 386 #define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(11) 387 #define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(10) 388 #define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(9) 389 #define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(8) 390 #define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(7) 391 #define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(6) 392 #define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(5) 393 #define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(4) 394 #define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(2) 395 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(1) 396 #define VDPU_REG_INTERRUPT_DEC_E BIT(0) 397 #define VDPU_REG_SOFT_RESET 0x0e8 398 #define VDPU_REG_PRED_FLT 0x0ec 399 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) 400 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) 401 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) 402 #define VDPU_REG_ADDITIONAL_CHROMA_ADDRESS 0x0f0 403 #define VDPU_REG_ADDR_QTABLE 0x0f4 404 #define VDPU_REG_DIRECT_MV_ADDR 0x0f8 405 #define VDPU_REG_ADDR_DST 0x0fc 406 #define VDPU_REG_ADDR_STR 0x100 407 #define VDPU_REG_REFBUF_RELATED 0x104 408 #define VDPU_REG_FWD_PIC(i) (0x128 + ((i) * 0x4)) 409 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) 410 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) 411 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 412 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 413 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 414 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 415 #define VDPU_REG_REF_PIC(i) (0x130 + ((i) * 0x4)) 416 #define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16) 417 #define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0) 418 #define VDPU_REG_H264_ADDR_REF(i) (0x150 + ((i) * 0x4)) 419 #define VDPU_REG_ADDR_REF_FIELD_E BIT(1) 420 #define VDPU_REG_ADDR_REF_TOPC_E BIT(0) 421 #define VDPU_REG_INITIAL_REF_PIC_LIST0 0x190 422 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5(x) (((x) & 0x1f) << 25) 423 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4(x) (((x) & 0x1f) << 20) 424 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 425 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 426 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 427 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 428 #define VDPU_REG_INITIAL_REF_PIC_LIST1 0x194 429 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11(x) (((x) & 0x1f) << 25) 430 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10(x) (((x) & 0x1f) << 20) 431 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9(x) (((x) & 0x1f) << 15) 432 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8(x) (((x) & 0x1f) << 10) 433 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7(x) (((x) & 0x1f) << 5) 434 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6(x) (((x) & 0x1f) << 0) 435 #define VDPU_REG_INITIAL_REF_PIC_LIST2 0x198 436 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 15) 437 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14(x) (((x) & 0x1f) << 10) 438 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13(x) (((x) & 0x1f) << 5) 439 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12(x) (((x) & 0x1f) << 0) 440 #define VDPU_REG_INITIAL_REF_PIC_LIST3 0x19c 441 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5(x) (((x) & 0x1f) << 25) 442 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4(x) (((x) & 0x1f) << 20) 443 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3(x) (((x) & 0x1f) << 15) 444 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 10) 445 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 5) 446 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 0) 447 #define VDPU_REG_INITIAL_REF_PIC_LIST4 0x1a0 448 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11(x) (((x) & 0x1f) << 25) 449 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10(x) (((x) & 0x1f) << 20) 450 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9(x) (((x) & 0x1f) << 15) 451 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8(x) (((x) & 0x1f) << 10) 452 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7(x) (((x) & 0x1f) << 5) 453 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6(x) (((x) & 0x1f) << 0) 454 #define VDPU_REG_INITIAL_REF_PIC_LIST5 0x1a4 455 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 15) 456 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14(x) (((x) & 0x1f) << 10) 457 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13(x) (((x) & 0x1f) << 5) 458 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12(x) (((x) & 0x1f) << 0) 459 #define VDPU_REG_INITIAL_REF_PIC_LIST6 0x1a8 460 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) 461 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) 462 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) 463 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) 464 #define VDPU_REG_LT_REF 0x1ac 465 #define VDPU_REG_VALID_REF 0x1b0 466 #define VDPU_REG_H264_PIC_MB_SIZE 0x1b8 467 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 22) 468 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 17) 469 #define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 9) 470 #define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 0) 471 #define VDPU_REG_H264_CTRL 0x1bc 472 #define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 16) 473 #define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) 474 #define VDPU_REG_CURRENT_FRAME 0x1c0 475 #define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(31) 476 #define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(30) 477 #define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16) 478 #define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0) 479 #define VDPU_REG_REF_FRAME 0x1c4 480 #define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 16) 481 #define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0) 482 #define VDPU_REG_DEC_CTRL6 0x1c8 483 #define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) 484 #define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) 485 #define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) 486 #define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0) 487 #define VDPU_REG_ENABLE_FLAG 0x1cc 488 #define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(8) 489 #define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(7) 490 #define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(6) 491 #define VDPU_REG_DEC_CTRL4_CABAC_E BIT(5) 492 #define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(4) 493 #define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(3) 494 #define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(2) 495 #define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(1) 496 #define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) 497 #define VDPU_REG_VP8_PIC_MB_SIZE 0x1e0 498 #define VDPU_REG_DEC_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) 499 #define VDPU_REG_DEC_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) 500 #define VDPU_REG_DEC_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) 501 #define VDPU_REG_DEC_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) 502 #define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) 503 #define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) 504 #define VDPU_REG_VP8_DCT_START_BIT 0x1e4 505 #define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26) 506 #define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20) 507 #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) 508 #define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) 509 #define VDPU_REG_VP8_CTRL0 0x1e8 510 #define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) 511 #define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18) 512 #define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8) 513 #define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) 514 #define VDPU_REG_VP8_DATA_VAL 0x1f0 515 #define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) 516 #define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) 517 #define VDPU_REG_PRED_FLT7 0x1f4 518 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1(x) (((x) & 0x3ff) << 22) 519 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2(x) (((x) & 0x3ff) << 12) 520 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3(x) (((x) & 0x3ff) << 2) 521 #define VDPU_REG_PRED_FLT8 0x1f8 522 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0(x) (((x) & 0x3ff) << 22) 523 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1(x) (((x) & 0x3ff) << 12) 524 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2(x) (((x) & 0x3ff) << 2) 525 #define VDPU_REG_PRED_FLT9 0x1fc 526 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3(x) (((x) & 0x3ff) << 22) 527 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0(x) (((x) & 0x3ff) << 12) 528 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1(x) (((x) & 0x3ff) << 2) 529 #define VDPU_REG_PRED_FLT10 0x200 530 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2(x) (((x) & 0x3ff) << 22) 531 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3(x) (((x) & 0x3ff) << 12) 532 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10) 533 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8) 534 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6) 535 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4) 536 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2) 537 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0) 538 #define VDPU_REG_FILTER_LEVEL 0x204 539 #define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18) 540 #define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12) 541 #define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6) 542 #define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0) 543 #define VDPU_REG_VP8_QUANTER0 0x208 544 #define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27) 545 #define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) 546 #define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) 547 #define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) 548 #define VDPU_REG_VP8_ADDR_REF0 0x20c 549 #define VDPU_REG_FILTER_MB_ADJ 0x210 550 #define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) 551 #define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) 552 #define VDPU_REG_FILT_MB_ADJ_0(x) (((x) & 0x7f) << 21) 553 #define VDPU_REG_FILT_MB_ADJ_1(x) (((x) & 0x7f) << 14) 554 #define VDPU_REG_FILT_MB_ADJ_2(x) (((x) & 0x7f) << 7) 555 #define VDPU_REG_FILT_MB_ADJ_3(x) (((x) & 0x7f) << 0) 556 #define VDPU_REG_FILTER_REF_ADJ 0x214 557 #define VDPU_REG_REF_PIC_ADJ_0(x) (((x) & 0x7f) << 21) 558 #define VDPU_REG_REF_PIC_ADJ_1(x) (((x) & 0x7f) << 14) 559 #define VDPU_REG_REF_PIC_ADJ_2(x) (((x) & 0x7f) << 7) 560 #define VDPU_REG_REF_PIC_ADJ_3(x) (((x) & 0x7f) << 0) 561 #define VDPU_REG_VP8_ADDR_REF2_5(i) (0x218 + ((i) * 0x4)) 562 #define VDPU_REG_VP8_GREF_SIGN_BIAS BIT(0) 563 #define VDPU_REG_VP8_AREF_SIGN_BIAS BIT(0) 564 #define VDPU_REG_VP8_DCT_BASE(i) (0x230 + ((i) * 0x4)) 565 #define VDPU_REG_VP8_ADDR_CTRL_PART 0x244 566 #define VDPU_REG_VP8_ADDR_REF1 0x250 567 #define VDPU_REG_VP8_SEGMENT_VAL 0x254 568 #define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) 569 #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) 570 #define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) 571 #define VDPU_REG_VP8_DCT_START_BIT2 0x258 572 #define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24) 573 #define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18) 574 #define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) 575 #define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) 576 #define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) 577 #define VDPU_REG_VP8_QUANTER1 0x25c 578 #define VDPU_REG_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27) 579 #define VDPU_REG_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) 580 #define VDPU_REG_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) 581 #define VDPU_REG_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) 582 #define VDPU_REG_VP8_QUANTER2 0x260 583 #define VDPU_REG_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) 584 #define VDPU_REG_REF_PIC_QUANT_4(x) (((x) & 0x7ff) << 11) 585 #define VDPU_REG_REF_PIC_QUANT_5(x) (((x) & 0x7ff) << 0) 586 #define VDPU_REG_PRED_FLT1 0x264 587 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3(x) (((x) & 0x3ff) << 22) 588 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0(x) (((x) & 0x3ff) << 12) 589 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1(x) (((x) & 0x3ff) << 2) 590 #define VDPU_REG_PRED_FLT2 0x268 591 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2(x) (((x) & 0x3ff) << 22) 592 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3(x) (((x) & 0x3ff) << 12) 593 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0(x) (((x) & 0x3ff) << 2) 594 #define VDPU_REG_PRED_FLT3 0x26c 595 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1(x) (((x) & 0x3ff) << 22) 596 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2(x) (((x) & 0x3ff) << 12) 597 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3(x) (((x) & 0x3ff) << 2) 598 #define VDPU_REG_PRED_FLT4 0x270 599 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0(x) (((x) & 0x3ff) << 22) 600 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1(x) (((x) & 0x3ff) << 12) 601 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2(x) (((x) & 0x3ff) << 2) 602 #define VDPU_REG_PRED_FLT5 0x274 603 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3(x) (((x) & 0x3ff) << 22) 604 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0(x) (((x) & 0x3ff) << 12) 605 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1(x) (((x) & 0x3ff) << 2) 606 #define VDPU_REG_PRED_FLT6 0x278 607 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2(x) (((x) & 0x3ff) << 22) 608 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3(x) (((x) & 0x3ff) << 12) 609 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0(x) (((x) & 0x3ff) << 2) 610 611 #define VEPU2_H264E_NUM_REGS 184 612 613 typedef struct h264e_vepu2_reg_set_t { 614 RK_U32 val[VEPU2_H264E_NUM_REGS]; 615 } H264eVpu2RegSet; 616 617 #endif 618