1 /* 2 * Copyright 2017 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H264E_VEPU1_REG_TBL_H__ 18 #define __HAL_H264E_VEPU1_REG_TBL_H__ 19 20 #include "rk_type.h" 21 22 #define BIT(n) (1<<(n)) 23 24 /* RK3288 Encoder registers. */ 25 #define VEPU_REG_INTERRUPT 0x004 26 #define VEPU_REG_INTERRUPT_SLICE_READY BIT(8) 27 #define VEPU_REG_INTERRUPT_TIMEOUT BIT(6) 28 #define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5) 29 #define VEPU_REG_INTERRUPT_RESET BIT(4) 30 #define VEPU_REG_INTERRUPT_BUS_ERROR BIT(3) 31 #define VEPU_REG_INTERRUPT_FRAME_READY BIT(2) 32 #define VEPU_REG_INTERRUPT_DIS_BIT BIT(1) 33 #define VEPU_REG_INTERRUPT_BIT BIT(0) 34 35 #define VEPU_REG_AXI_CTRL 0x008 36 #define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 24) 37 #define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 16) 38 #define VEPU_REG_OUTPUT_SWAP16 BIT(15) 39 #define VEPU_REG_INPUT_SWAP16 BIT(14) 40 #define VEPU_REG_INPUT_SWAP16_(x) (((x) & 1) << 14) 41 #define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8) 42 #define VEPU_REG_AXI_CTRL_BURST_DISABLE BIT(7) 43 #define VEPU_REG_AXI_CTRL_INCREMENT_MODE BIT(6) 44 #define VEPU_REG_AXI_CTRL_BURST_DISCARD BIT(5) 45 #define VEPU_REG_CLK_GATING_EN BIT(4) 46 #define VEPU_REG_OUTPUT_SWAP32 BIT(3) 47 #define VEPU_REG_INPUT_SWAP32 BIT(2) 48 #define VEPU_REG_INPUT_SWAP32_(x) (((x) & 1) << 2) 49 #define VEPU_REG_OUTPUT_SWAP8 BIT(1) 50 #define VEPU_REG_INPUT_SWAP8 BIT(0) 51 #define VEPU_REG_INPUT_SWAP8_(x) ((x) & 1) 52 53 #define VEPU_REG_ADDR_OUTPUT_STREAM 0x014 54 #define VEPU_REG_ADDR_OUTPUT_CTRL 0x018 55 #define VEPU_REG_ADDR_REF_LUMA 0x01c 56 #define VEPU_REG_ADDR_REF_CHROMA 0x020 57 58 #define VEPU_REG_ADDR_REC_LUMA 0x024 59 #define VEPU_REG_ADDR_REC_CHROMA 0x028 60 61 #define VEPU_REG_ADDR_IN_LUMA 0x02c 62 #define VEPU_REG_ADDR_IN_CB 0x030 63 #define VEPU_REG_ADDR_IN_CR 0x034 64 65 #define VEPU_REG_ENCODE_CTRL 0x038 66 #define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(31) 67 #define VEPU_REG_MV_WRITE_EN BIT(30) 68 #define VEPU_REG_SIZE_TABLE_PRESENT BIT(29) 69 #define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(28) 70 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 19) 71 #define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 10) 72 #define VEPU_REG_RECON_WRITE_DIS BIT(6) 73 #define VEPU_REG_PIC_TYPE(x) (((x) & 0x3) << 3) 74 #define VEPU_REG_ENCODE_FORMAT(x) (((x) & 0x3) << 1) 75 #define VEPU_REG_ENCODE_ENABLE BIT(0) 76 77 #define VEPU_REG_ENC_INPUT_IMAGE_CTRL 0x03c 78 #define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 29) 79 #define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 26) 80 #define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 12) 81 #define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 10) 82 #define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 6) 83 #define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 2) 84 #define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 0) 85 86 #define VEPU_REG_ENC_CTRL0 0x040 87 #define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26) 88 #define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22) 89 #define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18) 90 #define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13) 91 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) 92 #define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0) 93 94 #define VEPU_REG_ENC_CTRL1 0x044 95 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) 96 #define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16) 97 #define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0) 98 99 #define VEPU_REG_ENC_CTRL2 0x048 100 #define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 30) 101 #define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 23) 102 #define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(22) 103 #define VEPU_REG_H264_TRANS8X8_MODE BIT(21) 104 #define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 19) 105 #define VEPU_REG_ENTROPY_CODING_MODE BIT(18) 106 #define VEPU_REG_H264_INTER4X4_MODE BIT(17) 107 #define VEPU_REG_H264_STREAM_MODE BIT(16) 108 #define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 0) 109 110 #define VEPU_REG_ENC_CTRL3 0x04c 111 #define VEPU_REG_SPLIT_MV_MODE_EN BIT(30) 112 #define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 20) 113 #define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 10) 114 #define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 0) 115 116 #define VEPU_REG_ENC_CTRL_4 0x054 117 #define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 24) 118 #define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16) 119 #define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0) 120 121 #define VEPU_REG_STR_HDR_REM_MSB 0x058 122 #define VEPU_REG_STR_HDR_REM_LSB 0x05c 123 #define VEPU_REG_STR_BUF_LIMIT 0x060 124 125 #define VEPU_REG_MAD_CTRL 0x064 126 #define VEPU_REG_MAD_QP_ADJUSTMENT(x) (((x) & 0xf) << 28) 127 #define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 22) 128 #define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2) 129 130 #define VEPU_REG_QP_VAL 0x06c 131 #define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26) 132 #define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20) 133 #define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14) 134 #define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0) 135 136 #define VEPU_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4)) 137 #define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) 138 #define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) 139 #define VEPU_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \ 140 * (i & 1))) & 0xffff) \ 141 * 32) 142 143 #define VEPU_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4)) 144 #define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) 145 #define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) 146 147 #define VEPU_REG_CHKPT_DELTA_QP 0x090 148 #define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) 149 #define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) 150 #define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) 151 #define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) 152 #define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) 153 #define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) 154 #define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) 155 156 #define VEPU_REG_RLC_CTRL 0x094 157 #define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 23) 158 #define VEPU_REG_RLC_SUM (((x) & 0x007fffff) << 0) 159 #define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4) 160 161 #define VEPU_REG_MB_CTRL 0x098 162 #define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 16) 163 #define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 0) 164 165 #define VEPU_REG_ADDR_NEXT_PIC 0x09c 166 167 #define VEPU_REG_STABLILIZATION_OUTPUT 0x0a0 168 #define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 30) 169 #define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 0) 170 171 #define VEPU_REG_STABLE_MOTION_SUM 0x0a4 172 #define VEPU_REG_ADDR_CABAC_TBL 0x0cc 173 #define VEPU_REG_ADDR_MV_OUT 0x0d0 174 175 #define VEPU_REG_RGB2YUV_CONVERSION_COEF1 0x0d4 176 #define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16) 177 #define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0) 178 179 #define VEPU_REG_RGB2YUV_CONVERSION_COEF2 0x0d8 180 #define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16) 181 #define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0) 182 183 #define VEPU_REG_RGB_MASK_MSB 0x0dc 184 #define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 26) 185 #define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 21) 186 #define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 16) 187 #define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0) 188 189 #define VEPU_REG_INTRA_AREA_CTRL 0x0e0 190 #define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 24) 191 #define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 16) 192 #define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 8) 193 #define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 0) 194 195 #define VEPU_REG_CIR_INTRA_CTRL 0x0e4 196 #define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16) 197 #define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0) 198 199 #define VEPU_REG_ROI1 0x0f0 200 #define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 24) 201 #define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 16) 202 #define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 8) 203 #define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 0) 204 205 #define VEPU_REG_ROI2 0x0f4 206 #define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 24) 207 #define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 16) 208 #define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 8) 209 #define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 0) 210 211 #define VEPU_REG_MVC_RELATE 0x0f8 212 #define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 28) 213 #define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 19) 214 #define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 16) 215 #define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 13) 216 #define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 10) 217 #define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(9) 218 #define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(8) 219 #define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 4) 220 #define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 0) 221 222 #define VEPU_REG_DMV_PENALTY_TBL(i) (0x180 + ((i) * 0x4)) 223 #define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) (x << i * 8) 224 225 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i) (0x200 + ((i) * 0x4)) 226 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) (x << i * 8) 227 228 #define VEPU1_H264E_NUM_REGS 164 229 230 typedef struct H264eVpu1RegSet_t { 231 RK_U32 val[VEPU1_H264E_NUM_REGS]; 232 } H264eVpu1RegSet; 233 234 #endif 235