1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_VCORE_DVFSRC_PLAT_DEF_H 8 #define MT_VCORE_DVFSRC_PLAT_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #ifdef MT8196_VCORE_SUPPORT 13 #define VCORE_BASE_UV 0 14 #define VCORE_STEP_UV 6250 15 16 /* PMIC */ 17 #define VCORE_PMIC_TO_UV(pmic) \ 18 (((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV) 19 #define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \ 20 ((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV) 21 #else 22 #define VCORE_BASE_UV 0 23 #define VCORE_STEP_UV 5000 24 25 /* PMIC */ 26 #define VCORE_PMIC_TO_UV(pmic) \ 27 (((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV) 28 #define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \ 29 ((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV) 30 31 #ifndef v_min 32 #define v_min(a, b) MIN(a, b) 33 #endif 34 35 #ifndef v_max 36 #define v_max(a, b) MAZ(a, b) 37 #endif 38 #endif 39 40 #define VCORE_VB_INFO0 (EFUSEC_BASE + 0xD24) 41 #define VCORE_VB_INFO1 (EFUSEC_BASE + 0xD28) 42 #define VCORE_VB_INFO2 (EFUSEC_BASE + 0xD84) 43 44 static const struct reg_config dvfsrc_init_configs[] = { 45 { DVFSRC_TIMEOUT_NEXTREQ, 0x00001AFF }, 46 { DVFSRC_VCORE_USER_REQ, 0x00010F51 }, 47 { DVFSRC_BW_USER_REQ, 0x00010033 }, 48 /* EMI MONITOR */ 49 { DVFSRC_DDR_REQUEST3, 0x44444321 }, 50 { DVFSRC_DDR_REQUEST10, 0x44444321 }, 51 /* SW QOS */ 52 { DVFSRC_QOS_EN, 0x20F1007C }, 53 { DVFSRC_DDR_QOS0, 0x0000004B }, 54 { DVFSRC_DDR_QOS1, 0x0000009A }, 55 { DVFSRC_DDR_QOS2, 0x000000CE }, 56 { DVFSRC_DDR_QOS3, 0x00000134 }, 57 { DVFSRC_DDR_QOS4, 0x00000185 }, 58 { DVFSRC_DDR_QOS5, 0x000001F9 }, 59 { DVFSRC_DDR_QOS6, 0x0000024C }, 60 { DVFSRC_DDR_QOS7, 0x000002B4 }, 61 { DVFSRC_DDR_QOS8, 0x00000354 }, 62 { DVFSRC_DDR_REQUEST5, 0x87654321 }, 63 { DVFSRC_DDR_REQUEST8, 0x00000009 }, 64 /* LEVEL */ 65 { DVFSRC_LEVEL_LABEL_0_1, 0x9055A055 }, 66 { DVFSRC_LEVEL_LABEL_2_3, 0x80458055 }, 67 { DVFSRC_LEVEL_LABEL_4_5, 0x70558044 }, 68 { DVFSRC_LEVEL_LABEL_6_7, 0x70447045 }, 69 { DVFSRC_LEVEL_LABEL_8_9, 0x60456055 }, 70 { DVFSRC_LEVEL_LABEL_10_11, 0x60446035 }, 71 { DVFSRC_LEVEL_LABEL_12_13, 0x60336034 }, 72 { DVFSRC_LEVEL_LABEL_14_15, 0x50455055 }, 73 { DVFSRC_LEVEL_LABEL_16_17, 0x50445035 }, 74 { DVFSRC_LEVEL_LABEL_18_19, 0x50335034 }, 75 { DVFSRC_LEVEL_LABEL_20_21, 0x40454055 }, 76 { DVFSRC_LEVEL_LABEL_22_23, 0x40254035 }, 77 { DVFSRC_LEVEL_LABEL_24_25, 0x40344044 }, 78 { DVFSRC_LEVEL_LABEL_26_27, 0x40334024 }, 79 { DVFSRC_LEVEL_LABEL_28_29, 0x40224023 }, 80 { DVFSRC_LEVEL_LABEL_30_31, 0x30453055 }, 81 { DVFSRC_LEVEL_LABEL_32_33, 0x30253035 }, 82 { DVFSRC_LEVEL_LABEL_34_35, 0x30443015 }, 83 { DVFSRC_LEVEL_LABEL_36_37, 0x30243034 }, 84 { DVFSRC_LEVEL_LABEL_38_39, 0x30333014 }, 85 { DVFSRC_LEVEL_LABEL_40_41, 0x30133023 }, 86 { DVFSRC_LEVEL_LABEL_42_43, 0x30123022 }, 87 { DVFSRC_LEVEL_LABEL_44_45, 0x20553011 }, 88 { DVFSRC_LEVEL_LABEL_46_47, 0x20352045 }, 89 { DVFSRC_LEVEL_LABEL_48_49, 0x20152025 }, 90 { DVFSRC_LEVEL_LABEL_50_51, 0x20442005 }, 91 { DVFSRC_LEVEL_LABEL_52_53, 0x20242034 }, 92 { DVFSRC_LEVEL_LABEL_54_55, 0x20042014 }, 93 { DVFSRC_LEVEL_LABEL_56_57, 0x20232033 }, 94 { DVFSRC_LEVEL_LABEL_58_59, 0x20032013 }, 95 { DVFSRC_LEVEL_LABEL_60_61, 0x20122022 }, 96 { DVFSRC_LEVEL_LABEL_62_63, 0x20112002 }, 97 { DVFSRC_LEVEL_LABEL_64_65, 0x20002001 }, 98 { DVFSRC_LEVEL_LABEL_66_67, 0x10451055 }, 99 { DVFSRC_LEVEL_LABEL_68_69, 0x10251035 }, 100 { DVFSRC_LEVEL_LABEL_70_71, 0x10051015 }, 101 { DVFSRC_LEVEL_LABEL_72_73, 0x10341044 }, 102 { DVFSRC_LEVEL_LABEL_74_75, 0x10141024 }, 103 { DVFSRC_LEVEL_LABEL_76_77, 0x10331004 }, 104 { DVFSRC_LEVEL_LABEL_78_79, 0x10131023 }, 105 { DVFSRC_LEVEL_LABEL_80_81, 0x10221003 }, 106 { DVFSRC_LEVEL_LABEL_82_83, 0x10021012 }, 107 { DVFSRC_LEVEL_LABEL_84_85, 0x10011011 }, 108 { DVFSRC_LEVEL_LABEL_86_87, 0x00001000 }, 109 /* HRT */ 110 { DVFSRC_PMQOS_HRT_UNIT_SW_BW, 0x00000120 }, 111 { DVFSRC_ISP_HRT_UNIT_SW_BW, 0x0000010F }, 112 { DVFSRC_MD_HRT_UNIT_SW_BW, 0x0000010F }, 113 { DVFSRC_HRT_BASE_HRT_UNIT_SW_BW, 0x0000010F }, 114 { DVFSRC_HRT_REQUEST, 0x87654321 }, 115 { DVFSRC_HRT_REQUEST_1, 0x00000009 }, 116 { DVFSRC_HRT_HIGH, 0x000006A8 }, 117 { DVFSRC_HRT_HIGH_1, 0x00000DD7 }, 118 { DVFSRC_HRT_HIGH_2, 0x000012A8 }, 119 { DVFSRC_HRT_HIGH_3, 0x00001C0B }, 120 { DVFSRC_HRT_HIGH_4, 0x00002644 }, 121 { DVFSRC_HRT_HIGH_5, 0x000031AC }, 122 { DVFSRC_HRT_HIGH_6, 0x000039FD }, 123 { DVFSRC_HRT_HIGH_7, 0x00004435 }, 124 { DVFSRC_HRT_HIGH_8, 0x000053B6 }, 125 { DVFSRC_HRT_LOW, 0x000006A7 }, 126 { DVFSRC_HRT_LOW_1, 0x00000DD7 }, 127 { DVFSRC_HRT_LOW_2, 0x000012A8 }, 128 { DVFSRC_HRT_LOW_3, 0x00001C0B }, 129 { DVFSRC_HRT_LOW_4, 0x00002643 }, 130 { DVFSRC_HRT_LOW_5, 0x000031AB }, 131 { DVFSRC_HRT_LOW_6, 0x000039FD }, 132 { DVFSRC_HRT_LOW_7, 0x00004435 }, 133 { DVFSRC_HRT_LOW_8, 0x000053B6 }, 134 /* MDDDR */ 135 { DVFSRC_HRT_REQ_MD_URG, 0x003FF3FF }, 136 { DVFSRC_95MD_SCEN_BW7, 0x90000000 }, 137 { DVFSRC_95MD_SCEN_BW7_T, 0x90000000 }, 138 { DVFSRC_95MD_SCEN_BWU, 0x00000009 }, 139 { DVFSRC_MD_LATENCY_IMPROVE, 0x00000021 }, 140 { DVFSRC_DEBOUNCE_TIME, 0x0000179E }, 141 /* RISING */ 142 { DVFSRC_DDR_ADD_REQUEST, 0x76543210 }, 143 { DVFSRC_DDR_ADD_REQUEST_1, 0x99999998 }, 144 { DVFSRC_EMI_MON_DEBOUNCE_TIME, 0x4C2D0000 }, 145 /* MISC */ 146 { DVFSRC_DEFAULT_OPP_1, 0x00000000 }, 147 { DVFSRC_DEFAULT_OPP_2, 0x00000000 }, 148 { DVFSRC_DEFAULT_OPP_3, 0x00000000 }, 149 { DVFSRC_DEFAULT_OPP_4, 0x00000000 }, 150 { DVFSRC_DEFAULT_OPP_5, 0x00000000 }, 151 { DVFSRC_DEFAULT_OPP_6, 0x00000000 }, 152 { DVFSRC_DEFAULT_OPP_7, 0x00000000 }, 153 { DVFSRC_DEFAULT_OPP_8, 0x00000001 }, 154 { DVFSRC_BASIC_CONTROL_4, 0x0000020F }, 155 { DVFSRC_INT_EN, 0x00000002 }, 156 }; 157 158 static const struct reg_config lp5_7500_init_configs[] = { 159 /* SW QOS */ 160 { DVFSRC_DDR_REQUEST5, 0x77654321 }, 161 { DVFSRC_DDR_REQUEST8, 0x00000007 }, 162 /* HRT */ 163 { DVFSRC_HRT_REQUEST, 0x77654321 }, 164 { DVFSRC_HRT_REQUEST_1, 0x00000007 }, 165 /* MDDDR */ 166 { DVFSRC_95MD_SCEN_BW7, 0x70000000 }, 167 { DVFSRC_95MD_SCEN_BW7_T, 0x70000000 }, 168 { DVFSRC_95MD_SCEN_BWU, 0x00000007 }, 169 }; 170 171 static const struct reg_config lp5_8533_init_configs[] = { 172 /* SW QOS */ 173 { DVFSRC_DDR_REQUEST5, 0x87654321 }, 174 { DVFSRC_DDR_REQUEST8, 0x00000008 }, 175 /* HRT */ 176 { DVFSRC_HRT_REQUEST, 0x87654321 }, 177 { DVFSRC_HRT_REQUEST_1, 0x00000008 }, 178 /* MDDDR */ 179 { DVFSRC_95MD_SCEN_BW7, 0x80000000 }, 180 { DVFSRC_95MD_SCEN_BW7_T, 0x80000000 }, 181 { DVFSRC_95MD_SCEN_BWU, 0x00000008 }, 182 }; 183 184 static const struct reg_config lp5_10677_init_configs[] = { 185 /* SW QOS */ 186 { DVFSRC_DDR_QOS9, 0x000003C0 }, 187 { DVFSRC_DDR_REQUEST5, 0x87654321 }, 188 { DVFSRC_DDR_REQUEST8, 0x000000A9 }, 189 /* HRT */ 190 { DVFSRC_HRT_HIGH_9, 0x00005E80 }, 191 { DVFSRC_HRT_LOW_9, 0x00005E7F }, 192 { DVFSRC_HRT_REQUEST, 0x87654321 }, 193 { DVFSRC_HRT_REQUEST_1, 0x000000A9 }, 194 }; 195 196 static const struct reg_config lp5_8533_init_configs_auto[] = { 197 198 /* LEVEL */ 199 { DVFSRC_LEVEL_LABEL_0_1, 0x80449045 }, 200 { DVFSRC_LEVEL_LABEL_2_3, 0x70448044 }, 201 { DVFSRC_LEVEL_LABEL_4_5, 0x60346044 }, 202 { DVFSRC_LEVEL_LABEL_6_7, 0x50446033 }, 203 { DVFSRC_LEVEL_LABEL_8_9, 0x50335034 }, 204 { DVFSRC_LEVEL_LABEL_10_11, 0x40344044 }, 205 { DVFSRC_LEVEL_LABEL_12_13, 0x40334024 }, 206 { DVFSRC_LEVEL_LABEL_14_15, 0x40224023 }, 207 { DVFSRC_LEVEL_LABEL_16_17, 0x30343044 }, 208 { DVFSRC_LEVEL_LABEL_18_19, 0x30143024 }, 209 { DVFSRC_LEVEL_LABEL_20_21, 0x30233033 }, 210 { DVFSRC_LEVEL_LABEL_22_23, 0x30223013 }, 211 { DVFSRC_LEVEL_LABEL_24_25, 0x30113012 }, 212 { DVFSRC_LEVEL_LABEL_26_27, 0x20342044 }, 213 { DVFSRC_LEVEL_LABEL_28_29, 0x20142024 }, 214 { DVFSRC_LEVEL_LABEL_30_31, 0x20332004 }, 215 { DVFSRC_LEVEL_LABEL_32_33, 0x20132023 }, 216 { DVFSRC_LEVEL_LABEL_34_35, 0x20222003 }, 217 { DVFSRC_LEVEL_LABEL_36_37, 0x20022012 }, 218 { DVFSRC_LEVEL_LABEL_38_39, 0x20012011 }, 219 { DVFSRC_LEVEL_LABEL_40_41, 0x10442000 }, 220 { DVFSRC_LEVEL_LABEL_42_43, 0x10241034 }, 221 { DVFSRC_LEVEL_LABEL_44_45, 0x10041014 }, 222 { DVFSRC_LEVEL_LABEL_46_47, 0x10231033 }, 223 { DVFSRC_LEVEL_LABEL_48_49, 0x10031013 }, 224 { DVFSRC_LEVEL_LABEL_50_51, 0x10121022 }, 225 { DVFSRC_LEVEL_LABEL_52_53, 0x10111002 }, 226 { DVFSRC_LEVEL_LABEL_54_55, 0x10001001 }, 227 { DVFSRC_LEVEL_LABEL_56_57, 0x10341044 }, 228 { DVFSRC_LEVEL_LABEL_58_59, 0x10141024 }, 229 { DVFSRC_LEVEL_LABEL_60_61, 0x10331004 }, 230 { DVFSRC_LEVEL_LABEL_62_63, 0x10131023 }, 231 { DVFSRC_LEVEL_LABEL_64_65, 0x10221003 }, 232 { DVFSRC_LEVEL_LABEL_66_67, 0x10021012 }, 233 { DVFSRC_LEVEL_LABEL_68_69, 0x10011011 }, 234 { DVFSRC_LEVEL_LABEL_70_71, 0x00001000 }, 235 { DVFSRC_LEVEL_LABEL_72_73, 0x00000000 }, 236 { DVFSRC_LEVEL_LABEL_74_75, 0x00000000 }, 237 { DVFSRC_LEVEL_LABEL_76_77, 0x00000000 }, 238 { DVFSRC_LEVEL_LABEL_78_79, 0x00000000 }, 239 { DVFSRC_LEVEL_LABEL_80_81, 0x00000000 }, 240 { DVFSRC_LEVEL_LABEL_82_83, 0x00000000 }, 241 { DVFSRC_LEVEL_LABEL_84_85, 0x00000000 }, 242 { DVFSRC_LEVEL_LABEL_86_87, 0x00000000 }, 243 }; 244 245 #endif /* MT_VCORE_DVFSRC_PLAT_DEF_H */ 246