1 /*
2 * Copyright (c) 2023 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <boot_rkimg.h>
8 #include <dm.h>
9 #include <fdt_support.h>
10 #include <misc.h>
11 #include <mmc.h>
12 #include <scsi.h>
13 #include <spl.h>
14 #include <asm/io.h>
15 #include <asm/arch/bootrom.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/boot_mode.h>
19 #include <asm/arch/ioc_rk3576.h>
20 #include <asm/arch/rockchip_smccc.h>
21 #include <asm/system.h>
22 #include <asm/arch/vendor.h>
23 #include <optee_include/OpteeClientInterface.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define SYS_GRF_BASE 0x2600A000
28 #define SYS_GRF_SOC_CON2 0x0008
29 #define SYS_GRF_SOC_CON7 0x001c
30 #define SYS_GRF_SOC_CON11 0x002c
31 #define SYS_GRF_SOC_CON12 0x0030
32
33 #define GPIO0_IOC_BASE 0x26040000
34 #define GPIO0B_PULL_L 0x0024
35 #define GPIO0B_IE_L 0x002C
36
37 #define TOP_IOC_BASE 0x26044000
38 #define GPIO1A_IOMUX_SEL_L 0x0020
39 #define GPIO1A_IOMUX_SEL_H 0x0024
40 #define GPIO1B_IOMUX_SEL_L 0x0028
41 #define GPIO1B_IOMUX_SEL_H 0x002c
42 #define GPIO1C_IOMUX_SEL_L 0x0030
43 #define GPIO1C_IOMUX_SEL_H 0x0034
44 #define GPIO1D_IOMUX_SEL_L 0x0038
45 #define GPIO1D_IOMUX_SEL_H 0x003c
46 #define GPIO2A_IOMUX_SEL_L 0x0040
47 #define GPIO2A_IOMUX_SEL_H 0x0044
48
49 #define VCCIO_IOC_BASE 0x26046000
50 #define VCCIO_IOC_GPIO1C_PUL 0x118
51 #define VCCIO_IOC_GPIO1D_PUL 0x11C
52 #define VCCIO_IOC_GPIO2A_PUL 0x120
53
54 #define VCCIO6_IOC_BASE 0x2604a000
55 #define VCCIO7_IOC_BASE 0x2604b000
56 #define VCCIO7_IOC_GPIO4D_IOMUX_SEL_L 0x0398
57 #define VCCIO7_IOC_XIN_UFS_CON 0x0400
58
59 #define PMU1_SGRF_BASE 0x26002000
60 #define PMU1_SGRF_SOC_CON10 0x0028
61 #define PMU1_SGRF_SOC_CON11 0x002C
62
63 #define SYS_SGRF_BASE 0x26004000
64 #define SYS_SGRF_SOC_CON14 0x0058
65 #define SYS_SGRF_SOC_CON15 0x005C
66 #define SYS_SGRF_SOC_CON20 0x0070
67
68 #define FW_SYS_SGRF_BASE 0x26005000
69 #define SGRF_DOMAIN_CON1 0x4
70 #define SGRF_DOMAIN_CON2 0x8
71 #define SGRF_DOMAIN_CON3 0xc
72 #define SGRF_DOMAIN_CON4 0x10
73 #define SGRF_DOMAIN_CON5 0x14
74
75 #define USBGRF_BASE 0x2601e000
76 #define USB_GRF_USB3OTG0_CON1 0x0030
77
78 #define PMU1_GRF_BASE 0x26026000
79 #define OS_REG0 0x200
80 #define USB2PHY0_GRF_BASE 0x2602e000
81 #define USB2PHY1_GRF_BASE 0x26030000
82 #define USB2PHY_GRF_CON4 0x0010
83 #define USB2PHY_GRF_DBG_CON 0x0040
84 #define USB2PHY_GRF_LS_TIMEOUT 0x0044
85 #define USB2PHY_GRF_LS_DEB 0x0048
86 #define USB2PHY_GRF_RX_TIMEOUT 0x004c
87 #define USB2PHY_GRF_SEQ_LIMT 0x0050
88
89 #define TOP_CRU_BASE 0x27200000
90 #define TOP_CRU_GATE_CON19 0x084C
91 #define TOP_CRU_SOFTRST_CON19 0x0a4C
92 #define PHPPHYSOFTRST_CON01 0x8a04
93
94 #define PMU1_CRU_BASE 0x27220000
95 #define PMU1_CRU_CLKSEL_CON03 0x030c
96 #define PMU1_CRU_GATE_CON03 0x080C
97 #define PMU1_CRU_SOFTRST_CON03 0x0a0C
98
99 #define SATA0_BASE_ADDR 0x2a240000
100 #define SATA1_BASE_ADDR 0x2a250000
101 #define SATA_PI 0xC
102 #define SATA_PORT_CMD 0x118
103 #define SATA_FBS_ENABLE BIT(22)
104
105 #ifdef CONFIG_ARM64
106 #include <asm/armv8/mmu.h>
107
108 static struct mm_region rk3576_mem_map[] = {
109 {
110 .virt = 0x20000000UL,
111 .phys = 0x20000000UL,
112 .size = 0xb080000UL,
113 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
114 PTE_BLOCK_NON_SHARE |
115 PTE_BLOCK_PXN | PTE_BLOCK_UXN
116 }, {
117 .virt = 0x3fe70000UL,
118 .phys = 0x3fe70000UL,
119 .size = 0x190000UL,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
121 PTE_BLOCK_NON_SHARE |
122 PTE_BLOCK_PXN | PTE_BLOCK_UXN
123 }, {
124 .virt = 0x40000000UL,
125 .phys = 0x40000000UL,
126 .size = 0x100000000UL - 0x40000000UL,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
128 PTE_BLOCK_INNER_SHARE
129 }, {
130 .virt = 0x100000000UL,
131 .phys = 0x100000000UL,
132 .size = 0x400000000UL,
133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_INNER_SHARE
135 }, {
136 .virt = 0x900000000UL,
137 .phys = 0x900000000UL,
138 .size = 0x100800000UL,
139 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE |
141 PTE_BLOCK_PXN | PTE_BLOCK_UXN
142 }, {
143 /* List terminator */
144 0,
145 }
146 };
147
148 struct mm_region *mem_map = rk3576_mem_map;
149 #endif
150
board_debug_uart_init(void)151 void board_debug_uart_init(void)
152 {
153 }
154
155 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
156 [BROM_BOOTSOURCE_EMMC] = "/mmc@2a330000",
157 [BROM_BOOTSOURCE_SD] = "/mmc@2a310000",
158 [BROM_BOOTSOURCE_UFS] = "/ufs@2a2d0000",
159 };
160
161 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)162 void rockchip_stimer_init(void)
163 {
164 u32 reg;
165
166 /* If Timer already enabled, don't re-init it */
167 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
168 if (reg & 0x1)
169 return;
170 #ifdef COUNTER_FREQUENCY
171 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
172 #endif
173 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
174 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
175 writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
176 }
177 #endif
178
reset_misc(void)179 void reset_misc(void)
180 {
181 #ifdef CONFIG_SPL_BUILD
182 /* For RK3576 SPL, should extraly write os_reg0 and reset to maskrom. */
183 if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) == BOOT_BROM_DOWNLOAD)
184 writel(BOOT_BROM_DOWNLOAD, PMU1_GRF_BASE + OS_REG0);
185 #elif CONFIG_SUPPORT_USBPLUG
186 /*
187 * For RK3576 USBPLUG, should clear maskrom flag both in os_reg0 and os_reg16.
188 * It already clear os_reg16 under ./drivers/usb/gadget/f_rockusb.c
189 */
190 if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != BOOT_BROM_DOWNLOAD)
191 writel(0, (void *)PMU1_GRF_BASE + OS_REG0);
192 #endif
193 }
194
board_set_iomux(enum if_type if_type,int devnum,int routing)195 void board_set_iomux(enum if_type if_type, int devnum, int routing)
196 {
197 switch (if_type) {
198 case IF_TYPE_MMC:
199 if (devnum == 0) {
200 writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
201 writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_H);
202 writel(0xffff1111, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
203 } else if (devnum == 1) {
204 writel(0xffff1111, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
205 writel(0x00ff0011, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
206 /* Pull up */
207 writel(0x0FFF0FFF, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL);
208 }
209 break;
210 case IF_TYPE_MTD:
211 if (routing == 0) {
212 /* FSPI0 M0 */
213 writel(0xffff2222, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
214 writel(0xffff2020, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
215 } else if (routing == 1) {
216 /* FSPI1 M0 */
217 writel(0xffff2222, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
218 writel(0x00ff0022, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
219 /* Pull up */
220 writel(0x03ff03ff, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL);
221 } else if (routing == 2) {
222 /* FSPI1 M1 */
223 writel(0xf0003000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);
224 writel(0xffff3333, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);
225 writel(0x00f00030, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);
226 /* Pull up */
227 writel(0xffc0ffc0, VCCIO_IOC_BASE + VCCIO_IOC_GPIO1C_PUL);
228 }
229 break;
230 default:
231 printf("Bootdev 0x%x is not support\n", if_type);
232 }
233 }
234
board_unset_iomux(enum if_type if_type,int devnum,int routing)235 void board_unset_iomux(enum if_type if_type, int devnum, int routing)
236 {
237 switch (if_type) {
238 case IF_TYPE_MTD:
239 if (routing == 0) {
240 /* FSPI0 M0 -> GPIO */
241 writel(0xffff0000, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
242 writel(0xffff0000, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
243 } else if (routing == 1) {
244 /* FSPI1 M0 -> GPIO */
245 writel(0xffff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
246 writel(0x00ff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
247 } else if (routing == 2) {
248 /* FSPI1 M1 -> GPIO */
249 writel(0xf0000000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);
250 writel(0xffff0000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);
251 writel(0x00f00000, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);
252 }
253 break;
254 default:
255 break;
256 }
257 }
258
259 /* @brief: release reset for MCU
260 * @param id: id of MCU, like: bus_mcu, pmu_mcu
261 * @param entry_point: entry of firmware, use for address map
262 * */
fit_standalone_release(char * id,uintptr_t entry_point)263 int fit_standalone_release(char *id, uintptr_t entry_point)
264 {
265 if (!strcmp(id, "bus_mcu")) {
266 /* address map: map 0 to entry_point */
267 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
268 ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
269 entry_point);
270
271 /*
272 * bus m0 configuration:
273 * open bus m0 rtc / core / biu / root
274 */
275 writel(0x5c000000, TOP_CRU_BASE + TOP_CRU_GATE_CON19);
276
277 /* select bus m0 jtag GPIO2A2 GPIO2A3 */
278 //writel(0x003f0010, SYS_GRF_BASE + SYS_GRF_SOC_CON7);
279 //writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
280
281 /* release bus m0 jtag / core / biu */
282 writel(0x38000000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON19);
283 }
284 else if (!strcmp(id, "pmu_mcu")) {
285
286 /* pmu m0 configuration: */
287 /* open pmu m0 rtc / core / biu / root */
288 /* writel(0x59020000, PMU1_CRU_BASE + PMU1_CRU_GATE_CON03); */
289
290 /* select pmu m0 jtag */
291 /* writel(0x003f0008, SYS_GRF_BASE + SYS_GRF_SOC_CON7); */
292 /* writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); */
293
294 /* release pmu m0 jtag / core / biu */
295 /* writel(0x38000000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON03); */
296 }
297
298 return 0;
299 }
300
301 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)302 int arch_cpu_init(void)
303 {
304 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
305 u32 val;
306
307 /* Set the emmc to access ddr memory */
308 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
309 writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
310
311 /* Set the sdmmc0 to access ddr memory */
312 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
313 writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
314
315 /* Set the UFS to access ddr memory */
316 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
317 writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
318
319 /* Set the fspi0 and fspi1 to access ddr memory */
320 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
321 writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
322
323 /* Set the decom to access ddr memory */
324 val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
325 writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
326
327 /* UFS PHY select 26M from ppll */
328 writel(0x00030002, PMU1_CRU_BASE + PMU1_CRU_CLKSEL_CON03);
329
330 /* set iomux UFS_REFCLK, UFS_RSTN */
331 writel(0x00FF0011, VCCIO7_IOC_BASE + VCCIO7_IOC_GPIO4D_IOMUX_SEL_L);
332 /* set UFS_RSTN to high */
333 udelay(20);
334 writel(0x00100010, VCCIO7_IOC_BASE + VCCIO7_IOC_XIN_UFS_CON);
335
336 /*
337 * Set the GPIO0B0~B3 pull up and input enable.
338 * Keep consistent with other IO.
339 */
340 writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
341 writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
342
343 /*
344 * bus mcu_cache_peripheral_addr
345 * The uncache area ranges from 0x20000000 to 0x48200000
346 * and contains rpmsg shared memory
347 */
348 writel(0x20000000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON14);
349 writel(0x48200000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON15);
350
351 /*
352 * pmu mcu_cache_peripheral_addr
353 * The uncache area ranges from 0x20000000 to 0x48200000
354 * and contains rpmsg shared memory
355 */
356 /* writel(0x20000000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10); */
357 /* writel(0x48200000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON11); */
358
359 /* TODO: pmu mcu code addr need bl31 support */
360 /* writel(0x48200000, 0x26002030); */
361
362 /*
363 * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
364 * keep consistent with other pwm.
365 */
366 writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
367
368 /*
369 * Assert reset the combophy0 and combophy1,
370 * de-assert reset in Kernel combophy driver.
371 */
372 writel(0x01200120, TOP_CRU_BASE + PHPPHYSOFTRST_CON01);
373
374 /*
375 * Assert SIDDQ for USB 2.0 PHY1 to power down
376 * PHY1 analog block to save power. And let the
377 * PHY0 for OTG0 interface still in normal mode.
378 */
379 writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON4);
380
381 /*
382 * Enable USB to DEBUG
383 * 1. Set linestate timeout 8ms
384 * 2. Set linestate fiter time 500us
385 * 3. Set Rx timeout counter for RX pulldown 2s
386 * 4. Set handshake counter number for SE0 and
387 * SE1 sequence at least 5.
388 */
389 writel(0xff, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_TIMEOUT);
390 writel(0x10, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_DEB);
391 writel(0xffff, USB2PHY0_GRF_BASE + USB2PHY_GRF_RX_TIMEOUT);
392 writel(0x05, USB2PHY0_GRF_BASE + USB2PHY_GRF_SEQ_LIMT);
393 writel(0x00010001, USB2PHY0_GRF_BASE + USB2PHY_GRF_DBG_CON);
394
395 /* Enable noc slave response timeout */
396 writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
397 writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
398
399 /*
400 * Select usb otg0 pipe phy status to 0 that
401 * ensure rockusb can work at high-speed even
402 * if usb3 phy isn't ready.
403 */
404 writel(0x000c0008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);
405
406 /*
407 * Enable cci channels for below module AXI R/W
408 * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
409 */
410 writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
411 #endif
412
413 /* Enabled SDMMC iomux in default except FSPI1_M0 boot */
414 if (readl(TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L) != 0x2222)
415 board_set_iomux(IF_TYPE_MMC, 1, 0);
416
417 #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
418 board_set_iomux(IF_TYPE_MMC, 0, 0);
419 #elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
420 /*
421 * (IF_TYPE_MTD, 0, 0) FSPI0
422 * (IF_TYPE_MTD, 1, 0) FSPI1 M0
423 * (IF_TYPE_MTD, 2, 0) FSPI1 M1
424 */
425 board_set_iomux(IF_TYPE_MTD, 0, 0);
426 #endif /* #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) */
427
428 return 0;
429 }
430 #endif
431
432 #if defined(CONFIG_SCSI) && defined(CONFIG_CMD_SCSI) && defined(CONFIG_UFS)
rk_board_dm_fdt_fixup(const void * blob)433 int rk_board_dm_fdt_fixup(const void *blob)
434 {
435 struct blk_desc *desc = rockchip_get_bootdev();
436 const char *status = NULL;
437 int node = -1;
438
439 /*
440 * 1. Kernel DTS will enable UFS by default.
441 *
442 * 2. It hangs if Kernel UFS driver tries to access UFS registers when there
443 * is no power supply for UFS.
444 *
445 * So generally, disable UFS when detect fail.
446 *
447 * To save time spent on detecting UFS, you can disable UFS in kernel dts or
448 * U-Boot defconfig.
449 *
450 */
451 if (desc->if_type != IF_TYPE_SCSI) {
452 node = fdt_path_offset(blob, "/ufs@2a2d0000");
453 if (node >= 0) {
454 status = fdt_getprop(blob, node, "status", NULL);
455 if (status && strcmp(status, "disabled")) {
456 if (scsi_scan(true)) {
457 fdt_setprop((void *)blob, node, "status", "disabled", 9);
458 printf("FDT: UFS was not detected, disabling UFS.\n");
459 }
460 }
461 }
462 }
463
464 node = fdt_path_offset(blob, "/sata@2a240000");
465 if (node >= 0) {
466 /*
467 * Set SATA FBSCP and PORTS_IMPL for kernel drivers
468 */
469 writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
470 writel(1, SATA0_BASE_ADDR + SATA_PI);
471 writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
472 writel(1, SATA1_BASE_ADDR + SATA_PI);
473 }
474
475 return 0;
476 }
477 #endif
478
479 /* @brief: Fix up the device tree of gmac0
480 *
481 * This function enables GMAC0 after verifying the license.
482 *
483 * @param blob Pointer to the device tree blob
484 * @return 0 on success
485 **/
486 #if defined(CONFIG_ROCKCHIP_VENDOR_PARTITION)
rk_board_fdt_fixup(const void * blob)487 int rk_board_fdt_fixup(const void *blob)
488 {
489 char licence_str[1024] = {0};
490 int ret, size, node;
491
492 size = vendor_storage_read(MULTI_MODULE_KEY_ID, licence_str, 1024);
493 if (size > 0) {
494 ret = trusty_verify_config_ip(licence_str);
495 if (!ret)
496 printf("gmac0 can be enabled safely\n");
497 else
498 return 0;
499
500 node = fdt_path_offset(blob, "/ethernet@2a220000");
501 if (node < 0) {
502 printf("Error: /ethernet@2a220000 cannot find node\n");
503 } else {
504 ret = fdt_setprop_string((void *)blob, node, "status", "okay");
505 if (ret < 0)
506 printf("Error: /ethernet@2a220000 cannot set status property\n");
507 }
508 }
509
510 return 0;
511 }
512 #endif
513