1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 #ifndef _CLOCK_GROUP_QCOM_H_ 6 #define _CLOCK_GROUP_QCOM_H_ 7 8 #define GCC_WPSS_AHB_CLK 0x9d154 9 #define GCC_WPSS_AHB_BDG_MST_CLK 0x9d158 10 #define GCC_WPSS_RSCP_CLK 0x9d16c 11 #define GCC_TURING_CFG_AHB_CLK 0x45028 12 #define GCC_CFG_NOC_LPASS_CLK 0x47020 13 14 #define TURING_CC_OFFSET 0x00800000 15 #define TURING_CC_SIZE 0x00023000 16 #define TURING_Q6SS_Q6_AXIM_CLK 0xb000 17 #define TURING_CENG_CLK 0x4030 18 #define TURING_NSPNOC_CLK 0x4040 19 #define TURING_Q6SS_AHBS_AON_CLK 0x10000 20 #define TURING_VAPSS_GDSCR 0x16000 21 #define TURING_VAPSS_CFG_GDSCR 0x16004 22 #define TURING_VAPSS_GDS_HW_CTRL 0x1600c 23 24 #define VAPSS_GDSCR_SW_COLLAPSE_MASK 0x1 25 #define VAPSS_GDSCR_PWR_ON_MASK 0x80000000 26 #define VAPSS_GDSCR_RETAIN_FF_ENABLE_MASK 0x800 27 #define VAPSS_CFG_GDSCR_PWR_UP_COMPLETE_MASK 0x10000 28 #define VAPSS_GDS_HW_STATE_MASK 0x1E 29 #define VAPSS_GDS_HW_STATE_SHIFT 1 30 31 #define LPASS_GDSC_OFFSET 0x01000000 32 #define LPASS_GDSC_SIZE 0x0000c000 33 #define TOP_CC_LPI_Q6_AXIM_HS_CLK 0x4000 34 #define TOP_CC_AGGNOC_MPU_LS_CLK 0x7000 35 36 #endif /* _CLOCK_GROUP_QCOM_H_ */ 37 38