1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024, Telechips Inc. 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 #include <util.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 /* Peripherals */ 16 #define TCC_IO_BASE U(0x10000000) 17 #define TCC_IO_SIZE U(0x10000000) 18 19 /* GIC */ 20 #define GICD_BASE U(0x17301000) 21 #define GICC_BASE U(0x17302000) 22 23 /* Console */ 24 #define CONSOLE_UART_BASE U(0x16600000) 25 #define CONSOLE_UART_CLK_IN_HZ 24000000 26 #define CONSOLE_BAUDRATE 115200 27 28 /* OTP */ 29 #define OTP_CTRL_BASE U(0x19101000) 30 #define OTP_CMD_BASE U(0xE0004000) 31 32 /* TZC Cfg */ 33 #define TZC_BASE U(0xE8300000) 34 #define TZC_SIZE U(0x00100000) 35 #define TZC_OMC_BASE (TZC_BASE + U(0x80000)) 36 #define TZC_OMC_FILTERS U(4) 37 #define TZC_OMC_FILTER_OFFS U(0x10000) 38 #define TZC_OMC_INT_0 (U(231) + U(32)) 39 #define TZC_OMC_INT_1 (U(233) + U(32)) 40 #define TZC_OMC_INT_2 (U(235) + U(32)) 41 #define TZC_OMC_INT_3 (U(237) + U(32)) 42 #define TZC_TEEOS_REGION_NUM U(1) 43 44 /* DRAM Info */ 45 #define DRAM0_BASE U(0x20000000) 46 #define DRAM0_SIZE U(0xA0000000) /* 2.5 GiB */ 47 #define DRAM1_BASE U(0x1A0000000) 48 #define DRAM1_SIZE U(0x60000000) /* 1.5 GiB */ 49 50 #endif /*PLATFORM_CONFIG_H*/ 51