1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 #ifndef __PHYDMANTDIV_H__ 22 #define __PHYDMANTDIV_H__ 23 24 /*#define ANTDIV_VERSION "2.0" //2014.11.04*/ 25 /*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ 26 #define ANTDIV_VERSION "2.2" /*2015.01.16 Dino*/ 27 28 //1 ============================================================ 29 //1 Definition 30 //1 ============================================================ 31 32 #define ANTDIV_INIT 0xff 33 #define MAIN_ANT 1 //Ant A or Ant Main 34 #define AUX_ANT 2 //AntB or Ant Aux 35 #define MAX_ANT 3 // 3 for AP using 36 37 #define ANT1_2G 0 // = ANT2_5G 38 #define ANT2_2G 1 // = ANT1_5G 39 40 //Antenna Diversty Control Type 41 #define ODM_AUTO_ANT 0 42 #define ODM_FIX_MAIN_ANT 1 43 #define ODM_FIX_AUX_ANT 2 44 45 #define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) 46 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B) 47 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) 48 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) 49 50 #define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D) 51 52 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A) 53 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) 54 55 #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) 56 57 #define ODM_ANTDIV_2G BIT0 58 #define ODM_ANTDIV_5G BIT1 59 60 #define ANTDIV_ON 1 61 #define ANTDIV_OFF 0 62 63 #define FAT_ON 1 64 #define FAT_OFF 0 65 66 #define TX_BY_DESC 1 67 #define REG 0 68 69 #define RSSI_METHOD 0 70 #define EVM_METHOD 1 71 #define CRC32_METHOD 2 72 73 #define INIT_ANTDIV_TIMMER 0 74 #define CANCEL_ANTDIV_TIMMER 1 75 #define RELEASE_ANTDIV_TIMMER 2 76 77 #define CRC32_FAIL 1 78 #define CRC32_OK 0 79 80 #define Evm_RSSI_TH_High 25 81 #define Evm_RSSI_TH_Low 20 82 83 #define NORMAL_STATE_MIAN 1 84 #define NORMAL_STATE_AUX 2 85 #define TRAINING_STATE 3 86 87 #define FORCE_RSSI_DIFF 10 88 89 #define CSI_ON 1 90 #define CSI_OFF 0 91 92 #define DIVON_CSIOFF 1 93 #define DIVOFF_CSION 2 94 95 #define BDC_DIV_TRAIN_STATE 0 96 #define BDC_BFer_TRAIN_STATE 1 97 #define BDC_DECISION_STATE 2 98 #define BDC_BF_HOLD_STATE 3 99 #define BDC_DIV_HOLD_STATE 4 100 101 #define BDC_MODE_1 1 102 #define BDC_MODE_2 2 103 #define BDC_MODE_3 3 104 #define BDC_MODE_4 4 105 #define BDC_MODE_NULL 0xff 106 107 #define SWAW_STEP_PEAK 0 108 #define SWAW_STEP_DETERMINE 1 109 110 //1 ============================================================ 111 //1 structure 112 //1 ============================================================ 113 114 115 typedef struct _SW_Antenna_Switch_ 116 { 117 u1Byte Double_chk_flag; 118 u1Byte try_flag; 119 s4Byte PreRSSI; 120 u1Byte CurAntenna; 121 u1Byte PreAntenna; 122 u1Byte RSSI_Trying; 123 u1Byte TestMode; 124 u1Byte bTriggerAntennaSwitch; 125 u1Byte SelectAntennaMap; 126 u1Byte RSSI_target; 127 u1Byte reset_idx; 128 u2Byte Single_Ant_Counter; 129 u2Byte Dual_Ant_Counter; 130 u2Byte Aux_FailDetec_Counter; 131 u2Byte Retry_Counter; 132 133 // Before link Antenna Switch check 134 u1Byte SWAS_NoLink_State; 135 u4Byte SWAS_NoLink_BK_Reg860; 136 u4Byte SWAS_NoLink_BK_Reg92c; 137 u4Byte SWAS_NoLink_BK_Reg948; 138 BOOLEAN ANTA_ON; //To indicate Ant A is or not 139 BOOLEAN ANTB_ON; //To indicate Ant B is on or not 140 BOOLEAN Pre_Aux_FailDetec; 141 BOOLEAN RSSI_AntDect_bResult; 142 u1Byte Ant5G; 143 u1Byte Ant2G; 144 145 s4Byte RSSI_sum_A; 146 s4Byte RSSI_sum_B; 147 s4Byte RSSI_cnt_A; 148 s4Byte RSSI_cnt_B; 149 150 u8Byte lastTxOkCnt; 151 u8Byte lastRxOkCnt; 152 u8Byte TXByteCnt_A; 153 u8Byte TXByteCnt_B; 154 u8Byte RXByteCnt_A; 155 u8Byte RXByteCnt_B; 156 u1Byte TrafficLoad; 157 u1Byte Train_time; 158 u1Byte Train_time_flag; 159 RT_TIMER SwAntennaSwitchTimer; 160 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) 161 RT_TIMER SwAntennaSwitchTimer_8723B; 162 u4Byte PktCnt_SWAntDivByCtrlFrame; 163 BOOLEAN bSWAntDivByCtrlFrame; 164 #endif 165 166 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 167 #if USE_WORKITEM 168 RT_WORK_ITEM SwAntennaSwitchWorkitem; 169 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) 170 RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B; 171 #endif 172 #endif 173 #endif 174 /* CE Platform use 175 #ifdef CONFIG_SW_ANTENNA_DIVERSITY 176 _timer SwAntennaSwitchTimer; 177 u8Byte lastTxOkCnt; 178 u8Byte lastRxOkCnt; 179 u8Byte TXByteCnt_A; 180 u8Byte TXByteCnt_B; 181 u8Byte RXByteCnt_A; 182 u8Byte RXByteCnt_B; 183 u1Byte DoubleComfirm; 184 u1Byte TrafficLoad; 185 //SW Antenna Switch 186 187 188 #endif 189 */ 190 #ifdef CONFIG_HW_ANTENNA_DIVERSITY 191 //Hybrid Antenna Diversity 192 u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 193 u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 194 u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 195 u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 196 u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 197 u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 198 u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM]; 199 u1Byte TargetSTA; 200 u1Byte antsel; 201 u1Byte RxIdleAnt; 202 203 #endif 204 205 }SWAT_T, *pSWAT_T; 206 207 208 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 209 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) 210 typedef struct _BF_DIV_COEX_ 211 { 212 BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; 213 BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; 214 u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; 215 u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; 216 217 u1Byte BDCcoexType_wBfer; 218 u1Byte num_Txbfee_Client; 219 u1Byte num_Txbfer_Client; 220 u1Byte BDC_Try_counter; 221 u1Byte BDC_Hold_counter; 222 u1Byte BDC_Mode; 223 u1Byte BDC_active_Mode; 224 u1Byte BDC_state; 225 u1Byte BDC_RxIdleUpdate_counter; 226 u1Byte num_Client; 227 u1Byte pre_num_Client; 228 u1Byte num_BfTar; 229 u1Byte num_DivTar; 230 231 BOOLEAN bAll_DivSta_Idle; 232 BOOLEAN bAll_BFSta_Idle; 233 BOOLEAN BDC_Try_flag; 234 BOOLEAN BF_pass; 235 BOOLEAN DIV_pass; 236 }BDC_T,*pBDC_T; 237 #endif 238 #endif 239 240 241 typedef struct _FAST_ANTENNA_TRAINNING_ 242 { 243 u1Byte Bssid[6]; 244 u1Byte antsel_rx_keep_0; 245 u1Byte antsel_rx_keep_1; 246 u1Byte antsel_rx_keep_2; 247 u1Byte antsel_rx_keep_3; 248 u4Byte antSumRSSI[7]; 249 u4Byte antRSSIcnt[7]; 250 u4Byte antAveRSSI[7]; 251 u1Byte FAT_State; 252 u4Byte TrainIdx; 253 u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 254 u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 255 u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 256 u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 257 u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 258 u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 259 u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 260 u1Byte RxIdleAnt; 261 u1Byte AntDiv_OnOff; 262 BOOLEAN bBecomeLinked; 263 u4Byte MinMaxRSSI; 264 u1Byte idx_AntDiv_counter_2G; 265 u1Byte idx_AntDiv_counter_5G; 266 u1Byte AntDiv_2G_5G; 267 u4Byte CCK_counter_main; 268 u4Byte CCK_counter_aux; 269 u4Byte OFDM_counter_main; 270 u4Byte OFDM_counter_aux; 271 272 #ifdef ODM_EVM_ENHANCE_ANTDIV 273 u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 274 u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 275 u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 276 u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 277 BOOLEAN EVM_method_enable; 278 u1Byte TargetAnt_EVM; 279 u1Byte TargetAnt_CRC32; 280 u1Byte TargetAnt_enhance; 281 u1Byte pre_TargetAnt_enhance; 282 u2Byte Main_MPDU_OK_cnt; 283 u2Byte Aux_MPDU_OK_cnt; 284 285 u4Byte CRC32_Ok_Cnt; 286 u4Byte CRC32_Fail_Cnt; 287 u4Byte MainCRC32_Ok_Cnt; 288 u4Byte AuxCRC32_Ok_Cnt; 289 u4Byte MainCRC32_Fail_Cnt; 290 u4Byte AuxCRC32_Fail_Cnt; 291 #endif 292 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 293 u4Byte CCK_CtrlFrame_Cnt_main; 294 u4Byte CCK_CtrlFrame_Cnt_aux; 295 u4Byte OFDM_CtrlFrame_Cnt_main; 296 u4Byte OFDM_CtrlFrame_Cnt_aux; 297 u4Byte MainAnt_CtrlFrame_Sum; 298 u4Byte AuxAnt_CtrlFrame_Sum; 299 u4Byte MainAnt_CtrlFrame_Cnt; 300 u4Byte AuxAnt_CtrlFrame_Cnt; 301 #endif 302 BOOLEAN fix_ant_bfee; 303 BOOLEAN enable_ctrl_frame_antdiv; 304 BOOLEAN use_ctrl_frame_antdiv; 305 }FAT_T,*pFAT_T; 306 307 308 //1 ============================================================ 309 //1 enumeration 310 //1 ============================================================ 311 312 313 314 typedef enum _FAT_STATE 315 { 316 FAT_NORMAL_STATE = 0, 317 FAT_TRAINING_STATE = 1, 318 }FAT_STATE_E, *PFAT_STATE_E; 319 320 321 typedef enum _ANT_DIV_TYPE 322 { 323 NO_ANTDIV = 0xFF, 324 CG_TRX_HW_ANTDIV = 0x01, 325 CGCS_RX_HW_ANTDIV = 0x02, 326 FIXED_HW_ANTDIV = 0x03, 327 CG_TRX_SMART_ANTDIV = 0x04, 328 CGCS_RX_SW_ANTDIV = 0x05, 329 S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1 330 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; 331 332 333 //1 ============================================================ 334 //1 function prototype 335 //1 ============================================================ 336 337 338 VOID 339 ODM_StopAntennaSwitchDm( 340 IN PVOID pDM_VOID 341 ); 342 VOID 343 ODM_SetAntConfig( 344 IN PVOID pDM_VOID, 345 IN u1Byte antSetting // 0=A, 1=B, 2=C, .... 346 ); 347 348 349 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink 350 VOID ODM_SwAntDivRestAfterLink( 351 IN PVOID pDM_VOID 352 ); 353 354 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) 355 356 VOID 357 ODM_UpdateRxIdleAnt( 358 IN PVOID pDM_VOID, 359 IN u1Byte Ant 360 ); 361 362 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) 363 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 364 VOID 365 ODM_SW_AntDiv_Callback( 366 IN PRT_TIMER pTimer 367 ); 368 369 VOID 370 ODM_SW_AntDiv_WorkitemCallback( 371 IN PVOID pContext 372 ); 373 374 375 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 376 377 VOID 378 ODM_SW_AntDiv_WorkitemCallback( 379 IN PVOID pContext 380 ); 381 382 VOID 383 ODM_SW_AntDiv_Callback( 384 void *FunctionContext 385 ); 386 387 #endif 388 389 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 390 VOID 391 odm_S0S1_SwAntDivByCtrlFrame( 392 IN PVOID pDM_VOID, 393 IN u1Byte Step 394 ); 395 396 VOID 397 odm_AntselStatisticsOfCtrlFrame( 398 IN PVOID pDM_VOID, 399 IN u1Byte antsel_tr_mux, 400 IN u4Byte RxPWDBAll 401 ); 402 403 VOID 404 odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( 405 IN PVOID pDM_VOID, 406 IN PVOID p_phy_info_void, 407 IN PVOID p_pkt_info_void 408 ); 409 410 /* 411 VOID 412 odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( 413 IN PVOID pDM_VOID, 414 IN PVOID p_phy_info_void, 415 IN PVOID p_pkt_info_void 416 ); 417 */ 418 419 #endif 420 #endif 421 422 #ifdef ODM_EVM_ENHANCE_ANTDIV 423 VOID 424 odm_EVM_FastAntTrainingCallback( 425 IN PVOID pDM_VOID 426 ); 427 #endif 428 429 VOID 430 odm_HW_AntDiv( 431 IN PVOID pDM_VOID 432 ); 433 434 #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) 435 VOID 436 odm_FastAntTraining( 437 IN PVOID pDM_VOID 438 ); 439 440 VOID 441 odm_FastAntTrainingCallback( 442 IN PVOID pDM_VOID 443 ); 444 445 VOID 446 odm_FastAntTrainingWorkItemCallback( 447 IN PVOID pDM_VOID 448 ); 449 #endif 450 451 452 VOID 453 ODM_AntDivInit( 454 IN PVOID pDM_VOID 455 ); 456 457 VOID 458 ODM_AntDiv( 459 IN PVOID pDM_VOID 460 ); 461 462 VOID 463 odm_AntselStatistics( 464 IN PVOID pDM_VOID, 465 IN u1Byte antsel_tr_mux, 466 IN u4Byte MacId, 467 IN u4Byte utility, 468 IN u1Byte method 469 ); 470 /* 471 VOID 472 ODM_Process_RSSIForAntDiv( 473 IN OUT PVOID pDM_VOID, 474 IN PVOID p_phy_info_void, 475 IN PVOID p_pkt_info_void 476 ); 477 */ 478 479 480 VOID 481 ODM_Process_RSSIForAntDiv( 482 IN OUT PVOID pDM_VOID, 483 IN PVOID p_phy_info_void, 484 IN PVOID p_pkt_info_void 485 ); 486 487 488 489 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 490 VOID 491 ODM_SetTxAntByTxInfo( 492 IN PVOID pDM_VOID, 493 IN pu1Byte pDesc, 494 IN u1Byte macId 495 ); 496 497 #elif(DM_ODM_SUPPORT_TYPE == ODM_AP) 498 499 VOID 500 ODM_SetTxAntByTxInfo( 501 struct rtl8192cd_priv *priv, 502 struct tx_desc *pdesc, 503 unsigned short aid 504 ); 505 506 #endif 507 508 509 VOID 510 ODM_AntDiv_Config( 511 IN PVOID pDM_VOID 512 ); 513 514 515 VOID 516 ODM_UpdateRxIdleAnt_8723B( 517 IN PVOID pDM_VOID, 518 IN u1Byte Ant, 519 IN u4Byte DefaultAnt, 520 IN u4Byte OptionalAnt 521 ); 522 523 VOID 524 ODM_AntDivTimers( 525 IN PVOID pDM_VOID, 526 IN u1Byte state 527 ); 528 529 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) 530 531 VOID 532 ODM_AntDivReset( 533 IN PVOID pDM_VOID 534 ); 535 536 VOID 537 odm_AntennaDiversityInit( 538 IN PVOID pDM_VOID 539 ); 540 541 VOID 542 odm_AntennaDiversity( 543 IN PVOID pDM_VOID 544 ); 545 546 547 #endif //#ifndef __ODMANTDIV_H__ 548