1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Guochun Huang <hero.huang@rock-chips.com> 6 */ 7 #ifndef RK628_COMBTXPHY_H 8 #define RK628_COMBTXPHY_H 9 #include "rk628.h" 10 11 #define COMBTXPHY_BASE 0x90000 12 #define REG(x) ((x) + COMBTXPHY_BASE) 13 14 #define COMBTXPHY_CON0 REG(0x0000) 15 #define SW_TX_IDLE_MASK GENMASK(29, 20) 16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20) 17 #define SW_TX_PD_MASK GENMASK(17, 8) 18 #define SW_TX_PD(x) UPDATE(x, 17, 8) 19 #define SW_BUS_WIDTH_MASK GENMASK(6, 5) 20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5) 21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5) 22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5) 23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5) 24 #define SW_PD_PLL_MASK BIT(4) 25 #define SW_PD_PLL BIT(4) 26 #define SW_GVI_LVDS_EN_MASK BIT(3) 27 #define SW_GVI_LVDS_EN BIT(3) 28 #define SW_MIPI_DSI_EN_MASK BIT(2) 29 #define SW_MIPI_DSI_EN BIT(2) 30 #define SW_MODULEB_EN_MASK BIT(1) 31 #define SW_MODULEB_EN BIT(1) 32 #define SW_MODULEA_EN_MASK BIT(0) 33 #define SW_MODULEA_EN BIT(0) 34 #define COMBTXPHY_CON1 REG(0x0004) 35 #define COMBTXPHY_CON2 REG(0x0008) 36 #define COMBTXPHY_CON3 REG(0x000c) 37 #define COMBTXPHY_CON4 REG(0x0010) 38 #define COMBTXPHY_CON5 REG(0x0014) 39 #define SW_RATE(x) UPDATE(x, 26, 24) 40 #define SW_REF_DIV(x) UPDATE(x, 20, 16) 41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10) 42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0) 43 #define COMBTXPHY_CON6 REG(0x0018) 44 #define SW_PLL_CTL_CON0_MASK GENMASK(2, 0) 45 #define SW_PLL_CTL_CON0(x) UPDATE(x, 2, 0) 46 #define COMBTXPHY_CON7 REG(0x001c) 47 #define SW_TX_RTERM_MASK GENMASK(22, 20) 48 #define SW_TX_RTERM(x) UPDATE(x, 22, 20) 49 #define SW_TX_MODE_MASK GENMASK(17, 16) 50 #define SW_TX_MODE(x) UPDATE(x, 17, 16) 51 #define SW_TX_CTL_CON5_MASK BIT(10) 52 #define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10) 53 #define SW_TX_CTL_CON4_MASK GENMASK(9, 8) 54 #define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8) 55 #define BYPASS_095V_LDO_MASK BIT(3) 56 #define BYPASS_095V_LDO(x) UPDATE(x, 3, 3) 57 #define TX_COM_VOLT_ADJ_MASK GENMASK(2, 0) 58 #define TX_COM_VOLT_ADJ(x) UPDATE(x, 2, 0) 59 60 #define COMBTXPHY_CON8 REG(0x0020) 61 #define SW_SSC_DEPTH_MASK GENMASK(7, 4) 62 #define SW_SSC_DEPTH(x) UPDATE(x, 7, 4) 63 #define SW_SSC_EN_MASK BIT(0) 64 #define SW_SSC_EN(x) UPDATE(x, 0, 0) 65 #define COMBTXPHY_CON9 REG(0x0024) 66 #define SW_DSI_FSET_EN_MASK BIT(29) 67 #define SW_DSI_FSET_EN BIT(29) 68 #define SW_DSI_RCAL_EN_MASK BIT(28) 69 #define SW_DSI_RCAL_EN(x) UPDATE(x, 28, 28) 70 #define SW_DSI_RCAL_TRIM_MASK GENMASK(27, 24) 71 #define SW_DSI_RCAL_TRIM(x) UPDATE(x, 27, 24) 72 #define SW_DSI_LPTX_SR_TRIM_MASK GENMASK(6, 4) 73 #define SW_DSI_LPTX_SR_TRIM(x) UPDATE(x, 6, 4) 74 #define SW_DSI_HSTX_AMP_TRIM_MASK GENMASK(2, 0) 75 #define SW_DSI_HSTX_AMP_TRIM(x) UPDATE(x, 2, 0) 76 #define COMBTXPHY_CON10 REG(0x0028) 77 #define TX9_CKDRV_EN BIT(9) 78 #define TX8_CKDRV_EN BIT(8) 79 #define TX7_CKDRV_EN BIT(7) 80 #define TX6_CKDRV_EN BIT(6) 81 #define TX5_CKDRV_EN BIT(5) 82 #define TX4_CKDRV_EN BIT(4) 83 #define TX3_CKDRV_EN BIT(3) 84 #define TX2_CKDRV_EN BIT(2) 85 #define TX1_CKDRV_EN BIT(1) 86 #define TX0_CKDRV_EN BIT(0) 87 88 void rk628_combtxphy_set_gvi_division_mode(struct rk628 *rk628, bool division); 89 void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode); 90 void rk628_combtxphy_set_bus_width(struct rk628 *rk628, uint32_t bus_width); 91 uint32_t rk628_combtxphy_get_bus_width(struct rk628 *rk628); 92 void rk628_combtxphy_power_on(struct rk628 *rk628); 93 void rk628_combtxphy_power_off(struct rk628 *rk628); 94 #endif 95