1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * (C) Copyright 2024 Rockchip Electronics Co., Ltd
4 */
5
6 #ifndef _RK628_H_
7 #define _RK628_H_
8
9 #include <asm-generic/gpio.h>
10 #include <errno.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <i2c.h>
14 #include <dm/uclass.h>
15 #include <dm/uclass-id.h>
16 #include <power/regulator.h>
17 #include <linux/bitfield.h>
18 #include <linux/math64.h>
19 #include <drm_modes.h>
20
21 #include "../rockchip_phy.h"
22
23 #define DRIVER_VERSION "0.1.0"
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
25 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | \
26 (GENMASK((h), (l)) << 16))
27
28 #define GRF_SYSTEM_CON0 0x0000
29 #define SW_VSYNC_POL_MASK BIT(26)
30 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
31 #define SW_HSYNC_POL_MASK BIT(25)
32 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
33 #define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22)
34 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
35 #define SW_EDID_MODE_MASK BIT(21)
36 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
37 #define SW_I2S_DATA_OEN_MASK BIT(10)
38 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
39 #define SW_BT_DATA_OEN_MASK BIT(9)
40 #define SW_BT_DATA_OEN BIT(9)
41 #define SW_EFUSE_HDCP_EN_MASK BIT(8)
42 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
43 #define SW_OUTPUT_MODE_MASK GENMASK(5, 3)
44 #define SW_OUTPUT_MODE(x) UPDATE(x, 5, 3)
45 /* compatible with rk628f */
46 #define SW_OUTPUT_RGB_MODE_MASK GENMASK(7, 6)
47 #define SW_OUTPUT_RGB_MODE(x) UPDATE(x, 7, 6)
48 #define SW_HDMITX_EN_MASK BIT(5)
49 #define SW_HDMITX_EN(x) UPDATE(x, 5, 5)
50 #define SW_OUTPUT_COMBTX_MODE_MASK GENMASK(4, 3)
51 #define SW_OUTPUT_COMBTX_MODE(x) UPDATE(x, 4, 3)
52
53 #define SW_INPUT_MODE_MASK GENMASK(2, 0)
54 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
55 #define GRF_SYSTEM_CON1 0x0004
56 #define GRF_SYSTEM_CON2 0x0008
57 #define GRF_SYSTEM_CON3 0x000c
58 #define GRF_GPIO_RX_CEC_SEL_MASK BIT(7)
59 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
60 #define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6)
61 #define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6)
62 #define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5)
63 #define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
64 #define GRF_DPHY_CH1_EN_MASK BIT(1)
65 #define GRF_DPHY_CH1_EN(x) UPDATE(x, 1, 1)
66 #define GRF_AS_DSIPHY_MASK BIT(0)
67 #define GRF_AS_DSIPHY(x) UPDATE(x, 0, 0)
68 #define GRF_SCALER_CON0 0x0010
69 #define SCL_8_PIXEL_ALIGN(x) HIWORD_UPDATE(x, 12, 12)
70 #define SCL_COLOR_VER_EN(x) HIWORD_UPDATE(x, 10, 10)
71 #define SCL_COLOR_BAR_EN(x) HIWORD_UPDATE(x, 9, 9)
72 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
73 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
74 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
75 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
76 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
77 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
78 #define GRF_SCALER_CON1 0x0014
79 #define SCL_V_FACTOR(x) UPDATE(x, 31, 16)
80 #define SCL_H_FACTOR(x) UPDATE(x, 15, 0)
81 #define GRF_SCALER_CON2 0x0018
82 #define DSP_FRAME_VST(x) UPDATE(x, 28, 16)
83 #define DSP_FRAME_HST(x) UPDATE(x, 12, 0)
84 #define GRF_SCALER_CON3 0x001c
85 #define DSP_HS_END(x) UPDATE(x, 23, 16)
86 #define DSP_HTOTAL(x) UPDATE(x, 12, 0)
87 #define GRF_SCALER_CON4 0x0020
88 #define DSP_HACT_ST(x) UPDATE(x, 28, 16)
89 #define DSP_HACT_END(x) UPDATE(x, 12, 0)
90 #define GRF_SCALER_CON5 0x0024
91 #define DSP_VS_END(x) UPDATE(x, 23, 16)
92 #define DSP_VTOTAL(x) UPDATE(x, 12, 0)
93 #define GRF_SCALER_CON6 0x0028
94 #define DSP_VACT_ST(x) UPDATE(x, 28, 16)
95 #define DSP_VACT_END(x) UPDATE(x, 12, 0)
96 #define GRF_SCALER_CON7 0x002c
97 #define DSP_HBOR_ST(x) UPDATE(x, 28, 16)
98 #define DSP_HBOR_END(x) UPDATE(x, 12, 0)
99 #define GRF_SCALER_CON8 0x0030
100 #define DSP_VBOR_ST(x) UPDATE(x, 28, 16)
101 #define DSP_VBOR_END(x) UPDATE(x, 12, 0)
102 #define GRF_POST_PROC_CON 0x0034
103 #define SW_HDMITX_VSYNC_POL BIT(17)
104 #define SW_HDMITX_HSYNC_POL BIT(16)
105 #define SW_DCLK_OUT_INV_EN BIT(9)
106 #define SW_DCLK_IN_INV_EN BIT(8)
107 #define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5)
108 #define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5)
109 #define SW_HDMITX_VCLK_PLLREF_SEL_MASK BIT(4)
110 #define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4)
111 #define SW_HDMITX_DCLK_INV_EN BIT(3)
112 #define SW_SPLIT_MODE(x) UPDATE(x, 1, 1)
113 #define SW_SPLIT_EN BIT(0)
114 #define GRF_CSC_CTRL_CON 0x0038
115 #define SW_Y2R_MODE(x) HIWORD_UPDATE(x, 13, 12)
116 #define SW_FROM_CSC_MATRIX_EN(x) HIWORD_UPDATE(x, 11, 11)
117 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
118 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
119 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0)
120 #define GRF_LVDS_TX_CON 0x003c
121 #define SW_LVDS_CON_DUAL_SEL(x) HIWORD_UPDATE(x, 12, 12)
122 #define SW_LVDS_CON_DEN_POLARITY(x) HIWORD_UPDATE(x, 11, 11)
123 #define SW_LVDS_CON_HS_POLARITY(x) HIWORD_UPDATE(x, 10, 10)
124 #define SW_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 9, 9)
125 #define SW_LVDS_STARTPHASE(x) HIWORD_UPDATE(x, 8, 8)
126 #define SW_LVDS_CON_STARTSEL(x) HIWORD_UPDATE(x, 7, 7)
127 #define SW_LVDS_CON_CHASEL(x) HIWORD_UPDATE(x, 6, 6)
128 #define SW_LVDS_TIE_VSYNC_VALUE(x) HIWORD_UPDATE(x, 5, 5)
129 #define SW_LVDS_TIE_HSYNC_VALUE(x) HIWORD_UPDATE(x, 4, 4)
130 #define SW_LVDS_TIE_DEN_ONLY(x) HIWORD_UPDATE(x, 3, 3)
131 #define SW_LVDS_CON_MSBSEL(x) HIWORD_UPDATE(x, 2, 2)
132 #define SW_LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0)
133 #define GRF_RGB_DEC_CON0 0x0040
134 #define SW_HRES_MASK GENMASK(28, 16)
135 #define SW_HRES(x) UPDATE(x, 28, 16)
136 #define DUAL_DATA_SWAP BIT(6)
137 #define DEC_DUALEDGE_EN BIT(5)
138 #define SW_PROGRESS_EN BIT(4)
139 #define SW_BT1120_YC_SWAP BIT(3)
140 #define SW_BT1120_UV_SWAP BIT(2)
141 #define SW_CAP_EN_ASYNC BIT(1)
142 #define SW_CAP_EN_PSYNC BIT(0)
143 #define GRF_RGB_DEC_CON1 0x0044
144 #define SW_SET_X_MASK GENMASK(28, 16)
145 #define SW_SET_X(x) HIWORD_UPDATE(x, 28, 16)
146 #define SW_SET_Y_MASK GENMASK(28, 16)
147 #define SW_SET_Y(x) HIWORD_UPDATE(x, 28, 16)
148 #define GRF_RGB_DEC_CON2 0x0048
149 #define GRF_RGB_ENC_CON 0x004c
150 #define BT1120_UV_SWAP(x) HIWORD_UPDATE(x, 5, 5)
151 #define ENC_DUALEDGE_EN(x) HIWORD_UPDATE(x, 3, 3)
152 #define GRF_MIPI_LANE_DELAY_CON0 0x0050
153 #define GRF_MIPI_LANE_DELAY_CON1 0x0054
154 #define GRF_BT1120_DCLK_DELAY_CON0 0x0058
155 #define GRF_BT1120_DCLK_DELAY_CON1 0x005c
156 #define GRF_MIPI_TX0_CON 0x0060
157 #define DPIUPDATECFG BIT(26)
158 #define DPICOLORM BIT(25)
159 #define DPISHUTDN BIT(24)
160 #define CSI_PHYRSTZ BIT(21)
161 #define CSI_PHYSHUTDOWNZ BIT(20)
162 #define FORCETXSTOPMODE_MASK GENMASK(19, 16)
163 #define FORCETXSTOPMODE(x) UPDATE(x, 19, 16)
164 #define FORCERXMODE_MASK GENMASK(15, 12)
165 #define FORCERXMODE(x) UPDATE(x, 15, 12)
166 #define PHY_TESTCLR BIT(10)
167 #define PHY_TESTCLK BIT(9)
168 #define PHY_TESTEN BIT(8)
169 #define PHY_TESTDIN_MASK GENMASK(7, 0)
170 #define PHY_TESTDIN(x) UPDATE(x, 7, 0)
171 #define GRF_DPHY0_STATUS 0x0064
172 #define DPHY_PHYLOCK BIT(24)
173 #define PHY_TESTDOUT_SHIFT 8
174 #define GRF_MIPI_TX1_CON 0x0068
175 #define GRF_DPHY1_STATUS 0x006c
176 #define GRF_GPIO0AB_SEL_CON 0x0070
177 #define GRF_GPIO1AB_SEL_CON 0x0074
178 #define GRF_GPIO2AB_SEL_CON 0x0078
179 #define GRF_GPIO2C_SEL_CON 0x007c
180 #define GRF_GPIO3AB_SEL_CON 0x0080
181 #define GRF_GPIO2A_SMT 0x0090
182 #define GRF_GPIO2B_SMT 0x0094
183 #define GRF_GPIO2C_SMT 0x0098
184 #define GRF_GPIO3AB_SMT 0x009c
185 #define GRF_GPIO0A_P_CON 0x00a0
186 #define GRF_GPIO1A_P_CON 0x00a4
187 #define GRF_GPIO2A_P_CON 0x00a8
188 #define GRF_GPIO2B_P_CON 0x00ac
189 #define GRF_GPIO2C_P_CON 0x00b0
190 #define GRF_GPIO3A_P_CON 0x00b4
191 #define GRF_GPIO3B_P_CON 0x00b8
192 #define GRF_GPIO0B_D_CON 0x00c0
193 #define GRF_GPIO1B_D_CON 0x00c4
194 #define GRF_GPIO2A_D0_CON 0x00c8
195 #define GRF_GPIO2A_D1_CON 0x00cc
196 #define GRF_GPIO2B_D0_CON 0x00d0
197 #define GRF_GPIO2B_D1_CON 0x00d4
198 #define GRF_GPIO2C_D0_CON 0x00d8
199 #define GRF_GPIO2C_D1_CON 0x00dc
200 #define GRF_GPIO3A_D0_CON 0x00e0
201 #define GRF_GPIO3A_D1_CON 0x00e4
202 #define GRF_GPIO3B_D_CON 0x00e8
203 #define GRF_GPIO_SR_CON 0x00ec
204 #define GRF_SW_HDMIRXPHY_CRTL 0x00f4
205 #define GRF_INTR0_EN 0x0100
206 #define RK628F_HDMIRX_IRQ_EN(x) HIWORD_UPDATE(x, 9, 9)
207 #define RK628D_HDMIRX_IRQ_EN(x) HIWORD_UPDATE(x, 8, 8)
208 #define GRF_INTR0_CLR_EN 0x0104
209 #define GRF_INTR0_STATUS 0x0108
210 #define GRF_INTR0_RAW_STATUS 0x010c
211 #define GRF_INTR1_EN 0x0110
212 #define GRF_INTR1_CLR_EN 0x0114
213 #define GRF_INTR1_STATUS 0x0118
214 #define GRF_INTR1_RAW_STATUS 0x011c
215 #define GRF_SYSTEM_STATUS0 0x0120
216 /* 0: i2c mode and mcu mode; 1: i2c mode only */
217 #define I2C_ONLY_FLAG BIT(6)
218 #define GRF_SYSTEM_STATUS3 0x012c
219 #define DECODER_1120_LAST_LINE_NUM_MASK GENMASK(12, 0)
220 #define GRF_SYSTEM_STATUS4 0x0130
221 #define DECODER_1120_LAST_PIX_NUM_MASK GENMASK(12, 0)
222 #define GRF_OS_REG0 0x0140
223 #define GRF_OS_REG1 0x0144
224 #define GRF_OS_REG2 0x0148
225 #define GRF_OS_REG3 0x014c
226 #define GRF_RGB_RX_DBG_MEAS0 0x0170
227 #define RGB_RX_EVAL_TIME_MASK GENMASK(27, 16)
228 #define RGB_RX_MODET_EN BIT(1)
229 #define RGB_RX_DCLK_EN BIT(0)
230 #define GRF_RGB_RX_DBG_MEAS2 0x0178
231 #define RGB_RX_CLKRATE_MASK GENMASK(15, 0)
232 #define GRF_RGB_RX_DBG_MEAS3 0x017c
233 #define RGB_RX_CNT_EN_MASK BIT(0)
234 #define RGB_RX_CNT_EN(x) UPDATE(x, 0, 0)
235 #define GRF_RGB_RX_DBG_MEAS4 0x0180
236 #define GRF_BT1120_TIMING_CTRL0 0x0190
237 #define BT1120_DSP_HS_END(x) UPDATE(x, 28, 16)
238 #define BT1120_DSP_HTOTAL(x) UPDATE(x, 12, 0)
239 #define GRF_BT1120_TIMING_CTRL1 0x0194
240 #define BT1120_DSP_HACT_ST(x) UPDATE(x, 28, 16)
241 #define GRF_BT1120_TIMING_CTRL2 0x0198
242 #define BT1120_DSP_VS_END(x) UPDATE(x, 28, 16)
243 #define BT1120_DSP_VTOTAL(x) UPDATE(x, 12, 0)
244 #define GRF_BT1120_TIMING_CTRL3 0x019c
245 #define BT1120_DSP_VACT_ST(x) UPDATE(x, 28, 16)
246 #define GRF_CSC_MATRIX_COE01_COE00 0x01a0
247 #define GRF_CSC_MATRIX_COE10_COE02 0x01a4
248 #define GRF_CSC_MATRIX_COE12_COE11 0x01a8
249 #define GRF_CSC_MATRIX_COE21_COE20 0x01ac
250 #define GRF_CSC_MATRIX_COE22 0x01b0
251 #define GRF_CSC_MATRIX_OFFSET0 0x01b4
252 #define GRF_CSC_MATRIX_OFFSET1 0x01b8
253 #define GRF_CSC_MATRIX_OFFSET2 0x01bc
254 #define GRF_SOC_VERSION 0x0200
255 #define GRF_OBS_REG 0X0300
256 #define GRF_MAX_REGISTER GRF_OBS_REG
257
258 #define RK628D_VERSION 0x20200326
259 #define RK628F_VERSION 0x20230321
260
261 enum {
262 COMBTXPHY_MODULEA_EN = BIT(0),
263 COMBTXPHY_MODULEB_EN = BIT(1),
264 };
265
266 enum {
267 RK628_DEV_GRF,
268 RK628_DEV_COMBRXPHY,
269 RK628_DEV_HDMIRX = 3,
270 RK628_DEV_CSI,
271 RK628_DEV_DSI0,
272 RK628_DEV_DSI1,
273 RK628_DEV_HDMITX,
274 RK628_DEV_GVI,
275 RK628_DEV_COMBTXPHY,
276 RK628_DEV_ADAPTER,
277 RK628_DEV_EFUSE,
278 RK628_DEV_CRU,
279 RK628_DEV_GPIO0,
280 RK628_DEV_GPIO1,
281 RK628_DEV_GPIO2,
282 RK628_DEV_GPIO3,
283 RK628_DEV_MAX,
284 };
285
286 enum rk628_input_mode {
287 INPUT_MODE_HDMI,
288 INPUT_MODE_BT1120 = 2,
289 INPUT_MODE_RGB,
290 INPUT_MODE_YUV,
291 };
292
293
294 enum rk628_output_mode {
295 OUTPUT_MODE_GVI = 1,
296 OUTPUT_MODE_LVDS,
297 OUTPUT_MODE_HDMI,
298 OUTPUT_MODE_CSI,
299 OUTPUT_MODE_DSI,
300 OUTPUT_MODE_BT1120 = 8,
301 OUTPUT_MODE_RGB = 16,
302 OUTPUT_MODE_YUV = 24,
303 };
304
305 enum rk628_phy_mode {
306 RK628_PHY_MODE_INVALID,
307 RK628_PHY_MODE_VIDEO_MIPI,
308 RK628_PHY_MODE_VIDEO_LVDS,
309 RK628_PHY_MODE_VIDEO_GVI,
310 };
311
312 enum lvds_format {
313 LVDS_FORMAT_VESA_24BIT,
314 LVDS_FORMAT_JEIDA_24BIT,
315 LVDS_FORMAT_JEIDA_18BIT,
316 LVDS_FORMAT_VESA_18BIT,
317 };
318
319 enum lvds_link_type {
320 LVDS_SINGLE_LINK,
321 LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
322 LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
323 LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
324 LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
325 };
326
327 enum gvi_color_depth {
328 COLOR_DEPTH_RGB_YUV444_18BIT,
329 COLOR_DEPTH_RGB_YUV444_24BIT,
330 COLOR_DEPTH_RGB_YUV444_30BIT,
331 COLOR_DEPTH_YUV422_16BIT = 8,
332 COLOR_DEPTH_YUV422_20BIT,
333 };
334
335 enum dsi_mode_flags {
336 RK628_MIPI_DSI_MODE_VIDEO = 1,
337 RK628_MIPI_DSI_MODE_VIDEO_BURST = 2,
338 RK628_MIPI_DSI_MODE_VIDEO_SYNC_PULSE = 4,
339 RK628_MIPI_DSI_MODE_VIDEO_HFP = 8,
340 RK628_MIPI_DSI_MODE_VIDEO_HBP = 16,
341 RK628_MIPI_DSI_MODE_EOT_PACKET = 32,
342 RK628_MIPI_DSI_CLOCK_NON_CONTINUOUS = 64,
343 RK628_MIPI_DSI_MODE_LPM = 128,
344 };
345
346 enum dsi_bus_format {
347 RK628_MIPI_DSI_FMT_RGB888,
348 RK628_MIPI_DSI_FMT_RGB666,
349 RK628_MIPI_DSI_FMT_RGB666_PACKED,
350 RK628_MIPI_DSI_FMT_RGB565,
351 };
352
353 enum gvi_bus_format {
354 GVI_MEDIA_BUS_FMT_RGB666_1X18 = 9,
355 GVI_MEDIA_BUS_FMT_RGB888_1X24 = 10,
356 GVI_MEDIA_BUS_FMT_YUYV10_1X20 = 13,
357 GVI_MEDIA_BUS_FMT_YUYV8_1X16 = 17,
358 GVI_MEDIA_BUS_FMT_RGB101010_1X30 = 24,
359 };
360
361 enum bus_format {
362 BUS_FMT_RGB = 0,
363 BUS_FMT_YUV422 = 1,
364 BUS_FMT_YUV444 = 2,
365 BUS_FMT_YUV420 = 3,
366 BUS_FMT_UNKNOWN,
367 };
368
369 enum rk628_mode_sync_pol {
370 MODE_FLAG_NSYNC,
371 MODE_FLAG_PSYNC,
372 };
373
374 struct rk628_videomode {
375 u32 pixelclock; /* pixelclock in Hz */
376
377 u32 hactive;
378 u32 hfront_porch;
379 u32 hback_porch;
380 u32 hsync_len;
381
382 u32 vactive;
383 u32 vfront_porch;
384 u32 vback_porch;
385 u32 vsync_len;
386
387 unsigned int flags; /* display flags */
388 };
389
390 struct rk628_display_mode {
391 int clock; /* in kHz */
392 int hdisplay;
393 int hsync_start;
394 int hsync_end;
395 int htotal;
396 int vdisplay;
397 int vsync_start;
398 int vsync_end;
399 int vtotal;
400 unsigned int flags;
401 };
402
403 struct cmd_ctrl_hdr {
404 u8 dtype; /* data type */
405 u8 wait; /* ms */
406 u8 dlen; /* payload len */
407 } __packed;
408
409 struct cmd_desc {
410 struct cmd_ctrl_hdr dchdr;
411 u8 *payload;
412 };
413
414 struct panel_cmds {
415 u8 *buf;
416 unsigned int blen;
417 struct cmd_desc *cmds;
418 int cmd_cnt;
419 };
420
421 struct rk628_panel_simple {
422 struct udevice *backlight;
423
424 struct udevice *supply;
425 struct gpio_desc enable_gpio;
426 struct gpio_desc reset_gpio;
427 struct panel_cmds *on_cmds;
428 struct panel_cmds *off_cmds;
429
430 struct {
431 unsigned int prepare;
432 unsigned int enable;
433 unsigned int disable;
434 unsigned int unprepare;
435 unsigned int reset;
436 unsigned int init;
437 } delay;
438 };
439
440 struct rk628_dsi {
441 int bpp; /* 24/18/16*/
442 enum dsi_bus_format bus_format;
443 enum dsi_mode_flags mode_flags;
444 bool slave;
445 bool master;
446 uint8_t channel;
447 uint8_t lanes;
448 uint8_t id; /* 0:dsi0 1:dsi1 */
449 struct rk628 *rk628;
450 unsigned int lane_mbps; /* per lane */
451 };
452
453 struct rk628_lvds {
454 enum lvds_format format;
455 enum lvds_link_type link_type;
456 };
457
458 struct rk628_gvi {
459 enum gvi_bus_format bus_format;
460 enum gvi_color_depth color_depth;
461 int retry_times;
462 uint8_t lanes;
463 bool division_mode;
464 bool frm_rst;
465 u8 byte_mode;
466 };
467
468 struct rk628_combtxphy {
469 enum rk628_phy_mode mode;
470 unsigned int flags;
471 u8 ref_div;
472 u8 fb_div;
473 u16 frac_div;
474 u8 rate_div;
475 u32 bus_width;
476 bool division_mode;
477 };
478
479 struct rk628_rgb {
480 struct udevice *vccio_rgb;
481 bool bt1120_dual_edge;
482 bool bt1120_yc_swap;
483 bool bt1120_uv_swap;
484 };
485
486 struct rk628_hdmi_mode {
487 u32 hdisplay;
488 u32 hstart;
489 u32 hend;
490 u32 htotal;
491 u32 vdisplay;
492 u32 vstart;
493 u32 vend;
494 u32 vtotal;
495 u32 clock;
496 unsigned int flags;
497 };
498
499 struct rk628_hdmirx {
500 struct udevice *dev;
501 struct rk628 *parent;
502 struct rk628_hdmi_mode mode;
503 bool src_mode_4K_yuv420;
504 bool src_depth_10bit;
505 bool phy_lock;
506 bool is_hdmi2;
507 u32 input_format;
508 };
509
510 struct rk628 {
511 struct udevice *dev;
512 struct udevice *power_supply;
513 struct gpio_desc reset_gpio;
514 struct gpio_desc enable_gpio;
515 struct rk628_panel_simple *panel;
516 bool display_enabled;
517 u32 input_mode;
518 u32 output_mode;
519 struct drm_display_mode src_mode;
520 struct drm_display_mode dst_mode;
521 enum bus_format input_fmt;
522 enum bus_format output_fmt;
523 struct rk628_hdmirx hdmirx;
524 struct rk628_dsi dsi0;
525 struct rk628_dsi dsi1;
526 struct rk628_lvds lvds;
527 struct rk628_gvi gvi;
528 struct rk628_combtxphy combtxphy;
529 int sync_pol;
530 u32 version;
531 struct rk628_rgb rgb;
532 };
533
rk628_input_is_hdmi(struct rk628 * rk628)534 static inline bool rk628_input_is_hdmi(struct rk628 *rk628)
535 {
536 return rk628->input_mode & BIT(INPUT_MODE_HDMI);
537 }
538
rk628_input_is_rgb(struct rk628 * rk628)539 static inline bool rk628_input_is_rgb(struct rk628 *rk628)
540 {
541 return rk628->input_mode & BIT(INPUT_MODE_RGB);
542 }
543
rk628_input_is_bt1120(struct rk628 * rk628)544 static inline bool rk628_input_is_bt1120(struct rk628 *rk628)
545 {
546 return rk628->input_mode & BIT(INPUT_MODE_BT1120);
547 }
548
rk628_output_is_rgb(struct rk628 * rk628)549 static inline bool rk628_output_is_rgb(struct rk628 *rk628)
550 {
551 return rk628->output_mode & BIT(OUTPUT_MODE_RGB);
552 }
553
rk628_output_is_bt1120(struct rk628 * rk628)554 static inline bool rk628_output_is_bt1120(struct rk628 *rk628)
555 {
556 return rk628->output_mode & BIT(OUTPUT_MODE_BT1120);
557 }
558
rk628_output_is_gvi(struct rk628 * rk628)559 static inline bool rk628_output_is_gvi(struct rk628 *rk628)
560 {
561 return rk628->output_mode & BIT(OUTPUT_MODE_GVI);
562 }
563
rk628_output_is_lvds(struct rk628 * rk628)564 static inline bool rk628_output_is_lvds(struct rk628 *rk628)
565 {
566 return rk628->output_mode & BIT(OUTPUT_MODE_LVDS);
567 }
568
rk628_output_is_dsi(struct rk628 * rk628)569 static inline bool rk628_output_is_dsi(struct rk628 *rk628)
570 {
571 return rk628->output_mode & BIT(OUTPUT_MODE_DSI);
572 }
573
rk628_output_is_csi(struct rk628 * rk628)574 static inline bool rk628_output_is_csi(struct rk628 *rk628)
575 {
576 return rk628->output_mode & BIT(OUTPUT_MODE_CSI);
577 }
578
rk628_output_is_hdmi(struct rk628 * rk628)579 static inline bool rk628_output_is_hdmi(struct rk628 *rk628)
580 {
581 return rk628->output_mode & BIT(OUTPUT_MODE_HDMI);
582 }
583
rk628_set_input_bus_format(struct rk628 * rk628,enum bus_format format)584 static inline void rk628_set_input_bus_format(struct rk628 *rk628, enum bus_format format)
585 {
586 rk628->input_fmt = format;
587 }
588
rk628_get_input_bus_format(struct rk628 * rk628)589 static inline enum bus_format rk628_get_input_bus_format(struct rk628 *rk628)
590 {
591 return rk628->input_fmt;
592 }
593
rk628_set_output_bus_format(struct rk628 * rk628,enum bus_format format)594 static inline void rk628_set_output_bus_format(struct rk628 *rk628, enum bus_format format)
595 {
596 rk628->output_fmt = format;
597 }
598
rk628_get_output_bus_format(struct rk628 * rk628)599 static inline enum bus_format rk628_get_output_bus_format(struct rk628 *rk628)
600 {
601 return rk628->output_fmt;
602 }
603
rk628_i2c_write(struct rk628 * rk628,u32 reg,u32 val)604 static inline int rk628_i2c_write(struct rk628 *rk628, u32 reg, u32 val)
605 {
606 struct dm_i2c_chip *chip = dev_get_parent_platdata(rk628->dev);
607 struct i2c_msg msg;
608 u8 buf[] = {
609 (reg >> 0) & 0xff, (reg >> 8) & 0xff,
610 (reg >> 16) & 0xff, (reg >> 24) & 0xff,
611 (val >> 0) & 0xff, (val >> 8) & 0xff,
612 (val >> 16) & 0xff, (val >> 24) & 0xff
613 };
614 int ret;
615
616 msg.addr = chip->chip_addr;
617 msg.flags = 0;
618 msg.len = sizeof(buf);
619 msg.buf = buf;
620
621 ret = dm_i2c_xfer(rk628->dev, &msg, 1);
622 if (ret) {
623 dev_err(rk628->dev, "Could not execute transfer: %d\n", ret);
624 return ret;
625 }
626
627 return 0;
628 }
629
rk628_i2c_read(struct rk628 * rk628,u32 reg,u32 * val)630 static inline int rk628_i2c_read(struct rk628 *rk628, u32 reg, u32 *val)
631 {
632 struct dm_i2c_chip *chip = dev_get_parent_platdata(rk628->dev);
633 u32 data;
634 struct i2c_msg msg[] = {
635 {
636 .addr = chip->chip_addr,
637 .flags = 0,
638 .buf = (u8 *)®,
639 .len = 4,
640 }, {
641 .addr = chip->chip_addr,
642 .flags = I2C_M_RD,
643 .buf = (u8 *)&data,
644 .len = 4,
645 }
646 };
647 int ret;
648
649 ret = dm_i2c_xfer(rk628->dev, msg, 2);
650 if (ret) {
651 dev_err(rk628->dev, "Could not execute transfer: %d\n", ret);
652 return ret;
653 }
654
655 *val = data;
656
657 return 0;
658 }
659
rk628_i2c_update_bits(struct rk628 * rk628,u32 reg,u32 mask,u32 val)660 static inline int rk628_i2c_update_bits(struct rk628 *rk628, u32 reg, u32 mask, u32 val)
661 {
662 u32 tmp, orig;
663 int ret;
664
665 ret = rk628_i2c_read(rk628, reg, &orig);
666 if (ret)
667 return ret;
668
669 tmp = orig & ~mask;
670 tmp |= val & mask;
671
672 return rk628_i2c_write(rk628, reg, tmp);
673 }
674
675 #define rk628_read_poll_timeout(rk628, addr, val, cond, sleep_us, timeout_us) \
676 ({ \
677 unsigned long timeout = timer_get_us() + (timeout_us); \
678 for (;;) { \
679 rk628_i2c_read(rk628, addr, &val); \
680 if (cond) \
681 break; \
682 if ((timeout_us) && time_after(timer_get_us(), timeout)) { \
683 rk628_i2c_read(rk628, addr, &val); \
684 break; \
685 } \
686 if (sleep_us) \
687 udelay(sleep_us); \
688 } \
689 (cond) ? 0 : -ETIMEDOUT; \
690 })
691
692 #endif
693