1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * STMicroelectronics st_lsm6dsr sensor driver
4 *
5 * Copyright 2020 STMicroelectronics Inc.
6 *
7 * Lorenzo Bianconi <lorenzo.bianconi@st.com>
8 */
9
10 #ifndef ST_LSM6DSR_H
11 #define ST_LSM6DSR_H
12
13 #include <linux/device.h>
14 #include <linux/iio/iio.h>
15 #include <linux/delay.h>
16
17 #define ST_LSM6DSR_MAX_ODR 833
18 #define ST_LSM6DSR_ODR_LIST_SIZE 8
19 #define ST_LSM6DSR_ODR_EXPAND(odr, uodr) ((odr * 1000000) + uodr)
20
21 #define ST_LSM6DSR_DEV_NAME "lsm6dsr"
22
23 #define ST_LSM6DSR_REG_FUNC_CFG_ACCESS_ADDR 0x01
24 #define ST_LSM6DSR_REG_SHUB_REG_MASK BIT(6)
25 #define ST_LSM6DSR_REG_FUNC_CFG_MASK BIT(7)
26
27 #define ST_LSM6DSR_REG_FIFO_CTRL1_ADDR 0x07
28 #define ST_LSM6DSR_REG_FIFO_CTRL2_ADDR 0x08
29 #define ST_LSM6DSR_REG_FIFO_WTM_MASK GENMASK(8, 0)
30 #define ST_LSM6DSR_REG_FIFO_WTM8_MASK BIT(0)
31
32 #define ST_LSM6DSR_REG_FIFO_CTRL3_ADDR 0x09
33 #define ST_LSM6DSR_REG_BDR_XL_MASK GENMASK(3, 0)
34 #define ST_LSM6DSR_REG_BDR_GY_MASK GENMASK(7, 4)
35
36 #define ST_LSM6DSR_REG_FIFO_CTRL4_ADDR 0x0a
37 #define ST_LSM6DSR_REG_FIFO_MODE_MASK GENMASK(2, 0)
38 #define ST_LSM6DSR_REG_ODR_T_BATCH_MASK GENMASK(5, 4)
39 #define ST_LSM6DSR_REG_DEC_TS_MASK GENMASK(7, 6)
40
41 #define ST_LSM6DSR_REG_INT1_CTRL_ADDR 0x0d
42 #define ST_LSM6DSR_REG_INT2_CTRL_ADDR 0x0e
43 #define ST_LSM6DSR_REG_INT_FIFO_TH_MASK BIT(3)
44
45 #define ST_LSM6DSR_REG_WHOAMI_ADDR 0x0f
46 #define ST_LSM6DSR_WHOAMI_VAL 0x6b
47
48 #define ST_LSM6DSR_CTRL1_XL_ADDR 0x10
49 #define ST_LSM6DSR_CTRL2_G_ADDR 0x11
50 #define ST_LSM6DSR_REG_CTRL3_C_ADDR 0x12
51 #define ST_LSM6DSR_REG_SW_RESET_MASK BIT(0)
52 #define ST_LSM6DSR_REG_PP_OD_MASK BIT(4)
53 #define ST_LSM6DSR_REG_H_LACTIVE_MASK BIT(5)
54 #define ST_LSM6DSR_REG_BDU_MASK BIT(6)
55 #define ST_LSM6DSR_REG_BOOT_MASK BIT(7)
56
57 #define ST_LSM6DSR_REG_CTRL4_C_ADDR 0x13
58 #define ST_LSM6DSR_REG_DRDY_MASK BIT(3)
59
60 #define ST_LSM6DSR_REG_CTRL5_C_ADDR 0x14
61 #define ST_LSM6DSR_REG_ROUNDING_MASK GENMASK(6, 5)
62
63 #define ST_LSM6DSR_REG_CTRL9_XL_ADDR 0x18
64 #define ST_LSM6DSR_REG_I3C_DISABLE_MASK BIT(1)
65
66 #define ST_LSM6DSR_REG_CTRL10_C_ADDR 0x19
67 #define ST_LSM6DSR_REG_TIMESTAMP_EN_MASK BIT(5)
68
69 #define ST_LSM6DSR_REG_OUT_TEMP_L_ADDR 0x20
70
71 #define ST_LSM6DSR_REG_OUTX_L_G_ADDR 0x22
72 #define ST_LSM6DSR_REG_OUTY_L_G_ADDR 0x24
73 #define ST_LSM6DSR_REG_OUTZ_L_G_ADDR 0x26
74
75 #define ST_LSM6DSR_REG_OUTX_L_A_ADDR 0x28
76 #define ST_LSM6DSR_REG_OUTY_L_A_ADDR 0x2a
77 #define ST_LSM6DSR_REG_OUTZ_L_A_ADDR 0x2c
78
79 #define ST_LSM6DSR_REG_FIFO_STATUS1_ADDR 0x3a
80 #define ST_LSM6DSR_REG_FIFO_STATUS_DIFF GENMASK(9, 0)
81
82 #define ST_LSM6DSR_REG_TIMESTAMP0_ADDR 0x40
83 #define ST_LSM6DSR_REG_TIMESTAMP2_ADDR 0x42
84
85 #define ST_LSM6DSR_REG_TAP_CFG0_ADDR 0x56
86 #define ST_LSM6DSR_REG_TAP_X_EN_MASK BIT(3)
87 #define ST_LSM6DSR_REG_TAP_Y_EN_MASK BIT(2)
88 #define ST_LSM6DSR_REG_TAP_Z_EN_MASK BIT(1)
89 #define ST_LSM6DSR_REG_LIR_MASK BIT(0)
90
91 #define ST_LSM6DSR_REG_MD1_CFG_ADDR 0x5e
92 #define ST_LSM6DSR_REG_MD2_CFG_ADDR 0x5f
93 #define ST_LSM6DSR_REG_INT2_TIMESTAMP_MASK BIT(0)
94 #define ST_LSM6DSR_REG_INT_EMB_FUNC_MASK BIT(1)
95
96 #define ST_LSM6DSR_INTERNAL_FREQ_FINE 0x63
97
98 #define ST_LSM6DSR_REG_FIFO_DATA_OUT_TAG_ADDR 0x78
99
100 /* embedded registers */
101 #define ST_LSM6DSR_REG_EMB_FUNC_INT1_ADDR 0x0a
102 #define ST_LSM6DSR_REG_EMB_FUNC_INT2_ADDR 0x0e
103
104 /* Timestamp Tick 25us/LSB */
105 #define ST_LSM6DSR_TS_DELTA_NS 25000ULL
106
107 #define ST_LSM6DSR_TEMP_GAIN 256
108 #define ST_LSM6DSR_TEMP_FS_GAIN (1000000 / ST_LSM6DSR_TEMP_GAIN)
109 #define ST_LSM6DSR_TEMP_OFFSET 6400
110
111 #define ST_LSM6DSR_SAMPLE_SIZE 6
112 #define ST_LSM6DSR_TS_SAMPLE_SIZE 4
113 #define ST_LSM6DSR_TAG_SIZE 1
114 #define ST_LSM6DSR_FIFO_SAMPLE_SIZE (ST_LSM6DSR_SAMPLE_SIZE + \
115 ST_LSM6DSR_TAG_SIZE)
116 #define ST_LSM6DSR_MAX_FIFO_DEPTH 416
117
118 #define ST_LSM6DSR_DATA_CHANNEL(chan_type, addr, mod, ch2, scan_idx, \
119 rb, sb, sg) \
120 { \
121 .type = chan_type, \
122 .address = addr, \
123 .modified = mod, \
124 .channel2 = ch2, \
125 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
126 BIT(IIO_CHAN_INFO_SCALE), \
127 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
128 .scan_index = scan_idx, \
129 .scan_type = { \
130 .sign = sg, \
131 .realbits = rb, \
132 .storagebits = sb, \
133 .endianness = IIO_LE, \
134 }, \
135 }
136
137 static const struct iio_event_spec st_lsm6dsr_flush_event = {
138 #ifdef CONFIG_NO_GKI
139 .type = IIO_EV_TYPE_FIFO_FLUSH,
140 .dir = IIO_EV_DIR_EITHER,
141 #endif
142 };
143
144 static const struct iio_event_spec st_lsm6dsr_thr_event = {
145 .type = IIO_EV_TYPE_THRESH,
146 .dir = IIO_EV_DIR_RISING,
147 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
148 };
149
150 #define ST_LSM6DSR_EVENT_CHANNEL(ctype, etype) \
151 { \
152 .type = ctype, \
153 .modified = 0, \
154 .scan_index = -1, \
155 .indexed = -1, \
156 .event_spec = &st_lsm6dsr_##etype##_event, \
157 .num_event_specs = 1, \
158 }
159
160 #define ST_LSM6DSR_RX_MAX_LENGTH 64
161 #define ST_LSM6DSR_TX_MAX_LENGTH 16
162
163 /**
164 * @struct st_lsm6dsr_transfer_buffer
165 * @brief Buffer support for data transfer
166 *
167 * rx_buf: Data receive buffer.
168 * tx_buf: Data transmit buffer.
169 */
170 struct st_lsm6dsr_transfer_buffer {
171 u8 rx_buf[ST_LSM6DSR_RX_MAX_LENGTH];
172 u8 tx_buf[ST_LSM6DSR_TX_MAX_LENGTH] ____cacheline_aligned;
173 };
174
175 /**
176 * @struct st_lsm6dsr_transfer_function
177 * @brief Bus Transfer Function
178 *
179 * read: Bus read function to get register value from sensor.
180 * write: Bus write function to set register value to sensor.
181 */
182 struct st_lsm6dsr_transfer_function {
183 int (*read)(struct device *dev, u8 addr, int len, u8 *data);
184 int (*write)(struct device *dev, u8 addr, int len, const u8 *data);
185 };
186
187 /**
188 * @struct st_lsm6dsr_reg
189 * @brief Generic sensor register description
190 *
191 * addr: Register arress value.
192 * mask: Register bitmask.
193 */
194 struct st_lsm6dsr_reg {
195 u8 addr;
196 u8 mask;
197 };
198
199 enum st_lsm6dsr_suspend_resume_register {
200 ST_LSM6DSR_CTRL1_XL_REG = 0,
201 ST_LSM6DSR_CTRL2_G_REG,
202 ST_LSM6DSR_REG_CTRL3_C_REG,
203 ST_LSM6DSR_REG_CTRL4_C_REG,
204 ST_LSM6DSR_REG_CTRL5_C_REG,
205 ST_LSM6DSR_REG_CTRL10_C_REG,
206 ST_LSM6DSR_REG_TAP_CFG0_REG,
207 ST_LSM6DSR_REG_INT1_CTRL_REG,
208 ST_LSM6DSR_REG_INT2_CTRL_REG,
209 ST_LSM6DSR_REG_FIFO_CTRL1_REG,
210 ST_LSM6DSR_REG_FIFO_CTRL2_REG,
211 ST_LSM6DSR_REG_FIFO_CTRL3_REG,
212 ST_LSM6DSR_REG_FIFO_CTRL4_REG,
213 ST_LSM6DSR_SUSPEND_RESUME_REGS,
214 };
215
216 struct st_lsm6dsr_suspend_resume_entry {
217 u8 addr;
218 u8 val;
219 u8 mask;
220 };
221
222 /**
223 * @struct st_lsm6dsr_odr
224 * @brief ODR sensor table entry
225 *
226 * In the ODR table the possible ODR supported by sensor can be defined in the
227 * following format:
228 * .odr_avl[0] = { 0, 0, 0x00 },
229 * .odr_avl[1] = { 12, 500000, 0x01 }, ..... it means 12.5 Hz
230 * .odr_avl[2] = { 26, 0, 0x02 }, ..... it means 26.0 Hz
231 *
232 * hz: Most significant part of ODR value (in Hz).
233 * uhz: Least significant part of ODR value (in micro Hz).
234 * val: Register value tu set ODR.
235 */
236 struct st_lsm6dsr_odr {
237 int hz;
238 int uhz;
239 u8 val;
240 };
241
242 /**
243 * @struct st_lsm6dsr_odr_table_entry
244 * @brief ODR sensor table
245 *
246 * odr_size: ODR table size.
247 * reg: Sensor register description for ODR (address and mask).
248 * odr_avl: All supported ODR values.
249 */
250 struct st_lsm6dsr_odr_table_entry {
251 u8 odr_size;
252 struct st_lsm6dsr_reg reg;
253 struct st_lsm6dsr_odr odr_avl[ST_LSM6DSR_ODR_LIST_SIZE];
254 };
255
256 /**
257 * @struct st_lsm6dsr_fs
258 * @brief Full scale entry
259 *
260 * reg: Sensor register description for FS (address and mask).
261 * gain: The gain to obtain data value from raw data (LSB).
262 * val: Register value.
263 */
264 struct st_lsm6dsr_fs {
265 struct st_lsm6dsr_reg reg;
266 u32 gain;
267 u8 val;
268 };
269
270 /**
271 * @struct st_lsm6dsr_fs_table_entry
272 * @brief Full scale table
273 *
274 * size: Full scale number of entry.
275 * fs_avl: Full scale entry.
276 */
277 #define ST_LSM6DSR_FS_LIST_SIZE 5
278 #define ST_LSM6DSR_FS_ACC_LIST_SIZE 4
279 #define ST_LSM6DSR_FS_GYRO_LIST_SIZE 5
280 #define ST_LSM6DSR_FS_TEMP_LIST_SIZE 1
281 struct st_lsm6dsr_fs_table_entry {
282 u8 size;
283 struct st_lsm6dsr_fs fs_avl[ST_LSM6DSR_FS_LIST_SIZE];
284 };
285
286 #define ST_LSM6DSR_ACC_FS_2G_GAIN IIO_G_TO_M_S_2(61)//
287 #define ST_LSM6DSR_ACC_FS_4G_GAIN IIO_G_TO_M_S_2(61)//(122)
288 #define ST_LSM6DSR_ACC_FS_8G_GAIN IIO_G_TO_M_S_2(61)//(244)
289 #define ST_LSM6DSR_ACC_FS_16G_GAIN IIO_G_TO_M_S_2(61)//(488)
290
291 #define ST_LSM6DSR_GYRO_FS_250_GAIN IIO_DEGREE_TO_RAD(8750)//
292 #define ST_LSM6DSR_GYRO_FS_500_GAIN IIO_DEGREE_TO_RAD(8750)//(17500)
293 #define ST_LSM6DSR_GYRO_FS_1000_GAIN IIO_DEGREE_TO_RAD(8750)//(35000)
294 #define ST_LSM6DSR_GYRO_FS_2000_GAIN IIO_DEGREE_TO_RAD(8750)//(70000)
295 #define ST_LSM6DSR_GYRO_FS_4000_GAIN IIO_DEGREE_TO_RAD(8750)//(140000)
296
297 struct st_lsm6dsr_ext_dev_info {
298 const struct st_lsm6dsr_ext_dev_settings *ext_dev_settings;
299 u8 ext_dev_i2c_addr;
300 };
301
302 /**
303 * @enum st_lsm6dsr_sensor_id
304 * @brief Sensor Identifier
305 */
306 enum st_lsm6dsr_sensor_id {
307 ST_LSM6DSR_ID_GYRO,
308 ST_LSM6DSR_ID_ACC,
309 ST_LSM6DSR_ID_TEMP,
310 ST_LSM6DSR_ID_EXT0,
311 ST_LSM6DSR_ID_EXT1,
312 ST_LSM6DSR_ID_STEP_COUNTER,
313 ST_LSM6DSR_ID_STEP_DETECTOR,
314 ST_LSM6DSR_ID_SIGN_MOTION,
315 ST_LSM6DSR_ID_GLANCE,
316 ST_LSM6DSR_ID_MOTION,
317 ST_LSM6DSR_ID_NO_MOTION,
318 ST_LSM6DSR_ID_WAKEUP,
319 ST_LSM6DSR_ID_PICKUP,
320 ST_LSM6DSR_ID_ORIENTATION,
321 ST_LSM6DSR_ID_WRIST_TILT,
322 ST_LSM6DSR_ID_TILT,
323 ST_LSM6DSR_ID_MAX,
324 };
325
326 /**
327 * @enum st_lsm6dsr_sensor_id
328 * @brief Sensor Table Identifier
329 */
330 static const enum st_lsm6dsr_sensor_id st_lsm6dsr_main_sensor_list[] = {
331 [0] = ST_LSM6DSR_ID_GYRO,
332 [1] = ST_LSM6DSR_ID_ACC,
333 [2] = ST_LSM6DSR_ID_TEMP,
334 [3] = ST_LSM6DSR_ID_STEP_COUNTER,
335 [4] = ST_LSM6DSR_ID_STEP_DETECTOR,
336 [5] = ST_LSM6DSR_ID_SIGN_MOTION,
337 [6] = ST_LSM6DSR_ID_GLANCE,
338 [7] = ST_LSM6DSR_ID_MOTION,
339 [8] = ST_LSM6DSR_ID_NO_MOTION,
340 [9] = ST_LSM6DSR_ID_WAKEUP,
341 [10] = ST_LSM6DSR_ID_PICKUP,
342 [11] = ST_LSM6DSR_ID_ORIENTATION,
343 [12] = ST_LSM6DSR_ID_WRIST_TILT,
344 [13] = ST_LSM6DSR_ID_TILT,
345 };
346
347 /**
348 * @enum st_lsm6dsr_fifo_mode
349 * @brief FIFO Modes
350 */
351 enum st_lsm6dsr_fifo_mode {
352 ST_LSM6DSR_FIFO_BYPASS = 0x0,
353 ST_LSM6DSR_FIFO_CONT = 0x6,
354 };
355
356 /**
357 * @enum st_lsm6dsr_fifo_mode - FIFO Buffer Status
358 */
359 enum st_lsm6dsr_fifo_status {
360 ST_LSM6DSR_HW_FLUSH,
361 ST_LSM6DSR_HW_OPERATIONAL,
362 };
363
364 /**
365 * @struct st_lsm6dsr_sensor
366 * @brief ST IMU sensor instance
367 *
368 * id: Sensor identifier
369 * hw: Pointer to instance of struct st_lsm6dsr_hw
370 * ext_dev_info: Sensor hub i2c slave settings.
371 * trig: Sensor iio trigger.
372 * gain: Configured sensor sensitivity
373 * odr: Output data rate of the sensor [Hz]
374 * uodr: Output data rate of the sensor [uHz]
375 * offset: Sensor data offset
376 * decimator: Sensor decimator
377 * dec_counter: Sensor decimator counter
378 * old_data: Saved sensor data
379 * max_watermark: Max supported watermark level
380 * watermark: Sensor watermark level
381 * batch_reg: Sensor reg/mask for FIFO batching register
382 * last_fifo_timestamp: Store last sample timestamp in FIFO, used by flush
383 */
384 struct st_lsm6dsr_sensor {
385 enum st_lsm6dsr_sensor_id id;
386 struct st_lsm6dsr_hw *hw;
387
388 struct st_lsm6dsr_ext_dev_info ext_dev_info;
389
390 struct iio_trigger *trig;
391
392 u32 gain;
393 int odr;
394 int uodr;
395
396 u32 offset;
397 u8 decimator;
398 u8 dec_counter;
399
400 u16 max_watermark;
401 u16 watermark;
402
403 struct st_lsm6dsr_reg batch_reg;
404 s64 last_fifo_timestamp;
405 };
406
407 /**
408 * @struct st_lsm6dsr_hw
409 * @brief ST IMU MEMS hw instance
410 *
411 * dev: Pointer to instance of struct device (I2C or SPI).
412 * irq: Device interrupt line (I2C or SPI).
413 * lock: Mutex to protect read and write operations.
414 * fifo_lock: Mutex to prevent concurrent access to the hw FIFO.
415 * page_lock: Mutex to prevent concurrent memory page configuration.
416 * fifo_mode: FIFO operating mode supported by the device.
417 * state: hw operational state.
418 * enable_mask: Enabled sensor bitmask.
419 * fsm_enable_mask: FSM Enabled sensor bitmask.
420 * embfunc_pg0_irq_reg: Embedded function irq configuration register (page 0).
421 * embfunc_irq_reg: Embedded function irq configuration register (other).
422 * ext_data_len: Number of i2c slave devices connected to I2C master.
423 * odr: Timestamp sample ODR [Hz]
424 * uodr: Timestamp sample ODR [uHz]
425 * ts_offset: Hw timestamp offset.
426 * hw_ts: Latest hw timestamp from the sensor.
427 * hw_ts_high: Manage timestamp rollover
428 * tsample:
429 * hw_ts_old:
430 * delta_ts: Delta time between two consecutive interrupts.
431 * delta_hw_ts:
432 * ts: Latest timestamp from irq handler.
433 * iio_devs: Pointers to acc/gyro iio_dev instances.
434 * tf: Transfer function structure used by I/O operations.
435 * tb: Transfer buffers used by SPI I/O operations.
436 */
437 struct st_lsm6dsr_hw {
438 struct device *dev;
439 int irq;
440
441 struct mutex lock;
442 struct mutex fifo_lock;
443 struct mutex page_lock;
444
445 enum st_lsm6dsr_fifo_mode fifo_mode;
446 unsigned long state;
447 u32 enable_mask;
448 u32 requested_mask;
449 u32 suspend_mask;
450
451 u16 fsm_enable_mask;
452 u8 embfunc_irq_reg;
453 u8 embfunc_pg0_irq_reg;
454
455 u8 ext_data_len;
456
457 int odr;
458 int uodr;
459
460 s64 ts_offset;
461 u64 ts_delta_ns;
462 s64 hw_ts;
463 u32 val_ts_old;
464 u32 hw_ts_high;
465 s64 tsample;
466 s64 delta_ts;
467 s64 ts;
468
469 struct iio_dev *iio_devs[ST_LSM6DSR_ID_MAX];
470
471 const struct st_lsm6dsr_transfer_function *tf;
472 struct st_lsm6dsr_transfer_buffer tb;
473 };
474
475 /**
476 * @struct dev_pm_ops
477 * @brief Power management callback function structure
478 */
479 extern const struct dev_pm_ops st_lsm6dsr_pm_ops;
480
st_lsm6dsr_read_atomic(struct st_lsm6dsr_hw * hw,u8 addr,int len,u8 * data)481 static inline int st_lsm6dsr_read_atomic(struct st_lsm6dsr_hw *hw, u8 addr,
482 int len, u8 *data)
483 {
484 int err;
485
486 mutex_lock(&hw->page_lock);
487 err = hw->tf->read(hw->dev, addr, len, data);
488 mutex_unlock(&hw->page_lock);
489
490 return err;
491 }
492
st_lsm6dsr_write_atomic(struct st_lsm6dsr_hw * hw,u8 addr,int len,u8 * data)493 static inline int st_lsm6dsr_write_atomic(struct st_lsm6dsr_hw *hw, u8 addr,
494 int len, u8 *data)
495 {
496 int err;
497
498 mutex_lock(&hw->page_lock);
499 err = hw->tf->write(hw->dev, addr, len, data);
500 mutex_unlock(&hw->page_lock);
501
502 return err;
503 }
504
505 int __st_lsm6dsr_write_with_mask(struct st_lsm6dsr_hw *hw, u8 addr, u8 mask,
506 u8 val);
st_lsm6dsr_write_with_mask(struct st_lsm6dsr_hw * hw,u8 addr,u8 mask,u8 val)507 static inline int st_lsm6dsr_write_with_mask(struct st_lsm6dsr_hw *hw, u8 addr,
508 u8 mask, u8 val)
509 {
510 int err;
511
512 mutex_lock(&hw->page_lock);
513 err = __st_lsm6dsr_write_with_mask(hw, addr, mask, val);
514 mutex_unlock(&hw->page_lock);
515
516 return err;
517 }
518
st_lsm6dsr_set_page_access(struct st_lsm6dsr_hw * hw,u8 mask,u8 data)519 static inline int st_lsm6dsr_set_page_access(struct st_lsm6dsr_hw *hw,
520 u8 mask, u8 data)
521 {
522 int err;
523
524 err = __st_lsm6dsr_write_with_mask(hw,
525 ST_LSM6DSR_REG_FUNC_CFG_ACCESS_ADDR,
526 mask, data);
527 usleep_range(100, 150);
528
529 return err;
530 }
531
st_lsm6dsr_is_fifo_enabled(struct st_lsm6dsr_hw * hw)532 static inline bool st_lsm6dsr_is_fifo_enabled(struct st_lsm6dsr_hw *hw)
533 {
534 return hw->enable_mask & (BIT(ST_LSM6DSR_ID_STEP_COUNTER) |
535 BIT(ST_LSM6DSR_ID_GYRO) |
536 BIT(ST_LSM6DSR_ID_ACC) |
537 BIT(ST_LSM6DSR_ID_EXT0) |
538 BIT(ST_LSM6DSR_ID_EXT1));
539 }
540
541 int st_lsm6dsr_probe(struct device *dev, int irq,
542 const struct st_lsm6dsr_transfer_function *tf_ops);
543 int st_lsm6dsr_remove(struct device *dev);
544 int st_lsm6dsr_shub_set_enable(struct st_lsm6dsr_sensor *sensor, bool enable);
545 int st_lsm6dsr_shub_probe(struct st_lsm6dsr_hw *hw);
546 int st_lsm6dsr_sensor_set_enable(struct st_lsm6dsr_sensor *sensor,
547 bool enable);
548 int st_lsm6dsr_irq_setup(struct st_lsm6dsr_hw *hw);
549 int st_lsm6dsr_buffers_setup(struct st_lsm6dsr_hw *hw);
550 int st_lsm6dsr_deallocate_buffers(struct st_lsm6dsr_hw *hw);
551 int st_lsm6dsr_get_odr_val(enum st_lsm6dsr_sensor_id id, int odr, int uodr,
552 int *podr, int *puodr, u8 *val);
553 int st_lsm6dsr_update_watermark(struct st_lsm6dsr_sensor *sensor,
554 u16 watermark);
555 ssize_t st_lsm6dsr_flush_fifo(struct device *dev,
556 struct device_attribute *attr,
557 const char *buf, size_t size);
558 ssize_t st_lsm6dsr_get_max_watermark(struct device *dev,
559 struct device_attribute *attr,
560 char *buf);
561 ssize_t st_lsm6dsr_get_watermark(struct device *dev,
562 struct device_attribute *attr,
563 char *buf);
564 ssize_t st_lsm6dsr_set_watermark(struct device *dev,
565 struct device_attribute *attr,
566 const char *buf, size_t size);
567 int st_lsm6dsr_set_page_access(struct st_lsm6dsr_hw *hw, u8 mask, u8 data);
568 int st_lsm6dsr_suspend_fifo(struct st_lsm6dsr_hw *hw);
569 int st_lsm6dsr_set_fifo_mode(struct st_lsm6dsr_hw *hw,
570 enum st_lsm6dsr_fifo_mode fifo_mode);
571 int __st_lsm6dsr_set_sensor_batching_odr(struct st_lsm6dsr_sensor *sensor,
572 bool enable);
573 int st_lsm6dsr_fsm_init(struct st_lsm6dsr_hw *hw);
574 int st_lsm6dsr_fsm_get_orientation(struct st_lsm6dsr_hw *hw, u8 *data);
575 int st_lsm6dsr_embfunc_sensor_set_enable(struct st_lsm6dsr_sensor *sensor,
576 bool enable);
577 int st_lsm6dsr_step_counter_set_enable(struct st_lsm6dsr_sensor *sensor,
578 bool enable);
579 int st_lsm6dsr_reset_step_counter(struct iio_dev *iio_dev);
580 int st_lsm6dsr_update_batching(struct iio_dev *iio_dev, bool enable);
581 int st_lsm6dsr_reset_hwts(struct st_lsm6dsr_hw *hw);
582 #endif /* ST_LSM6DSR_H */
583