1 /* 2 * (C) Copyright 2011 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * 5 * (C) Copyright 2015 6 * Kamil Lulko, <kamil.lulko@gmail.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _MACH_STM32_H_ 12 #define _MACH_STM32_H_ 13 14 #include <asm/arch-stm32/stm32f.h> 15 16 /* 17 * Peripheral memory map 18 */ 19 #define STM32_SYSMEM_BASE 0x1FFF0000 20 21 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) 22 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) 23 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) 24 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) 25 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) 26 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) 27 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) 28 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) 29 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) 30 31 /* 32 * Register maps 33 */ 34 struct stm32_u_id_regs { 35 u32 u_id_low; 36 u32 u_id_mid; 37 u32 u_id_high; 38 }; 39 40 struct stm32_rcc_regs { 41 u32 cr; /* RCC clock control */ 42 u32 pllcfgr; /* RCC PLL configuration */ 43 u32 cfgr; /* RCC clock configuration */ 44 u32 cir; /* RCC clock interrupt */ 45 u32 ahb1rstr; /* RCC AHB1 peripheral reset */ 46 u32 ahb2rstr; /* RCC AHB2 peripheral reset */ 47 u32 ahb3rstr; /* RCC AHB3 peripheral reset */ 48 u32 rsv0; 49 u32 apb1rstr; /* RCC APB1 peripheral reset */ 50 u32 apb2rstr; /* RCC APB2 peripheral reset */ 51 u32 rsv1[2]; 52 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ 53 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ 54 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ 55 u32 rsv2; 56 u32 apb1enr; /* RCC APB1 peripheral clock enable */ 57 u32 apb2enr; /* RCC APB2 peripheral clock enable */ 58 u32 rsv3[2]; 59 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ 60 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ 61 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ 62 u32 rsv4; 63 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ 64 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ 65 u32 rsv5[2]; 66 u32 bdcr; /* RCC Backup domain control */ 67 u32 csr; /* RCC clock control & status */ 68 u32 rsv6[2]; 69 u32 sscgr; /* RCC spread spectrum clock generation */ 70 u32 plli2scfgr; /* RCC PLLI2S configuration */ 71 u32 pllsaicfgr; 72 u32 dckcfgr; 73 }; 74 75 struct stm32_pwr_regs { 76 u32 cr; 77 u32 csr; 78 }; 79 80 /* 81 * Registers access macros 82 */ 83 #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) 84 #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) 85 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { 86 [0 ... 3] = 16 * 1024, 87 [4] = 64 * 1024, 88 [5 ... 11] = 128 * 1024 89 }; 90 91 #endif /* _MACH_STM31_H_ */ 92