1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2020-2024, STMicroelectronics 4 */ 5 #ifndef _DT_BINDINGS_FIREWALL_STM32MP25_RIFSC_H 6 #define _DT_BINDINGS_FIREWALL_STM32MP25_RIFSC_H 7 8 /* RIFSC ID */ 9 #define STM32MP25_RIFSC_TIM1_ID 0 10 #define STM32MP25_RIFSC_TIM2_ID 1 11 #define STM32MP25_RIFSC_TIM3_ID 2 12 #define STM32MP25_RIFSC_TIM4_ID 3 13 #define STM32MP25_RIFSC_TIM5_ID 4 14 #define STM32MP25_RIFSC_TIM6_ID 5 15 #define STM32MP25_RIFSC_TIM7_ID 6 16 #define STM32MP25_RIFSC_TIM8_ID 7 17 #define STM32MP25_RIFSC_TIM10_ID 8 18 #define STM32MP25_RIFSC_TIM11_ID 9 19 #define STM32MP25_RIFSC_TIM12_ID 10 20 #define STM32MP25_RIFSC_TIM13_ID 11 21 #define STM32MP25_RIFSC_TIM14_ID 12 22 #define STM32MP25_RIFSC_TIM15_ID 13 23 #define STM32MP25_RIFSC_TIM16_ID 14 24 #define STM32MP25_RIFSC_TIM17_ID 15 25 #define STM32MP25_RIFSC_TIM20_ID 16 26 #define STM32MP25_RIFSC_LPTIM1_ID 17 27 #define STM32MP25_RIFSC_LPTIM2_ID 18 28 #define STM32MP25_RIFSC_LPTIM3_ID 19 29 #define STM32MP25_RIFSC_LPTIM4_ID 20 30 #define STM32MP25_RIFSC_LPTIM5_ID 21 31 #define STM32MP25_RIFSC_SPI1_ID 22 32 #define STM32MP25_RIFSC_SPI2_ID 23 33 #define STM32MP25_RIFSC_SPI3_ID 24 34 #define STM32MP25_RIFSC_SPI4_ID 25 35 #define STM32MP25_RIFSC_SPI5_ID 26 36 #define STM32MP25_RIFSC_SPI6_ID 27 37 #define STM32MP25_RIFSC_SPI7_ID 28 38 #define STM32MP25_RIFSC_SPI8_ID 29 39 #define STM32MP25_RIFSC_SPDIFRX_ID 30 40 #define STM32MP25_RIFSC_USART1_ID 31 41 #define STM32MP25_RIFSC_USART2_ID 32 42 #define STM32MP25_RIFSC_USART3_ID 33 43 #define STM32MP25_RIFSC_UART4_ID 34 44 #define STM32MP25_RIFSC_UART5_ID 35 45 #define STM32MP25_RIFSC_USART6_ID 36 46 #define STM32MP25_RIFSC_UART7_ID 37 47 #define STM32MP25_RIFSC_UART8_ID 38 48 #define STM32MP25_RIFSC_UART9_ID 39 49 #define STM32MP25_RIFSC_LPUART1_ID 40 50 #define STM32MP25_RIFSC_I2C1_ID 41 51 #define STM32MP25_RIFSC_I2C2_ID 42 52 #define STM32MP25_RIFSC_I2C3_ID 43 53 #define STM32MP25_RIFSC_I2C4_ID 44 54 #define STM32MP25_RIFSC_I2C5_ID 45 55 #define STM32MP25_RIFSC_I2C6_ID 46 56 #define STM32MP25_RIFSC_I2C7_ID 47 57 #define STM32MP25_RIFSC_I2C8_ID 48 58 #define STM32MP25_RIFSC_SAI1_ID 49 59 #define STM32MP25_RIFSC_SAI2_ID 50 60 #define STM32MP25_RIFSC_SAI3_ID 51 61 #define STM32MP25_RIFSC_SAI4_ID 52 62 #define STM32MP25_RIFSC_MDF1_ID 54 63 #define STM32MP25_RIFSC_ADF1_ID 55 64 #define STM32MP25_RIFSC_FDCAN_ID 56 65 #define STM32MP25_RIFSC_HDP_ID 57 66 #define STM32MP25_RIFSC_ADC12_ID 58 67 #define STM32MP25_RIFSC_ADC3_ID 59 68 #define STM32MP25_RIFSC_ETH1_ID 60 69 #define STM32MP25_RIFSC_ETH2_ID 61 70 #define STM32MP25_RIFSC_USBH_ID 63 71 #define STM32MP25_RIFSC_USB3DR_ID 66 72 #define STM32MP25_RIFSC_COMBOPHY_ID 67 73 #define STM32MP25_RIFSC_PCIE_ID 68 74 #define STM32MP25_RIFSC_UCPD1_ID 69 75 #define STM32MP25_RIFSC_ETHSW_DEIP_ID 70 76 #define STM32MP25_RIFSC_ETHSW_ACM_CFG_ID 71 77 #define STM32MP25_RIFSC_ETHSW_ACM_MSGBUF_ID 72 78 #define STM32MP25_RIFSC_STGEN_ID 73 79 #define STM32MP25_RIFSC_OCTOSPI1_ID 74 80 #define STM32MP25_RIFSC_OCTOSPI2_ID 75 81 #define STM32MP25_RIFSC_SDMMC1_ID 76 82 #define STM32MP25_RIFSC_SDMMC2_ID 77 83 #define STM32MP25_RIFSC_SDMMC3_ID 78 84 #define STM32MP25_RIFSC_GPU_ID 79 85 #define STM32MP25_RIFSC_LTDC_CMN_ID 80 86 #define STM32MP25_RIFSC_DSI_CMN_ID 81 87 #define STM32MP25_RIFSC_LVDS_ID 84 88 #define STM32MP25_RIFSC_CSI_ID 86 89 #define STM32MP25_RIFSC_DCMIPP_ID 87 90 #define STM32MP25_RIFSC_DCMI_PSSI_ID 88 91 #define STM32MP25_RIFSC_VDEC_ID 89 92 #define STM32MP25_RIFSC_VENC_ID 90 93 #define STM32MP25_RIFSC_RNG_ID 92 94 #define STM32MP25_RIFSC_PKA_ID 93 95 #define STM32MP25_RIFSC_SAES_ID 94 96 #define STM32MP25_RIFSC_HASH_ID 95 97 #define STM32MP25_RIFSC_CRYP1_ID 96 98 #define STM32MP25_RIFSC_CRYP2_ID 97 99 #define STM32MP25_RIFSC_IWDG1_ID 98 100 #define STM32MP25_RIFSC_IWDG2_ID 99 101 #define STM32MP25_RIFSC_IWDG3_ID 100 102 #define STM32MP25_RIFSC_IWDG4_ID 101 103 #define STM32MP25_RIFSC_IWDG5_ID 102 104 #define STM32MP25_RIFSC_WWDG1_ID 103 105 #define STM32MP25_RIFSC_WWDG2_ID 104 106 #define STM32MP25_RIFSC_VREFBUF_ID 106 107 #define STM32MP25_RIFSC_DTS_ID 107 108 #define STM32MP25_RIFSC_RAMCFG_ID 108 109 #define STM32MP25_RIFSC_CRC_ID 109 110 #define STM32MP25_RIFSC_SERC_ID 110 111 #define STM32MP25_RIFSC_OCTOSPIM_ID 111 112 #define STM32MP25_RIFSC_GICV2M_ID 112 113 #define STM32MP25_RIFSC_I3C1_ID 114 114 #define STM32MP25_RIFSC_I3C2_ID 115 115 #define STM32MP25_RIFSC_I3C3_ID 116 116 #define STM32MP25_RIFSC_I3C4_ID 117 117 #define STM32MP25_RIFSC_ICACHE_DCACHE_ID 118 118 #define STM32MP25_RIFSC_LTDC_L1L2_ID 119 119 #define STM32MP25_RIFSC_LTDC_L3_ID 120 120 #define STM32MP25_RIFSC_LTDC_ROT_ID 121 121 #define STM32MP25_RIFSC_DSI_TRIG_ID 122 122 #define STM32MP25_RIFSC_DSI_RDFIFO_ID 123 123 #define STM32MP25_RIFSC_OTFDEC1_ID 125 124 #define STM32MP25_RIFSC_OTFDEC2_ID 126 125 #define STM32MP25_RIFSC_IAC_ID 127 126 127 /* RIF-aware IPs */ 128 #define STM32MP25_RIFSC_PWR_ID 155 129 #define STM32MP25_RIFSC_GPIOA_ID 160 130 #define STM32MP25_RIFSC_GPIOB_ID 161 131 #define STM32MP25_RIFSC_GPIOC_ID 162 132 #define STM32MP25_RIFSC_GPIOD_ID 163 133 #define STM32MP25_RIFSC_GPIOE_ID 164 134 #define STM32MP25_RIFSC_GPIOF_ID 165 135 #define STM32MP25_RIFSC_GPIOG_ID 166 136 #define STM32MP25_RIFSC_GPIOH_ID 167 137 #define STM32MP25_RIFSC_GPIOI_ID 168 138 #define STM32MP25_RIFSC_GPIOJ_ID 169 139 #define STM32MP25_RIFSC_GPIOK_ID 170 140 #define STM32MP25_RIFSC_GPIOZ_ID 171 141 142 /* Global lock bindings */ 143 #define RIFSC_RIMU_GLOCK 1 144 #define RIFSC_RISUP_GLOCK 2 145 146 /* masters ID */ 147 #define RIMU_ID_OFFSET 200 148 #define RIMU_ID(idx) ((idx) + RIMU_ID_OFFSET) 149 150 /* 151 * CID selection mode 152 * RIF_CIDSEL_P configuration by hardware or inherited from RISUP 153 * RIF_CIDSEL_M configuration from provided RIMU data 154 */ 155 #define RIF_CIDSEL_P 0 156 #define RIF_CIDSEL_M 1 157 158 #define RIMUPROT_RIMC_M_ID_SHIFT 0 159 #define RIMUPROT_RIMC_MODE_SHIFT 10 160 #define RIMUPROT_RIMC_MCID_SHIFT 12 161 #define RIMUPROT_RIMC_MSEC_SHIFT 16 162 #define RIMUPROT_RIMC_MPRIV_SHIFT 17 163 #define RIMUPROT_RIMC_ATTRx_SHIFT 8 164 #define RIMUPROT_RIMC_M_ID_MASK GENMASK_32(7, 0) 165 #define RIMUPROT_RIMC_MCID_MASK GENMASK_32(15, 12) 166 #define RIMUPROT_RIMC_ATTRx_MASK (BIT(RIMUPROT_RIMC_MODE_SHIFT) | \ 167 RIMUPROT_RIMC_MCID_MASK | \ 168 BIT(RIMUPROT_RIMC_MSEC_SHIFT) | \ 169 BIT(RIMUPROT_RIMC_MPRIV_SHIFT)) 170 171 #define RIMUPROT(rimuid, mcid, msec, mpriv, mode) \ 172 (((rimuid) << RIMUPROT_RIMC_M_ID_SHIFT) | \ 173 ((mpriv) << RIMUPROT_RIMC_MPRIV_SHIFT) | \ 174 ((msec) << RIMUPROT_RIMC_MSEC_SHIFT) | \ 175 ((mcid) << RIMUPROT_RIMC_MCID_SHIFT) | \ 176 ((mode) << RIMUPROT_RIMC_MODE_SHIFT)) 177 178 /* RISAL ID */ 179 #define RISAL_ID(idx) (idx) 180 181 /* RISAL CID subregion modes */ 182 #define RIFSC_RISAL_SRDIS 0x0 183 #define RIFSC_RISAL_SREN 0x1 184 185 /* RISAL Block id */ 186 #define RIFSC_RISAL_BLOCK_A 0x0 187 #define RIFSC_RISAL_BLOCK_B 0x1 188 189 #define RIFSC_RISAL_REG_ID_SHIFT 0 190 #define RIFSC_RISAL_BLOCK_ID_SHIFT 8 191 #define RIFSC_RISAL_REGx_CFGR_SHIFT 16 192 #define RIFSC_RISAL_SREN_SHIFT 16 193 #define RIFSC_RISAL_LOCK_SHIFT 17 194 #define RIFSC_RISAL_SRCID_SHIFT 20 195 #define RIFSC_RISAL_SEC_SHIFT 24 196 #define RIFSC_RISAL_PRIV_SHIFT 25 197 #define RIFSC_RISAL_REG_ID_MASK GENMASK_32(7, 0) 198 #define RIFSC_RISAL_BLOCK_ID_MASK GENMASK_32(15, 8) 199 #define RIFSC_RISAL_SRCID_MASK GENMASK_32(22, 20) 200 #define RIFSC_RISAL_REGx_CFGR_MASK (BIT(RIFSC_RISAL_SREN_SHIFT) | \ 201 BIT(RIFSC_RISAL_LOCK_SHIFT) | \ 202 RIFSC_RISAL_SRCID_MASK | \ 203 BIT(RIFSC_RISAL_SEC_SHIFT) | \ 204 BIT(RIFSC_RISAL_PRIV_SHIFT)) 205 206 #define RISALPROT(risalid, blockid, srcid, lock, sec, priv, sren) \ 207 (((risalid) << RIFSC_RISAL_REG_ID_SHIFT) | \ 208 ((blockid) << RIFSC_RISAL_BLOCK_ID_SHIFT) | \ 209 ((priv) << RIFSC_RISAL_PRIV_SHIFT) | \ 210 ((sec) << RIFSC_RISAL_SEC_SHIFT) | \ 211 ((srcid) << RIFSC_RISAL_SRCID_SHIFT) | \ 212 ((lock) << RIFSC_RISAL_LOCK_SHIFT) | \ 213 ((sren) << RIFSC_RISAL_SREN_SHIFT)) 214 215 #endif /* _DT_BINDINGS_FIREWALL_STM32MP25_RIFSC_H */ 216 217