1 /*
2 * Copyright (c) 2023-2026, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP2_DEF_H
8 #define STM32MP2_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #ifndef __ASSEMBLER__
12 #include <drivers/st/bsec.h>
13 #include <drivers/st/stm32mp2_clk.h>
14 #include <drivers/st/stm32mp2_risaf.h>
15 #include <drivers/st/stm32mp_rifsc_regs.h>
16 #endif
17 #if STM32MP21
18 #include <drivers/st/stm32mp21_pwr.h>
19 #include <drivers/st/stm32mp21_rcc.h>
20 #else /* STM32MP21 */
21 #include <drivers/st/stm32mp2_pwr.h>
22 #include <drivers/st/stm32mp25_rcc.h>
23 #endif /* STM32MP21 */
24 #if STM32MP21
25 #include <dt-bindings/clock/st,stm32mp21-rcc.h>
26 #include <dt-bindings/clock/stm32mp21-clksrc.h>
27 #include <dt-bindings/reset/st,stm32mp21-rcc.h>
28 #include <dt-bindings/soc/stm32mp21-rif.h>
29 #endif /* STM32MP21 */
30 #if STM32MP23
31 #include <dt-bindings/clock/stm32mp25-clks.h>
32 #include <dt-bindings/clock/stm32mp25-clksrc.h>
33 #include <dt-bindings/reset/stm32mp25-resets.h>
34 #include <dt-bindings/soc/stm32mp23-rif.h>
35 #endif /* STM32MP23 */
36 #if STM32MP25
37 #include <dt-bindings/clock/stm32mp25-clks.h>
38 #include <dt-bindings/clock/stm32mp25-clksrc.h>
39 #include <dt-bindings/reset/stm32mp25-resets.h>
40 #include <dt-bindings/soc/stm32mp25-rif.h>
41 #endif /* STM32MP25 */
42 #include <dt-bindings/gpio/stm32-gpio.h>
43 #include <dt-bindings/soc/rif.h>
44
45 #ifndef __ASSEMBLER__
46 #include <boot_api.h>
47 #include <stm32mp2_private.h>
48 #include <stm32mp_common.h>
49 #include <stm32mp_dt.h>
50 #include <stm32mp_shared_resources.h>
51 #endif
52
53 /*******************************************************************************
54 * CHIP ID
55 ******************************************************************************/
56 #if STM32MP21
57 #define STM32MP2_CHIP_ID U(0x503)
58
59 #define STM32MP211A_PART_NB U(0x40073E7D)
60 #define STM32MP211C_PART_NB U(0x0007307D)
61 #define STM32MP211D_PART_NB U(0xC0073E7D)
62 #define STM32MP211F_PART_NB U(0x8007307D)
63 #define STM32MP213A_PART_NB U(0x40073E1D)
64 #define STM32MP213C_PART_NB U(0x0007301D)
65 #define STM32MP213D_PART_NB U(0xC0073E1D)
66 #define STM32MP213F_PART_NB U(0x8007301D)
67 #define STM32MP215A_PART_NB U(0x40033E0D)
68 #define STM32MP215C_PART_NB U(0x0003300D)
69 #define STM32MP215D_PART_NB U(0xC0033E0D)
70 #define STM32MP215F_PART_NB U(0x8003300D)
71 #endif /* STM32MP21 */
72
73 #if STM32MP23
74 #define STM32MP2_CHIP_ID U(0x505)
75
76 #define STM32MP231A_PART_NB U(0x400B3FEF)
77 #define STM32MP231C_PART_NB U(0x000B31EF)
78 #define STM32MP231D_PART_NB U(0xC00B3FEF)
79 #define STM32MP231F_PART_NB U(0x800B31EF)
80 #define STM32MP233A_PART_NB U(0x400B3F8E)
81 #define STM32MP233C_PART_NB U(0x000B318E)
82 #define STM32MP233D_PART_NB U(0xC00B3F8E)
83 #define STM32MP233F_PART_NB U(0x800B318E)
84 #define STM32MP235A_PART_NB U(0x40082F82)
85 #define STM32MP235C_PART_NB U(0x00082182)
86 #define STM32MP235D_PART_NB U(0xC0082F82)
87 #define STM32MP235F_PART_NB U(0x80082182)
88 #endif /* STM32MP23 */
89
90 #if STM32MP25
91 #define STM32MP2_CHIP_ID U(0x505)
92
93 #define STM32MP251A_PART_NB U(0x400B3E6D)
94 #define STM32MP251C_PART_NB U(0x000B306D)
95 #define STM32MP251D_PART_NB U(0xC00B3E6D)
96 #define STM32MP251F_PART_NB U(0x800B306D)
97 #define STM32MP253A_PART_NB U(0x400B3E0C)
98 #define STM32MP253C_PART_NB U(0x000B300C)
99 #define STM32MP253D_PART_NB U(0xC00B3E0C)
100 #define STM32MP253F_PART_NB U(0x800B300C)
101 #define STM32MP255A_PART_NB U(0x40082E00)
102 #define STM32MP255C_PART_NB U(0x00082000)
103 #define STM32MP255D_PART_NB U(0xC0082E00)
104 #define STM32MP255F_PART_NB U(0x80082000)
105 #define STM32MP257A_PART_NB U(0x40002E00)
106 #define STM32MP257C_PART_NB U(0x00002000)
107 #define STM32MP257D_PART_NB U(0xC0002E00)
108 #define STM32MP257F_PART_NB U(0x80002000)
109 #endif /* STM32MP25 */
110
111 #define STM32MP2_REV_A U(0x08)
112 #define STM32MP2_REV_B U(0x10)
113 #define STM32MP2_REV_X U(0x12)
114 #define STM32MP2_REV_Y U(0x11)
115 #define STM32MP2_REV_Z U(0x09)
116
117 /*******************************************************************************
118 * PACKAGE ID
119 ******************************************************************************/
120 #if STM32MP21
121 #define STM32MP21_PKG_CUSTOM U(0)
122 #define STM32MP21_PKG_AL_VFBGA361 U(1)
123 #define STM32MP21_PKG_AN_VFBGA273 U(3)
124 #define STM32MP21_PKG_AO_VFBGA225 U(4)
125 #define STM32MP21_PKG_AM_TFBGA289 U(5)
126 #endif /* STM32MP21 */
127 #if STM32MP23
128 #define STM32MP23_PKG_CUSTOM U(0)
129 #define STM32MP23_PKG_AL_VFBGA361 U(1)
130 #define STM32MP23_PKG_AK_VFBGA424 U(3)
131 #define STM32MP23_PKG_AJ_TFBGA361 U(7)
132 #endif /* STM32MP23 */
133 #if STM32MP25
134 #define STM32MP25_PKG_CUSTOM U(0)
135 #define STM32MP25_PKG_AL_VFBGA361 U(1)
136 #define STM32MP25_PKG_AK_VFBGA424 U(3)
137 #define STM32MP25_PKG_AI_TFBGA436 U(5)
138 #define STM32MP25_PKG_UNKNOWN U(7)
139 #endif /* STM32MP25 */
140
141 /*******************************************************************************
142 * STM32MP2 memory map related constants
143 ******************************************************************************/
144 #define STM32MP_SYSRAM_BASE U(0x0E000000)
145 #define STM32MP_SYSRAM_SIZE U(0x00040000)
146 #if STM32MP21
147 #define SRAM1_BASE U(0x0E060000)
148 #else /* STM32MP21 */
149 #define SRAM1_BASE U(0x0E040000)
150 #endif /* STM32MP21 */
151 #define SRAM1_SIZE_FOR_TFA U(0x00010000)
152 #if STM32MP21
153 #define RETRAM_BASE U(0x0E040000)
154 #else /* STM32MP21 */
155 #define RETRAM_BASE U(0x0E080000)
156 #endif /* STM32MP21 */
157 #define RETRAM_SIZE U(0x00020000)
158
159 #if defined(IMAGE_BL2) && STM32MP_USB_PROGRAMMER && !STM32MP21
160 #define STM32MP_USB_DWC3_SIZE PAGE_SIZE
161 #define STM32MP_USB_DWC3_BASE (STM32MP_SYSRAM_BASE + \
162 STM32MP_SYSRAM_SIZE - \
163 STM32MP_SYSRAM_DEVICE_SIZE)
164
165 #define STM32MP_SYSRAM_DEVICE_SIZE STM32MP_USB_DWC3_SIZE
166 #define STM32MP_SYSRAM_DEVICE_BASE STM32MP_USB_DWC3_BASE
167
168 #define STM32MP_SYSRAM_MEM_SIZE (STM32MP_SYSRAM_SIZE - \
169 STM32MP_SYSRAM_DEVICE_SIZE)
170 #define STM32MP_SYSRAM_MEM_BASE STM32MP_SYSRAM_BASE
171 #endif /* IMAGE_BL2 && STM32MP_USB_PROGRAMMER && !STM32MP21 */
172
173 /* DDR configuration */
174 #define STM32MP_DDR_BASE U(0x80000000)
175 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
176
177 /* DDR power initializations */
178 #ifndef __ASSEMBLER__
179 enum ddr_type {
180 STM32MP_DDR3,
181 STM32MP_DDR4,
182 STM32MP_LPDDR4
183 };
184 #endif
185
186 /* Section used inside TF binaries */
187 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
188 #if STM32MP21
189 /* 576 Bytes reserved for header */
190 #define STM32MP_HEADER_SIZE U(0x00000240)
191 #else /* STM32MP21 */
192 /* 512 Bytes reserved for header */
193 #define STM32MP_HEADER_SIZE U(0x00000200)
194 #endif /* STM32MP21 */
195 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \
196 STM32MP_PARAM_LOAD_SIZE)
197
198 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
199 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
200
201 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
202 STM32MP_PARAM_LOAD_SIZE + \
203 STM32MP_HEADER_SIZE)
204
205 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
206 (STM32MP_PARAM_LOAD_SIZE + \
207 STM32MP_HEADER_SIZE))
208
209 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
210 #define STM32MP_BL2_RO_SIZE U(0x0001F000) /* 124 KB */
211 #define STM32MP_BL2_SIZE U(0x00028000) /* 160 KB for BL2 */
212 #else /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
213 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
214 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
215 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
216
217 /* Allocate remaining sysram to BL31 Binary only */
218 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \
219 STM32MP_BL2_SIZE)
220
221 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
222 STM32MP_SYSRAM_SIZE - \
223 STM32MP_BL2_SIZE)
224
225 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
226
227 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
228 STM32MP_BL2_RO_SIZE)
229
230 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
231 STM32MP_SYSRAM_SIZE - \
232 STM32MP_BL2_RW_BASE)
233
234 /* BL2 and BL32/sp_min require 4 tables */
235 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
236
237 /*
238 * MAX_MMAP_REGIONS is usually:
239 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
240 */
241 #if STM32MP_USB_PROGRAMMER || defined(IMAGE_BL31)
242 #define MAX_MMAP_REGIONS 7
243 #else
244 #define MAX_MMAP_REGIONS 6
245 #endif
246
247 /* DTB initialization value */
248 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
249
250 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
251 STM32MP_BL2_DTB_SIZE)
252
253 #if defined(IMAGE_BL2)
254 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
255 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
256 #endif
257
258 #if STM32MP_DDR_FIP_IO_STORAGE
259 #define STM32MP_DDR_FW_BASE SRAM1_BASE
260 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400)
261 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800)
262 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
263 #endif
264
265 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
266 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
267
268 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
269 #define STM32MP_BL33_MAX_SIZE U(0x400000)
270 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
271 STM32MP_BL33_MAX_SIZE)
272 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
273 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
274
275 /*******************************************************************************
276 * STM32MP2 device/io map related constants (used for MMU)
277 ******************************************************************************/
278 #define STM32MP_DEVICE_BASE U(0x40000000)
279 #define STM32MP_DEVICE_SIZE U(0x40000000)
280
281 /*******************************************************************************
282 * STM32MP2 RCC
283 ******************************************************************************/
284 #define RCC_BASE U(0x44200000)
285
286 /*******************************************************************************
287 * STM32MP2 PWR
288 ******************************************************************************/
289 #define PWR_BASE U(0x44210000)
290
291 /*******************************************************************************
292 * STM32MP2 GPIO
293 ******************************************************************************/
294 #define GPIOA_BASE U(0x44240000)
295 #define GPIOB_BASE U(0x44250000)
296 #define GPIOC_BASE U(0x44260000)
297 #define GPIOD_BASE U(0x44270000)
298 #define GPIOE_BASE U(0x44280000)
299 #define GPIOF_BASE U(0x44290000)
300 #define GPIOG_BASE U(0x442A0000)
301 #define GPIOH_BASE U(0x442B0000)
302 #define GPIOI_BASE U(0x442C0000)
303 #if !STM32MP21
304 #define GPIOJ_BASE U(0x442D0000)
305 #define GPIOK_BASE U(0x442E0000)
306 #endif /* !STM32MP21 */
307 #define GPIOZ_BASE U(0x46200000)
308 #define GPIO_BANK_OFFSET U(0x10000)
309
310 #define STM32MP_GPIOS_PIN_MAX_COUNT 16
311 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
312
313 /*******************************************************************************
314 * STM32MP2 UART
315 ******************************************************************************/
316 #define USART1_BASE U(0x40330000)
317 #define USART2_BASE U(0x400E0000)
318 #define USART3_BASE U(0x400F0000)
319 #define UART4_BASE U(0x40100000)
320 #define UART5_BASE U(0x40110000)
321 #define USART6_BASE U(0x40220000)
322 #define UART7_BASE U(0x40370000)
323 #if STM32MP25
324 #define UART8_BASE U(0x40380000)
325 #define UART9_BASE U(0x402C0000)
326 #define STM32MP_NB_OF_UART U(9)
327 #else /* STM32MP25 */
328 #define STM32MP_NB_OF_UART U(7)
329 #endif /* STM32MP25 */
330
331 /* For UART crash console */
332 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
333 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
334 #ifdef ULTRA_FLY
335 #define STM32MP_DEBUG_USART_BASE USART1_BASE
336 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
337 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
338 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
339 #define DEBUG_UART_TX_GPIO_PORT 3
340 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
341 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
342 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
343 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR
344 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
345 #define DEBUG_UART_RST_REG RCC_USART1CFGR
346 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
347 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR
348 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR
349 #else
350 #define STM32MP_DEBUG_USART_BASE USART2_BASE
351 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
352 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
353 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
354 #define DEBUG_UART_TX_GPIO_PORT 4
355 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
356 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
357 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
358 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
359 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
360 #define DEBUG_UART_RST_REG RCC_USART2CFGR
361 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
362 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
363 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
364 #endif
365
366 /*******************************************************************************
367 * STM32MP2 SDMMC
368 ******************************************************************************/
369 #define STM32MP_SDMMC1_BASE U(0x48220000)
370 #define STM32MP_SDMMC2_BASE U(0x48230000)
371 #define STM32MP_SDMMC3_BASE U(0x48240000)
372
373 /*******************************************************************************
374 * STM32MP2 OSPI
375 ******************************************************************************/
376 /* OSPI 1 & 2 memory map area */
377 #define STM32MP_OSPI_MM_BASE U(0x60000000)
378 #define STM32MP_OSPI_MM_SIZE U(0x10000000)
379
380 /*******************************************************************************
381 * STM32MP2 BSEC / OTP
382 ******************************************************************************/
383 /*
384 * 367 available OTPs, the other are masked
385 * - ECIES key: 368 to 375 (only readable by bootrom)
386 * - HWKEY: 376 to 383 (never reloadable or readable)
387 */
388 #define STM32MP2_OTP_MAX_ID U(0x16F)
389 #define STM32MP2_MID_OTP_START U(0x80)
390 #define STM32MP2_UPPER_OTP_START U(0x100)
391
392 /* OTP labels */
393 #define PART_NUMBER_OTP "part-number-otp"
394 #define REVISION_OTP "rev_otp"
395 #define PACKAGE_OTP "package-otp"
396 #define HCONF1_OTP "otp124"
397 #define NAND_OTP "otp16"
398 #define NAND2_OTP "otp20"
399 #define BOARD_ID_OTP "board-id"
400 #define UID_OTP "uid-otp"
401 #define LIFECYCLE2_OTP "otp18"
402 #define PKH_OTP "otp144"
403 #define ENCKEY_OTP "otp260"
404
405 /* OTP mask */
406 /* PACKAGE */
407 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
408 #define PACKAGE_OTP_PKG_SHIFT U(0)
409
410 /* IWDG OTP */
411 #define HCONF1_OTP_IWDG_HW_POS U(0)
412 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
413 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
414
415 /* NAND OTP */
416 /* NAND parameter storage flag */
417 #define NAND_PARAM_STORED_IN_OTP BIT_32(31)
418
419 /* NAND page size in bytes */
420 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
421 #define NAND_PAGE_SIZE_SHIFT U(29)
422 #define NAND_PAGE_SIZE_2K U(0)
423 #define NAND_PAGE_SIZE_4K U(1)
424 #define NAND_PAGE_SIZE_8K U(2)
425
426 /* NAND block size in pages */
427 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
428 #define NAND_BLOCK_SIZE_SHIFT U(27)
429 #define NAND_BLOCK_SIZE_64_PAGES U(0)
430 #define NAND_BLOCK_SIZE_128_PAGES U(1)
431 #define NAND_BLOCK_SIZE_256_PAGES U(2)
432
433 /* NAND number of block (in unit of 256 blocks) */
434 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
435 #define NAND_BLOCK_NB_SHIFT U(19)
436 #define NAND_BLOCK_NB_UNIT U(256)
437
438 /* NAND bus width in bits */
439 #define NAND_WIDTH_MASK BIT_32(18)
440 #define NAND_WIDTH_SHIFT U(18)
441
442 /* NAND number of ECC bits per 512 bytes */
443 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
444 #define NAND_ECC_BIT_NB_SHIFT U(15)
445 #define NAND_ECC_BIT_NB_UNSET U(0)
446 #define NAND_ECC_BIT_NB_1_BITS U(1)
447 #define NAND_ECC_BIT_NB_4_BITS U(2)
448 #define NAND_ECC_BIT_NB_8_BITS U(3)
449 #define NAND_ECC_ON_DIE U(4)
450
451 /* NAND number of planes */
452 #define NAND_PLANE_BIT_NB_MASK BIT_32(14)
453
454 /* NAND2 OTP */
455 #define NAND2_PAGE_SIZE_SHIFT U(16)
456
457 /* NAND2 config distribution */
458 #define NAND2_CONFIG_DISTRIB BIT_32(0)
459 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
460 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
461
462 /* MONOTONIC OTP */
463 #define MAX_MONOTONIC_VALUE U(32)
464
465 /* UID OTP */
466 #define UID_WORD_NB U(3)
467
468 /* Lifecycle OTP */
469 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
470
471 /*******************************************************************************
472 * STM32MP2 TAMP
473 ******************************************************************************/
474 #define PLAT_MAX_TAMP_INT U(5)
475 #define PLAT_MAX_TAMP_EXT U(3)
476 #define TAMP_BASE U(0x46010000)
477 #define TAMP_SMCR (TAMP_BASE + U(0x20))
478 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
479 #define TAMP_BKP_REG_CLK CK_BUS_RTC
480 #define TAMP_BKP_SEC_NUMBER U(10)
481 #define TAMP_COUNTR U(0x40)
482
483 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)484 static inline uintptr_t tamp_bkpr(uint32_t idx)
485 {
486 return TAMP_BKP_REGISTER_BASE + (idx << 2);
487 }
488 #endif
489
490 /*******************************************************************************
491 * STM32MP2 USB
492 ******************************************************************************/
493 #if STM32MP21
494 #define USB_OTG_BASE U(0x48300000)
495 #else /* STM32MP21 */
496 #define USB_DWC3_BASE U(0x48300000)
497 #endif /* STM32MP21 */
498
499 /*******************************************************************************
500 * STM32MP2 DDRCTRL
501 ******************************************************************************/
502 #define DDRCTRL_BASE U(0x48040000)
503
504 /*******************************************************************************
505 * STM32MP2 DDRDBG
506 ******************************************************************************/
507 #define DDRDBG_BASE U(0x48050000)
508
509 /*******************************************************************************
510 * STM32MP2 DDRPHYC
511 ******************************************************************************/
512 #define DDRPHYC_BASE U(0x48C00000)
513
514 /*******************************************************************************
515 * Miscellaneous STM32MP2 peripherals base address
516 ******************************************************************************/
517 #define BSEC_BASE U(0x44000000)
518 #define DBGMCU_BASE U(0x4A010000)
519 #define HASH_BASE U(0x42010000)
520 #define RTC_BASE U(0x46000000)
521 #define STGEN_BASE U(0x48080000)
522 #define SYSCFG_BASE U(0x44230000)
523
524 /*******************************************************************************
525 * STM32MP RIF
526 ******************************************************************************/
527 #define RIFSC_BASE U(0x42080000)
528 #define RISAB1_BASE U(0x420F0000)
529 #define RISAB2_BASE U(0x42100000)
530 #define RISAB3_BASE U(0x42110000)
531 #define RISAB5_BASE U(0x42130000)
532
533 #define RISAF1_INST 0
534 #define RISAF2_INST 1
535 #define RISAF4_INST 3
536 #define RISAF5_INST 4
537 #define RISAF_MAX_INSTANCE 5
538
539 #define RISAF1_BASE U(0x420A0000)
540 #define RISAF2_BASE U(0x420B0000)
541 #define RISAF4_BASE U(0x420D0000)
542 #define RISAF5_BASE U(0x420E0000)
543
544 #define USE_RISAF2
545 #define USE_RISAF4
546
547 #ifdef USE_RISAF1
548 #define RISAF1_MAX_REGION 4
549 #else
550 #define RISAF1_MAX_REGION 0
551 #endif
552 #ifdef USE_RISAF2
553 #define RISAF2_MAX_REGION 4
554 #else
555 #define RISAF2_MAX_REGION 0
556 #endif
557 #ifdef USE_RISAF4
558 /* Consider only encrypted region maximum number, to save memory consumption */
559 #define RISAF4_MAX_REGION 4
560 #else
561 #define RISAF4_MAX_REGION 0
562 #endif
563 #ifdef USE_RISAF5
564 #define RISAF5_MAX_REGION 2
565 #else
566 #define RISAF5_MAX_REGION 0
567 #endif
568 #define RISAF_MAX_REGION (RISAF1_MAX_REGION + RISAF2_MAX_REGION + \
569 RISAF4_MAX_REGION + RISAF5_MAX_REGION)
570
571 #if STM32MP21
572 #define RISAF_KEY_SIZE_IN_BYTES RISAF_MCE_KEY_256BITS_SIZE_IN_BYTES
573 #else /* STM32MP21 */
574 #define RISAF_KEY_SIZE_IN_BYTES RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES
575 #endif /* STM32MP21 */
576 #define RISAF_SEED_SIZE_IN_BYTES U(4)
577
578 /*******************************************************************************
579 * RIFSC
580 ******************************************************************************/
581 #if STM32MP21
582 #define STM32MP21_RIMU_OTG_HS U(4)
583
584 /*
585 * OTG_HS Secure/Priv Master (DMA) access
586 */
587 #define RIFSC_USB_BOOT_OTG_HS_RIMC_CONF (RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC | \
588 RIF_CID1 << RIFSC_RIMC_ATTRx_MCID_SHIFT | \
589 RIFSC_RIMC_ATTRx_CIDSEL)
590 #else /* !STM32MP21 */
591 #define STM32MP2_RIMU_USB3DR U(4)
592
593 /*
594 * USB3DR Secure/Priv Master (DMA) access
595 */
596 #define RIFSC_USB_BOOT_USB3DR_RIMC_CONF (RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC | \
597 RIF_CID1 << RIFSC_RIMC_ATTRx_MCID_SHIFT | \
598 RIFSC_RIMC_ATTRx_CIDSEL)
599 #endif /* STM32MP21 */
600
601 /*******************************************************************************
602 * STM32MP CA35SSC
603 ******************************************************************************/
604 #define A35SSC_BASE U(0x48800000)
605
606 /*******************************************************************************
607 * REGULATORS
608 ******************************************************************************/
609 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
610 #define PLAT_NB_RDEVS U(19)
611 /* 2 FIXED */
612 #define PLAT_NB_FIXED_REGUS U(2)
613
614 /*******************************************************************************
615 * Device Tree defines
616 ******************************************************************************/
617 #define DT_BSEC_COMPAT "st,stm32mp25-bsec"
618 #define DT_DDR_COMPAT "st,stm32mp2-ddr"
619 #if STM32MP21
620 #define DT_PWR_COMPAT "st,stm32mp21-pwr"
621 #define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc"
622 #else
623 #define DT_PWR_COMPAT "st,stm32mp25-pwr"
624 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
625 #endif
626 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
627 #define DT_UART_COMPAT "st,stm32h7-uart"
628
629 #endif /* STM32MP2_DEF_H */
630