1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/gic.h> 14 #include <drivers/arm/tzc_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/cassert.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/spinlock.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #if TRANSFER_LIST 23 #include <transfer_list.h> 24 #endif 25 26 /******************************************************************************* 27 * Forward declarations 28 ******************************************************************************/ 29 struct meminfo; 30 struct image_info; 31 struct bl_params; 32 33 typedef struct arm_tzc_regions_info { 34 unsigned long long base; 35 unsigned long long end; 36 unsigned int sec_attr; 37 unsigned int nsaid_permissions; 38 } arm_tzc_regions_info_t; 39 40 typedef struct arm_gpt_info { 41 pas_region_t *pas_region_base; 42 unsigned int pas_region_count; 43 uintptr_t l0_base; 44 uintptr_t l1_base; 45 size_t l0_size; 46 size_t l1_size; 47 gpccr_pps_e pps; 48 gpccr_pgs_e pgs; 49 } arm_gpt_info_t; 50 51 /******************************************************************************* 52 * Default mapping definition of the TrustZone Controller for ARM standard 53 * platforms. 54 * Configure: 55 * - Region 0 with no access; 56 * - Region 1 with secure access only; 57 * - the remaining DRAM regions access from the given Non-Secure masters. 58 ******************************************************************************/ 59 60 #if ENABLE_FEAT_RME 61 #define ARM_TZC_RME_REGIONS_DEF \ 62 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 63 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 64 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 67 PLAT_ARM_TZC_NS_DEV_ACCESS} 68 #endif /* ENABLE_FEAT_RME */ 69 70 #if ENABLE_FEAT_RME 71 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 72 MEASURED_BOOT 73 #define ARM_TZC_REGIONS_DEF \ 74 ARM_TZC_RME_REGIONS_DEF, \ 75 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 76 TZC_REGION_S_RDWR, 0} 77 #else 78 #define ARM_TZC_REGIONS_DEF \ 79 ARM_TZC_RME_REGIONS_DEF 80 #endif 81 82 #else 83 #define ARM_TZC_REGIONS_DEF \ 84 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 85 TZC_REGION_S_RDWR, 0}, \ 86 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 87 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 88 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 89 PLAT_ARM_TZC_NS_DEV_ACCESS} 90 #endif 91 92 #define ARM_CASSERT_MMAP \ 93 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 94 assert_plat_arm_mmap_mismatch); \ 95 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 96 <= MAX_MMAP_REGIONS, \ 97 assert_max_mmap_regions); 98 99 void arm_setup_romlib(void); 100 101 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 102 /* 103 * Use this macro to instantiate lock before it is used in below 104 * arm_lock_xxx() macros 105 */ 106 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 107 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 108 109 #if !HW_ASSISTED_COHERENCY 110 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 111 #else 112 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 113 #endif 114 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 115 116 /* 117 * These are wrapper macros to the Coherent Memory Bakery Lock API. 118 */ 119 #define arm_lock_init() bakery_lock_init(&arm_lock) 120 #define arm_lock_get() bakery_lock_get(&arm_lock) 121 #define arm_lock_release() bakery_lock_release(&arm_lock) 122 123 #else 124 125 /* 126 * Empty macros for all other BL stages other than BL31 and BL32 127 */ 128 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 129 #define ARM_LOCK_GET_INSTANCE 0 130 #define arm_lock_init() 131 #define arm_lock_get() 132 #define arm_lock_release() 133 134 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 135 136 #ifdef __aarch64__ 137 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO64 138 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT64 139 #else 140 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO32 141 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT32 142 #endif 143 144 #if ARM_RECOM_STATE_ID_ENC 145 /* 146 * Macros used to parse state information from State-ID if it is using the 147 * recommended encoding for State-ID. 148 */ 149 #define ARM_LOCAL_PSTATE_WIDTH 4 150 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 151 152 /* Last in Level for the OS-initiated */ 153 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 154 (ARM_LOCAL_PSTATE_WIDTH * \ 155 (PLAT_MAX_PWR_LVL + 1))) 156 157 /* Macros to construct the composite power state */ 158 159 /* Make composite power state parameter till power level 0 */ 160 #if PSCI_EXTENDED_STATE_ID 161 162 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 163 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 164 #else 165 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 166 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 167 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 168 ((type) << PSTATE_TYPE_SHIFT)) 169 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 170 171 /* Make composite power state parameter till power level 1 */ 172 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 173 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 174 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 175 176 /* Make composite power state parameter till power level 2 */ 177 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 178 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 179 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 180 181 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 182 183 /* ARM State switch error codes */ 184 #define STATE_SW_E_PARAM (-2) 185 #define STATE_SW_E_DENIED (-3) 186 187 /* plat_get_rotpk_info() flags */ 188 #define ARM_ROTPK_REGS_ID 1 189 #define ARM_ROTPK_DEVEL_RSA_ID 2 190 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 191 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 192 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 193 194 #define ARM_USE_DEVEL_ROTPK \ 195 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 196 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 197 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 198 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 199 200 /* IO storage utility functions */ 201 int arm_io_setup(void); 202 203 /* Set image specification in IO block policy */ 204 int arm_set_image_source(unsigned int image_id, const char *part_name, 205 uintptr_t *dev_handle, uintptr_t *image_spec); 206 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 207 208 /* Security utility functions */ 209 void arm_tzc400_setup(uintptr_t tzc_base, 210 const arm_tzc_regions_info_t *tzc_regions); 211 struct tzc_dmc500_driver_data; 212 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 213 const arm_tzc_regions_info_t *tzc_regions); 214 215 /* Console utility functions */ 216 void arm_console_boot_init(void); 217 void arm_console_boot_end(void); 218 void arm_console_runtime_init(void); 219 void arm_console_runtime_end(void); 220 221 /* Systimer utility function */ 222 void arm_configure_sys_timer(void); 223 224 /* PM utility functions */ 225 int arm_validate_power_state(unsigned int power_state, 226 psci_power_state_t *req_state); 227 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 228 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 229 void arm_system_pwr_domain_save(void); 230 void arm_system_pwr_domain_resume(void); 231 int arm_psci_read_mem_protect(int *enabled); 232 int arm_nor_psci_write_mem_protect(int val); 233 void arm_nor_psci_do_static_mem_protect(void); 234 void arm_nor_psci_do_dyn_mem_protect(void); 235 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 236 237 /* Topology utility function */ 238 int arm_check_mpidr(u_register_t mpidr); 239 240 /* BL1 utility functions */ 241 void arm_bl1_early_platform_setup(void); 242 void arm_bl1_platform_setup(void); 243 void arm_bl1_plat_arch_setup(void); 244 245 /* BL2 utility functions */ 246 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 247 u_register_t arg2, u_register_t arg3); 248 void arm_bl2_platform_setup(void); 249 uint32_t arm_get_spsr(unsigned int image_id); 250 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 251 int arm_bl2_handle_post_image_load(unsigned int image_id); 252 struct bl_params *arm_get_next_bl_params(void); 253 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 254 255 /* BL2U utility functions */ 256 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 257 void *plat_info); 258 void arm_bl2u_platform_setup(void); 259 void arm_bl2u_plat_arch_setup(void); 260 261 /* BL31 utility functions */ 262 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 263 u_register_t arg2, u_register_t arg3); 264 void arm_bl31_platform_setup(void); 265 void arm_bl31_plat_runtime_setup(void); 266 void arm_bl31_plat_arch_setup(void); 267 268 /* Firmware Handoff utility functions */ 269 #if TRANSFER_LIST 270 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 271 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 272 struct transfer_list_header *secure_tl); 273 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 274 struct transfer_list_header *ns_tl); 275 struct transfer_list_entry * 276 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 277 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 278 #endif 279 280 /* TSP utility functions */ 281 void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, 282 u_register_t arg2, u_register_t arg3); 283 284 /* SP_MIN utility functions */ 285 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 286 u_register_t arg2, u_register_t arg3); 287 void arm_sp_min_plat_runtime_setup(void); 288 void arm_sp_min_plat_arch_setup(void); 289 290 /* FIP TOC validity check */ 291 bool arm_io_is_toc_valid(void); 292 293 /* Utility functions for Dynamic Config */ 294 295 void arm_bl1_set_mbedtls_heap(void); 296 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 297 298 #if IMAGE_BL2 299 void arm_bl2_dyn_cfg_init(void); 300 #endif /* IMAGE_BL2 */ 301 302 #if MEASURED_BOOT 303 #if DICE_PROTECTION_ENVIRONMENT 304 int arm_set_nt_fw_info(int *ctx_handle); 305 int arm_set_tb_fw_info(int *ctx_handle); 306 int arm_get_tb_fw_info(int *ctx_handle); 307 #else 308 /* Specific to event log backend */ 309 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 310 int arm_set_nt_fw_info( 311 /* 312 * Currently OP-TEE does not support reading DTBs from Secure memory 313 * and this option should be removed when feature is supported. 314 */ 315 #ifdef SPD_opteed 316 uintptr_t log_addr, 317 #endif 318 size_t log_size, uintptr_t *ns_log_addr); 319 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 320 size_t log_max_size); 321 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 322 size_t *log_max_size); 323 #endif /* DICE_PROTECTION_ENVIRONMENT */ 324 #endif /* MEASURED_BOOT */ 325 326 /* 327 * Free the memory storing initialization code only used during an images boot 328 * time so it can be reclaimed for runtime data 329 */ 330 void arm_free_init_memory(void); 331 332 /* 333 * Make the higher level translation tables read-only 334 */ 335 void arm_xlat_make_tables_readonly(void); 336 337 /* 338 * Mandatory functions required in ARM standard platforms 339 */ 340 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 341 342 /* should not be used, but keep for compatibility */ 343 #if USE_GIC_DRIVER == 0 344 void plat_arm_gic_driver_init(void); 345 void plat_arm_gic_init(void); 346 void plat_arm_gic_cpuif_enable(void); 347 void plat_arm_gic_cpuif_disable(void); 348 void plat_arm_gic_redistif_on(void); 349 void plat_arm_gic_redistif_off(void); 350 void plat_arm_gic_pcpu_init(void); 351 void plat_arm_gic_save(void); 352 void plat_arm_gic_resume(void); 353 #elif USE_GIC_DRIVER == 3 354 extern uintptr_t arm_gicr_base_addrs[]; 355 #endif 356 void plat_arm_security_setup(void); 357 void plat_arm_pwrc_setup(void); 358 #if !HW_ASSISTED_COHERENCY 359 void plat_arm_interconnect_init(void); 360 void plat_arm_interconnect_enter_coherency(void); 361 void plat_arm_interconnect_exit_coherency(void); 362 #endif /* HW_ASSISTED_COHERENCY */ 363 void plat_arm_program_trusted_mailbox(uintptr_t address); 364 bool plat_arm_bl1_fwu_needed(void); 365 int plat_arm_ni_setup(uintptr_t global_cfg); 366 __dead2 void plat_arm_error_handler(int err); 367 368 /* 369 * Optional functions in ARM standard platforms 370 */ 371 void gic_set_gicr_frames(const uintptr_t *plat_gicr_frames); 372 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 373 unsigned int *flags); 374 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 375 unsigned int *flags); 376 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 377 unsigned int *flags); 378 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 379 unsigned int *flags); 380 381 #if ARM_PLAT_MT 382 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 383 #endif 384 385 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 386 387 /* 388 * This function is called after loading SCP_BL2 image and it is used to perform 389 * any platform-specific actions required to handle the SCP firmware. 390 */ 391 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 392 393 /* 394 * Optional functions required in ARM standard platforms 395 */ 396 void plat_arm_io_setup(void); 397 int plat_arm_get_alt_image_source( 398 unsigned int image_id, 399 uintptr_t *dev_handle, 400 uintptr_t *image_spec); 401 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 402 const mmap_region_t *plat_arm_get_mmap(void); 403 404 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 405 void arm_gpt_setup(void); 406 407 /* Allow platform to override psci_pm_ops during runtime */ 408 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 409 410 /* Execution state switch in ARM platforms */ 411 int arm_execution_state_switch(unsigned int smc_fid, 412 uint32_t pc_hi, 413 uint32_t pc_lo, 414 uint32_t cookie_hi, 415 uint32_t cookie_lo, 416 void *handle); 417 418 /* Optional functions for SP_MIN */ 419 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 420 u_register_t arg2, u_register_t arg3); 421 422 /* global variables */ 423 extern plat_psci_ops_t plat_arm_psci_pm_ops; 424 extern const mmap_region_t plat_arm_mmap[]; 425 extern const unsigned int arm_pm_idle_states[]; 426 extern struct transfer_list_header *secure_tl; 427 428 /* secure watchdog */ 429 void plat_arm_secure_wdt_start(void); 430 void plat_arm_secure_wdt_stop(void); 431 void plat_arm_secure_wdt_refresh(void); 432 433 /* Get SOC-ID of ARM platform */ 434 uint32_t plat_arm_get_soc_id(void); 435 436 #endif /* PLAT_ARM_H */ 437