1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
8
9 #include <linux/bitops.h>
10 #include <linux/mtd/cfi.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/spi/spi-mem.h>
13
14 /*
15 * Note on opcode nomenclature: some opcodes have a format like
16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
17 * of I/O lines used for the opcode, address, and data (respectively). The
18 * FUNCTION has an optional suffix of '4', to represent an opcode which
19 * requires a 4-byte (32-bit) address.
20 */
21
22 /* Flash opcodes. */
23 #define SPINOR_OP_WRDI 0x04 /* Write disable */
24 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
28 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
29 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
30 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
37 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
40 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
41 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
45 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
47 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
48 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
49 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
50 #define SPINOR_OP_WRCR 0x31 /* Write configure register */
51 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
52 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
53 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
54 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
55
56 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
57 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
58 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
59 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
60 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
61 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
62 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
63 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
64 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
65 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
66 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
67 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
68 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
69 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
70 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
71 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
72 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
73
74 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
75 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
76 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
77 #define SPINOR_OP_READ_1_4_4_DTR 0xed
78
79 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
80 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
81 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
82
83 /* Used for SST flashes only. */
84 #define SPINOR_OP_BP 0x02 /* Byte program */
85 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
86
87 /* Used for S3AN flashes only */
88 #define SPINOR_OP_XSE 0x50 /* Sector erase */
89 #define SPINOR_OP_XPP 0x82 /* Page program */
90 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
91
92 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
93 #define XSR_RDY BIT(7) /* Ready */
94
95
96 /* Used for Macronix and Winbond flashes. */
97 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
98 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
99
100 /* Used for Spansion flashes only. */
101 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
102 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
103
104 /* Used for Micron flashes only. */
105 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
106 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
107
108 /* Status Register bits. */
109 #define SR_WIP BIT(0) /* Write in progress */
110 #define SR_WEL BIT(1) /* Write enable latch */
111 /* meaning of other SR_* bits may differ between vendors */
112 #define SR_BP0 BIT(2) /* Block protect 0 */
113 #define SR_BP1 BIT(3) /* Block protect 1 */
114 #define SR_BP2 BIT(4) /* Block protect 2 */
115 #define SR_BP3 BIT(5) /* Block protect 3 */
116 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
117 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
118 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
119 #define SR_SRWD BIT(7) /* SR write protect */
120 /* Spansion/Cypress specific status bits */
121 #define SR_E_ERR BIT(5)
122 #define SR_P_ERR BIT(6)
123
124 #define SR1_QUAD_EN_BIT6 BIT(6)
125
126 #define SR_BP_SHIFT 2
127
128 /* Enhanced Volatile Configuration Register bits */
129 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
130
131 /* Flag Status Register bits */
132 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
133 #define FSR_E_ERR BIT(5) /* Erase operation status */
134 #define FSR_P_ERR BIT(4) /* Program operation status */
135 #define FSR_PT_ERR BIT(1) /* Protection error bit */
136
137 /* Status Register 2 bits. */
138 #define SR2_QUAD_EN_BIT1 BIT(1)
139 #define SR2_QUAD_EN_BIT2 BIT(2)
140 #define SR2_QUAD_EN_BIT7 BIT(7)
141
142 /* Supported SPI protocols */
143 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
144 #define SNOR_PROTO_INST_SHIFT 16
145 #define SNOR_PROTO_INST(_nbits) \
146 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
147 SNOR_PROTO_INST_MASK)
148
149 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
150 #define SNOR_PROTO_ADDR_SHIFT 8
151 #define SNOR_PROTO_ADDR(_nbits) \
152 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
153 SNOR_PROTO_ADDR_MASK)
154
155 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
156 #define SNOR_PROTO_DATA_SHIFT 0
157 #define SNOR_PROTO_DATA(_nbits) \
158 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
159 SNOR_PROTO_DATA_MASK)
160
161 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
162
163 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
164 (SNOR_PROTO_INST(_inst_nbits) | \
165 SNOR_PROTO_ADDR(_addr_nbits) | \
166 SNOR_PROTO_DATA(_data_nbits))
167 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
168 (SNOR_PROTO_IS_DTR | \
169 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
170
171 enum spi_nor_protocol {
172 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
173 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
174 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
175 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
176 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
177 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
178 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
179 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
180 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
181 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
182
183 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
184 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
185 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
186 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
187 };
188
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)189 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
190 {
191 return !!(proto & SNOR_PROTO_IS_DTR);
192 }
193
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)194 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
195 {
196 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
197 SNOR_PROTO_INST_SHIFT;
198 }
199
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)200 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
201 {
202 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
203 SNOR_PROTO_ADDR_SHIFT;
204 }
205
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)206 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
207 {
208 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
209 SNOR_PROTO_DATA_SHIFT;
210 }
211
spi_nor_get_protocol_width(enum spi_nor_protocol proto)212 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
213 {
214 return spi_nor_get_protocol_data_nbits(proto);
215 }
216
217 /**
218 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
219 * supported by the SPI controller (bus master).
220 * @mask: the bitmask listing all the supported hw capabilies
221 */
222 struct spi_nor_hwcaps {
223 u32 mask;
224 };
225
226 /*
227 *(Fast) Read capabilities.
228 * MUST be ordered by priority: the higher bit position, the higher priority.
229 * As a matter of performances, it is relevant to use Octal SPI protocols first,
230 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
231 * (Slow) Read.
232 */
233 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
234 #define SNOR_HWCAPS_READ BIT(0)
235 #define SNOR_HWCAPS_READ_FAST BIT(1)
236 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
237
238 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
239 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
240 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
241 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
242 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
243
244 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
245 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
246 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
247 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
248 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
249
250 #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
251 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
252 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
253 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
254 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
255
256 /*
257 * Page Program capabilities.
258 * MUST be ordered by priority: the higher bit position, the higher priority.
259 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
260 * legacy SPI 1-1-1 protocol.
261 * Note that Dual Page Programs are not supported because there is no existing
262 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
263 * implements such commands.
264 */
265 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
266 #define SNOR_HWCAPS_PP BIT(16)
267
268 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
269 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
270 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
271 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
272
273 #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
274 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
275 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
276 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
277
278 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
279 SNOR_HWCAPS_READ_4_4_4 | \
280 SNOR_HWCAPS_READ_8_8_8 | \
281 SNOR_HWCAPS_PP_4_4_4 | \
282 SNOR_HWCAPS_PP_8_8_8)
283
284 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
285 SNOR_HWCAPS_READ_1_2_2_DTR | \
286 SNOR_HWCAPS_READ_1_4_4_DTR | \
287 SNOR_HWCAPS_READ_1_8_8_DTR)
288
289 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
290 SNOR_HWCAPS_PP_MASK)
291
292 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
293 struct spi_nor;
294
295 /**
296 * struct spi_nor_controller_ops - SPI NOR controller driver specific
297 * operations.
298 * @prepare: [OPTIONAL] do some preparations for the
299 * read/write/erase/lock/unlock operations.
300 * @unprepare: [OPTIONAL] do some post work after the
301 * read/write/erase/lock/unlock operations.
302 * @read_reg: read out the register.
303 * @write_reg: write data to the register.
304 * @read: read data from the SPI NOR.
305 * @write: write data to the SPI NOR.
306 * @erase: erase a sector of the SPI NOR at the offset @offs; if
307 * not provided by the driver, SPI NOR will send the erase
308 * opcode via write_reg().
309 */
310 struct spi_nor_controller_ops {
311 int (*prepare)(struct spi_nor *nor);
312 void (*unprepare)(struct spi_nor *nor);
313 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
314 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
315 size_t len);
316
317 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
318 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
319 const u8 *buf);
320 int (*erase)(struct spi_nor *nor, loff_t offs);
321 };
322
323 /*
324 * Forward declarations that are used internally by the core and manufacturer
325 * drivers.
326 */
327 struct flash_info;
328 struct spi_nor_manufacturer;
329 struct spi_nor_flash_parameter;
330
331 /**
332 * struct spi_nor - Structure for defining the SPI NOR layer
333 * @mtd: an mtd_info structure
334 * @lock: the lock for the read/write/erase/lock/unlock operations
335 * @dev: pointer to an SPI device or an SPI NOR controller device
336 * @spimem: pointer to the SPI memory device
337 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
338 * layer is not DMA-able
339 * @bouncebuf_size: size of the bounce buffer
340 * @info: SPI NOR part JEDEC MFR ID and other info
341 * @manufacturer: SPI NOR manufacturer
342 * @page_size: the page size of the SPI NOR
343 * @addr_width: number of address bytes
344 * @erase_opcode: the opcode for erasing a sector
345 * @read_opcode: the read opcode
346 * @read_dummy: the dummy needed by the read operation
347 * @program_opcode: the program opcode
348 * @sst_write_second: used by the SST write operation
349 * @flags: flag options for the current SPI NOR (SNOR_F_*)
350 * @read_proto: the SPI protocol for read operations
351 * @write_proto: the SPI protocol for write operations
352 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
353 * @controller_ops: SPI NOR controller driver specific operations.
354 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
355 * The structure includes legacy flash parameters and
356 * settings that can be overwritten by the spi_nor_fixups
357 * hooks, or dynamically when parsing the SFDP tables.
358 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
359 * @priv: pointer to the private data
360 */
361 struct spi_nor {
362 struct mtd_info mtd;
363 struct mutex lock;
364 struct device *dev;
365 struct spi_mem *spimem;
366 u8 *bouncebuf;
367 size_t bouncebuf_size;
368 const struct flash_info *info;
369 const struct spi_nor_manufacturer *manufacturer;
370 u32 page_size;
371 u8 addr_width;
372 u8 erase_opcode;
373 u8 read_opcode;
374 u8 read_dummy;
375 u8 program_opcode;
376 enum spi_nor_protocol read_proto;
377 enum spi_nor_protocol write_proto;
378 enum spi_nor_protocol reg_proto;
379 bool sst_write_second;
380 u32 flags;
381
382 const struct spi_nor_controller_ops *controller_ops;
383
384 struct spi_nor_flash_parameter *params;
385
386 struct {
387 struct spi_mem_dirmap_desc *rdesc;
388 struct spi_mem_dirmap_desc *wdesc;
389 } dirmap;
390
391 struct miscdevice *misc_dev;
392 void *priv;
393 };
394
spi_nor_set_flash_node(struct spi_nor * nor,struct device_node * np)395 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
396 struct device_node *np)
397 {
398 mtd_set_of_node(&nor->mtd, np);
399 }
400
spi_nor_get_flash_node(struct spi_nor * nor)401 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
402 {
403 return mtd_get_of_node(&nor->mtd);
404 }
405
406 /**
407 * spi_nor_scan() - scan the SPI NOR
408 * @nor: the spi_nor structure
409 * @name: the chip type name
410 * @hwcaps: the hardware capabilities supported by the controller driver
411 *
412 * The drivers can use this fuction to scan the SPI NOR.
413 * In the scanning, it will try to get all the necessary information to
414 * fill the mtd_info{} and the spi_nor{}.
415 *
416 * The chip type name can be provided through the @name parameter.
417 *
418 * Return: 0 for success, others for failure.
419 */
420 int spi_nor_scan(struct spi_nor *nor, const char *name,
421 const struct spi_nor_hwcaps *hwcaps);
422
423 /**
424 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
425 * @nor: the spi_nor structure
426 */
427 void spi_nor_restore(struct spi_nor *nor);
428
429 #endif
430