xref: /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/sleep_def.h (revision c0047dec92fb161a60074938793d59491987f476) 
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SLEEP_DEF_H
8 #define SLEEP_DEF_H
9 /*FIXME*/
10 /*
11  * Auto generated by DE, please DO NOT modify this file directly.
12  */
13 
14 /* --- SPM Flag Define --- */
15 #define SPM_FLAG_DISABLE_INFRA_PDN	BIT(0)
16 #define SPM_FLAG_DISABLE_DPM_PDN	BIT(1)
17 #define SPM_FLAG_DISABLE_MCUPM_PDN	BIT(2)
18 #define SPM_FLAG_DISABLE_DPY_PDN	BIT(3)
19 #define SPM_FLAG_ENABLE_LVTS_WORKAROUND	BIT(4)
20 #define SPM_FLAG_DISABLE_SYSRAM_SLEEP	BIT(5)
21 #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	BIT(6)
22 #define SPM_FLAG_DISABLE_BUS_CLK_OFF	BIT(7)
23 #define SPM_FLAG_DISABLE_VCORE_DVS	BIT(8)
24 #define SPM_FLAG_DISABLE_DDR_DFS	BIT(9)
25 #define SPM_FLAG_DISABLE_EMI_DFS	BIT(10)
26 #define SPM_FLAG_DISABLE_BUS_DFS	BIT(11)
27 #define SPM_FLAG_DISABLE_COMMON_SCENARIO	BIT(12)
28 #define SPM_FLAG_DISABLE_CPU_PDN	BIT(13)
29 #define SPM_FLAG_DISABLE_ARMPLL_OFF	BIT(14)
30 #define SPM_FLAG_DISABLE_DDRPHY_PDN	BIT(15)
31 #define SPM_FLAG_KEEP_CSYSPWRACK_HIGH	BIT(16)
32 #define SPM_FLAG_ENABLE_VDD2_DVS	BIT(17)
33 #define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	BIT(18)
34 #define SPM_FLAG_RUN_COMMON_SCENARIO	BIT(19)
35 #define SPM_FLAG_USE_SRCCLKENO2	BIT(20)
36 #define SPM_FLAG_ENABLE_AOV	BIT(21)
37 #define SPM_FLAG_ENABLE_MD_MUMTAS	BIT(22)
38 #define SPM_FLAG_DISABLE_DVFSQ	BIT(23)
39 #define SPM_FLAG_ENABLE_EMI_SSC	BIT(24)
40 #define SPM_FLAG_ENABLE_VMDDRDVS	BIT(25)
41 #define SPM_FLAG_VCORE_STATE	BIT(26)
42 #define SPM_FLAG_VTCXO_STATE	BIT(27)
43 #define SPM_FLAG_INFRA_STATE	BIT(28)
44 #define SPM_FLAG_APSRC_STATE	BIT(29)
45 #define SPM_FLAG_VRF18_STATE	BIT(30)
46 #define SPM_FLAG_DDREN_STATE	BIT(31)
47 
48 /* --- SPM Flag1 Define --- */
49 #define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M	BIT(0)
50 #define SPM_FLAG1_DISABLE_SYSPLL_OFF	BIT(1)
51 #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH	BIT(2)
52 #define SPM_FLAG1_DISABLE_CSOPLU_OFF	BIT(3)
53 #define SPM_FLAG1_FW_SET_CSOPLU_ON	BIT(4)
54 #define SPM_FLAG1_DISABLE_EMI_CLK_TO_CSOPLU	BIT(5)
55 #define SPM_FLAG1_DISABLE_NO_RESUME	BIT(6)
56 #define SPM_FLAG1_ENABLE_VS3_VOSEL_CTRL	BIT(7)
57 #define SPM_FLAG1_ENABLE_VS2_VS3_VOTER	BIT(8)
58 #define SPM_FLAG1_POLLING_BUS_PROTECT	BIT(9)
59 #define SPM_FLAG1_DISABLE_SRCLKEN_LOW	BIT(10)
60 #define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH	BIT(11)
61 #define SPM_FLAG1_DISABLE_TOP_26M_CK_OFF	BIT(12)
62 #define SPM_FLAG1_DISABLE_PCM_26M_SWITCH	BIT(13)
63 #define SPM_FLAG1_DISABLE_CKSQ_OFF	BIT(14)
64 #define SPM_FLAG1_DO_DPSW_0P725V	BIT(15)
65 #define SPM_FLAG1_ENABLE_COMMON_APSRC	BIT(16)
66 #define SPM_FLAG1_ENABLE_DFD_SOC_MTCMOS_EN	BIT(17)
67 #define SPM_FLAG1_ENABLE_LP5_DVFS	BIT(18)
68 #define SPM_FLAG1_ENABLE_EMI_DFS_BACKUP_SOLUTION	BIT(19)
69 #define SPM_FLAG1_DISABLE_INFRA_SRAM_SLEEP	BIT(20)
70 #define SPM_FLAG1_DISABLE_AXI_MEM_CLK_OFF	BIT(21)
71 #define SPM_FLAG1_DISABLE_VCORE_LP	BIT(22)
72 #define SPM_FLAG1_RESERVED_BIT23	BIT(23)
73 #define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL	BIT(24)
74 #define SPM_FLAG1_DISABLE_PERI_OFF	BIT(25)
75 #define SPM_FLAG1_ENABLE_MCU_INFRA_PARITY	BIT(26)
76 #define SPM_FLAG1_RESERVED_BIT27	BIT(27)
77 #define SPM_FLAG1_RESERVED_BIT28	BIT(28)
78 #define SPM_FLAG1_RESERVED_BIT29	BIT(29)
79 #define SPM_FLAG1_ENABLE_WAKE_PROF	BIT(30)
80 #define SPM_FLAG1_ENABLE_SLEEP_PROF	BIT(31)
81 
82 /* --- SPM DEBUG Define --- */
83 #define SPM_DBG_DEBUG_IDX_26M_WAKE	BIT(0)
84 #define SPM_DBG_DEBUG_IDX_26M_SLEEP	BIT(1)
85 #define SPM_DBG_DEBUG_IDX_INFRA_WAKE	BIT(2)
86 #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP	BIT(3)
87 #define SPM_DBG_DEBUG_IDX_APSRC_WAKE	BIT(4)
88 #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP	BIT(5)
89 #define SPM_DBG_DEBUG_IDX_VRF18_WAKE	BIT(6)
90 #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP	BIT(7)
91 #define SPM_DBG_DEBUG_IDX_VCORE_WAKE	BIT(8)
92 #define SPM_DBG_DEBUG_IDX_VCORE_OFF	BIT(9)
93 #define SPM_DBG_DEBUG_IDX_DDREN_WAKE	BIT(10)
94 #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP	BIT(11)
95 #define SPM_DBG_DEBUG_IDX_PMIC_SLEEP	BIT(12)
96 #define SPM_DBG_DEBUG_IDX_PMIC_WAKE	BIT(13)
97 #define SPM_DBG_DEBUG_IDX_EMI_WAKE	BIT(14)
98 #define SPM_DBG_DEBUG_IDX_EMI_SLEEP	BIT(15)
99 #define SPM_DBG_DEBUG_IDX_SYSRAM_SLP	BIT(16)
100 #define SPM_DBG_DEBUG_IDX_SSPM_WFI	BIT(17)
101 #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP	BIT(18)
102 #define SPM_DBG_DEBUG_IDX_SSPM_ON	BIT(19)
103 #define SPM_DBG_DEBUG_IDX_SYSRAM_ON	BIT(20)
104 #define SPM_DBG_DEBUG_IDX_AOVBUS_130M	BIT(21)
105 #define SPM_DBG_DEBUG_IDX_AOV_MODE	BIT(22)
106 #define SPM_DBG_DEBUG_IDX_SPM_DVFS_NO_REQ	BIT(23)
107 #define SPM_DBG_DEBUG_IDX_SPM_NORMAL_WAKEUP	BIT(28)
108 #define SPM_DBG_DEBUG_IDX_SPM_WAKEUP_BY_NONE	BIT(29)
109 
110 /* --- SPM DEBUG1 Define --- */
111 #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP	BIT(0)
112 #define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START	BIT(1)
113 #define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF	BIT(2)
114 #define SPM_DBG1_DEBUG_IDX_SYSPLL_ON	BIT(3)
115 /* #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DFS		BIT(4) */
116 #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF	BIT(5)
117 #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON	BIT(6)
118 #define SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_0	BIT(7)
119 #define SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_1	BIT(8)
120 #define SPM_DBG1_DEBUG_IDX_SPM_DFD_SOC_MTCMOS_EN	BIT(9)
121 #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC	BIT(11)
122 #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M	BIT(12)
123 #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K	BIT(13)
124 #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M	BIT(14)
125 #define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF	BIT(15)
126 #define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON	BIT(16)
127 #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW	BIT(17)
128 #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH	BIT(18)
129 #define SPM_DBG1_DEBUG_IDX_VMDDRVDDQ_OFF	BIT(19)
130 #define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	BIT(20)
131 #define SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT	BIT(21)
132 #define SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT	BIT(22)
133 #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT	BIT(23)
134 #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT	BIT(24)
135 #define SPM_DBG1_DEBUG_IDX_VMDDRVDDQ_ON	BIT(25)
136 #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT	BIT(26)
137 #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT	BIT(27)
138 #define SPM_DBG1_DEBUG_IDX_SPM_PMIF_CMD_RDY_ABORT	BIT(28)
139 #define SPM_DBG1_DEBUG_IDX_MCUPM_RESORE	BIT(29)
140 #define SPM_DBG1_DEBUG_IDX_DISABLE_DVFSRC	BIT(31)
141 
142 #endif /* SLEEP_DEF_H */
143